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LMP8603MM/NOPB [TI]

具有直列式滤波器功能的 -22V 至 60V、双向电流感应放大器 | DGK | 8 | -40 to 125;
LMP8603MM/NOPB
型号： LMP8603MM/NOPB
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

具有直列式滤波器功能的 -22V 至 60V、双向电流感应放大器 | DGK | 8 | -40 to 125

放大器
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LMP8602, LMP8602Q, LMP8603, LMP8603Q  
www.ti.com  
SNOSB36D –JULY 2009–REVISED MARCH 2013  
60V Common Mode, Fixed Gain, Bidirectional Precision Current Sensing Amplifier  
Check for Samples: LMP8602, LMP8602Q, LMP8603, LMP8603Q  
1
FEATURES  
DESCRIPTION  
The LMP8602 and LMP8603 are fixed gain precision  
amplifiers. The parts will amplify and filter small  
differential signals in the presence of high common  
mode voltages. The input common mode voltage  
range is –22V to +60V when operating from a single  
5V supply. With a 3.3V supply, the input common  
mode voltage range is from –4V to +27V. The  
LMP8602 and LMP8603 are members of the Linear  
Monolithic Precision (LMP®) family and are ideal  
parts for unidirectional and bidirectional current  
sensing applications. All parameter values of the  
parts that are shown in the tables are 100% tested  
and all bold values are also 100% tested over  
temperature.  
2
•
Unless Otherwise Noted, Typical Values at TA  
= 25°C, VS = 5.0V, Gain = 50x (LMP8602), Gain  
= 100x (LMP8603)  
•
•
•
•
•
•
TCVos 10μV/°C max  
CMRR 90 dB Min  
Input Offset Voltage 1 mV Max  
CMVR at VS = 3.3V −4V to 27V  
CMVR at VS = 5.0V −22V to 60V  
Operating Ambient Temperature Range −40°C  
to 125°C  
•
•
•
Single Supply Bidirectional Operation  
All Min / Max Limits 100% Tested  
The parts have a precise gain of 50x for the  
LMP8602 and 100x for the LMP8603, which are  
adequate in most targeted applications to drive an  
ADC to its full scale value. The fixed gain is achieved  
in two separate stages, a preamplifier with a gain of  
10x and an output stage buffer amplifier with a gain  
of 5x for the LMP8602 and 10x for the LMP8603. The  
connection between the two stages of the signal path  
is brought out on two pins to enable the possibility to  
create an additional filter network around the output  
buffer amplifier. These pins can also be used for  
alternative configurations with different gain as  
described in the applications section.  
LMP8602Q and LMP8603Q Available in  
Automotive AEC-Q100 Grade 1 Qualified  
Version  
APPLICATIONS  
•
High Side and Low Side Driver Configuration  
Current Sensing  
•
•
•
•
•
•
Bidirectional Current Measurement  
Current Loop to Voltage Conversion  
Automotive Fuel Injection Control  
Transmission Control  
Power Steering  
Battery Management Systems  
Typical Applications  
D
S
I
I
L
Inductive  
Load  
C
load  
G
+5V  
48V  
48V  
I
B
+
-
+5V  
+3.3V  
+
-
+
-
Charger  
D
S
G
Inductive  
Load  
24V  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
All trademarks are the property of their respective owners.  
2
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2009–2013, Texas Instruments Incorporated  
LMP8602, LMP8602Q, LMP8603, LMP8603Q  
SNOSB36D –JULY 2009–REVISED MARCH 2013  
www.ti.com  
DESCRIPTION (CONTINUED)  
The mid-rail offset adjustment pin enables the user to use these devices for bidirectional single supply voltage  
current sensing. The output signal is bidirectional and mid-rail referenced when this pin is connected to the  
positive supply rail. With the offset pin connected to ground, the output signal is unidirectional and ground-  
referenced.  
The LMP8602 and LMP8603 are available in a 8–Pin SOIC package and in a 8–Pin VSSOP package.  
The LMP8602Q and LMP8603Q incorporate enhanced manufacturing and support processes for the automotive  
market, including defect detection methodologies. Reliability qualification is compliant with the requirements and  
temperature grades defined in the AEC Q100 standard.  
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam  
during storage or handling to prevent electrostatic damage to the MOS gates.  
Absolute Maximum Ratings(1)(2)  
For input pins only  
For all other pins  
±4000V  
±2000V  
Human Body  
ESD Tolerance(3)  
Machine Model  
200V  
Charge Device Model  
1000V  
Supply Voltage (VS - GND)  
6.0V  
Continuous Input Voltage (−IN and +IN)(4)  
−22V to 60V  
−25V to 65V  
Transient (400 ms)  
Maximum Voltage at A1, A2, OFFSET and OUT Pins  
VS +0.3V and  
GND -0.3V  
Storage Temperature Range  
Junction Temperature(5)  
−65°C to 150°C  
150°C  
Mounting Temperature  
Infrared or Convection (20 sec)  
Wave Soldering Lead (10 sec)  
235°C  
260°C  
(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of  
the device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or  
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating  
Conditions indicate conditions at which the device is functional and the device should not be beyond such conditions. All voltages are  
measured with respect to the ground pin, unless otherwise specified.  
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and  
specifications.  
(3) Human Body Model per MIL-STD-883, Method 3015.7. Machine Model, per JESD22-A115-A. Field-Induced Charge-Device Model, per  
JESD22-C101-C.  
(4) For the VSSOP package, the bare board spacing at the solder pads of the package will be to small for reliable use at higher voltages  
(VCM >25V) Therefore it is strongly advised to add a conformal coating on the PCB assembled with the LMP8602 and LMP8603.  
(5) The maximum power dissipation must be derated at elevated temperatures and is dictated by TJ(MAX), θJA, and the ambient temperature,  
TA. The maximum allowable power dissipation PDMAX = (TJ(MAX) - TA) / θJA or the number given in Absolute Maximum Ratings,  
whichever is lower.  
2
Submit Documentation Feedback  
Copyright © 2009–2013, Texas Instruments Incorporated  
Product Folder Links: LMP8602 LMP8602Q LMP8603 LMP8603Q  
LMP8602, LMP8602Q, LMP8603, LMP8603Q  
www.ti.com  
SNOSB36D –JULY 2009–REVISED MARCH 2013  
Operating Ratings(1)  
Supply Voltage (VS – GND)  
Offset Voltage (Pin 7 )  
3.0V to 5.5V  
0 to VS  
Temperature Range(2)  
Package Thermal Resistance(2)  
Packaged devices  
8-Pin SOIC (θJA  
8-Pin VSSOP (θJA  
−40°C to +125°C  
190°C/W  
)
)
203°C/W  
(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of  
the device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or  
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating  
Conditions indicate conditions at which the device is functional and the device should not be beyond such conditions. All voltages are  
measured with respect to the ground pin, unless otherwise specified.  
(2) The maximum power dissipation must be derated at elevated temperatures and is dictated by TJ(MAX), θJA, and the ambient temperature,  
TA. The maximum allowable power dissipation PDMAX = (TJ(MAX) - TA) / θJA or the number given in Absolute Maximum Ratings,  
whichever is lower.  
3.3V Electrical Characteristics(1)  
Unless otherwise specified, all limits ensured at TA = 25°C, VS = 3.3V, GND = 0V, −4V ≤ VCM ≤ 27V, and RL = ∞, Offset (Pin  
7) is grounded, 10nF between VS and GND. Boldface limits apply at the temperature extremes.  
Min  
Typ  
Max  
Symbol  
Parameter  
Conditions  
Units  
(2)  
(3)  
(2)  
Overall Performance (From -IN (pin 1) and +IN (pin 8) to OUT (pin 5) with pins A1 (pin 3) and A2 (pin 4) connected)  
IS  
Supply Current  
Total Gain  
1
50  
1.3  
mA  
V/V  
LMP8602  
49.75  
99.5  
50.25  
100.5  
±20  
AV  
LMP8603  
100  
−2.7  
0.7  
Gain Drift(4)  
Slew Rate(5)  
−40°C ≤ TA ≤ 125°C  
VIN = ±0.165V  
ppm/°C  
V/μs  
kHz  
SR  
0.4  
50  
BW  
Bandwidth  
60  
VOS  
Input Offset Voltage  
Input Offset Voltage Drift(6)  
VCM = VS / 2  
0.15  
2
±1  
mV  
TCVOS  
−40°C ≤ TA ≤ 125°C  
0.1 Hz − 10 Hz, 6 Sigma  
Spectral Density, 1 kHz  
DC, 3.0V ≤ VS ≤ 3.6V, VCM = VS/2  
LMP8602  
±10  
μV/°C  
μVP-P  
nV/√Hz  
dB  
16.4  
830  
86  
en  
Input Referred Voltage Noise  
Power Supply Rejection Ratio  
PSRR  
70  
±0.25  
±1  
%
Input Referred  
±0.33  
±1.5  
mV  
Mid−scale Offset Scaling Accuracy  
LMP8603  
±0.45  
%
Input Referred  
±0.248  
mV  
Preamplifier (From input pins -IN (pin 1) and +IN (pin 8) to A1 (pin 3))  
RCM  
RDM  
VOS  
Input Impedance Common Mode  
Input Impedance Differential Mode  
Input Offset Voltage  
−4V ≤ VCM ≤ 27V  
−4V ≤ VCM ≤ 27V  
VCM = VS / 2  
250  
500  
295  
590  
±0.15  
96  
350  
700  
±1  
kΩ  
kΩ  
mV  
dB  
DC CMRR DC Common Mode Rejection Ratio  
−2V ≤ VCM ≤ 24V  
f = 1 kHz  
86  
AC Common Mode Rejection Ratio(7)  
80  
94  
AC CMRR  
dB  
V
f = 10 kHz  
85  
CMVR  
Input Common Mode Voltage Range  
for 80 dB CMRR  
−4  
27  
(1) The electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as otherwise  
modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not  
ensured.  
(2) Datasheet min/max specification limits are ensured by test.  
(3) Typical values represent the most likely parameter norms at TA = +25°C, and at the Recommended Operation Conditions at the time of  
product characterization and are not ensured.  
(4) Both the gain of the preamplifier A1V and the gain of the buffer amplifier A2V are measured individually. The over all gain of both  
amplifiers AV is also measured to assure the gain of all parts is always within the AV limits.  
(5) Slew rate is the average of the rising and falling slew rates.  
(6) Offset voltage drift determined by dividing the change in VOS at temperature extremes into the total temperature change.  
(7) AC Common Mode Signal is a 5VPP sine-wave (0V to 5V) at the given frequency.  
Copyright © 2009–2013, Texas Instruments Incorporated  
Submit Documentation Feedback  
3
Product Folder Links: LMP8602 LMP8602Q LMP8603 LMP8603Q  
LMP8602, LMP8602Q, LMP8603, LMP8603Q  
SNOSB36D –JULY 2009–REVISED MARCH 2013  
www.ti.com  
3.3V Electrical Characteristics(1) (continued)  
Unless otherwise specified, all limits ensured at TA = 25°C, VS = 3.3V, GND = 0V, −4V ≤ VCM ≤ 27V, and RL = ∞, Offset (Pin  
7) is grounded, 10nF between VS and GND. Boldface limits apply at the temperature extremes.  
Min  
Typ  
Max  
Symbol  
Parameter  
Conditions  
Units  
(2)  
(3)  
(2)  
K1  
Gain(4)  
9.95  
10.0  
100  
±5  
10.05  
101  
±50  
10  
V/V  
kΩ  
RF-INT  
Output Impedance Filter Resistor  
99  
TCRF-INT  
Output Impedance Filter Resistor Drift  
ppm/°C  
mV  
VOL  
VOH  
RL = ∞  
2
A1 VOUT  
A1 Output Voltage Swing  
3.2  
3.25  
V
Output Buffer (From A2 (pin 4) to OUT ( pin 5 )  
−2  
−2.5  
2
2.5  
VOS  
K2  
Input Offset Voltage  
Gain(4)  
0V ≤ VCM ≤ VS  
±0.5  
mV  
V/V  
LMP8602  
LMP8603  
4.975  
9.95  
5
5.025  
10.05  
10  
−40  
fA  
IB  
Input Bias Current of A2(8)  
±20  
40  
n A  
VOL  
RL = 100 kΩ  
,
LMP8602  
LMP8603  
10  
10  
mV  
V
80  
A2 VOUT  
A2 Output Voltage Swing(9)(10)  
Output Short-Circuit Current(11)  
VOH  
RL = 100 kΩ  
,
3.28  
3.29  
Sourcing, VIN = VS, VOUT = GND  
Sinking, VIN = GND, VOUT = VS  
-25  
30  
-38  
46  
-60  
65  
ISC  
mA  
(8) Positive current corresponds to current flowing into the device.  
(9) For this test input is driven from A1 stage in uni-directional mode (Offset pin connected to GND).  
(10) For VOL, RL is connected to VS and for VOH, RL is connected to GND.  
(11) Short-Circuit test is a momentary test. Continuous short circuit operation at elevated ambient temperature can result in exceeding the  
maximum allowed junction temperature of 150°C.  
5V Electrical Characteristics(1)  
Unless otherwise specified, all limits ensured for at TA = 25°C, VS = 5V, GND = 0V, −22V ≤ VCM ≤ 60V, and RL = ∞, Offset  
(Pin 7) is grounded, 10nF between VS and GND. Boldface limits apply at the temperature extremes.  
Min  
Typ  
Max  
Symbol  
Parameter  
Conditions  
Units  
(2)  
(3)  
(2)  
Overall Performance (From -IN (pin 1) and +IN (pin 8) to OUT (pin 5) with pins A1 (pin 3) and A2 (pin 4) connected)  
IS  
Supply Current  
Total Gain(4)  
1.1  
50  
1.5  
mA  
V/V  
LMP8602  
49.75  
99.5  
50.25  
100.5  
±20  
AV  
LMP8603  
100  
−2.8  
0.83  
60  
Gain Drift  
Slew Rate(5)  
−40°C ≤ TA ≤ 125°C  
VIN = ±0.25V  
ppm/°C  
V/μs  
SR  
0.6  
50  
BW  
Bandwidth  
kHz  
VOS  
Input Offset Voltage  
Input Offset Voltage Drift(6)  
0.15  
2
±1  
mV  
TCVOS  
−40°C ≤ TA ≤ 125°C  
±10  
μV/°C  
μVP-P  
nV/√Hz  
0.1 Hz − 10 Hz, 6 Sigma  
Spectral Density, 1 kHz  
17.5  
890  
eN  
Input Referred Voltage Noise  
(1) The electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as otherwise  
modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not  
ensured.  
(2) Datasheet min/max specification limits are ensured by test.  
(3) Typical values represent the most likely parameter norms at TA = +25°C, and at the Recommended Operation Conditions at the time of  
product characterization and are not ensured.  
(4) Both the gain of the preamplifier A1V and the gain of the buffer amplifier A2V are measured individually. The over all gain of both  
amplifiers AV is also measured to assure the gain of all parts is always within the AV limits.  
(5) Slew rate is the average of the rising and falling slew rates.  
(6) Offset voltage drift determined by dividing the change in VOS at temperature extremes into the total temperature change.  
4
Submit Documentation Feedback  
Copyright © 2009–2013, Texas Instruments Incorporated  
Product Folder Links: LMP8602 LMP8602Q LMP8603 LMP8603Q  
LMP8602, LMP8602Q, LMP8603, LMP8603Q  
www.ti.com  
SNOSB36D –JULY 2009–REVISED MARCH 2013  
5V Electrical Characteristics(1) (continued)  
Unless otherwise specified, all limits ensured for at TA = 25°C, VS = 5V, GND = 0V, −22V ≤ VCM ≤ 60V, and RL = ∞, Offset  
(Pin 7) is grounded, 10nF between VS and GND. Boldface limits apply at the temperature extremes.  
Min  
Typ  
Max  
Symbol  
Parameter  
Conditions  
Units  
(2)  
(3)  
(2)  
PSRR  
Power Supply Rejection Ratio  
DC 4.5V ≤ VS ≤ 5.5V  
70  
90  
dB  
%
LMP8602  
LMP8603  
±0.25  
±1  
Input Referred  
Input Referred  
±0.50  
±1.5  
mV  
%
Mid−scale Offset Scaling Accuracy  
±0.45  
±0.375  
mV  
Preamplifier (From input pins -IN (pin 1) and +IN (pin 8) to A1 (pin 3))  
0V ≤ VCM ≤ 60V  
250  
165  
500  
300  
295  
193  
590  
386  
±0.15  
105  
96  
350  
250  
700  
500  
±1  
kΩ  
kΩ  
kΩ  
kΩ  
mV  
dB  
RCM  
Input Impedance Common Mode  
−20V ≤ VCM< 0V  
0V ≤ VCM ≤ 60V  
−20V ≤ VCM < 0V  
VCM = VS / 2  
RDM  
VOS  
Input Impedance Differential Mode  
Input Offset Voltage  
DC CMRR DC Common Mode Rejection Ratio  
AC CMRR AC Common Mode Rejection Ratio(7)  
−20V ≤ VCM ≤ 60V  
f = 1 kHz  
90  
80  
dB  
f = 10 kHz  
83  
CMVR  
K1  
Input Common Mode Voltage Range  
Gain(4)  
for 80 dB CMRR  
−22  
9.95  
99  
60  
10.05  
101  
±50  
10  
V
V/V  
kΩ  
10  
100  
±5  
RF-INT  
TCRF-INT  
Output Impedance Filter Resistor  
Output Impedance Filter Resistor Drift  
ppm/°C  
mV  
VOL  
VOH  
RL = ∞  
2
A1 VOUT  
A1 Ouput Voltage Swing  
4.95  
4.985  
V
Output Buffer (From A2 (pin 4) to OUT ( pin 5 )  
−2  
−2.5  
2
2.5  
VOS  
K2  
Input Offset Voltage  
Gain(8)  
0V ≤ VCM ≤ VS  
±0.5  
mV  
V/V  
LMP8602  
LMP8603  
4.975  
9.95  
5
5.025  
10.05  
10  
−40  
fA  
IB  
Input Bias Current of A2(9)  
±20  
40  
nA  
VOL  
RL = 100 kΩ  
,
LMP8602  
LMP8603  
10  
10  
mV  
V
80  
A2 VOUT  
A2 Ouput Voltage Swing(10) (11)  
Output Short-Circuit Current(12)  
VOH  
RL = 100 kΩ  
,
4.98  
4.99  
Sourcing, VIN = VS, VOUT = GND  
Sinking, VIN = GND, VOUT = VS  
–25  
30  
–42  
48  
–60  
65  
ISC  
mA  
(7) AC Common Mode Signal is a 5VPP sine-wave (0V to 5V) at the given frequency.  
(8) Both the gain of the preamplifier A1V and the gain of the buffer amplifier A2V are measured individually. The over all gain of both  
amplifiers AV is also measured to assure the gain of all parts is always within the AV limits.  
(9) Positive current corresponds to current flowing into the device.  
(10) For this test input is driven from A1 stage in uni-directional mode (Offset pin connected to GND).  
(11) For VOL, RL is connected to VS and for VOH, RL is connected to GND.  
(12) Short-Circuit test is a momentary test. Continuous short circuit operation at elevated ambient temperature can result in exceeding the  
maximum allowed junction temperature of 150°C.  
Copyright © 2009–2013, Texas Instruments Incorporated  
Submit Documentation Feedback  
5
Product Folder Links: LMP8602 LMP8602Q LMP8603 LMP8603Q  
 
LMP8602, LMP8602Q, LMP8603, LMP8603Q  
SNOSB36D –JULY 2009–REVISED MARCH 2013  
www.ti.com  
BLOCK DIAGRAM  
OFFSET  
7
V
S
6
Level shift  
+IN  
-IN  
8
1
+
5
Preamplifier  
Gain = 10  
-
Output Buffer  
Gain = K2  
OUT  
100 kW  
2
3
4
GND  
A1 A2  
Figure 1. K2 = 5 for LMP8602, K2 = 10 for LMP8603  
Connection Diagram  
1
2
8
7
-IN  
+IN  
GND  
OFFSET  
V
S
A1  
A2  
6
5
3
4
OUT  
Figure 2. 8-Pin SOIC / VSSOP  
Top View  
PIN DESCRIPTIONS  
Pin  
2
Name  
GND  
VS  
Description  
Power Ground  
Power Supply  
Inputs  
6
Positive Supply Voltage  
Negative Input  
1
−IN  
8
+IN  
Positive Input  
3
A1  
Preamplifier output  
Filter Network  
4
A2  
Input from the external filter network and / or A1  
DC Offset for bidirectional signals  
Single ended output  
Offset  
7
OFFSET  
OUT  
Output  
5
6
Submit Documentation Feedback  
Copyright © 2009–2013, Texas Instruments Incorporated  
Product Folder Links: LMP8602 LMP8602Q LMP8603 LMP8603Q  
LMP8602, LMP8602Q, LMP8603, LMP8603Q  
www.ti.com  
SNOSB36D –JULY 2009–REVISED MARCH 2013  
Typical Performance Characteristics  
Unless otherwise specified, all limits ensured for at TA = 25°C, VS = 5V, GND = 0V, −22V ≤ VCM ≤ 60V, and RL = ∞, Offset  
(Pin 7) connected to VS, 10nF between VS and GND.  
VOS vs. VCM at VS = 3.3V  
VOS vs. VCM at VS = 5V  
1.0  
0.8  
0.6  
0.4  
0.2  
0
1.0  
0.8  
0.6  
0.4  
0.2  
0
-0.2  
-0.4  
-0.6  
-0.8  
-1.0  
-0.2  
-0.4  
-0.6  
-0.8  
-1.0  
V
S
= 3.3V  
V
S
= 5V  
-4  
0
4
8
12 16 20 24 28 30  
(V)  
-20 -10  
0
10 20 30 40 50 60  
(V)  
V
CM  
V
CM  
Figure 3.  
Figure 4.  
Input Bias Current Over Temperature (+IN and −IN pins)  
Input Bias Current Over Temperature (+IN and −IN pins)  
at VS = 3.3V  
at VS = 5V  
100  
75  
200  
150  
100  
50  
50  
25  
125°C  
0
-25  
-50  
125°C  
0
-50  
-100  
-40°C  
-40°C  
10  
-10  
0
20  
30  
-30  
-10  
10  
30  
(V)  
50  
70  
V
(V)  
V
CM  
CM  
Figure 5.  
Figure 6.  
Input Bias Current Over Temperature (A2 pin)  
at VS = 5V  
Input Bias Current Over Temperature (A2 pin)  
at VS = 5V  
200  
150  
100  
100  
-40°C  
0
-100  
50  
25°C  
-200  
0
-50  
0
-300  
1
2
3
4
5
0
1
2
3
4
5
V
(V)  
CM  
V
(V)  
CM  
Figure 7.  
Figure 8.  
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Typical Performance Characteristics (continued)  
Unless otherwise specified, all limits ensured for at TA = 25°C, VS = 5V, GND = 0V, −22V ≤ VCM ≤ 60V, and RL = ∞, Offset  
(Pin 7) connected to VS, 10nF between VS and GND.  
Input Referred Voltage Noise vs. Frequency  
PSRR vs. Frequency  
1.5  
100  
80  
60  
40  
20  
0
1.2  
V
= 5V  
S
0.9  
0.6  
0.3  
0
V
= 3.3V  
S
0.1  
1
10  
100  
1k  
10k 100k  
10  
100  
1k  
10k  
100k  
FREQUENCY (Hz)  
FREQUENCY (Hz)  
Figure 9.  
Figure 10.  
Gain vs. Frequency LMP8602  
Gain vs. Frequency LMP8603  
40  
50  
30  
20  
40  
30  
20  
10  
0
10  
0
-10  
-20  
-30  
-40  
-10  
-20  
-30  
V
V
= 3.3V, 5V  
S
V
V
= 3.3V, 5V  
S
= V /2  
S
OUT  
= V /2  
S
OUT  
100  
1k  
10k  
100k  
1M  
100  
1k  
10k  
100k  
1M  
FREQUENCY (Hz)  
FREQUENCY (Hz)  
Figure 11.  
Figure 12.  
CMRR vs. Frequency at VS = 3.3V  
CMRR vs. Frequency at VS = 5V  
120  
120  
100  
80  
60  
40  
20  
0
100  
80  
60  
40  
20  
0
V
= 5V  
S
V
S
= 3.3V  
100  
1k  
10k  
100k  
100  
1k  
10k  
100k  
FREQUENCY (Hz)  
FREQUENCY (Hz)  
Figure 13.  
Figure 14.  
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Typical Performance Characteristics (continued)  
Unless otherwise specified, all limits ensured for at TA = 25°C, VS = 5V, GND = 0V, −22V ≤ VCM ≤ 60V, and RL = ∞, Offset  
(Pin 7) connected to VS, 10nF between VS and GND.  
Step Response at VS = 3.3V  
Step Response at VS = 5V  
RL = 10kΩ LMP8602  
RL = 10kΩ LMP8602  
TIME (20 ms/DIV)  
TIME (20 ms/DIV)  
Figure 15.  
Figure 16.  
Settling Time (Falling Edge) at VS = 3.3V  
LMP8602  
Settling Time (Falling Edge) at VS = 5V  
LMP8602  
TIME (5 ms/DIV)  
TIME (5 us/DIV)  
Figure 17.  
Figure 18.  
Settling Time (Rising Edge) at VS = 3.3V  
LMP8602  
Settling Time (Rising Edge) at VS = 5V  
LMP8602  
TIME (5 ms/DIV)  
TIME (5 us/DIV)  
Figure 19.  
Figure 20.  
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Typical Performance Characteristics (continued)  
Unless otherwise specified, all limits ensured for at TA = 25°C, VS = 5V, GND = 0V, −22V ≤ VCM ≤ 60V, and RL = ∞, Offset  
(Pin 7) connected to VS, 10nF between VS and GND.  
Step Response at VS = 3.3V  
Step Response at VS = 5V  
RL = 10kΩ LMP8603  
RL = 10kΩ LMP8603  
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
TIME (20 us/DIV)  
TIME (20 us/DIV)  
Figure 21.  
Figure 22.  
Settling Time (Falling Edge) at VS = 3.3V  
LMP8603  
Settling Time (Falling Edge) at VS = 5V  
LMP8603  
TIME (5 us/DIV)  
TIME (5 us/DIV)  
Figure 23.  
Figure 24.  
Settling Time (Rising Edge) at VS = 3.3V  
LMP8603  
Settling Time (Rising Edge) at VS = 5V  
LMP8603  
TIME (5 us/DIV)  
TIME (5 us/DIV)  
Figure 25.  
Figure 26.  
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Typical Performance Characteristics (continued)  
Unless otherwise specified, all limits ensured for at TA = 25°C, VS = 5V, GND = 0V, −22V ≤ VCM ≤ 60V, and RL = ∞, Offset  
(Pin 7) connected to VS, 10nF between VS and GND.  
Positive Swing vs. RLOAD at VS = 3.3V  
Positive Swing vs. RLOAD VS = 5V  
3.30  
3.28  
3.26  
3.24  
3.22  
3.20  
5.00  
4.98  
4.96  
4.94  
4.92  
4.90  
4.88  
1k  
10k  
100k  
1
10k  
100k  
LOAD RESISTANCE (ꢀ)  
LOAD RESISTANCE (ꢀ)  
Figure 27.  
Figure 28.  
Negative Swing vs. RLOAD at VS = 3.3V  
Negative Swing vs. RLOAD at VS = 5V  
60  
50  
40  
30  
20  
10  
0
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
1k  
10k  
100k  
1k  
10k  
100k  
LOAD RESISTANCE (ꢀ)  
LOAD RESISTANCE (ꢀ)  
Figure 29.  
Figure 30.  
Gain Drift Distribution LMP8602  
5000 parts  
Gain Drift Distribution LMP8603  
5000 parts  
20  
15  
10  
5
15  
12  
9
6
3
0
0
-10 -8 -6 -4 -2  
0
2
4
6
8
10  
-10 -8 -6 -4 -2  
0
2
4
6
8
10  
GAIN DRIFT (ppm/°C)  
GAIN DRIFT (ppm/°C)  
Figure 31.  
Figure 32.  
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Typical Performance Characteristics (continued)  
Unless otherwise specified, all limits ensured for at TA = 25°C, VS = 5V, GND = 0V, −22V ≤ VCM ≤ 60V, and RL = ∞, Offset  
(Pin 7) connected to VS, 10nF between VS and GND.  
Gain error Distribution at VS = 3.3V LMP8602  
Gain error Distribution at VS = 3.3V LMP8603  
5000 parts  
5000 parts  
20  
15  
10  
5
20  
15  
10  
5
0
0
-0.50  
-0.25  
0.00  
0.25  
0.50  
-10 -8 -6 -4 -2  
0
2
4
6
8
10  
GAIN DRIFT (ppm/°C)  
GAIN ERROR (%)  
Figure 33.  
Figure 34.  
Gain error Distribution at VS = 5V LMP8602  
5000 parts  
Gain error Distribution at VS = 5V LMP8603  
5000 parts  
20  
20  
15  
10  
5
15  
10  
5
0
0
-0.50  
-0.25  
0.00  
0.25  
0.50  
-10 -8 -6 -4 -2  
0
2
4
6
8
10  
GAIN DRIFT (ppm/°C)  
GAIN ERROR (%)  
Figure 35.  
Figure 36.  
CMRR Distribution at VS = 3.3V  
5000 parts  
CMRR Distribution at VS = 5V  
5000 parts  
30  
25  
20  
15  
10  
5
30  
25  
20  
15  
10  
5
0
0
80  
90  
100  
110  
120  
130  
140  
80  
90  
100  
110  
120  
130  
140  
CMRR (dB)  
CMRR (dB)  
Figure 37.  
Figure 38.  
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Typical Performance Characteristics (continued)  
Unless otherwise specified, all limits ensured for at TA = 25°C, VS = 5V, GND = 0V, −22V ≤ VCM ≤ 60V, and RL = ∞, Offset  
(Pin 7) connected to VS, 10nF between VS and GND.  
VOS Distribution at VS = 3.3V  
VOS Distribution at VS = 5V  
5000 parts  
5000 parts  
35  
30  
25  
20  
15  
10  
5
35  
30  
25  
20  
15  
10  
5
0
0
-1.0  
-0.6  
-0.2  
V
0
0.2  
0.6  
1.0  
-1.0  
-0.6  
-0.2  
V
0
0.2  
0.6  
1.0  
(mV)  
(mV)  
OS  
OS  
Figure 39.  
Figure 40.  
TCVOS Distribution  
5000 parts  
30  
25  
20  
15  
10  
5
0
-10 -8 -6 -4 -2  
TCV  
0
2
4
6
8
10  
(éV/°C)  
OS  
Figure 41.  
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APPLICATION INFORMATION  
GENERAL  
The LMP8602 and LMP8603 are fixed gain differential voltage precision amplifiers with a gain of 50x for the  
LMP8602, and 100x for the LMP8603. The input common mode voltage range is -22V to +60V when operating  
from a single 5V supply or -4V to +27V input common mode voltage range when operating from a single 3.3V  
supply. The LMP8602 and LMP8603 are members of the LMP family and are ideal parts for unidirectional and  
bidirectional current sensing applications. Because of the proprietary chopping level-shift input stage the  
LMP8602 and LMP8603 achieve very low offset, very low thermal offset drift, and very high CMRR. The  
LMP8602 and LMP8603 will amplify and filter small differential signals in the presence of high common mode  
voltages.  
The LMP8602/LMP8602Q/LMP8603/LMP8603Q use level shift resistors at the inputs. Because of these  
resistors, the LMP8602/LMP8602Q/LMP8603/LMP8603Q can easily withstand very large differential input  
voltages that may exist in fault conditions where some other less protected high-performance current sense  
amplifiers might sustain permanent damage.  
PERFORMANCE GUARANTIES  
To guaranty the high performance of the LMP8602/LMP8602Q/LMP8603/LMP8603Q, all minimum and maximum  
values shown in the parameter tables of this datasheet are 100% tested where all bold limits are also 100%  
tested over temperature.  
THEORY OF OPERATION  
The schematic shown in Figure 42 gives a schematic representation of the internal operation of the  
LMP8602/LMP8603.  
The signal on the input pins is typically a small differential voltage across a current sensing shunt resistor. The  
input signal may appear at a high common mode voltage. The input signals are accessed through two input  
resistors. The proprietary chopping level-shift current circuit pulls or pushes current through the input resistors to  
bring the common mode voltage behind these resistors within the supply rails. Subsequently, the signal is gained  
up by a factor of 10 (K1) and brought out on the A1 pin through a trimmed 100 kΩ resistor. In the application,  
additional gain adjustment or filtering components can be added between the A1 and A2 pins as will be  
explained in subsequent sections. The signal on the A2 pin is further amplified by a factor (K2) which equals a  
factor of 5 for the LMP8602 and a factor of 10 for the LMP8603. The output signal of the final gain stage is  
provided on the OUT pin. The OFFSET pin allows the output signal to be level-shifted to enable bidirectional  
current sensing as will be explained below.  
OFFSET  
V
S
7
6
Level shift  
+IN  
-IN  
8
1
+
5
Preamplifier  
Gain = 10  
-
Output Buffer  
Gain = K2  
OUT  
100 kW  
2
3
4
GND  
A1 A2  
K2 = 5 for LMP8602, K2 = 10 for LMP8603  
Figure 42. Theory of Operation  
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ADDITIONAL SECOND ORDER LOW PASS FILTER  
The LMP8602/LMP8602Q/LMP8603/LMP8603Q has a third order Butterworth low-pass characteristic with a  
typical bandwidth of 60 kHz integrated in the preamplifier stage of the part. The bandwidth of the output buffer  
can be reduced by adding a capacitor on the A1 pin to create a first order low pass filter with a time constant  
determined by the 100 kΩ internal resistor and the external filter capacitor.  
It is also possible to create an additional second order Sallen-Key low pass filter as shown in Figure 43 by  
adding external components R2, C1 and C2. Together with the internal 100 kΩ resistor R1, this circuit creates a  
second order low-pass filter characteristic.  
OFFSET  
7
8
IN  
IN  
+
5
Level  
shift  
Output Buffer  
Gain = K2  
Preamplifier  
Gain = K1  
-
OUT  
1
Internal  
R
1
100 kW  
3
4
A1  
A2  
R
2
C
1
C
2
K1 = 10, K2 = 5 for LMP8602, K2 = 10 for LMP8603  
Figure 43. Second Order Low Pass Filter  
When the corner frequency of the additional filter is much lower than 60 kHz, the transfer function of the  
described amplifier can be written as:  
1
K1 * K2  
R1R2C1C2  
H(s) =  
(1 - K2)  
1
1
s2 + s *  
+
+
1
+
R1C2 R2C2  
R2C1  
R1R2C1C2  
where  
•
•
K1 equals the gain of the preamplifier  
K2 that of the buffer amplifier  
(1)  
The above equation can be written in the normalized frequency response for a 2nd order low pass filter:  
K2  
G(jw) = K1 *  
(jw)2  
wo  
jw  
+
+ 1  
2
Qwo  
(2)  
(3)  
The Cutt-off frequency ωo in rad/sec (divide by 2π to get the cut-off frequency in Hz) is given by:  
1
wo =  
R1R2C1C2  
And the quality factor of the filter is given by:  
R1R2C1C2  
Q =  
R1C1 + R2C1 + (1 - K2) * R1C2  
(4)  
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For any filter gain K > 1x, the design procedure can be very simple if the two capacitors are chosen to in a  
certain ratio.  
C1  
C2 =  
K2 - 1  
(5)  
Inserting this in the above equation for Q results in:  
2
C1  
R1R2  
K2 - 1  
Q =  
(K2 - 1)R1C1  
R1C1 + R2C1 -  
K2 - 1  
(6)  
Which results in:  
2
R1R2  
K2 - 1  
R2  
C1  
R1R2  
K2 - 1  
Q =  
=
C1R2  
(7)  
In this case, given the predetermined value of R1 = 100 kΩ (the internal resistor), the quality factor is set solely  
by the value of the resistor R2.  
R2 can be calculated based on the desired value of Q as the first step of the design procedure with the following  
equation:  
R1  
R2  
=
2
(
)
-
K 1 Q  
(8)  
For the gain of 5 for the LMP8602 this results in:  
R1  
R2 =  
4Q2  
(9)  
For the gain of 10 for the LMP8603 this is:  
R1  
R2 =  
9Q2  
(10)  
For instance, the value of Q can be set to 0.5√2 to create a Butterworth response, to 1/√3 to create a Bessel  
response, or a 0.5 to create a critically damped response. Once the value of R2 has been found, the second and  
last step of the design procedure is to calculate the required value of C to give the desired low-pass cut-off  
frequency using:  
(K2 - 1)Q  
C1 =  
R1w0  
(11)  
Which for the gain = 5 will give:  
4Q  
C1 =  
R1w0  
(12)  
and for the gain = 10:  
9Q  
C1 =  
R1w0  
(13)  
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For C2 the value is calculated with:  
C1  
C2 =  
K2 - 1  
(14)  
Or for a gain = 5:  
C1  
C2 =  
4
(15)  
(16)  
and for a gain = 10:  
C1  
C2 =  
9
Note that the frequency response achieved using this procedure will only be accurate if the cut-off frequency of  
the second order filter is much smaller than the intrinsic 60 kHz low-pass filter. In other words, to have the  
frequency response of the LMP8602/LMP8602Q/LMP8603/LMP8603Q circuit chosen such that the internal poles  
do not affect the external second order filter.  
For a desired Q = 0.707 and a cut off frequency = 3 kHz, this will result for the LMP8602 in rounded values for  
R2 = 51 kΩ, C1 = 1.5 nF and C2 = 3.9 nF  
And for the LMP8603 this will result in rounded values for R2 = 22 kΩ, C1 = 3.3 nF and C2 = 0.39 nF  
GAIN ADJUSTMENT  
The gain of the LMP8602 is 50 and the gain of the LMP8603 is 100, however, this gain can be adjusted as the  
signal path in between the two internal amplifiers is available on the external pins.  
Reduce Gain  
Figure 44 shows the configuration that can be used to reduce the gain of the LMP8602 and the LMP8603 in  
unidirectional sensing applications.  
OFFSET  
7
+IN  
-IN  
8
1
+
5
OUT  
Level  
shift  
Preamplifier  
Output Buffer  
Gain = K2  
Gain = 10  
-
Internal  
Resistor  
100 kW  
3
4
A2  
A1  
R
r
Figure 44. Reduce Gain for Unidirectional Application  
Rr creates a resistive divider together with the internal 100 kΩ resistor such that, for the LMP8602, the reduced  
gain Gr becomes:  
50 Rr  
Gr =  
Rr + 100 kW  
(17)  
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For the LMP8603:  
100 Rr  
Gr =  
Rr + 100 kW  
(18)  
Given a desired value of the reduced gain Gr, using this equation the required value for Rr can be calculated for  
the LMP8602 with:  
Gr  
Rr = 100 kW X  
50 - Gr  
(19)  
and for the LMP8603 with:  
Gr  
100 - Gr  
Rr = 100 kW x  
(20)  
Figure 45 shows the configuration that can be used to reduce the gain of the LMP8602 and the LMP8603 in  
bidirectional sensing applications. The required value for Rr can be calculated with the equations above. The  
maximum mid-scale offset scaling accuracy of the LMP8602 is ±1% and the maximum mid-scale offset scaling  
accuracy of the LMP8603 is ±1.5%. The pair of resistors selected have to match much better than 1% and 1.5%  
to prevent a significant error contribution to the offset voltage.  
OFFSET  
7
+IN  
-IN  
8
1
+
5
OUT  
Level  
shift  
Preamplifier  
Gain = 10  
Output Buffer  
Gain = K2  
-
Internal  
Resistor  
100 kW  
3
4
A2  
A1  
V
= OFFSET  
X
2R  
r
2R  
r
Figure 45. Reduce Gain for Bidirectional Application  
Increase Gain  
Figure 46 shows the configuration that can be used to increase the gain of the LMP8602/ LMP8602Q/ LMP8603/  
LMP8603Q.  
Ri creates positive feedback from the output pin to the input of the buffer amplifier. The positive feedback  
increases the gain. The increased gain Gi for the LMP8602 becomes:  
50 Ri  
Gi =  
Ri - 400 kW  
(21)  
and for the LMP8603:  
100 Ri  
Gi =  
Ri - 900 kW  
(22)  
From this equation, for a desired value of the gain, the required value of Ri can be calculated for the LMP8602  
with:  
Gi  
Ri = 400 kW X  
Gi - 50  
(23)  
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and for the LMP8603 with:  
Gi  
Ri = 900 kW x  
Gi - 100  
(24)  
It should be noted from the equation for the gain Gi that for large gains Ri approaches 100 kΩ x (K2 - 1). In this  
case, the denominator in the equation becomes close to zero. In practice, for large gains the denominator will be  
determined by tolerances in the values of the external resistor Ri and the internal 100 kΩ resistor, and the K2  
gain error. In this case, the gain becomes very inaccurate. If the denominator becomes equal to zero, the system  
will even become unstable. It is recommended to limit the application of this technique to gain increases of a  
factor 2.5 or smaller.  
OFFSET  
7
+IN  
-IN  
8
1
+
5
Level  
shift  
OUT  
Output Buffer  
Gain = K2  
Preamplifier  
Gain = 10  
-
Internal  
Resistor  
100 kW  
3
4
A2  
A1  
R
i
Figure 46. Increase Gain  
BIDIRECTIONAL CURRENT SENSING  
The signal on the A1 and OUT pins is ground-referenced when the OFFSET pin is connected to ground. This  
means that the output signal can only represent positive values of the current through the shunt resistor, so only  
currents flowing in one direction can be measured. When the offset pin is tied to the positive supply rail, the  
signal on the A1 and OUT pins is referenced to a mid-rail voltage which allows bidirectional current sensing.  
When the offset pin is connected to a voltage source, the output signal will be level shifted to that voltage divided  
by two. In principle, the output signal can be shifted to any voltage between 0 and VS/2 by applying twice that  
voltage from a low impedance source to the OFFSET pin.  
With the offset pin connected to the supply pin (VS) the operation of the amplifier will be fully bidirectional and  
symmetrical around 0V differential at the input pins. The signal at the output will follow this voltage difference  
multiplied by the gain and at an offset voltage at the output of half VS.  
Example:  
With 5V supply and a gain of 50x for the LMP8602, a differential input signal of +10 mV will result in 3.0V at the  
output pin. similarly -10 mV at the input will result in 2.0V at the output pin.  
With 5V supply and a gain of 100x for the LMP8603, a differential input signal of +10 mV will result in 3.5V at the  
(1)  
output pin. similarly -10 mV at the input will result in 1.5V at the output pin.  
POWER SUPPLY DECOUPLING  
In order to decouple the LMP8602/LMP8602Q/LMP8603/LMP8603Q from AC noise on the power supply, it is  
recommended to use a 0.1 µF bypass capacitor between the VS and GND pins. This capacitor should be placed  
as close as possible to the supply pins. In some cases an additional 10 µF bypass capacitor may further reduce  
the supply noise.  
(1) The OFFSET pin has to be driven from a very low-impedance source (<10Ω). This is because the OFFSET pin internally connects  
directly to the resistive feedback networks of the two gain stages. When the OFFSET pin is driven from a relatively large impedance  
(e.g. a resistive divider between the supply rails) accuracy will decrease.  
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SNOSB36D –JULY 2009–REVISED MARCH 2013  
www.ti.com  
LAYOUT CONSIDERATIONS  
The two input signals of the LMP8602/LMP8602Q/LMP8603/LMP8603Q are differential signals and should be  
handled as a differential pair. For optimum performance these signals should be closely together and of equal  
length. Keep all impedances in both traces equal and do not allow any other signal or ground in between the  
traces of this signals.  
The connection between the preamplifier and the output buffer amplifier is a high impedance signal due to the  
100 kΩ series resistor at the output of the preamplifier. Keep the traces at this point as short as possible and  
away from interfering signals.  
The LMP8602/LMP8602Q/LMP8603/LMP8603Q is available in a 8–Pin SOIC package and in a 8–Pin VSSOP  
package. For the VSSOP package, the bare board spacing at the solder pads of the package will be too small for  
reliable use at higher voltages (VCM > 25V) In this situation it is strongly advised to add a conformal coating on  
the PCB assembled with the LMP8602/LMP8602Q/LMP8603/LMP8603Q in VSSOP package.  
DRIVING SWITCHED CAPACITIVE LOADS  
Some ADCs load their signal source with a sample and hold capacitor. The capacitor may be discharged prior to  
being connected to the signal source. If the LMP8602/LMP8602Q/LMP8603/ LMP8603Q is driving such ADCs  
the sudden current that should be delivered when the sampling occurs may disturb the output signal. This effect  
was simulated with the circuit shown in Figure 47 where the output is connected to a capacitor that is driven by a  
rail to rail square wave.  
V
S
Output Buffer  
0V  
Figure 47. Driving Switched Capacitive Load  
This circuit simulates the switched connection of a discharged capacitor to the LMP8602/LMP8602Q/LMP8603/  
LMP8603Q output. The resulting VOUT disturbance signals are shown in Figure 48 and Figure 49.  
V
S
= 3.3V  
0.5  
0.4  
0.3  
0.2  
0.1  
0
-0.1  
-0.2  
-0.3  
-0.4  
-0.5  
100  
0
50  
150  
TIME (ns)  
200  
250  
300  
Figure 48. Capacitive Load Response at 3.3V  
20  
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www.ti.com  
SNOSB36D –JULY 2009–REVISED MARCH 2013  
V
S
= 5V  
0.4  
0.2  
0
-0.2  
-0.4  
-0.6  
-0.8  
-1.0  
0
50  
100  
150  
200  
250  
300  
TIME (ns)  
Figure 49. Capacitive Load Response at 5.0V  
These figures can be used to estimate the disturbance that will be caused when driving a switched capacitive  
load. To minimize the error signal introduced by the sampling that occurs on the ADC input, an additional RC  
filter can be placed in between the LMP8602/LMP8602Q/LMP8603/LMP8603Q and the ADC as illustrated in  
Figure 50.  
Output Buffer  
ADC  
Figure 50. Reduce Error When Driving ADCs  
The external capacitor absorbs the charge that flows when the ADC sampling capacitor is connected. The  
external capacitor should be much larger than the sample and hold capacitor at the input of the ADC and the RC  
time constant of the external filter should be such that the speed of the system is not affected.  
LOW SIDE CURRENT SENSING APPLICATION WITH LARGE COMMON MODE TRANSIENTS  
Figure 51 illustrates a low side current sensing application with a low side driver. The power transistor is pulse  
width modulated to control the average current flowing through the inductive load which is connected to a  
relatively high battery voltage. The current through the load is measured across a shunt resistor RSENSE in series  
with the load. When the power transistor is on, current flows from the battery through the inductive load, the  
shunt resistor and the power transistor to ground. In this case, the common mode voltage on the shunt is close  
to ground. When the power transistor is off, current flows through the inductive load, through the shunt resistor  
and through the freewheeling diode. In this case the common mode voltage on the shunt is at least one diode  
voltage drop above the battery voltage. Therefore, in this application the common mode voltage on the shunt is  
varying between a large positive voltage and a relatively low voltage. Because the large common mode voltage  
range of the LMP8602/LMP8603 and because of the high AC common mode rejection ratio, the  
LMP8602/LMP8603 is very well suited for this application.  
For this application the following example can be used for the calculation of the output signal:  
When using a sense resistor, RSENSE, of 0.01 Ω and a current of 1A, then the output voltage at the input pins of  
the LMP8602 is: RSENSE * ILOAD = 0.01 Ω * 1A = 0.01V  
With the gain of 50 for the LMP8602 this will give an output of 0.5V. Or in other words, VOUT = 0.5V/A.  
For the LMP8603 the calculation is similar, but with a gain of 100, giving an output of 1 V/A.  
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SNOSB36D –JULY 2009–REVISED MARCH 2013  
www.ti.com  
OFFSET  
7
INDUCTIVE  
LOAD  
+IN  
8
1
+
5
Level  
shift  
OUT  
Output Buffer  
Gain = K2  
Preamplifier  
R
SENSE  
Gain = 10  
-
24V  
Internal  
Resistor  
100 kW  
-IN  
3
4
A2  
A1  
POWER  
SWITCH  
C1  
Figure 51. Low Side Current Sensing Application with Large Common Mode Transients  
HIGH SIDE CURRENT SENSING APPLICATION WITH NEGATIVE COMMON MODE TRANSIENTS  
Figure 52 illustrates the application of the LMP8602/LMP8603 in a high side sensing application. This application  
is similar to the low side sensing discussed above, except in this application the common mode voltage on the  
shunt drops below ground when the driver is switched off. Because the common mode voltage range of the  
LMP8602/LMP8603 extends below the negative rail, the LMP8602/LMP8603 is also very well suited for this  
application.  
OFFSET  
POWER  
7
SWITCH  
+IN  
-IN  
8
1
24V  
+
5
Level  
shift  
OUT  
Output Buffer  
Gain = K2  
Preamplifier  
R
SENSE  
Gain = 10  
-
Internal  
Resistor  
100 kW  
INDUCTIVE  
LOAD  
3
4
A2  
A1  
C1  
Figure 52. High Side Current Sensing Application with Negative Common Mode Transients  
22  
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LMP8602, LMP8602Q, LMP8603, LMP8603Q  
www.ti.com  
SNOSB36D –JULY 2009–REVISED MARCH 2013  
BATTERY CURRENT MONITOR APPLICATION  
This application example shows how the LMP8602/LMP8603 can be used to monitor the current flowing in and  
out a battery pack. The fact that the LMP8602/LMP8603 can measure small voltages at a high offset voltage  
outside the parts own supply range makes this part a very good choice for such applications. If the load current  
of the battery is higher then the charging current, the output voltage of the LMP8602/LMP8603 will be above the  
“half offset voltage” for a net current flowing out of the battery. When the charging current is higher then the load  
current the output will be below this “half offset voltage”.  
I
I
Charge  
Load  
LOAD  
Charger  
V
S
OFFSET  
I
- I  
Charge Load  
7
+IN  
-IN  
8
1
+
5
Level  
shift  
OUT  
Output Buffer  
Gain = K2  
Preamplifier  
R
SENSE  
Gain = 10  
-
Internal  
Resistor  
100 kW  
3
4
A2  
A1  
C1  
Figure 53. Battery Current Monitor Application  
ADVANCED BATTERY CHARGER APPLICATION  
The above circuit can be used to realize an advanced battery charger that has the capability to monitor the exact  
net current that flows in and out the battery as show in Figure 54. The output signal of the  
LMP8602/LMP8602Q/LMP8603/LMP8603Q is digitized with the A/D converter and used as an input for the  
charge controller. The charge controller can be used to regulate the charger circuit to deliver exactly the current  
that is required by the load, avoiding overcharging a fully loaded battery.  
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SNOSB36D –JULY 2009–REVISED MARCH 2013  
www.ti.com  
I
Load  
LOAD  
V
S
I
- I  
OFFSET  
Charge Load  
7
+IN  
-IN  
8
I
Charge  
+
5
Level  
shift  
OUT  
Output Buffer  
Gain = K2  
Preamplifier  
Gain = 10  
A/D  
R
SENSE  
12V  
1
-
Internal  
Resistor  
100 kW  
3
4
A2  
A1  
C1  
Charge  
Controler  
Charger  
K2 = 5 for LMP8602  
K2 = 10 for LMP8603  
Figure 54. Advanced Battery Charger Application  
24  
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Product Folder Links: LMP8602 LMP8602Q LMP8603 LMP8603Q  
 
LMP8602, LMP8602Q, LMP8603, LMP8603Q  
www.ti.com  
SNOSB36D –JULY 2009–REVISED MARCH 2013  
REVISION HISTORY  
Changes from Revision C (March 2013) to Revision D  
Page  
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 24  
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Product Folder Links: LMP8602 LMP8602Q LMP8603 LMP8603Q  
PACKAGE OPTION ADDENDUM  
www.ti.com  
11-Apr-2013  
PACKAGING INFORMATION  
Orderable Device  
LMP8602MA/NOPB  
LMP8602MAX/NOPB  
LMP8602MM/NOPB  
LMP8602MME/NOPB  
LMP8602MMX/NOPB  
LMP8602QMA/NOPB  
LMP8602QMAX/NOPB  
LMP8602QMM/NOPB  
LMP8602QMME/NOPB  
LMP8602QMMX/NOPB  
LMP8603MA/NOPB  
LMP8603MAX/NOPB  
LMP8603MM/NOPB  
LMP8603MME/NOPB  
LMP8603MMX/NOPB  
LMP8603QMA/NOPB  
LMP8603QMAX/NOPB  
Status Package Type Package Pins Package  
Eco Plan Lead/Ball Finish  
MSL Peak Temp  
Op Temp (°C)  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
Top-Side Markings  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4)  
ACTIVE  
SOIC  
SOIC  
D
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
95  
Green (RoHS  
& no Sb/Br)  
CU SN  
CU SN  
CU SN  
CU SN  
CU SN  
CU SN  
CU SN  
CU SN  
CU SN  
CU SN  
CU SN  
CU SN  
CU SN  
CU SN  
CU SN  
CU SN  
CU SN  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
LMP86  
02MA  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
D
DGK  
DGK  
DGK  
D
2500  
1000  
250  
Green (RoHS  
& no Sb/Br)  
LMP86  
02MA  
VSSOP  
VSSOP  
VSSOP  
SOIC  
Green (RoHS  
& no Sb/Br)  
AN3A  
AN3A  
AN3A  
Green (RoHS  
& no Sb/Br)  
3500  
95  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
LMP86  
02QMA  
SOIC  
D
2500  
1000  
250  
Green (RoHS  
& no Sb/Br)  
LMP86  
02QMA  
VSSOP  
VSSOP  
VSSOP  
SOIC  
DGK  
DGK  
DGK  
D
Green (RoHS  
& no Sb/Br)  
AF7A  
AF7A  
AF7A  
Green (RoHS  
& no Sb/Br)  
3500  
95  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
LMP86  
03MA  
SOIC  
D
2500  
1000  
250  
Green (RoHS  
& no Sb/Br)  
LMP86  
03MA  
VSSOP  
VSSOP  
VSSOP  
SOIC  
DGK  
DGK  
DGK  
D
Green (RoHS  
& no Sb/Br)  
AP3A  
AP3A  
AP3A  
Green (RoHS  
& no Sb/Br)  
3500  
95  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
LMP86  
03QMA  
SOIC  
D
2500  
Green (RoHS  
& no Sb/Br)  
LMP86  
03QMA  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
11-Apr-2013  
Orderable Device  
Status Package Type Package Pins Package  
Eco Plan Lead/Ball Finish  
MSL Peak Temp  
Op Temp (°C)  
-40 to 125  
Top-Side Markings  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4)  
LMP8603QMM/NOPB  
LMP8603QMME/NOPB  
LMP8603QMMX/NOPB  
ACTIVE  
VSSOP  
VSSOP  
VSSOP  
DGK  
8
8
8
1000  
Green (RoHS  
& no Sb/Br)  
CU SN  
CU SN  
CU SN  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
AH7A  
ACTIVE  
ACTIVE  
DGK  
DGK  
250  
Green (RoHS  
& no Sb/Br)  
-40 to 125  
AH7A  
AH7A  
3500  
Green (RoHS  
& no Sb/Br)  
-40 to 125  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability  
information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that  
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between  
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight  
in homogeneous material)  
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4)  
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a  
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
OTHER QUALIFIED VERSIONS OF LMP8602, LMP8602-Q1, LMP8603, LMP8603-Q1 :  
Addendum-Page 2  
PACKAGE OPTION ADDENDUM  
www.ti.com  
11-Apr-2013  
Catalog: LMP8602, LMP8603  
•
Automotive: LMP8602-Q1, LMP8603-Q1  
•
NOTE: Qualified Version Definitions:  
Catalog - TI's standard catalog product  
•
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects  
•
Addendum-Page 3  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
8-Apr-2013  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
LMP8602MAX/NOPB  
LMP8602MM/NOPB  
LMP8602MME/NOPB  
LMP8602MMX/NOPB  
LMP8602QMAX/NOPB  
LMP8602QMM/NOPB  
SOIC  
VSSOP  
VSSOP  
VSSOP  
SOIC  
D
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
2500  
1000  
250  
330.0  
178.0  
178.0  
330.0  
330.0  
178.0  
178.0  
330.0  
330.0  
178.0  
178.0  
330.0  
330.0  
178.0  
178.0  
330.0  
12.4  
12.4  
12.4  
12.4  
12.4  
12.4  
12.4  
12.4  
12.4  
12.4  
12.4  
12.4  
12.4  
12.4  
12.4  
12.4  
6.5  
5.3  
5.3  
5.3  
6.5  
5.3  
5.3  
5.3  
6.5  
5.3  
5.3  
5.3  
6.5  
5.3  
5.3  
5.3  
5.4  
3.4  
3.4  
3.4  
5.4  
3.4  
3.4  
3.4  
5.4  
3.4  
3.4  
3.4  
5.4  
3.4  
3.4  
3.4  
2.0  
1.4  
1.4  
1.4  
2.0  
1.4  
1.4  
1.4  
2.0  
1.4  
1.4  
1.4  
2.0  
1.4  
1.4  
1.4  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
12.0  
12.0  
12.0  
12.0  
12.0  
12.0  
12.0  
12.0  
12.0  
12.0  
12.0  
12.0  
12.0  
12.0  
12.0  
12.0  
Q1  
Q1  
Q1  
Q1  
Q1  
Q1  
Q1  
Q1  
Q1  
Q1  
Q1  
Q1  
Q1  
Q1  
Q1  
Q1  
DGK  
DGK  
DGK  
D
3500  
2500  
1000  
250  
VSSOP  
DGK  
DGK  
DGK  
D
LMP8602QMME/NOPB VSSOP  
LMP8602QMMX/NOPB VSSOP  
3500  
2500  
1000  
250  
LMP8603MAX/NOPB  
LMP8603MM/NOPB  
LMP8603MME/NOPB  
LMP8603MMX/NOPB  
LMP8603QMAX/NOPB  
LMP8603QMM/NOPB  
SOIC  
VSSOP  
VSSOP  
VSSOP  
SOIC  
DGK  
DGK  
DGK  
D
3500  
2500  
1000  
250  
VSSOP  
DGK  
DGK  
DGK  
LMP8603QMME/NOPB VSSOP  
LMP8603QMMX/NOPB VSSOP  
3500  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
8-Apr-2013  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
LMP8602MAX/NOPB  
LMP8602MM/NOPB  
LMP8602MME/NOPB  
LMP8602MMX/NOPB  
LMP8602QMAX/NOPB  
LMP8602QMM/NOPB  
LMP8602QMME/NOPB  
LMP8602QMMX/NOPB  
LMP8603MAX/NOPB  
LMP8603MM/NOPB  
LMP8603MME/NOPB  
LMP8603MMX/NOPB  
LMP8603QMAX/NOPB  
LMP8603QMM/NOPB  
LMP8603QMME/NOPB  
LMP8603QMMX/NOPB  
SOIC  
VSSOP  
VSSOP  
VSSOP  
SOIC  
D
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
2500  
1000  
250  
367.0  
210.0  
210.0  
367.0  
367.0  
210.0  
210.0  
367.0  
367.0  
210.0  
210.0  
367.0  
367.0  
210.0  
210.0  
367.0  
367.0  
185.0  
185.0  
367.0  
367.0  
185.0  
185.0  
367.0  
367.0  
185.0  
185.0  
367.0  
367.0  
185.0  
185.0  
367.0  
35.0  
35.0  
35.0  
35.0  
35.0  
35.0  
35.0  
35.0  
35.0  
35.0  
35.0  
35.0  
35.0  
35.0  
35.0  
35.0  
DGK  
DGK  
DGK  
D
3500  
2500  
1000  
250  
VSSOP  
VSSOP  
VSSOP  
SOIC  
DGK  
DGK  
DGK  
D
3500  
2500  
1000  
250  
VSSOP  
VSSOP  
VSSOP  
SOIC  
DGK  
DGK  
DGK  
D
3500  
2500  
1000  
250  
VSSOP  
VSSOP  
VSSOP  
DGK  
DGK  
DGK  
3500  
Pack Materials-Page 2  
IMPORTANT NOTICE  
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changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest  
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms  
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Products  
Applications  
Audio  
www.ti.com/audio  
amplifier.ti.com  
dataconverter.ti.com  
www.dlp.com  
Automotive and Transportation www.ti.com/automotive  
Communications and Telecom www.ti.com/communications  
Amplifiers  
Data Converters  
DLP® Products  
DSP  
Computers and Peripherals  
Consumer Electronics  
Energy and Lighting  
Industrial  
www.ti.com/computers  
www.ti.com/consumer-apps  
www.ti.com/energy  
dsp.ti.com  
Clocks and Timers  
Interface  
www.ti.com/clocks  
interface.ti.com  
logic.ti.com  
www.ti.com/industrial  
www.ti.com/medical  
Medical  
Logic  
Security  
www.ti.com/security  
Power Mgmt  
Microcontrollers  
RFID  
power.ti.com  
Space, Avionics and Defense  
Video and Imaging  
www.ti.com/space-avionics-defense  
www.ti.com/video  
microcontroller.ti.com  
www.ti-rfid.com  
www.ti.com/omap  
OMAP Applications Processors  
Wireless Connectivity  
TI E2E Community  
e2e.ti.com  
www.ti.com/wirelessconnectivity  
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265  
Copyright © 2013, Texas Instruments Incorporated  

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