LMP8603QMA/NOPB [TI]
具有直列式滤波器功能的 AEC-Q100、-22V 至 60V、双向电流感应放大器 | D | 8 | -40 to 125;
| 型号： | LMP8603QMA/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有直列式滤波器功能的 AEC-Q100、-22V 至 60V、双向电流感应放大器 | D | 8 | -40 to 125 放大器 |
| 文件： | 总44页 (文件大小：1825K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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LMP8601, LMP8601-Q1
LMP8602, LMP8602-Q1
LMP8603, LMP8603-Q1
ZHCSFO1H –SEPTEMBER 2008–REVISED APRIL 2016
LMP860x、LMP860x-Q1 60V、双向、低侧或高侧、电压输出
电流感测放大器
1 特性
3 说明
1
•
•
•
•
•
•
•
增益 = 20x（LMP8601 和 LMP8601-Q1）
LMP8601、LMP8602、LMP8603 (LMP860x) 和
LMP8601-Q1、LMP8602-Q1、LMP8603-Q1
(LMP860x-Q1) 器件均为增益固定的精密电流感测放大
器（也称分流监测计）。当由 5V 或 3.3V 单电源供电
时，输入共模电压范围分别为 –22V 至 +60V 和 –4V
至 +27V。LMP860x 和 LMP860x-Q1 是单向和双向电
流感测 应用的理想元件。。
增益 = 50x（LMP8602 和 LMP8602-Q1）
增益 = 100x（LMP8603 和 LMP8603-Q1）
TCVOS：10μV/°C（最大值）
共模抑制比 (CMRR)：90dB（最小值）
输入偏移电压：1mV（典型值）
VS = 3.3V 时的共模电压范围 (CMVR)：-4V 至
27V
此类器件的精密增益分别为 20x （LPM8601 和
LPM8601-Q1）、50x（LPM8602 和 LPM8602-Q1）
和 100x（LPM8603 和 LPM8603-Q1），足以满足多
数目标 应用 将模数转换器 (ADC) 驱动至满量程值的要
求。固定增益在两个独立级中实现，包括增益为 10x
的前置放大器和增益为 2x（LMP8601 和 LMP8601-
Q1）、5x（LMP8602 和 LMP8602-Q1）或
•
•
•
•
•
VS = 5V 时的 CMVR：–22V 至 60V
单电源双向供电运行
所有最小和最大限值完全经过测试
符合汽车类应用的 Q1 器件
Q1 器件具有符合 ACE-Q100 标准的下列结果：
–
–
–
器件温度等级 1：环境运行温度范围为 -40°C
至 125°C
10x（LMP8603 和 LMP8603-Q1）的输出级缓冲放大
器。连接两级的路径通过两引脚引出，支持选择使用附
加滤波器网络或修改增益。
器件温度等级 0：-40°C 至 150°C（仅限
LMP8601EDRQ1）
器件人体模型 (HBM) 静电放电 (ESD) 分类等级
2
偏移输入引脚允许此类器件执行单向或双向单电源电压
电流感测。
（输入电流为 3A）
–
–
器件带电器件模型 (CDM) ESD 分类等级 C6
器件机器模型 (MM) ESD 分类等级 M2
LMP860x-Q1 器件采用增强型制造与支持工艺，适用
于汽车市场，符合 AEC-Q100 标准。
2 应用
器件信息(1)
•
•
•
•
•
•
•
高侧和低侧驱动器配置电流感测
器件型号
封装
封装尺寸（标称值）
双向电流测量
电压转换的电流循环
汽车喷油控制
传动控制
LMP860x
SOIC (8)
4.90mm x 3.91mm
LMP860x-Q1
LMP8602、LMP8603
LMP8602-Q1、LMP8603-Q1
VSSOP (8) 3.00mm × 3.00mm
电动助力转向
电池管理系统
(1) 要了解所有可用封装，请参见数据表末尾的封装选项附录。
典型 应用
D
I
I
L
Inductive
Load
C
load
G
+5V
48V
48V
I
B
+
-
+5V
S
+3.3V
+
-
+
-
Charger
D
S
G
Inductive
Load
24V
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SNOSAR2
LMP8601, LMP8601-Q1
LMP8602, LMP8602-Q1
LMP8603, LMP8603-Q1
ZHCSFO1H –SEPTEMBER 2008–REVISED APRIL 2016
www.ti.com.cn
目录
7.3 Feature Description................................................. 19
7.4 Device Functional Modes........................................ 22
Application and Implementation ........................ 26
8.1 Application Information............................................ 26
8.2 Typical Applications ............................................... 26
Power Supply Recommendations...................... 31
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings: LMP860x ............................................ 4
6.3 ESD Ratings: LMP860x-Q1 ...................................... 4
6.4 Recommended Operating Conditions....................... 4
6.5 Thermal Information.................................................. 5
6.6 Electrical Characteristics: VS = 3.3 V........................ 5
6.7 Electrical Characteristics: VS = 5 V........................... 7
6.8 Typical Characteristics.............................................. 9
Detailed Description ............................................ 18
7.1 Overview ................................................................. 18
7.2 Functional Block Diagram ....................................... 18
8
9
10 Layout................................................................... 31
10.1 Layout Guidelines ................................................. 31
10.2 Layout Example .................................................... 31
11 器件和文档支持 ..................................................... 32
11.1 器件支持................................................................ 32
11.2 相关链接................................................................ 32
11.3 社区资源................................................................ 32
11.4 商标....................................................................... 32
11.5 静电放电警告......................................................... 32
11.6 Glossary................................................................ 32
12 机械、封装和可订购信息....................................... 32
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision G (July 2015) to Revision H
Page
•
•
•
•
•
•
•
•
•
•
•
已添加新温度等级 0 型号 LMP8601-Q1 ................................................................................................................................. 1
已将 LMP8602、LMP8602-Q1、LMP8603 和 LMP8603-Q1 器件及相关信息添加至数据表 ................................................. 1
已更改特性要点....................................................................................................................................................................... 1
已更改 说明部分...................................................................................................................................................................... 1
Added new values to Thermal Information table.................................................................................................................... 5
Changed RθJA value in Thermal Information table.................................................................................................................. 5
Deleted previous Note 1 from Electrical Characteristics tables.............................................................................................. 5
Changed all AV1 to K1 throughout data sheet for consistency.............................................................................................. 6
Changed all AV2 to K2 throughout data sheet for consistency.............................................................................................. 6
Deleted previous Note 1 from Electrical Characteristics tables.............................................................................................. 7
已删除相关文档部分；SNOSB36 数据表内容现与本数据表合并 ......................................................................................... 32
Changes from Revision F (January 2014) to Revision G
Page
•
已添加 ESD 额定值表以及引脚配置和功能，特性 描述，器件功能模式，应用和实施，电源相关建议，布局，器件和
文档支持以及机械、封装和可订购信息部分。........................................................................................................................ 1
Changes from Revision E (March 2013) to Revision F
Page
•
Added four typical curves ..................................................................................................................................................... 17
Changes from Revision D (October 2009) to Revision E
Page
•
Changed layout of National Data Sheet to TI format ........................................................................................................... 30
2
Copyright © 2008–2016, Texas Instruments Incorporated
LMP8601, LMP8601-Q1
LMP8602, LMP8602-Q1
LMP8603, LMP8603-Q1
www.ti.com.cn
ZHCSFO1H –SEPTEMBER 2008–REVISED APRIL 2016
5 Pin Configuration and Functions
D Package
8-Pin SOIC
Top View
DGK Package
8-Pin VSSOP
Top View
1
2
8
7
1
2
-IN
-IN
8
7
+IN
+IN
GND
GND
OFFSET
OFFSET
V
S
V
S
A1
A2
6
5
A1
A2
3
4
3
4
6
5
OUT
OUT
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
A1
NO.
3
O
I
Preamplifier output
A2
4
Input from the external filter network and, or A1
Power ground
GND
+IN
2
P
I
8
Positive input
-IN
1
I
Negative input
OFFSET
OUT
VS
7
I
DC offset for bidirectional signals
Single-ended output
5
O
P
6
Positive supply voltage
Copyright © 2008–2016, Texas Instruments Incorporated
3
LMP8601, LMP8601-Q1
LMP8602, LMP8602-Q1
LMP8603, LMP8603-Q1
ZHCSFO1H –SEPTEMBER 2008–REVISED APRIL 2016
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–22
MAX
6
UNIT
Supply voltage (VS – GND)
V
V
V
V
Continuous input voltage (–IN and +IN)
Transient (400 ms)
60
–25
65
Maximum voltage at A1, A2, OFFSET and OUT pins
VS + 0.3
–40
GND – 0.3
150
LMP8601EDRQ1 only
Operating temperature, TA
°C
°C
°C
°C
All other devices
–40
125
Junction temperature(2)
–40
150
Infrared or convection (20 sec)
Mounting temperature
235
Wave soldering lead (10 sec)
260
Storage temperature, Tstg
–65
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The maximum power dissipation must be derated at elevated temperatures and is dictated by TJ(MAX), RθJA, and the ambient
temperature, TA. The maximum allowable power dissipation PDMAX = (TJ(MAX) – TA) / RθJA or the number given in Absolute Maximum
Ratings, whichever is lower.
6.2 ESD Ratings: LMP860x
VALUE
±2000
±4000
±1000
±200
UNIT
All pins except 1 and 8
Pins 1 and 8
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Electrostatic
discharge
V(ESD)
V
Machine model
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 ESD Ratings: LMP860x-Q1
VALUE
±2000
±4000
±1000
±200
UNIT
All pins except 1 and 8
Human body model (HBM), per AEC Q100-002(1)
Pins 1 and 8
Electrostatic
discharge
V(ESD)
V
Charged-device model (CDM), per AEC Q100-011
Machine model
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
3
MAX
UNIT
Supply voltage (VS – GND)
OFFSET voltage (Pin 7)
5.5
VS
V
V
0
LMP8601EDRQ1 only
All other devices
–40
–40
150
125
(1)
Operating temperature, TA
°C
(1) The maximum power dissipation must be derated at elevated temperatures and is dictated by TJ(MAX), RθJA, and the ambient
temperature, TA. The maximum allowable power dissipation PDMAX = (TJ(MAX) – TA) / RθJA or the number given in Absolute Maximum
Ratings, whichever is lower.
4
Copyright © 2008–2016, Texas Instruments Incorporated
LMP8601, LMP8601-Q1
LMP8602, LMP8602-Q1
LMP8603, LMP8603-Q1
www.ti.com.cn
ZHCSFO1H –SEPTEMBER 2008–REVISED APRIL 2016
6.5 Thermal Information
LMP8602,
LMP860x,
LMP860x-Q1
LMP8602-Q1,
LMP8603,
THERMAL METRIC(1)
UNIT
LMP8603-Q1
D (SOIC)
8 PINS
113.1
57.3
DGK (VSSOP)
8 PINS
171.1
64.1
RθJA
Junction-to-ambient thermal resistance(2)
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
53.5
91.1
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
11.1
9.4
ψJB
53.0
89.7
RθJC(bot)
N/A
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(2) The maximum power dissipation must be derated at elevated temperatures and is dictated by TJ(MAX), RθJA, and the ambient
temperature, TA. The maximum allowable power dissipation PDMAX = (TJ(MAX) – TA) / RθJA or the number given in Absolute Maximum
Ratings, whichever is lower.
6.6 Electrical Characteristics: VS = 3.3 V
at TA = 25°C, VS = 3.3 V, GND = 0 V, –4 V ≤ VCM ≤ 27 V, RL = ∞, OFFSET (pin 7) is grounded, and 10 nF between VS and
GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN(1)
TYP(2)
MAX(1)
UNIT
mA
OVERALL PERFORMANCE (FROM -IN (PIN 1) AND +IN (PIN 8) TO OUT (PIN 5) WITH PINS A1 (PIN 3) AND A2 (PIN 4) CONNECTED)
1
IS
Supply current
Total gain
Over full temperature range
LMP8601, LMP8601-Q1
LMP8602, LMP8602-Q1
LMP8603, LMP8603-Q1
Over full temperature range
VIN = ±0.165 V
0.6
19.9
1.3
20.1
20
50
AV
49.75
99.5
50.25
100.5
V/V
100
–2.7
0.7
60
Gain Drift(3)
Slew rate(4)
±20 ppm/°C
V/μs
SR
0.4
50
BW
Bandwidth
kHz
VOS
Input offset voltage
Input offset voltage drift(5)
VCM = VS / 2
0.15
2
±1
mV
TCVOS
Over full temperature range
0.1 Hz - 10 Hz, 6 sigma
Spectral density, 1 kHz
±10
μV/°C
μVP-P
16.4
830
86
en
Input-referred voltage noise
Power-supply rejection ratio
nV/√Hz
3.0 V ≤ VS ≤ 3.6 V,
DC, VCM = VS/2
PSRR
dB
Over full temperature range
70
±0.15%
±0.25%
±0.45%
±0.5%
±0.413
±1%
LMP8601,
LMP8601-Q1
Input referred
Input referred
Input referred
mV
mV
mV
LMP8602,
LMP8602-Q1
Midscale offset scaling accuracy
±0.33
±1.5%
±0.248
LMP8603,
LMP8603-Q1
(1) Data sheet min and max limits are specified by test.
(2) Typical values represent the most likely parameter norms at TA = 25°C, and at the Recommended Operation Conditions at the time of
product characterization.
(3) Both the gain of preamplifier K1 and the gain of buffer amplifier K2 are measured individually. The overall gain of both amplifiers (AV) is
also measured to assure the gain of all parts is always within the AV limits.
(4) Slew rate is the average of the rising and falling slew rates.
(5) Offset voltage drift determined by dividing the change in VOS at temperature extremes into the total temperature change.
Copyright © 2008–2016, Texas Instruments Incorporated
5
LMP8601, LMP8601-Q1
LMP8602, LMP8602-Q1
LMP8603, LMP8603-Q1
ZHCSFO1H –SEPTEMBER 2008–REVISED APRIL 2016
www.ti.com.cn
Electrical Characteristics: VS = 3.3 V (continued)
at TA = 25°C, VS = 3.3 V, GND = 0 V, –4 V ≤ VCM ≤ 27 V, RL = ∞, OFFSET (pin 7) is grounded, and 10 nF between VS and
GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN(1)
TYP(2)
295
MAX(1)
UNIT
PREAMPLIFIER (FROM INPUT PINS -IN, (PIN 1) AND +IN (PIN 8) TO A1 (PIN 3))
RCM
Input impedance common mode
–4 V ≤ VCM ≤ 27 V
kΩ
Over full temperature range
Over full temperature range
250
500
350
590
RDM
Input impedance differential mode
Input offset voltage
–4 V ≤ VCM ≤ 27 V
VCM = VS / 2
kΩ
mV
dB
700
±1
VOS
±0.15
96
DC CMRR
DC common-mode rejection ratio
–2 V ≤ VCM ≤ 24 V
Over full temperature range
Over full temperature range
86
80
f = 1 kHz
94
85
AC CMRR
AC common-mode rejection ratio(6)
dB
f = 10 kHz
CMVR
K1
Input common-mode voltage range
Preamplifier gain(3)
for 80-dB CMRR
–4
27
V
9.95
10.0
100
10.05
V/V
RF-INT
Output impedance filter resistor
–40°C ≤ TA ≤ 125°C
99
97
101
103
kΩ
–40°C ≤ TA ≤ 150°C, LMP8601EDRQ1 only
TCRF-INT
Output impedance filter resistor drift
Over full temperature range
±5
2
±50 ppm/°C
VOL, RL = ∞
mV
10
Over full temperature range
A1 VOUT
A1 output voltage swing
3.25
±0.5
VOH, RL = ∞
V
Over full temperature range
3.2
OUTPUT BUFFER (FROM A2 (PIN 4) TO OUT (PIN 5 ))
–2
–2.5
2
mV
2.5
VOS
K2
IB
Input offset voltage
0V ≤ VCM ≤ VS
Over full temperature range
LMP8601, LMP8601-Q1
LMP8602, LMP8602-Q1
LMP8603, LMP8603-Q1
1.99
2
5
2.01
Output buffer gain(3)
Input bias current of A2(7)
4.975
9.95
5.025
10.05
V/V
10
–40
fA
,
Over full temperature range
LMP8601,
±20
20
nA
4
10
Over full
temperature range
LMP8601-Q1,
LMP8602,
LMP8602-Q1
VOL, RL = 100 kΩ
mV
Over full
temperature range
40
80
(9)
A2 VOUT
A2 output voltage swing(8)
10
LMP8603,
LMP8603-Q1
Over full
temperature range
3.29
VOH, RL = 100 kΩ
V
Over full temperature range
3.28
–25
30
Sourcing, VIN = VS, VOUT = GND
Sinking, VIN = GND, VOUT = VS
–38
46
–60
65
ISC
Output short-circuit current(10)
mA
(6) AC common-mode signal is a 5-VPP sine-wave (0 V to 5 V) at the given frequency.
(7) Positive current corresponds to current flowing into the device.
(8) For this test input is driven from A1 stage.
(9) For VOL, RL is connected to VS and for VOH, RL is connected to GND.
(10) Short-Circuit test is a momentary test. Continuous short circuit operation at elevated ambient temperature can result in exceeding the
maximum allowed junction temperature of 150°C.
6
Copyright © 2008–2016, Texas Instruments Incorporated
LMP8601, LMP8601-Q1
LMP8602, LMP8602-Q1
LMP8603, LMP8603-Q1
www.ti.com.cn
ZHCSFO1H –SEPTEMBER 2008–REVISED APRIL 2016
6.7 Electrical Characteristics: VS = 5 V
at TA = 25°C, VS = 5 V, GND = 0 V, –22 V ≤ VCM ≤ 60 V, RL = ∞, OFFSET (pin 7) is grounded, and 10 nF between VS and
GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN(1)
TYP(2)
MAX(1)
UNIT
mA
OVERALL PERFORMANCE (FROM -IN (PIN 1) AND +IN (PIN 8) TO OUT (PIN 5) WITH PINS A1 (PIN 3) AND A2 (PIN 4) CONNECTED)
1.1
IS
Supply current
Total gain(3)
Over full temperature range
LMP8601, LMP8601-Q1
LMP8602, LMP8602-Q1
LMP8603, LMP8603-Q1
–40°C ≤ TA ≤ 125°C
0.7
19.9
1.5
20.1
20
50
AV
49.75
99.5
50.25
100.5
V/V
100
–2.8
0.83
60
Gain drift
±20 ppm/°C
V/μs
SR
Slew rate(4)
VIN = ±0.25 V
0.6
50
BW
Bandwidth
kHz
VOS
Input offset voltage
Input offset voltage drift(5)
0.15
2
±1
mV
TCVOS
–40°C ≤ TA ≤ 125°C
±10
μV/°C
μVP-P
0.1 Hz - 10 Hz, 6 sigma
Spectral density, 1 kHz
17.5
890
90
eN
Input-referred voltage noise
Power-supply rejection ratio
nV/√Hz
4.5 V ≤ VS ≤ 5.5 V,
DC
PSRR
dB
Over full temperature range
70
±0.15%
±0.25%
±0.45%
±0.5%
±0.625
±1%
LMP8601,
LMP8601-Q1
Input-referred
Input-referred
Input-referred
mV
mV
mV
LMP8602,
LMP8602-Q1
Midscale offset scaling accuracy
±0.50
±1.5%
±0.375
LMP8603,
LMP8603-Q1
(1) Data sheet min and max limits are specified by test.
(2) Typical values represent the most likely parameter norms at TA = 25°C, and at the Recommended Operation Conditions at the time of
product characterization.
(3) Both the gain of preamplifier K1 and the gain of buffer amplifier K2 are measured individually. The overall gain of both amplifiers (AV) is
also measured to assure the gain of all parts is always within the AV limits.
(4) Slew rate is the average of the rising and falling slew rates.
(5) Offset voltage drift determined by dividing the change in VOS at temperature extremes into the total temperature change.
Copyright © 2008–2016, Texas Instruments Incorporated
7
LMP8601, LMP8601-Q1
LMP8602, LMP8602-Q1
LMP8603, LMP8603-Q1
ZHCSFO1H –SEPTEMBER 2008–REVISED APRIL 2016
www.ti.com.cn
Electrical Characteristics: VS = 5 V (continued)
at TA = 25°C, VS = 5 V, GND = 0 V, –22 V ≤ VCM ≤ 60 V, RL = ∞, OFFSET (pin 7) is grounded, and 10 nF between VS and
GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN(1)
TYP(2)
295
MAX(1)
UNIT
PREAMPLIFIER (FROM INPUT PINS -IN (PIN 1) AND +IN (PIN 8) TO A1 (PIN 3))
0 V ≤ VCM ≤ 60 V
kΩ
kΩ
kΩ
Over full temperature range
Over full temperature range
Over full temperature range
Over full temperature range
250
165
500
300
350
250
700
RCM
Input impedance, common mode
Input impedance, differential mode
193
–20 V ≤ VCM ≤ 0 V
0 V ≤ VCM ≤ 60 V
590
RDM
386
–20 V ≤ VCM ≤ 0 V
VCM = VS / 2
kΩ
mV
dB
500
±1
VOS
Input offset voltage
±0.15
105
DC CMRR
DC common-mode rejection ratio
–20 V ≤ VCM ≤ 60 V
Over full temperature range
Over full temperature range
90
80
f = 1 kHz
96
83
AC CMRR
AC common-mode rejection ratio(6)
dB
f = 10 kHz
CMVR
K1
Input common-mode voltage range
Preamplifier gain(3)
for 80-dB CMRR
–22
60
V
9.95
10
10.05
V/V
100
RF-INT
Output impedance filter resistor
–40°C ≤ TA ≤ 125°C,
99
97
101
103
kΩ
–40°C ≤ TA ≤ 150°C, LMP8601EDRQ1 only
TCRF-INT
Output impedance filter resistor drift
±5
2
±50 ppm/°C
VOL, RL = ∞
mV
10
Over full temperature range
A1 VOUT
A1 output voltage swing
4.985
±0.5
VOH, RL = ∞
V
Over full temperature range
4.95
OUTPUT BUFFER (FROM A2 (PIN 4) TO OUT (PIN 5))
–2
–2.5
2
mV
2.5
VOS
K2
IB
Input offset voltage
0V ≤ VCM ≤ VS
Over full temperature range
LMP8601, LMP8601-Q1
LMP8602, LMP8602-Q1
LMP8603, LMP8603-Q1
1.99
2
5
2.01
Output buffer gain(3)
Input bias current of A2(7)
4.975
9.95
5.025
10.05
V/V
10
–40
fA
Over full temperature range
LMP8601,
±20
20
nA
4
10
Over full
temperature range
LMP8601-Q1,
LMP8602,
LMP8602-Q1
VOL, RL = ∞
mV
Over full
temperature range
40
80
(9)
A2 VOUT
A2 output voltage swing(8)
10
LMP8602,
LMP8603-Q1
Over full
temperature range
4.99
VOH, RL = ∞
V
Over full temperature range
4.98
–25
30
Sourcing, VIN = VS, VOUT = GND
Sinking, VIN = GND, VOUT = VS
–42
48
–60
65
ISC
Output short-circuit current(10)
mA
(6) AC common-mode signal is a 5-VPP sine-wave (0 V to 5 V) at the given frequency.
(7) Positive current corresponds to current flowing into the device.
(8) For this test input is driven from A1 stage.
(9) For VOL, RL is connected to VS and for VOH, RL is connected to GND.
(10) Short-Circuit test is a momentary test. Continuous short circuit operation at elevated ambient temperature can result in exceeding the
maximum allowed junction temperature of 150°C.
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6.8 Typical Characteristics
at TA = 25°C, VS = 5 V, GND = 0 V, –22 ≤ VCM ≤ 60 V, RL = ∞, OFFSET (pin 7) connected to VS, and 10 nF between VS and
GND (unless otherwise noted)
1.0
0.8
0.6
0.4
0.2
0
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
V
S
= 3.3V
V
S
= 5V
-4
0
4
8
12 16 20 24 28 30
(V)
-20 -10
0
10 20 30 40 50 60
(V)
V
CM
V
CM
Figure 1. VOS vs VCM at VS = 3.3 V
Figure 2. VOS vs VCM at VS = 5 V
100
75
50
25
0
200
150
100
50
125°C
125°C
0
-40°C
-25
-50
-40°C
-50
-100
-30
-10
10
V
30
(V)
50
70
-10
0
10
(V)
20
30
V
CM
CM
Figure 4. Input Bias Current Over Temperature (+IN and –IN
pins) at VS = 5 V
Figure 3. Input Bias Current Over Temperature (+IN and –IN
pins) at VS = 3.3 V
100
200
150
100
-40°C
0
-100
50
25°C
-200
-300
0
-50
0
1
2
3
4
5
0
1
2
3
4
5
V
(V)
V
(V)
CM
CM
Figure 5. Input Bias Current Over Temperature (A2 pin) at
VS = 5 V
Figure 6. Input Bias Current Over Temperature (A2 pin) at
VS = 5 V
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Typical Characteristics (continued)
at TA = 25°C, VS = 5 V, GND = 0 V, –22 ≤ VCM ≤ 60 V, RL = ∞, OFFSET (pin 7) connected to VS, and 10 nF between VS and
GND (unless otherwise noted)
1.5
1.2
0.9
0.6
0.3
0
100
80
60
40
20
0
V
= 5V
S
V
= 3.3V
S
0.1
1
10
100
1k
10k 100k
10
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 7. Input-Referred Voltage Noise vs Frequency
Figure 8. PSRR vs Frequency
30
30
20
20
10
10
0
0
-10
-10
-20
-30
-40
-50
-20
-30
V
V
= 5V
V
V
= 3.3V
S
S
-40
= V /2
S
= V /2
S
OUT
OUT
-50
100
1k
10k
100k
1M
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 10. Gain vs Frequency at VS = 5 V
120
FREQUENCY (Hz)
Figure 9. Gain vs Frequency at VS = 3.3 V
120
100
80
60
40
20
0
100
80
60
40
20
0
V
= 5V
S
V
S
= 3.3V
100
1k
10k
100k
100
1k
FREQUENCY (Hz)
Figure 11. CMRR vs Frequency at VS = 3.3 V
10k
100k
FREQUENCY (Hz)
Figure 12. CMRR vs Frequency at VS = 5 V
10
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Typical Characteristics (continued)
at TA = 25°C, VS = 5 V, GND = 0 V, –22 ≤ VCM ≤ 60 V, RL = ∞, OFFSET (pin 7) connected to VS, and 10 nF between VS and
GND (unless otherwise noted)
V
= 5V
V
= 3.3V
S
S
R
= 10 kΩ
R
= 10 kΩ
L
L
TIME (20 µs/DIV)
TIME (20 µs/DIV)
Figure 13. Step Response at VS = 3.3 V
LMP8601 and LMP8601-Q1
Figure 14. Step Response at VS = 5 V
LMP8601 and LMP8601-Q1
V
S
= 3.3V
V
S
= 5V
TIME (5 µs/DIV)
TIME (5 µs/DIV)
Figure 15. Settling Time (Falling Edge) at VS = 3.3 V
LMP8601 and LMP8601-Q1
Figure 16. Settling Time (Falling Edge) at VS = 5 V
LMP8601 and LMP8601-Q1
V
= 5V
V
= 3.3V
S
S
TIME (5 µs/DIV)
TIME (5 µs/DIV)
Figure 17. Settling Time (Rising Edge) at VS = 3.3 V
LMP8601 and LMP8601-Q1
Figure 18. Settling Time (Rising Edge) at VS = 5 V
LMP8601 and LMP8601-Q1
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Typical Characteristics (continued)
at TA = 25°C, VS = 5 V, GND = 0 V, –22 ≤ VCM ≤ 60 V, RL = ∞, OFFSET (pin 7) connected to VS, and 10 nF between VS and
GND (unless otherwise noted)
TIME (20 ms/DIV)
TIME (20 ms/DIV)
Figure 19. Step Response at VS = 3.3 V, RL = 10 kΩ
Figure 20. Step Response at VS = 5 V, RL = 10 kΩ
LMP8602 and LMP8602-Q1
LMP8602 and LMP8602-Q1
TIME (5 ms/DIV)
TIME (5 us/DIV)
Figure 21. Settling Time (Falling Edge) at VS = 3.3 V
LMP8602 and LMP8602-Q1
Figure 22. Settling Time (Falling Edge) at VS = 5 V
LMP8602 and LMP8602-Q1
TIME (5 ms/DIV)
TIME (5 us/DIV)
Figure 23. Settling Time (Rising Edge) at VS = 3.3 V
LMP8602 and LMP8602-Q1
Figure 24. Settling Time (Rising Edge) at VS = 5 V
LMP8602 and LMP8602-Q1
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Typical Characteristics (continued)
at TA = 25°C, VS = 5 V, GND = 0 V, –22 ≤ VCM ≤ 60 V, RL = ∞, OFFSET (pin 7) connected to VS, and 10 nF between VS and
GND (unless otherwise noted)
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
TIME (20 us/DIV)
TIME (20 us/DIV)
Figure 25. Step Response at VS = 3.3 V, RL = 10 kΩ
Figure 26. Step Response at VS = 5 V, RL = 10 kΩ
LMP8603 and LMP8603-Q1
LMP8603 and LMP8603-Q1
TIME (5 us/DIV)
TIME (5 us/DIV)
Figure 27. Settling Time (Falling Edge) at VS = 3.3 V
LMP8603 and LMP8603-Q1
Figure 28. Settling Time (Falling Edge) at VS = 5 V
LMP8603 and LMP8603-Q1
TIME (5 us/DIV)
TIME (5 us/DIV)
Figure 29. Settling Time (Rising Edge) at VS = 3.3 V
LMP8603 and LMP8603-Q1
Figure 30. Settling Time (Rising Edge) at VS = 5 V
LMP8603 and LMP8603-Q1
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Typical Characteristics (continued)
at TA = 25°C, VS = 5 V, GND = 0 V, –22 ≤ VCM ≤ 60 V, RL = ∞, OFFSET (pin 7) connected to VS, and 10 nF between VS and
GND (unless otherwise noted)
3.30
3.28
3.26
3.24
3.22
3.20
60
50
40
30
20
10
0
V
= 3.3V
= 0V
= V /2
S
S
V
IN
V
CM
V
= 3.3V
= 165 mV
= V /2
S
S
V
IN
V
CM
1k
10k
LOAD RESISTANCE (Ω)
100k
1k
10k
LOAD RESISTANCE (Ω)
100k
Figure 31. Positive Swing vs RLOAD at VS = 3.3 V
Figure 32. Negative Swing vs RLOAD at VS = 3.3 V
90
5.00
V
= 5V
= 0V
S
75
60
45
30
15
0
4.98
4.96
4.94
4.92
V
IN
V
CM
= V /2
S
4.90
4.88
V
= 5V
= 250 mV
= V /2
S
S
V
IN
V
CM
1k
10k
LOAD RESISTANCE (Ω)
100k
1k
10k
LOAD RESISTANCE (Ω)
100k
Figure 34. Negative Swing vs RLOAD at VS = 5 V
Figure 33. Positive Swing vs RLOAD VS = 5 V
35
35
V
= 3.3V
6000 parts
V
= 5V
6000 parts
S
S
30
25
20
15
10
5
30
25
20
15
10
5
0
-1.0
0
-1.0
-0.6
-0.2
0
0.2
0.6
1.0
-0.6
-0.2
0
0.2
0.6
1.0
V
(mV)
V
(mV)
OS
OS
Figure 35. VOS Distribution at VS = 3.3 V
Figure 36. VOS Distribution at VS = 5 V
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Typical Characteristics (continued)
at TA = 25°C, VS = 5 V, GND = 0 V, –22 ≤ VCM ≤ 60 V, RL = ∞, OFFSET (pin 7) connected to VS, and 10 nF between VS and
GND (unless otherwise noted)
30
25
20
15
10
5
30
25
20
15
10
5
1300 parts
1300 parts
0
-10 -8 -6 -4 -2
0
-10 -8 -6 -4 -2
0
2
4
6
8
10
0
2
4
6
8
10
TCV
(µV/°C)
GAIN DRIFT (ppm/°C)
OS
Figure 37. TCVOS Distribution
Figure 38. Gain Drift Distribution, 1300 Parts
LMP8601 and LMP8601-Q1
20
15
10
5
15
12
9
6
3
0
0
-10 -8 -6 -4 -2
0
2
4
6
8
10
-10 -8 -6 -4 -2
0
2
4
6
8
10
GAIN DRIFT (ppm/°C)
GAIN DRIFT (ppm/°C)
Figure 39. Gain Drift Distribution, 5000 Parts
LMP8602 and LMP8602-Q1
Figure 40. Gain Drift Distribution, 5000 Parts
LMP8603 and LMP8603-Q1
20
20
V
= 3.3V
S
V
= 5V
S
6000 parts
6000 parts
15
10
5
15
10
5
0
0
-0.50
-0.25
0.00
0.25
0.50
-0.50
-0.25
0.00
0.25
0.50
GAIN ERROR (%)
GAIN ERROR (%)
Figure 41. Gain Error Distribution at VS = 3.3 V
LMP8601 and LMP8601-Q1
Figure 42. Gain Error Distribution at VS = 5 V
LMP8601 and LMP8601-Q1
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Typical Characteristics (continued)
at TA = 25°C, VS = 5 V, GND = 0 V, –22 ≤ VCM ≤ 60 V, RL = ∞, OFFSET (pin 7) connected to VS, and 10 nF between VS and
GND (unless otherwise noted)
20
15
10
5
20
15
10
5
0
0
-0.50
-0.25
0.00
0.25
0.50
-0.50
-0.25
0.00
0.25
0.50
GAIN ERROR (%)
GAIN ERROR (%)
Figure 43. Gain Error Distribution at VS = 3.3 V, 5000 Parts
LMP8602 and LMP8602-Q1
Figure 44. Gain Error Distribution at VS = 5 V, 5000 Parts
LMP8602 and LMP8602-Q1
20
15
10
5
20
15
10
5
0
0
-10 -8 -6 -4 -2
0
2
4
6
8
10
-10 -8 -6 -4 -2
0
2
4
6
8
10
GAIN DRIFT (ppm/°C)
GAIN DRIFT (ppm/°C)
Figure 45. Gain Error Distribution at VS = 3.3 V, 5000 Parts
LMP8603 and LMP8603-Q1
Figure 46. Gain Error Distribution at VS = 5 V
LMP8603 and LMP8603-Q1
30
30
V
S
= 5V
V
S
= 3.3V
6000 parts
6000 parts
25
20
15
10
5
25
20
15
10
5
0
0
80
90
100
CMRR (dB)
Figure 47. CMRR Distribution at VS = 3.3 V
110
120
130
140
80
90
100
110
120
130
140
CMRR (dB)
Figure 48. CMRR Distribution at VS = 5 V
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Typical Characteristics (continued)
at TA = 25°C, VS = 5 V, GND = 0 V, –22 ≤ VCM ≤ 60 V, RL = ∞, OFFSET (pin 7) connected to VS, and 10 nF between VS and
GND (unless otherwise noted)
5
4
3
2
1
0
60
50
40
30
20
10
0
VS = 5V, VCM = 0V
VS = 5V, VCM = 0V
0
50
100
150
200
250
-2.5
-1.5
-0.5
0.5
1.5
2.5
VIN (mV)
VIN (mV)
C001
C003
Figure 49. Output Voltage vs VIN
Figure 50. Output Voltage vs VIN (Enlarged Close to 0 V)
5
4
3
2
1
0
60
VS = 3.3V, VCM = 0V
VS = 3.3V, VCM = 0V
50
40
30
20
10
0
0
50
100
150
200
250
-2.5
-1.5
-0.5
0.5
1.5
2.5
VIN (mV)
VIN (mV)
C002
C004
Figure 51. Output Voltage vs VIN
Figure 52. Output Voltage vs VIN (Enlarged Close to 0 V)
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7 Detailed Description
7.1 Overview
The LMP860x and LMP860x-Q1 are fixed gain differential voltage precision amplifiers, with a –22-V to +60-V
input common-mode voltage range when operating from a single 5-V supply, or a –4-V to +27-V input common-
mode voltage range when operating from a single 3.3-V supply. The LMP8601 and LMP8601-Q1 have a gain of
20x, the LMP8602 and LMP8602-Q1 have a gain of 50x, and the LMP8603 and LMP8603-Q1 have a gain of
100x.
The LMP860x and LMP860x-Q1 are members of the LMP family and are ideal parts for unidirectional and
bidirectional current sensing applications. Because of the proprietary chopping level-shift input stage, the
LMP860x and LMP860x-Q1 achieve very low offset, very low thermal offset drift, and very high CMRR. The
LMP860x and LMP860x-Q1 amplify and filter small differential signals in the presence of high common-mode
voltages.
The LMP860x and LMP860x-Q1 use level shift resistors at the inputs. Because of these resistors, the LMP860x
and LMP860x-Q1 can easily withstand very large differential input voltages that may exist in fault conditions
where some other less protected high-performance current sense amplifiers might sustain permanent damage.
7.1.1 Theory of Operation
The schematic shown in the Functional Block Diagram gives a basic representation of the internal operation of
the LMP860x and LMP860x-Q1.
The signal on the input pins is typically a small differential voltage developed across a current sensing shunt
resistor. The input signal may also appear at a high common-mode voltage. The input signals are accessed
through two input resistors that change the voltage into a current. The proprietary chopping level-shift current
circuit pulls or pushes current through the input resistors to bring the common-mode voltage behind these
resistors within the supply rails.
Subsequently, the signal is gained up by a factor of 10 and brought out on the A1 pin through a trimmed 100-kΩ
resistor. In the application, additional gain adjustment or filtering components can be added between the A1 and
A2 pins as explained in subsequent sections. The signal on the A2 pin is further amplified by a factor of 2
(LMP8601 and LMP8601-Q1), 5 (LMP8602, LMP8602-Q1), or 10 (LMP8603, LMP8603-Q1), and brought out on
the OUT pin.
7.2 Functional Block Diagram
OFFSET
7
V
S
6
Level shift
+IN
-IN
8
1
+
5
Preamplifier
Gain = 10
-
Output Buffer
Gain = K2
OUT
100 kW
2
3
4
GND
A1 A2
NOTE: K2 = 2 for LMP8601, LMP8601-Q1; 5 for LMP8602, LMP8602-Q1; or 10 for LMP8603, LMP8603-Q1.
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7.3 Feature Description
7.3.1 Offset Input Pin
The OFFSET pin allows the output signal to be level-shifted to enable bidirectional current sensing. The output
signal is bidirectional and mid-rail referenced when the offset pin is connected to the positive supply rail. With the
offset pin connected to ground, the output signal is unidirectional and ground-referenced.
The signal on the A1 and OUT pins is ground-referenced when the offset pin is connected to ground. This means
that the output signal can only represent positive values of the current through the shunt resistor, so only
currents flowing in one direction can be measured.
When the offset pin is tied to the positive supply rail, the signal on the A1 and OUT pins is referenced to a mid-
rail voltage which allows bidirectional current sensing. The operation of the amplifier will be fully bidirectional and
symmetrical around 0 V differential at the input pins. The signal at the output will follow this voltage difference
multiplied by the gain and at an offset voltage at the output of half VS.
When the offset pin is connected to an external voltage source, the output signal will be level shifted to that
voltage divided by two. In principle, the output signal can be shifted to any voltage between 0 and VS / 2 by
applying twice that voltage to the OFFSET pin.
NOTE
The OFFSET pin must be driven from a very low-impedance source (< 10 Ω). This low
source impedance is required because the OFFSET pin internally connects directly to the
resistive feedback networks of the two gain stages. When the OFFSET pin is driven from
a relatively large impedance (for example, a resistive divider between the supply rails),
accuracy decreases.
Examples:
•
•
•
LMP8601, LMP8601-Q1: A 5-V supply, a gain of 20x, OFFSET pin tied to VS, and a differential input signal of
10 mV results in 2.7 V at the output pin. Similarly, –10 mV at the input results in 2.3 V at the output pin.
LMP8602, LMP8602-Q1: A 5-V supply, a gain of 50x, and a differential input signal of 10 mV results in 3.0 V
at the output pin. Similarly, –10 mV at the input results in 2.0 V at the output pin.
LMP8603, LMP8603-Q1: A 5-V supply, a gain of 100x, and a differential input signal of 10 mV results in 3.5 V
at the output pin. Similarly, –10 mV at the input results in 1.5 V at the output pin.(1)
(1)
(1) The OFFSET pin must be driven from a very low-impedance source (< 10 Ω) because the OFFSET pin internally connects directly to the
resistive feedback networks of the two gain stages. When the OFFSET pin is driven from a relatively large impedance (for example, a
resistive divider between the supply rails), accuracy decreases.
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Feature Description (continued)
7.3.2 Additional Second-Order Low-Pass Filter
The LMP86x1 and LMP86x1-Q1 have a third-order Butterworth lowpass characteristic with a typical bandwidth of
60 kHz integrated in the preamplifier stage. The bandwidth of the output buffer can be reduced by adding a
capacitor on the A1 pin to create a first-order low-pass filter with a time constant determined by the 100-kΩ
internal resistor and the external filter capacitor.
It is also possible to create an additional second-order, Sallen-Key, low-pass filter by adding external
components R2, C1 and C2. Together with the internal 100-kΩ resistor R1 as illustrated in Figure 53, this circuit
creates a second-order, low-pass filter characteristic.
OFFSET
7
8
IN
IN
+
5
Level
shift
Output Buffer
Gain = K2
Preamplifier
Gain = K1
-
OUT
1
Internal
R
1
100 kW
3
4
A1
A2
R
2
C
1
C
2
NOTE: K1 = 10; K2 = 2 for LMP8601, LMP8601-Q1; 5 for LMP8602, LMP8602-Q1; or 10 for LMP8603, LMP8603-Q1.
Figure 53. Second-Order Low-Pass Filter
When the corner frequency of the additional filter is much lower than 60 kHz, the transfer function of the
described amplifier can be written as:
1
K1 * K2
R1R2C1C2
H(s) =
(1 - K2)
1
1
s2 + s *
+
1
+
+
R1C2
R2C1
R2C2
R1R2C1C2
where
•
K1 equals the gain of the preamplifier and K2 that of the buffer amplifier.
(1)
Equation 1 can be written in the normalized frequency response for a second-order lowpass filter:
K2
G(jw) = K1 *
(jw)2
wo
jw
+
+ 1
2
Qwo
(2)
(3)
The cutoff frequency ωo in rad/sec (divide by 2π to get the cut-off frequency in Hz) is given by:
1
wo =
R1R2C1C2
20
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Feature Description (continued)
and the quality factor of the filter is given by:
R1R2C1C2
Q =
R1C1 + R2C1 + (1 - K2) * R1C2
(4)
(5)
With K2 = 2x, Equation 4 transforms results in:
R1R2C1C2
Q =
R1C1 + R2C1 - R1C2
For any filter gain K > 1x, the design procedure can be very simple if the two capacitors are chosen to in a
certain ratio.
C1
C2 =
K2 - 1
(6)
Inserting this in Equation 4 for Q results in:
2
C1
R1R2
K2 - 1
Q =
(K2 - 1)R1C1
R1C1 + R2C1 -
K2 - 1
(7)
Which results in:
2
R1R2
K2 - 1
R2
C1
R1R2
K2 - 1
Q =
=
C1R2
(8)
In this case, given the predetermined value of R1 = 100 kΩ (the internal resistor), the quality factor is set solely
by the value of the resistor R2.
R2 can be calculated based on the desired value of Q as the first step of the design procedure with the following
equation:
R1
R2
=
2
(
)
-
K 1 Q
(9)
For the gain of 2 for the LMP8601 and LMP8601-Q1, the result is:
R1
Q2
R2 =
(10)
For the gain of 5 for the LMP8602 and LMP8602-Q1, the result is:
R1
R2 =
4Q2
(11)
(12)
For the gain of 10 for the LMP8603 and LMP8603-Q1, the result is:
R1
R2 =
9Q2
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Feature Description (continued)
For instance, the value of Q can be set to 0.5√2 to create a Butterworth response, to 1/√3 to create a Bessel
response, or a 0.5 to create a critically damped response. After the value of R2 has been found, the second and
last step of the design procedure is to calculate the required value of C to give the desired low-pass cut-off
frequency using:
(K2 - 1)Q
C1 =
R1w0
(13)
For the gain = 2, the result is:
Q
C =
R1wo
(14)
The gain = 5 results in:
4Q
C1 =
R1w0
(15)
The gain = 10 gives:
9Q
C1 =
R1w0
(16)
For C2 the value is calculated with:
C1
C2 =
K2 - 1
(17)
For a gain = 2:
C2 = C1
(18)
Or for a gain = 5:
C1
C2 =
4
(19)
(20)
And for a gain = 10:
C1
C2 =
9
Note that the frequency response achieved using this procedure is only accurate if the cut-off frequency of the
second-order filter is much smaller than the intrinsic 60-kHz, low-pass filter. In other words, choose the frequency
response of the LMP860x or LMP860x-Q1 circuit so that the internal poles do not affect the external second-
order filter.
7.4 Device Functional Modes
7.4.1 Gain Adjustment
The gain of the LMP860x and LMP860x-Q1 is fixed; however, the overall gain may be adjusted as the signal
path between the two internal amplifiers is available on the A1 and A2 pins.
22
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Device Functional Modes (continued)
7.4.1.1 Reducing Gain
Figure 54 shows the configuration that can be used to reduce the gain of the LMP8601 and LMP8601-Q1.
OFFSET
7
+IN
-IN
8
1
+
5
Level
shift
OUT
Output Buffer
Gain = K2
Preamplifier
Gain = 10
-
Internal
Resistor
100 kW
3
4
A2
A1
R
r
NOTE: K2 = 2 for LMP8601, LMP8601-Q1; 5 for LMP8602, LMP8602-Q1; or 10 for LMP8603, LMP8603-Q1.
Figure 54. Reduce Gain
Rr creates a resistive divider together with the internal 100-kΩ resistor such that the reduced gain Gr becomes:
20 Rr
Gr =
Rr + 100 kW
(21)
For the LMP8602 and LMP8602-Q1:
50 Rr
Gr =
Rr + 100 kW
(22)
And for the LMP8603 and LMP8603-Q1:
100 Rr
Gr =
Rr + 100 kW
(23)
Given a desired value of the reduced gain Gr, using this equation, the LMP8601 and LMP8601-Q1 required value
for the Rr is calculated with:
Gr
Rr = 100 kW X
20 - Gr
(24)
For the LMP8602 and LMP8602-Q1:
Gr
Rr = 100 kW X
50 - Gr
(25)
And for the LMP8603 and LMP8603-Q1:
Gr
100 - Gr
Rr = 100 kW x
(26)
7.4.1.2 Increasing Gain
Figure 55 shows the configuration that can be used to increase the gain of the LMP8601 and LMP8601-Q1.
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Device Functional Modes (continued)
OFFSET
7
+IN
-IN
8
1
+
5
Level
shift
OUT
Output Buffer
Gain = K2
Preamplifier
Gain = 10
-
Internal
Resistor
100 kW
3
4
A2
A1
R
i
NOTE: K2 = 2 for LMP8601, LMP8601-Q1; 5 for LMP8602, LMP8602-Q1; or 10 for LMP8603, LMP8603-Q1.
Figure 55. Increase Gain
Ri creates positive feedback from the output pin to the input of the buffer amplifier. The positive feedback
increases the gain. The increased gain Gi for the LMP8601 and LMP8601-Q1 becomes:
20 Ri
Gi =
Ri - 100 kW
(27)
For the LMP8602 and LMP8602-Q1:
50 Ri
Gi =
Ri - 400 kW
(28)
And for the LMP8603 and LMP8603-Q1:
100 Ri
Gi =
Ri - 900 kW
(29)
From this equation, for a desired value of the gain, the LMP8601 and LMP8601-Q1 required value of Ri is
calculated with:
Gi
Ri = 100 kW X
Gi - 20
(30)
For the LMP8602 and LMP8602-Q1:
Gi
Ri = 400 kW X
Gi - 50
(31)
And for the LMP8603 with:
Gi
Gi - 100
Ri = 900 kW x
(32)
Note that from the equation for the gain Gi, for large gains, Ri approaches 100 kΩ. In this case, the denominator
in the equation becomes close to zero. In practice, for large gains, the denominator is determined by tolerances
in the value of the external resistor Ri and the internal 100-kΩ resistor. In this case, the gain becomes very
inaccurate. If the denominator becomes equal to zero, the system becomes unstable. TI recommends to limit the
application of this technique to gain values of 50 or smaller.
24
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Device Functional Modes (continued)
7.4.2 Driving Switched Capacitive Loads
Some ADCs load their signal source with a sample and hold capacitor. The capacitor may be discharged prior to
being connected to the signal source. If the LMP860x and LMP860x-Q1 are driving such ADCs, the sudden
current that should be delivered when the sampling occurs may disturb the output signal. This effect was
simulated with the circuit shown in Figure 56 where the output is to a capacitor that is driven by a rail-to-rail
square wave.
V
S
LMP8601/
LMP8601Q
0V
Figure 56. Driving Switched Capacitive Load
This circuit simulates the switched connection of a discharged capacitor to the LMP860x and LMP860x-Q1
output. The resulting VOUT disturbance signals are shown in Figure 57 and Figure 58.
0.4
0.2
0.5
0.4
0.3
0.2
0.1
0
V
S
= 5V
V
= 3.3V
S
0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.1
-0.2
-0.3
-0.4
-0.5
100
0
50
100
150
200
250
300
0
50
150
TIME (ns)
Figure 57. Capacitive Load Response at 3.3 V
200
250
300
TIME (ns)
Figure 58. Capacitive Load Response at 5.0 V
These figures can be used to estimate the disturbance that will be caused when driving a switched capacitive
load. To minimize the error signal introduced by the sampling that occurs on the ADC input, place an additional
RC filter between the LMP860x or LMP860x-Q1 and the ADC, as illustrated in Figure 59.
Output Buffer
ADC
Figure 59. Reduce Error When Driving ADCs
The external capacitor absorbs the charge that flows when the ADC sampling capacitor is connected. The
external capacitor should be much larger than the sample-and-hold capacitor at the input of the ADC, and the
RC time constant of the external filter should be such that the speed of the system is not affected.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Specifying Performance
To specify the high performance of the LMP860x and LMP860x-Q1, all minimum and maximum values shown in
the parameter tables of this data sheet are 100% tested, and all over temperature limits are also 100% tested
over temperature.
8.2 Typical Applications
8.2.1 High-Side, Current-Sensing Application
Figure 60 illustrates the application of the LMP860x and LMP860x-Q1 in a high-side sensing application. This
application is similar to the low-side sensing discussed below, except in this application the common-mode
voltage on the shunt drops below ground when the driver is switched off. Because the common-mode voltage
range of the LMP860x and LMP860x-Q1 extends below the negative rail, the LMP860x and LMP860x-Q1 are
also very well suited for this application.
POWER
SWITCH
OFFSET
7
INDUCTIVE
LOAD
+IN
8
1
24V
+
5
Level
shift
OUT
Output Buffer
Gain = K2
Preamplifier
R
SENSE
Gain = 10
-
Internal
Resistor
100 kW
-IN
3
4
A2
A1
C1
NOTE: For this application example, K2 = 2.
Figure 60. High-Side, Current-Sensing Application
26
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Typical Applications (continued)
8.2.1.1 Design Requirements
Using the circuit in Figure 60, the requirement is to measure coil current up to 10 A and drive the ADC input to a
maximum of 3.3 V. The OFFSET pin is grounded, so zero current will result in a zero volt output.
8.2.1.2 Detailed Design Procedure
First, the value of RSENSE must be determined. RSENSE can be found by dividing the maximum desired output
swing by the gain to determine the maximum input voltage. In this example, the LMP8601 is used, with a gain of
20 V/V, as shown in Equation 33:
3.3 V
VOUTMAX
Gain
=
=
= 165 mV
VINMAX
20 V/V
(33)
Knowing 165 mV must be generated, the ideal value of the sense resistor can be determined through simple
ohms law:
165 mV
VINMAX
=
=
= 16.5 mΩ
RSENSE
10A
ILOADMAX
(34)
The ideal sense resistor value is 16.5 mΩ. The closest standard value is 15 mΩ, but this value may cause the
output to slightly overrange at 10 V. It is recommended to reduce the expected maximum output by a few percent
to allow for overloads and component tolerances. The next most popular values would be 10 mΩ, 15 mΩ, and 20
mΩ. 10 mΩ allows for a maximum output of 2 V at 10 A, but may be too low and not use the full output range. 20
mΩ provides more sensitivity, but limits the maximum current to 8.25 A. 15 mΩ is a good compromise at 11 A
maximum, and allows for some component tolerance variation.
If a suitable sense resistor value is not available, it is possible to adjust the gain as detailed in the Gain
Adjustment section.
The sense resistor does dissipates power, so the maximum wattage rating and appropriate power deratings must
be observed. In the example above, the sense resistor dissipates 0.165 V × 10 A = 1.65 W, so a sense resistor
of at least twice the maximum expected power should be used (greater than 4 W).
8.2.1.3 Application Curve
Below is the expected output value using a 15-mΩ sense resistor.
5.0
V
= 5V
S
4.0
3.0
2.0
1.0
0.0
V
= 3.3V
S
R
= 15mΩ
SENSE
0
2
4
6
8
10
12
14 16
18
20
Load Current (A)
C001
Figure 61. Expected Output Voltage vs Load Current Using 15-mΩ Sense Resistor
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Typical Applications (continued)
8.2.2 Low-Side, Current-Sensing Application
Figure 62 illustrates a low-side, current-sensing application with a low-side driver. The power transistor is pulse
width modulated to control the average current flowing through the inductive load which is connected to a
relatively high battery voltage. The current through the load is measured across a shunt resistor RSENSE in series
with the load. When the power transistor is on, current flows from the battery through the inductive load, the
shunt resistor and the power transistor to ground. In this case, the common-mode voltage on the shunt is close
to ground. When the power transistor is off, current flows through the inductive load, through the shunt resistor
and through the freewheeling diode. In this case the common-mode voltage on the shunt is at least one diode
voltage drop above the battery voltage. Therefore, in this application the common-mode voltage on the shunt is
varying between a large positive voltage and a relatively low voltage. Because the large common-mode voltage
range of the LMP860x and LMP860x-Q1 and because of the high ac common-mode rejection ratio, the LMP860x
and LMP860x-Q1 are very well suited for this application.
OFFSET
7
INDUCTIVE
LOAD
+IN
-IN
8
1
+
5
Level
shift
OUT
Output Buffer
Gain = K2
Preamplifier
R
SENSE
Gain = 10
-
24V
Internal
Resistor
100 kW
3
4
A2
A1
POWER
SWITCH
C1
RSENSE = 0.01 Ω, K2 = 2, VOUT = 0.2 V/A
Figure 62. Low-Side Current-Sensing Application
For this application, the following example can be used for the calculation of the sense voltage (VSENSE):
When using a sense resistor, RSENSE, of 0.01 Ω and a current, ILOAD, of 1 A, the sense voltage at the input pins of
the LMP860x and LMP860x-Q1 is:
VSENSE = RSENSE × ILOAD = 0.01 Ω × 1 A = 0.01 V
(35)
With the gain of 20 for the LMP8601, the result is an output of 0.2 V. Or in other words, VOUT = 0.2 V/A. The
result is the same for the LMP8601-Q1.
For the LMP8602 and LMP8602-Q1 with a gain of 50, the output is 0.5 V/A.
For the LMP8603 and LMP8603-Q1 with a gain of 100, the output is 1 V/A.
28
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Typical Applications (continued)
8.2.3 Battery Current Monitor Application
This application example shows how the LMP860x and LMP860x-Q1 can be used to monitor the current flowing
in and out of a battery pack. The fact that the LMP860x and LMP860x-Q1 can measure small voltages at a high
offset voltage outside the parts own supply range makes this part a very good choice for such applications. If the
load current of the battery is higher then the charging current, the output voltage of the LMP860x and LMP860x-
Q1 will be above the half offset voltage for a net current flowing out of the battery. When the charging current is
higher then the load current the output will be below this half offset voltage.
I
I
Charge
Load
LOAD
Charger
V
S
OFFSET
I
- I
Charge Load
7
+IN
-IN
8
1
+
5
Level
shift
OUT
Output Buffer
Gain = K2
Preamplifier
R
SENSE
Gain = 10
-
Internal
Resistor
100 kW
3
4
A2
A1
C1
NOTE: K2 = 2 for LMP8601, LMP8601-Q1; 5 for LMP8602, LMP8602-Q1; or 10 for LMP8603, LMP8603-Q1.
Figure 63. Battery Current Monitor Application
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Typical Applications (continued)
8.2.4 Advanced Battery Charger Application
Figure 63 can be used to realize an advanced battery charger that has the capability to monitor the exact net
current that flows in and out the battery as show in Figure 64. The output signal of the LMP860x and LMP860x-
Q1 is digitized with the ADC and used as an input for the charge controller. The Charge controller can be used to
regulate the charger circuit to deliver exactly the current that is required by the load, avoiding overcharging a fully
loaded battery.
I
Load
LOAD
V
S
I
- I
OFFSET
Charge Load
7
+IN
-IN
8
I
Charge
+
5
Level
shift
OUT
Output Buffer
Gain = K2
Preamplifier
Gain = 10
A/D
R
SENSE
12V
1
-
Internal
Resistor
100 kW
3
4
A2
A1
C1
Charge
Controler
Charger
NOTE: K2 = 2 for LMP8601, LMP8601-Q1; 5 for LMP8602, LMP8602-Q1; or 10 for LMP8603, LMP8603-Q1.
Figure 64. Advanced Battery Charger Application
8.2.5 Current Loop Receiver Application
Many industrial applications use 4-mA to 20-mA transmitters to send an analog value of a sensor to a central
control room. The LMP860x and LMP860x-Q1 can be used as a current loop receiver as shown in Figure 65.
V
S
OFFSET
7
+IN
-IN
8
1
+
4 mA to 20 mA
CURRENT LOOP
5
OUT
Level
shift
Output Buffer
Gain = K2
Preamplifier
R
SENSE
Gain = 10
-
Internal
Resistor
100 kW
3
4
A2
A1
C1
NOTE: K2 = 2 for LMP8601, LMP8601-Q1; 5 for LMP8602, LMP8602-Q1; or 10 for LMP8603, LMP8603-Q1.
Figure 65. Current-Loop Receiver Application
30
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9 Power Supply Recommendations
In order to decouple the LMP860x and LMP860x-Q1 from AC noise on the power supply, place a 0.1-μF bypass
capacitor between the VS and GND pins. Place this capacitor as close as possible to the supply pins. In some
cases, an additional 10-μF bypass capacitor may further reduce the supply noise.
10 Layout
10.1 Layout Guidelines
The traces leading to and from the sense resistor can be significant error sources. With small value sense
resistors (< 100 mΩ), any trace resistance shared with the load current can cause significant errors.
The amplifier inputs should be directly connected to the sense resistor pads using Kelvin or 4-wire connection
techniques. The traces should be one continuous piece of copper from the sense resistor pad to the amplifier
input pin pad, and ideally on the same copper layer with minimal vias or connectors. This can be important
around the sense resistor if it is generating any significant heat gradients.
To minimize noise pickup and thermal errors, the input traces should be treated as a differential signal pair and
routed tightly together with a direct path to the input pins. The input traces should be run away from noise
sources, such as digital lines, switching supplies or motor drive lines. Remember that these traces can contain
high voltage, and should have the appropriate trace routing clearances.
Since the sense traces only carry the amplifier bias current, the connecting input traces can be thinner, signal
level traces. Excessive Resistance in the trace should also be avoided.
The paths of the traces should be identical, including connectors and vias, so that any errors will be equal and
cancel.
The sense resistor will heat up as the load increases. As the resistor heats up, the resistance generally goes up,
which will cause a change in the readings. The sense resistor should have as much heatsinking as possible to
remove this heat through the use of heatsinks or large copper areas coupled to the resistor pads. A reading
drifting over time after turnon can usually be traced back to sense resistor heating.
10.2 Layout Example
Figure 66. Kelvin or 4–wire Connection to the Sense Resistor
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11 器件和文档支持
11.1 器件支持
11.1.1 开发支持
《LMP8601 TINA SPICE 模型》，SNOM084
TINA-TI 基于 SPICE 的模拟仿真程序，http://www.ti.com.cn/tool/cn/tina-ti
11.2 相关链接
表 1 列出了快速访问链接。范围包括技术文档、支持与社区资源、工具和软件，并且可以快速访问样片或购买链
接。
表 1. 相关链接
器件
产品文件夹
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
样片与购买
技术文档
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
工具与软件
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
支持与社区
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
LMP8601
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
LMP8601-Q1
LMP8602
LMP8602-Q1
LMP8603
LMP8603-Q1
11.3 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
32
版权 © 2008–2016, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMP8601EDRQ1
LMP8601MA/NOPB
LMP8601MAX/NOPB
LMP8601QMA/NOPB
LMP8601QMAX/NOPB
LMP8602MA/NOPB
LMP8602MAX/NOPB
ACTIVE
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
D
D
D
D
D
D
D
8
8
8
8
8
8
8
2500 RoHS & Green
95 RoHS & Green
2500 RoHS & Green
95 RoHS & Green
2500 RoHS & Green
95 RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 150
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
LMP86
01EDQ1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SN
SN
SN
SN
SN
SN
LMP86
01MA
LMP86
01MA
LMP86
01QMA
LMP86
01QMA
LMP86
02MA
2500 RoHS & Green
1000 RoHS & Green
LMP86
02MA
LMP8602MM/NOPB
LMP8602MME/NOPB
LMP8602MMX/NOPB
LMP8602QMA/NOPB
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VSSOP
VSSOP
VSSOP
SOIC
DGK
DGK
DGK
D
8
8
8
8
SN
SN
SN
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
AN3A
AN3A
AN3A
250
3500 RoHS & Green
95 RoHS & Green
RoHS & Green
LMP86
02QMA
LMP8602QMAX/NOPB
ACTIVE
SOIC
D
8
2500 RoHS & Green
1000 RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
LMP86
02QMA
LMP8602QMM/NOPB
LMP8602QMME/NOPB
LMP8602QMMX/NOPB
LMP8603MA/NOPB
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VSSOP
VSSOP
VSSOP
SOIC
DGK
DGK
DGK
D
8
8
8
8
SN
SN
SN
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
AF7A
AF7A
AF7A
250
3500 RoHS & Green
95 RoHS & Green
RoHS & Green
LMP86
03MA
LMP8603MAX/NOPB
LMP8603MM/NOPB
ACTIVE
ACTIVE
SOIC
D
8
8
2500 RoHS & Green
1000 RoHS & Green
SN
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
LMP86
03MA
VSSOP
DGK
AP3A
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMP8603MME/NOPB
LMP8603MMX/NOPB
LMP8603QMA/NOPB
ACTIVE
ACTIVE
ACTIVE
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
8
8
250
RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
AP3A
AP3A
3500 RoHS & Green
95 RoHS & Green
SN
SN
LMP86
03QMA
LMP8603QMAX/NOPB
ACTIVE
SOIC
D
8
2500 RoHS & Green
1000 RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
LMP86
03QMA
LMP8603QMM/NOPB
LMP8603QMME/NOPB
LMP8603QMMX/NOPB
ACTIVE
ACTIVE
ACTIVE
VSSOP
VSSOP
VSSOP
DGK
DGK
DGK
8
8
8
SN
SN
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
AH7A
AH7A
AH7A
250
RoHS & Green
3500 RoHS & Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMP8601QMAX/NOPB
LMP8602MMX/NOPB
LMP8602QMAX/NOPB
LMP8603MAX/NOPB
LMP8603MM/NOPB
LMP8603MME/NOPB
LMP8603MMX/NOPB
LMP8603QMAX/NOPB
LMP8603QMM/NOPB
SOIC
VSSOP
SOIC
D
8
8
8
8
8
8
8
8
8
8
8
2500
3500
2500
2500
1000
250
330.0
330.0
330.0
330.0
178.0
178.0
330.0
330.0
178.0
178.0
330.0
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
6.5
5.3
6.5
6.5
5.3
5.3
5.3
6.5
5.3
5.3
5.3
5.4
3.4
5.4
5.4
3.4
3.4
3.4
5.4
3.4
3.4
3.4
2.0
1.4
2.0
2.0
1.4
1.4
1.4
2.0
1.4
1.4
1.4
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
DGK
D
SOIC
D
VSSOP
VSSOP
VSSOP
SOIC
DGK
DGK
DGK
D
3500
2500
1000
250
VSSOP
DGK
DGK
DGK
LMP8603QMME/NOPB VSSOP
LMP8603QMMX/NOPB VSSOP
3500
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LMP8601QMAX/NOPB
LMP8602MMX/NOPB
LMP8602QMAX/NOPB
LMP8603MAX/NOPB
LMP8603MM/NOPB
SOIC
VSSOP
SOIC
D
8
8
8
8
8
8
8
8
8
8
8
2500
3500
2500
2500
1000
250
356.0
356.0
356.0
356.0
208.0
208.0
356.0
356.0
208.0
208.0
356.0
356.0
356.0
356.0
356.0
191.0
191.0
356.0
356.0
191.0
191.0
356.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
DGK
D
SOIC
D
VSSOP
VSSOP
VSSOP
SOIC
DGK
DGK
DGK
D
LMP8603MME/NOPB
LMP8603MMX/NOPB
LMP8603QMAX/NOPB
LMP8603QMM/NOPB
LMP8603QMME/NOPB
LMP8603QMMX/NOPB
3500
2500
1000
250
VSSOP
VSSOP
VSSOP
DGK
DGK
DGK
3500
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jun-2023
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
LMP8601MA/NOPB
LMP8601QMA/NOPB
LMP8602MA/NOPB
LMP8602QMA/NOPB
LMP8603MA/NOPB
LMP8603QMA/NOPB
D
D
D
D
D
D
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
8
8
8
8
8
8
95
95
95
95
95
95
495
495
495
495
495
495
8
8
8
8
8
8
4064
4064
4064
4064
4064
4064
3.05
3.05
3.05
3.05
3.05
3.05
Pack Materials-Page 3
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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