LMR10515YMF/NOPB [TI]
采用 SOT-23 和 LLP 封装的 5.5V 输入电压、1.5A 降压稳压器 | DBV | 5 | -40 to 125;型号: | LMR10515YMF/NOPB |
厂家: | TEXAS INSTRUMENTS |
描述: | 采用 SOT-23 和 LLP 封装的 5.5V 输入电压、1.5A 降压稳压器 | DBV | 5 | -40 to 125 开关 控制器 开关式稳压器 开关式控制器 电源电路 开关式稳压器或控制器 |
文件: | 总22页 (文件大小:454K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LMR10515
LMR10515 SIMPLE SWITCHER ® 5.5Vin, 1.5A Step-Down Voltage Regulator in
SOT-23 and LLP
Literature Number: SNVS728A
November 1, 2011
LMR10515
SIMPLE SWITCHER® 5.5Vin, 1.5A Step-Down Voltage
Regulator in SOT-23 and LLP
Features
Performance Benefits
Input voltage range of 3V to 5.5V
Extremely easy to use
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Output voltage range of 0.6V to 4.5V
Tiny overall solution reduces system cost
Output current up to 1.5A
Applications
1.6MHz (LMR10515X) and 3 MHz (LMR10515Y)
switching frequencies
Point-of-Load Conversions from 3.3V, and 5V Rails
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Low shutdown Iq, 30 nA typical
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Space Constrained Applications
Internal soft-start
Battery Powered Equipment
Internally compensated
Industrial Distributed Power Applications
Current-Mode PWM operation
Power Meters
Thermal shutdown
Portable Hand-Held Instruments
SOT23-5 (2.92 x 2.84 x 1 mm) and LLP-6 (3 x 3 x 0.8 mm)
packaging
Fully enabled for WEBENCH® Power Designer
■
System Performance
Efficiency vs Load Current - "X" VIN = 5V
Efficiency vs Load Current - "Y" VIN = 5V
100
100
90
80
70
60
90
80
70
60
50
50
1.8Vout
1.8Vout
3.3Vout
3.3Vout
40
40
0.00 0.25 0.50 0.75 1.00 1.25 1.50
LOAD CURRENT (A)
0.00 0.25 0.50 0.75 1.00 1.25 1.50
LOAD CURRENT (A)
30166196
30166197
Typical Application
30166164
© 2011 Texas Instruments Incorporated
301661
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Connection Diagrams
30166103
30166101
5-Pin SOT-23
Top Mark
6-Pin LLP
Ordering Information
Frequency
Order Number
NSC Package
Drawing
Package Type
Supplied As
Option
LMR10515XMFE
LMR10515XMF
250 units Tape and Reel
1000 units Tape and Reel
3000 units Tape and Reel
250 units Tape and Reel
1000 units Tape and Reel
4500 units Tape and Reel
250 units Tape and Reel
1000 units Tape and Reel
3000 units Tape and Reel
250 units Tape and Reel
1000 units Tape and Reel
4500 units Tape and Reel
SOT23-5
MF05A
SDE06A
MF05A
SH6B
L265B
SJ1B
LMR10515XMFX
1.6 MHz
LMR10515XSDE
LMR10515XSD
LMR10515XSDX
LMR10515YMFE
LMR10515YMF
LLP-6
SOT23-5
LLP-6
LMR10515YMFX
3 MHz
LMR10515YSDE
LMR10515YSD
LMR10515YSDX
SDE06A
L269B
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Pin Descriptions 5-Pin SOT23
Pin
1
Name
SW
Function
Switch node. Connect to the inductor and catch diode.
2
GND
Signal and power ground pin. Place the bottom resistor of the feedback network as close as
possible to this pin.
3
4
FB
EN
Feedback pin. Connect to external resistor divider to set output voltage.
Enable control input. Logic high enables operation. Do not allow this pin to float or be greater
than VIN + 0.3V.
5
VIN
Input supply voltage.
Pin Descriptions 6-Pin LLP
Pin
1
Name
FB
Function
Feedback pin. Connect to external resistor divider to set output voltage.
2
GND
Signal and power ground pin. Place the bottom resistor of the feedback network as close
as possible to this pin.
3
4
5
6
SW
VIND
VINA
EN
Switch node. Connect to the inductor and catch diode.
Power Input supply.
Control circuitry supply voltage. Connect VINA to VIND on PC board.
Enable control input. Logic high enables operation. Do not allow this pin to float or be greater
than VINA + 0.3V.
DAP
Die Attach Pad
Connect to system ground for low thermal impedance, but it cannot be used as a primary
GND connection.
3
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Storage Temperature
Soldering Information
For soldering specifications:
see product folder at www.national.com and
www.national.com/ms/MS/MS-SOLDERING.pdf
−65°C to +150°C
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the Texas Instruments Sales Office/
Distributors for availability and specifications.
VIN
-0.5V to 7V
ꢀ
FB Voltage
EN Voltage
SW Voltage
ESD Susceptibility
Junction Temperature (Note 2)
-0.5V to 3V
-0.5V to 7V
-0.5V to 7V
2kV
Operating Ratings
VIN
3V to 5.5V
−40°C to +125°C
Junction Temperature
150°C
Electrical Characteristics (Note 3), (Note 4) VIN = 5V unless otherwise indicated under the Conditions
column. Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of
-40°C to +125°C. Minimum and Maximum limits are guaranteed through test, design, or statistical correlation. Typical values
represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only.
Symbol
Parameter
Feedback Voltage
Conditions
Min
Typ
0.600
0.02
Max
Units
V
VFB
0.588
0.612
Feedback Voltage Line Regulation
Feedback Input Bias Current
VIN = 3V to 5V
%/V
ΔVFB/VIN
IB
0.1
2.73
2.3
0.43
1.6
3.0
94
100
nA
V
VIN Rising
VIN Falling
2.90
Undervoltage Lockout
UVLO Hysteresis
UVLO
1.85
V
LMR10515-X
LMR10515-Y
LMR10515-X
LMR10515-Y
LMR10515-X
LMR10515-Y
LLP-6 Package
SOT23-5 Package
VIN = 3.3V
1.2
2.25
86
1.95
3.75
FSW
DMAX
DMIN
Switching Frequency
MHz
Maximum Duty Cycle
Minimum Duty Cycle
Switch On Resistance
%
%
82
90
5
7
150
130
2.5
RDS(ON)
ICL
mΩ
A
195
0.4
Switch Current Limit
Shutdown Threshold Voltage
Enable Threshold Voltage
Switch Leakage
1.8
1.8
VEN_TH
V
ISW
IEN
100
100
3.3
4.3
30
nA
nA
Enable Pin Current
Sink/Source
LMR10515X VFB = 0.55
LMR10515Y VFB = 0.55
All Options VEN = 0V
5
mA
Quiescent Current (switching)
Quiescent Current (shutdown)
IQ
6.5
nA
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Symbol
Parameter
Junction to Ambient
0 LFPM Air Flow (Note 5)
Conditions
LLP-6 Package
Min
Typ
80
Max
Units
θJA
°C/W
SOT23-5 Package
LLP-6 Package
118
18
θJC
Junction to Case
°C/W
°C
SOT23-5 Package
80
TSD
Thermal Shutdown Temperature
165
Note 1: Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating Range indicates conditions for which the device is
intended to be functional, but does not guarantee specfic performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics.
Note 2: Thermal shutdown will occur if the junction temperature exceeds the maximum junction temperature of the device.
Note 3: Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlation using Statistical
Quality Control (SQC) methods. Limits are used to calculate National’s Average Outgoing Quality Level (AOQL).
Note 4: Typical numbers are at 25°C and represent the most likely parametric norm.
Note 5: Applies for packages soldered directly onto a 3” x 3” PC board with 2oz. copper on 4 layers in still air.
5
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Typical Performance Characteristics
Unless stated otherwise, all curves taken at VIN = 5.0V with configuration in typical application circuit shown in Figure 3. TJ = 25°
C, unless otherwise specified.
η vs Load "X" Vin = 5V, Vo = 1.8V & 3.3V
η vs Load "Y" Vin = 5V, Vo = 3.3V & 1.8V
100
100
90
80
70
60
90
80
70
60
50
50
1.8Vout
1.8Vout
3.3Vout
3.3Vout
40
40
0.00 0.25 0.50 0.75 1.00 1.25 1.50
LOAD CURRENT (A)
0.00 0.25 0.50 0.75 1.00 1.25 1.50
LOAD CURRENT (A)
30166196
30166197
Load Regulation
Vin = 3.3V, Vo = 1.8V (All Options)
η vs Load "X,and Y" Vin = 3.3V, Vo = 1.8V
100
90
80
70
60
50
LMR10515X
LMR10515Y
40
0.00 0.25 0.50 0.75 1.00 1.25 1.50
LOAD CURRENT (A)
30166198
30166144
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Load Regulation
Vin = 5V, Vo = 1.8V (All Options)
Load Regulation
Vin = 5V, Vo = 3.3V (All Options)
30166145
30166146
Oscillator Frequency vs Temperature - "X"
Oscillator Frequency vs Temperature - "Y"
30166124
30166136
Current Limit vs Temperature
Vin = 3.3V
RDSON vs Temperature (LLP-6 Package)
30166183
30166123
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RDSON vs Temperature (SOT23-5 Package)
LMR10515X IQ (Quiescent Current)
30166184
30166128
LMR10515Y IQ (Quiescent Current)
Line Regulation
Vo = 1.8V, Io = 500mA
30166137
30166153
VFB vs Temperature
30166127
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Gain vs Frequency
(Vin = 5V, Vo = 1.2V @ 1A)
Phase Plot vs Frequency
(Vin = 5V, Vo = 1.2V @ 1A)
30166156
30166157
9
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Simplified Block Diagram
30166104
FIGURE 1.
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General Description
The LMR10515 regulator is a monolithic, high frequency,
PWM step-down DC/DC converter in a 5 pin SOT23 and a 6
Pin LLP package. It provides all the active functions to provide
local DC/DC conversion with fast transient response and ac-
curate regulation in the smallest possible PCB area. With a
minimum of external components, the LMR10515 is easy to
use. The ability to drive 1.5A loads with an internal 130 mΩ
PMOS switch results in the best power density available. The
world-class control circuitry allows on-times as low as 30ns,
thus supporting exceptionally high frequency conversion over
the entire 3V to 5.5V input operating range down to the min-
imum output voltage of 0.6V. The LMR10515 is internally
compensated, so it is simple to use and requires few external
components. Switching frequency is internally set to 1.6 MHz,
or 3.0 MHz, allowing the use of extremely small surface mount
inductors and chip capacitors. Even though the operating fre-
quency is high, efficiencies up to 93% are easy to achieve.
External shutdown is included, featuring an ultra-low stand-
by current of 30 nA. The LMR10515 utilizes current-mode
control and internal compensation to provide high-perfor-
mance regulation over a wide range of operating conditions.
Additional features include internal soft-start circuitry to re-
duce inrush current, pulse-by-pulse current limit, thermal
shutdown, and output over-voltage protection.
30166166
FIGURE 2. Typical Waveforms
SOFT-START
This function forces VOUT to increase at a controlled rate dur-
ing start up. During soft-start, the error amplifier’s reference
voltage ramps from 0V to its nominal value of 0.6V in approx-
imately 600 µs. This forces the regulator output to ramp up in
a controlled fashion, which helps reduce inrush current.
Applications Information
THEORY OF OPERATION
OUTPUT OVERVOLTAGE PROTECTION
The following operating description of the LMR10515 will refer
to the Simplified Block Diagram (Figure 1) and to the wave-
forms in Figure 2. The LMR10515 supplies a regulated output
voltage by switching the internal PMOS control switch at con-
stant frequency and variable duty cycle. A switching cycle
begins at the falling edge of the reset pulse generated by the
internal oscillator. When this pulse goes low, the output con-
trol logic turns on the internal PMOS control switch. During
this on-time, the SW pin voltage (VSW) swings up to approxi-
mately VIN, and the inductor current (IL) increases with a linear
slope. IL is measured by the current sense amplifier, which
generates an output proportional to the switch current. The
sense signal is summed with the regulator’s corrective ramp
and compared to the error amplifier’s output, which is propor-
tional to the difference between the feedback voltage and
VREF. When the PWM comparator output goes high, the out-
put switch turns off until the next switching cycle begins.
During the switch off-time, inductor current discharges
through the Schottky catch diode, which forces the SW pin to
swing below ground by the forward voltage (VD) of the Schot-
tky catch diode. The regulator loop adjusts the duty cycle (D)
to maintain a constant output voltage.
The over-voltage comparator compares the FB pin voltage to
a voltage that is 15% higher than the internal reference
VREF. Once the FB pin voltage goes 15% above the internal
reference, the internal PMOS control switch is turned off,
which allows the output voltage to decrease toward regula-
tion.
UNDERVOLTAGE LOCKOUT
Under-voltage lockout (UVLO) prevents the LMR10515 from
operating until the input voltage exceeds 2.73V (typ). The
UVLO threshold has approximately 430 mV of hysteresis, so
the part will operate until VIN drops below 2.3V (typ). Hystere-
sis prevents the part from turning off during power up if VIN is
non-monotonic.
CURRENT LIMIT
The LMR10515 uses cycle-by-cycle current limiting to protect
the output switch. During each switching cycle, a current limit
comparator detects if the output switch current exceeds 2.5A
(typ), and turns off the switch until the next switching cycle
begins.
THERMAL SHUTDOWN
Thermal shutdown limits total power dissipation by turning off
the output switch when the IC junction temperature exceeds
165°C. After thermal shutdown occurs, the output switch
doesn’t turn on until the junction temperature drops to ap-
proximately 150°C.
11
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30166195
FIGURE 3. Typical Application Schematic
Design Guide
INDUCTOR SELECTION
The Duty Cycle (D) can be approximated quickly using the
ratio of output voltage (VO) to input voltage (VIN):
In general,
ΔiL = 0.1 x (IOUT) → 0.2 x (IOUT
)
If ΔiL = 20% of 1.50A, the peak current in the inductor will be
1.8A. The minimum guaranteed current limit over all operating
conditions is 1.8A. One can either reduce ΔiL, or make the
engineering judgment that zero margin will be safe enough.
The typical current limit is 2.5A.
The catch diode (D1) forward voltage drop and the voltage
drop across the internal PMOS must be included to calculate
a more accurate duty cycle. Calculate D by using the following
formula:
The LMR10515 operates at frequencies allowing the use of
ceramic output capacitors without compromising transient re-
sponse. Ceramic capacitors allow higher inductor ripple with-
out significantly increasing output ripple. See the output
capacitor section for more details on calculating output volt-
age ripple. Now that the ripple current is determined, the
inductance is calculated by:
VSW can be approximated by:
VSW = IOUT x RDSON
The diode forward drop (VD) can range from 0.3V to 0.7V de-
pending on the quality of the diode. The lower the VD, the
higher the operating efficiency of the converter. The inductor
value determines the output ripple current. Lower inductor
values decrease the size of the inductor, but increase the
output ripple current. An increase in the inductor value will
decrease the output ripple current.
Where
One must ensure that the minimum current limit (1.8A) is not
exceeded, so the peak current in the inductor must be calcu-
lated. The peak current (ILPK) in the inductor is calculated by:
When selecting an inductor, make sure that it is capable of
supporting the peak output current without saturating. Induc-
tor saturation will result in a sudden reduction in inductance
and prevent the regulator from operating correctly. Because
of the speed of the internal current limit, the peak current of
the inductor need only be specified for the required maximum
output current. For example, if the designed maximum output
current is 1.0A and the peak current is 1.25A, then the induc-
tor should be specified with a saturation current limit of >
1.25A. There is no need to specify the saturation or peak cur-
rent of the inductor at the 2.5A typical switch current limit. The
difference in inductor size is a factor of 5. Because of the op-
erating frequency of the LMR10515, ferrite based inductors
are preferred to minimize core losses. This presents little re-
striction since the variety of ferrite-based inductors is huge.
Lastly, inductors with lower series resistance (RDCR) will pro-
ILPK = IOUT + ΔiL
30166105
FIGURE 4. Inductor Current
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vide better operating efficiency. For recommended inductors
see Example Circuits.
tances in the inductor to the output. A ceramic capacitor will
bypass this noise while a tantalum will not. Since the output
capacitor is one of the two external components that control
the stability of the regulator control loop, most applications will
require a minimum of 22 µF of output capacitance. Capaci-
tance often, but not always, can be increased significantly
with little detriment to the regulator stability. Like the input ca-
pacitor, recommended multilayer ceramic capacitors are X7R
or X5R types.
INPUT CAPACITOR
An input capacitor is necessary to ensure that VIN does not
drop excessively during switching transients. The primary
specifications of the input capacitor are capacitance, voltage,
RMS current rating, and ESL (Equivalent Series Inductance).
The recommended input capacitance is 22 µF.The input volt-
age rating is specifically stated by the capacitor manufacturer.
Make sure to check any recommended deratings and also
verify if there is any significant change in capacitance at the
operating input voltage and the operating temperature. The
CATCH DIODE
The catch diode (D1) conducts during the switch off-time. A
Schottky diode is recommended for its fast switching times
and low forward voltage drop. The catch diode should be
chosen so that its current rating is greater than:
input capacitor maximum RMS input current rating (IRMS-IN
must be greater than:
)
ID1 = IOUT x (1-D)
The reverse breakdown rating of the diode must be at least
the maximum input voltage plus appropriate margin. To im-
prove efficiency, choose a Schottky diode with a low forward
voltage drop.
Neglecting inductor ripple simplifies the above equation to:
OUTPUT VOLTAGE
The output voltage is set using the following equation where
R2 is connected between the FB pin and GND, and R1 is
connected between VO and the FB pin. A good value for R2
is 10k. When designing a unity gain converter (Vo = 0.6V), R1
should be between 0Ω and 100Ω, and R2 should be equal or
greater than 10kΩ.
It can be shown from the above equation that maximum RMS
capacitor current occurs when D = 0.5. Always calculate the
RMS at the point where the duty cycle D is closest to 0.5. The
ESL of an input capacitor is usually determined by the effec-
tive cross sectional area of the current path. A large leaded
capacitor will have high ESL and a 0805 ceramic chip capac-
itor will have very low ESL. At the operating frequencies of the
LMR10515, leaded capacitors may have an ESL so large that
the resulting impedance (2πfL) will be higher than that re-
quired to provide stable operation. As a result, surface mount
capacitors are strongly recommended.
VREF = 0.60V
PCB LAYOUT CONSIDERATIONS
Sanyo POSCAP, Tantalum or Niobium, Panasonic SP, and
multilayer ceramic capacitors (MLCC) are all good choices for
both input and output capacitors and have very low ESL. For
MLCCs it is recommended to use X7R or X5R type capacitors
due to their tolerance and temperature characteristics. Con-
sult capacitor manufacturer datasheets to see how rated
capacitance varies over operating conditions.
When planning layout there are a few things to consider when
trying to achieve a clean, regulated output. The most impor-
tant consideration is the close coupling of the GND connec-
tions of the input capacitor and the catch diode D1. These
ground ends should be close to one another and be connect-
ed to the GND plane with at least two through-holes. Place
these components as close to the IC as possible. Next in im-
portance is the location of the GND connection of the output
capacitor, which should be near the GND connections of CIN
and D1. There should be a continuous ground plane on the
bottom layer of a two-layer board except under the switching
node island. The FB pin is a high impedance node and care
should be taken to make the FB trace short to avoid noise
pickup and inaccurate regulation. The feedback resistors
should be placed as close as possible to the IC, with the GND
of R1 placed as close as possible to the GND of the IC. The
VOUT trace to R2 should be routed away from the inductor and
any other traces that are switching. High AC currents flow
through the VIN, SW and VOUT traces, so they should be as
short and wide as possible. However, making the traces wide
increases radiated noise, so the designer must make this
trade-off. Radiated noise can be decreased by choosing a
shielded inductor. The remaining components should also be
placed as close as possible to the IC. Please see Application
Note AN-1229 for further considerations and the LMR10515
demo board as an example of a good layout.
OUTPUT CAPACITOR
The output capacitor is selected based upon the desired out-
put ripple and transient response. The initial current of a load
transient is provided mainly by the output capacitor. The out-
put ripple of the converter is:
When using MLCCs, the ESR is typically so low that the ca-
pacitive ripple may dominate. When this occurs, the output
ripple will be approximately sinusoidal and 90° phase shifted
from the switching action. Given the availability and quality of
MLCCs and the expected output voltage of designs using the
LMR10515, there is really no need to review any other ca-
pacitor technologies. Another benefit of ceramic capacitors is
their ability to bypass high frequency noise. A certain amount
of switching edge noise will couple through parasitic capaci-
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If the inductor ripple current is fairly small, the conduction
losses can be simplified to:
Calculating Efficiency, and Junction
Temperature
The complete LMR10515 DC/DC converter efficiency can be
calculated in the following manner.
PCOND = IOUT2 x RDSON x D
Switching losses are also associated with the internal PFET.
They occur during the switch on and off transition periods,
where voltages and currents overlap resulting in power loss.
The simplest means to determine this loss is to empirically
measuring the rise and fall times (10% to 90%) of the switch
at the switch node.
Switching Power Loss is calculated as follows:
Or
PSWR = 1/2(VIN x IOUT x FSW x TRISE
)
PSWF = 1/2(VIN x IOUT x FSW x TFALL
PSW = PSWR + PSWF
)
Another loss is the power required for operation of the internal
circuitry:
Calculations for determining the most significant power loss-
es are shown below. Other losses totaling less than 2% are
not discussed.
PQ = IQ x VIN
IQ is the quiescent operating current, and is typically
around3.3 mA for the 1.6 MHz frequency option.
Power loss (PLOSS) is the sum of two basic types of losses in
the converter: switching and conduction. Conduction losses
usually dominate at higher output loads, whereas switching
losses remain relatively fixed and dominate at lower output
loads. The first step in determining the losses is to calculate
the duty cycle (D):
Typical Application power losses are:
Power Loss Tabulation
VIN
VOUT
IOUT
VD
5.0V
3.3V
POUT
4.125W
188mW
1.25A
0.45V
1.6MHz
3.3mA
4nS
PDIODE
FSW
IQ
VSW is the voltage drop across the internal PFET when it is
on, and is equal to:
PQ
PSWR
16.5mW
20mW
TRISE
TFALL
RDS(ON)
INDDCR
D
4nS
PSWF
20mW
VSW = IOUT x RDSON
PCOND
PIND
PLOSS
PINTERNAL
156mW
110mW
511mW
213mW
150mΩ
70mΩ
0.667
88%
VD is the forward voltage drop across the Schottky catch
diode. It can be obtained from the diode manufactures Elec-
trical Characteristics section. If the voltage drop across the
inductor (VDCR) is accounted for, the equation becomes:
η
ΣPCOND + PSW + PDIODE + PIND + PQ = PLOSS
ΣPCOND + PSWF + PSWR + PQ = PINTERNAL
PINTERNAL = 213 mW
The conduction losses in the free-wheeling Schottky diode
are calculated as follows:
Thermal Definitions
TJ = Chip junction temperature
TA = Ambient temperature
PDIODE = VD x IOUT x (1-D)
RθJC = Thermal resistance from chip junction to device case
RθJA = Thermal resistance from chip junction to ambient air
Heat in the LMR10515 due to internal power dissipation is
removed through conduction and/or convection.
Often this is the single most significant power loss in the cir-
cuit. Care should be taken to choose a Schottky diode that
has a low forward voltage drop.
Conduction: Heat transfer occurs through cross sectional ar-
eas of material. Depending on the material, the transfer of
heat can be considered to have poor to good thermal con-
ductivity properties (insulator vs. conductor).
Another significant external power loss is the conduction loss
in the output inductor. The equation can be simplified to:
PIND = IOUT2 x RDCR
Heat Transfer goes as:
The LMR10515 conduction loss is mainly associated with the
internal PFET:
Silicon → package → lead frame → PCB
Convection: Heat transfer is by means of airflow. This could
be from a fan or natural convection. Natural convection occurs
when air currents rise from the hot device to cooler air.
Thermal impedance is defined as:
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14
Thermal impedance from the silicon junction to the ambient
air is defined as:
Once this is determined, the maximum ambient temperature
allowed for a desired junction temperature can be found.
An example of calculating RθJA for an application using the
LMR10515 is shown below.
A sample PCB is placed in an oven with no forced airflow. The
ambient temperature was raised to 140°C, and at that tem-
perature, the device went into thermal shutdown.
The PCB size, weight of copper used to route traces and
ground plane, and number of layers within the PCB can great-
ly effect RθJA. The type and number of thermal vias can also
make a large difference in the thermal impedance. Thermal
vias are necessary in most applications. They conduct heat
from the surface of the PCB to the ground plane. Four to six
thermal vias should be placed under the exposed pad to the
ground plane if the LLP package is used.
From the previous example:
PINTERNAL = 213 mW
Thermal impedance also depends on the thermal properties
of the application operating conditions (Vin, Vo, Io etc), and
the surrounding circuitry.
Since the junction temperature must be kept below 125°C,
then the maximum ambient temperature can be calculated as:
Silicon Junction Temperature Determination Method 1:
To accurately measure the silicon temperature for a given
application, two methods can be used. The first method re-
quires the user to know the thermal impedance of the silicon
junction to case temperature.
Tj - (RθJA x PLOSS) = TA
125°C - (117°C/W x 213 mW) = 100°C
LLP Package
RθJC is approximately 18°C/Watt for the 6-pin LLP package
with the exposed pad. Knowing the internal dissipation from
the efficiency calculation given previously, and the case tem-
perature, which can be empirically measured on the bench
we have:
where TC is the temperature of the exposed pad and can be
measured on the bottom side of the PCB.
30166168
Therefore:
FIGURE 5. Internal LLP Connection
Tj = (RθJC x PLOSS) + TC
From the previous example:
Tj = (RθJC x PINTERNAL) + TC
Tj = 18°C/W x 0.213W + TC
For certain high power applications, the PCB land may be
modified to a "dog bone" shape (see Figure 6). By increasing
the size of ground plane, and adding thermal vias, the RθJA
for the application can be reduced.
The second method can give a very accurate silicon junction
temperature.
The first step is to determine RθJA of the application. The
LMR10515 has over-temperature protection circuitry. When
the silicon temperature reaches 165°C, the device stops
switching. The protection circuitry has a hysteresis of about
15°C. Once the silicon temperature has decreased to approx-
imately 150°C, the device will start to switch again. Knowing
this, the RθJA for any application can be characterized during
the early stages of the design one may calculate the RθJA by
placing the PCB circuit into a thermal chamber. Raise the
ambient temperature in the given working application until the
circuit enters thermal shutdown. If the SW-pin is monitored, it
will be obvious when the internal PFET stops switching, indi-
cating a junction temperature of 165°C. Knowing the internal
power dissipation from the above methods, the junction tem-
perature, and the ambient temperature RθJA can be deter-
mined.
30166106
FIGURE 6. 6-Lead LLP PCB Dog Bone Layout
15
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LMR10515X Design Example 1
30166107
FIGURE 7. LMR10515X (1.6MHz): Vin = 5V, Vo = 1.2V @ 1.5A
LMR10515X Design Example 2
30166160
FIGURE 8. LMR10515X (1.6MHz): Vin = 5V, Vo = 3.3V @ 1.5A
www.ti.com
16
LMR10515Y Design Example 3
30166108
FIGURE 9. LMR10515Y (3MHz): Vin = 5V, Vo = 3.3V @ 1.5A
LMR10515Y Design Example 4
30166162
FIGURE 10. LMR10515Y (3MHz): Vin = 5V, Vo = 1.2V @ 1.5A
17
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Physical Dimensions inches (millimeters) unless otherwise noted
5-Lead SOT-23 Package
NS Package Number MF05A
6-Lead LLP Package
NS Package Number SDE06A
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18
Notes
19
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Notes
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