LMR14050 [TI]
具有 40μA IQ 的 SIMPLE SWITCHER®、40V、5A 2.2MHz 降压转换器;
| 型号： | LMR14050 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 40μA IQ 的 SIMPLE SWITCHER®、40V、5A 2.2MHz 降压转换器 转换器 |
| 文件： | 总34页 (文件大小：1346K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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LMR14050
ZHCSDH4A –FEBRUARY 2015–REVISED MARCH 2015
LMR14050 SIMPLE SWITCHER® 40V 5A、2.2MHz 降压转换器，具有
40μA IQ
1 特性
3 说明
1
•
输入电压范围：4V 至 40V
5A 持续输出电流
LMR14050 器件是一款具有集成型高侧 MOSFET 的
40V、5A 降压稳压器。 该器件具有 4V 至 40V 的宽输
入电压范围，适用于从工业到汽车各类应用中非稳压电
源的电源调节。 该稳压器在休眠模式下的静态电流为
40µA，非常适合电池供电类系统。 并且在关断模式下
具有 1μA 的超低电流，可进一步延长电池使用寿命。
该稳压器的可调开关频率范围较宽，这使得效率或外部
元件尺寸能够得到优化。 内部环路补偿意味着用户不
用承担设计环路补偿组件的枯燥工作。 并且还能够以
最大限度减少器件的外部元件数。 精密使能输入简化
了稳压器控制和系统电源排序。 此外，该器件还内置
多种保护特性：逐周期电流限制保护、应对功耗过大的
热感测和热关断保护、以及输出过压保护。
•
•
•
40µA 超低工作静态电流
90mΩ 高侧金属氧化物半导体场效应晶体
(MOSFET)
•
•
•
•
•
•
•
•
•
•
•
最短导通时间：75ns
电流模式控制
可调节开关频率范围：200kHz 至 2.5MHz
与外部时钟频率同步
内部补偿方便使用
支持高占空比运行
精密使能引脚
关断电流：1µA
外部软启动
器件信息(1)
热保护、过压保护和短路保护
8 引脚 HSOIC PowerPAD™ 封装
器件型号
封装
封装尺寸（标称值）
LMR14050SDDA
HSOIC-8
4.89mm x 3.90mm
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
2 应用范围
•
•
•
•
汽车电池稳压
工业用电源
电信和数据通信系统
电池供电系统
4 简化电路原理图
VIN up to 40 V
效率与输出电流间的关系
CIN
VIN
100
90
80
70
60
50
40
30
BOOT
SW
EN
CBOOT
L
VOUT
RT/SYNC
RT
D
RFBT
COUT
SS
RFBB
FB
CSS
GND
20
VOUT = 5 V
VOUT = 3.3 V
10
0
VIN = 12 V, gSW = 300 kHz
0.01
0.001
0.1
1 10
IOUT (A)
D001
1
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
English Data Sheet: SNVSAA6
LMR14050
ZHCSDH4A –FEBRUARY 2015–REVISED MARCH 2015
www.ti.com.cn
目录
8.1 Overview ................................................................... 8
8.2 Functional Block Diagram ......................................... 8
8.3 Feature Description................................................... 9
Application and Implementation ........................ 15
9.1 Application Information............................................ 15
9.2 Typical Application ................................................. 15
1
2
3
4
5
6
7
特性.......................................................................... 1
应用范围................................................................... 1
说明.......................................................................... 1
简化电路原理图........................................................ 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4
7.2 ESD Ratings.............................................................. 4
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information.................................................. 4
7.5 Electrical Characteristics........................................... 5
7.6 Switching Characteristics.......................................... 5
7.7 Typical Characteristics.............................................. 6
Detailed Description .............................................. 8
9
10 Power Supply Recommendations ..................... 21
11 Layout................................................................... 21
11.1 Layout Guidelines ................................................. 21
11.2 Layout Example .................................................... 22
12 器件和文档支持 ..................................................... 23
12.1 商标....................................................................... 23
12.2 静电放电警告......................................................... 23
12.3 术语表 ................................................................... 23
13 机械封装和可订购信息 .......................................... 24
8
5 修订历史记录
Changes from Original (February 2015) to Revision A
Page
•
已更改 “产品预览”至“量产数据”。 .......................................................................................................................................... 1
2
Copyright © 2015, Texas Instruments Incorporated
LMR14050
www.ti.com.cn
ZHCSDH4A –FEBRUARY 2015–REVISED MARCH 2015
6 Pin Configuration and Functions
HSOIC
8-Pin
Top View
HSOIC PACKAGE
(TOP VIEW)
BOOT
SW
1
8
VIN
GND
SS
2
3
4
7
6
5
Thermal Pad
(9)
EN
RT/SYNC
FB
Pin Functions
DESCRIPTION
(1)
PIN
TYPE
NAME
NO.
BOOT
1
O
I
Bootstrap capacitor connection for high-side MOSFET driver. Connect a high quality 0.1 μF
capacitor from BOOT to SW.
VIN
EN
2
3
Connect to power supply and bypass capacitors CIN. Path from VIN pin to high frequency
bypass CIN and GND must be as short as possible.
I
Enable pin, with internal pull-up current source. Pull below 1.2 V to disable. Float or connect
to VIN to enable. Adjust the input under voltage lockout with two resistors. See the Enable
and Adjusting Under voltage lockout section.
RT/SYNC
4
I
Resistor Timing or External Clock input. An internal amplifier holds this pin at a fixed voltage
when using an external resistor to ground to set the switching frequency. If the pin is pulled
above the PLL upper threshold, a mode change occurs and the pin becomes a
synchronization input. The internal amplifier is disabled and the pin is a high impedance clock
input to the internal PLL. If clocking edges stop, the internal amplifier is re-enabled and the
operating mode returns to frequency programming by resistor.
FB
5
I
Feedback input pin, connect to the feedback divider to set VOUT. Do not short this pin to
ground during operation.
SS
GND
SW
6
7
8
O
G
O
Soft-start control pin. Connect to a capacitor to set soft-start time.
System ground pin.
Switching output of the regulator. Internally connected to high-side power MOSFET. Connect
to power inductor.
Thermal Pad
9
G
Major heat dissipation path of the die. Must be connected to ground plane on PCB.
(1) I = Input, O = Output, G = Ground
Copyright © 2015, Texas Instruments Incorporated
3
LMR14050
ZHCSDH4A –FEBRUARY 2015–REVISED MARCH 2015
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
-0.3
-0.3
-0.3
-0.3
-0.3
MAX
44
UNIT
VIN, EN to GND
BOOT to GND
49
Input Voltages
SS to GND
5
V
FB to GND
7
RT/SYNC to GND
BOOT to SW
3.6
6.5
44
Output Voltages
V
SW to GND
-3
TJ
Junction temperature
Storage temperature
-40
-65
150
150
°C
°C
Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
PARAMETER
DEFINITION
Human body model (HBM)(1)
Charged device model (CDM)(2)
VALUE
UNIT
2
Electrostatic
discharge
V(ESD)
kV
0.5
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4
MAX
UNIT
VIN
40
28
VOUT
0.8
Buck Regulator
Control
BOOT
45
V
V
SW
-1
0
40
FB
5
EN
0
40
RT/SYNC
0
3.3
3
SS
0
Switching frequency range at RT mode
Switching frequency range at SYNC mode
Operating junction temperature, TJ
200
250
-40
2500
2300
125
Frequency
kHz
°C
Temperature
7.4 Thermal Information
DDA
8 PINS
42.5
9.9
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (top) thermal resistance
Junction-to-case (bottom) thermal resistance
Junction-to-board thermal resistance
ψJT
ψJB
25.4
56.1
3.8
°C/W
RθJC(top)
RθJC(bot)
RθJB
25.5
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
4
Copyright © 2015, Texas Instruments Incorporated
LMR14050
www.ti.com.cn
ZHCSDH4A –FEBRUARY 2015–REVISED MARCH 2015
7.5 Electrical Characteristics
Limits apply over the recommended operating junction temperature (TJ) range of -40°C to +125°C, unless otherwise stated.
Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise specified, the following
conditions apply: VIN = 4.0 V to 40 V
PARAMETER
POWER SUPPLY (VIN PIN)
TEST CONDITION
MIN
TYP
MAX UNIT
VIN
Operation input voltage
4
40
V
V
UVLO
Under voltage lockout thresholds
Rising threshold
3.5
3.7
285
1.0
40
3.9
Hysteresis
mV
μA
μA
ISHDN
IQ
Shutdown supply current
VEN = 0 V, TA = 25°C, 4.0 V ≤ VIN ≤ 40 V
VFB = 1.0 V, TA = 25°C
3.0
Operating quiescent current (non-
switching)
ENABLE (EN PIN)
VEN_TH
EN Threshold Voltage
EN PIN current
1.05
1.20
-4.6
-1.0
-3.6
1.38
V
IEN_PIN
Enable threshold +50 mV
Enable threshold -50 mV
μA
μA
IEN_HYS
EN hysteresis current
EXTERNAL SOFT-START
ISS
SS pin current
TA = 25°C
3
μA
VOLTAGE REFERENCE (FB PIN)
VFB
Feedback voltage
TJ = 25°C
0.744 0.750 0.756
0.735 0.750 0.765
V
V
TJ = -40°C to 125°C
HIGH-SIDE MOSFET
RDS_ON
On-resistance
VIN = 12 V, BOOT to SW = 5.8 V
VIN = 12 V, TA = 25°C, Open Loop
90
180
9.7
mΩ
High-side MOSFET CURRENT LIMIT
ILIMT
THERMAL PERFORMANCE
TSHDN Thermal shutdown threshold
THYS Hysteresis
Current limit
6.2
7.9
A
170
12
°C
7.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
400
1.7
TYP MAX UNIT
fSW
Switching frequency
RT = 49.9 kΩ, 1% accuracy
500
600
kHz
VSYNC_HI
VSYNC_LO
TSYNC_MIN
SYNC clock high level threshold
SYNC clock low level threshold
Minimum SYNC input pulse width
V
0.5
Measured at 500 kHz, VSYNC_HI > 3 V,
VSYNC_LO < 0.3 V
30
ns
TLOCK_IN
TON_MIN
PLL lock in time
Measured at 500 kHz
100
75
µs
ns
Minimum controllable on time
VIN = 12 V, BOOT to SW = 5.8 V, ILoad
1 A
=
DMAX
Maximum duty cycle
fSW = 200 kHz
97
%
Copyright © 2015, Texas Instruments Incorporated
5
LMR14050
ZHCSDH4A –FEBRUARY 2015–REVISED MARCH 2015
www.ti.com.cn
7.7 Typical Characteristics
Unless otherwise specified the following conditions apply: VIN = 12 V, fSW = 300 kHz, L = 6.5 µH, COUT = 47 µF x 4, TA = 25°C
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VIN = 36 V
VIN = 24 V
VIN = 12 V
VIN = 36 V
VIN = 24 V
VIN = 12 V
0.001
0.01
0.1
1
10
0.001
0.01
0.1
1
10
IOUT (A)
IOUT (A)
D002
D003
VOUT = 5 V
fSW = 500 kHz
VOUT = 5 V
fSW = 1 MHz
Figure 1. Efficiency vs. Load Current
Figure 2. Efficiency vs. Load Current
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VIN = 24 V
VIN = 12 V
VIN = 5 V
VIN = 24 V
VIN = 12 V
VIN = 5 V
0.001
0.01
0.1
1
10
0.001
0.01
0.1
1
10
IOUT (A)
IOUT (A)
D009
D010
VOUT = 3.3 V
fSW = 1 MHz
VOUT = 3.3 V
fSW = 2.2 MHz
Figure 3. Efficiency vs. Load Current
Figure 4. Efficiency vs. Load Current
125
100
75
50
25
0
0.08
0.06
0.04
0.02
0
VFB Falling
VFB Rising
VIN = 36 V
VIN = 24 V
VIN = 12 V
-0.02
-0.04
-0.06
-0.08
0.001
0.01
0.1
1
10
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
IOUT (A)
VFB (V)
D004
D005
VOUT = 5 V
fSW = 500 kHz
VOUT = 5 V
fSW = 500 kHz
Figure 6. Frequency vs VFB
Figure 5. Load Regulation
6
Copyright © 2015, Texas Instruments Incorporated
LMR14050
www.ti.com.cn
ZHCSDH4A –FEBRUARY 2015–REVISED MARCH 2015
Typical Characteristics (continued)
Unless otherwise specified the following conditions apply: VIN = 12 V, fSW = 300 kHz, L = 6.5 µH, COUT = 47 µF x 4, TA = 25°C
6
5
4
3
2
6
5
4
3
2
IOUT = 5 A
IOUT = 2.5 A
IOUT = 0.5 A
IOUT = 5 A
IOUT = 2.5 A
IOUT = 0.5 A
4
4.5
5
5.5
6
6.5
4
4.5
5
5.5
6
6.5
VIN (V)
VIN (V)
D011
D012
VOUT = 5 V
fSW = 500 kHz
VOUT = 5V
fSW = 1 MHz
Figure 8. Dropout Curve
Figure 7. Dropout Curve
3.6
3.3
3
3.6
3.3
3
2.7
2.4
2.1
1.8
1.5
2.7
2.4
2.1
1.8
1.5
IOUT = 5 A
IOUT = 2.5 A
IOUT = 0.5 A
IOUT = 5 A
IOUT = 2.5 A
IOUT = 0.5 A
3.6
3.8
4
4.2
4.4
4.6
4.8
5
3.6
3.8
4
4.2
4.4
4.6
4.8
5
VIN (V)
VIN (V)
D013
D014
VOUT = 5 V
fSW = 2.2 MHz
VOUT = 3.3 V
fSW = 2.2 MHz
Figure 10. Dropout Curve
Figure 9. Dropout Curve
45
40
35
30
25
20
15
10
5
3.75
3.7
3.65
3.6
IQ
UVLO_H
3.55
3.5
UVLO_L
ISHDN
3.45
3.4
0
0
5
10
15
20
25
30
35
40
45
-50
-25
0
25
50
75
100
125
150
VIN (V)
Temperature (°C)
D006
D007
IOUT = 0 A
Figure 11. Shut-down Current and Quiescent Current
Figure 12. UVLO Threshold
Copyright © 2015, Texas Instruments Incorporated
7
LMR14050
ZHCSDH4A –FEBRUARY 2015–REVISED MARCH 2015
www.ti.com.cn
8 Detailed Description
8.1 Overview
The LMR14050 SIMPLE SWITCHER® regulator is an easy to use step-down DC-DC converter that operates
from 4.0 V to 40 V supply voltage. It integrates a 90 mΩ (typical) high-side MOSFET, and is capable of delivering
up to 5 A DC load current with exceptional efficiency and thermal performance in a very small solution size. The
operating current is typically 40 μA under no load condition (not switching). When the device is disabled, the
supply current is typically 1 μA. An extended family is available in 2 A and 3.5 A load options in pin to pin
compatible packages.
The LMR14050 implements constant frequency peak current mode control with Sleep-mode at light load to
achieve high efficiency. The device is internally compensated, which reduces design time, and requires fewer
external components. The switching frequency is programmable from 200 kHz to 2.5 MHz by an external resistor
RT. The LMR14050 is also capable of synchronization to an external clock within the 250 kHz to 2.3 MHz
frequency range, which allows the device to be optimized to fit small board space at higher frequency, or high
efficient power conversion at lower frequency.
Other optional features are included for more comprehensive system requirements, including precision enable,
adjustable soft-start time, and approximate 97% duty cycle by BOOT capacitor recharge circuit. These features
provide a flexible and easy to use platform for a wide range of applications. Protection features include over
temperature shutdown, VOUT over voltage protection (OVP), VIN under-voltage lockout (UVLO), cycle-by-cycle
current limit, and short-circuit protection with frequency fold-back.
8.2 Functional Block Diagram
EN
VIN
Thermal
Shutdown
UVLO
Enable
Comparator
Shutdown
Shutdown
Logic
Voltage
Reference
Enable
Threshold
Boot
Charge
OV
Boot
UVLO
ERROR
AMPLIFIER
PWM
Comparator
FB
BOOT
PWM
Control
Logic
Comp
Components
Shutdown
Slope
Compensation
6
SW
Frequency
Shift
Bootstrap
Control
VIN
Oscillator
with PLL
SS
GND
RT/SYNC
8
Copyright © 2015, Texas Instruments Incorporated
LMR14050
www.ti.com.cn
ZHCSDH4A –FEBRUARY 2015–REVISED MARCH 2015
8.3 Feature Description
8.3.1 Fixed Frequency Peak Current Mode Control
The following operation description of the LMR14050 will refer to the Function Block Diagram and to the
waveforms in Figure 13. LMR14050 output voltage is regulated by turning on the high-side N-MOSFET with
controlled ON time. During high-side switch ON time, the SW pin voltage swings up to approximately VIN, and the
inductor current iL increase with linear slope (VIN – VOUT) / L. When high-side switch is off, inductor current
discharges through freewheel diode with a slope of –VOUT / L. The control parameter of Buck converter is defined
as Duty Cycle D = tON /TSW, where tON is the high-side switch ON time and TSW is the switching period. The
regulator control loop maintains a constant output voltage by adjusting the duty cycle D. In an ideal Buck
converter, where losses are ignored, D is proportional to the output voltage and inversely proportional to the input
voltage: D = VOUT / VIN.
VSW
D = tON/ TSW
VIN
tON
tOFF
t
0
-VD
TSW
iL
ILPK
IOUT
ûiL
t
0
Figure 13. SW Node and Inductor Current Waveforms in
Continuous Conduction Mode (CCM)
The LMR14050 employs fixed frequency peak current mode control. A voltage feedback loop is used to get
accurate DC voltage regulation by adjusting the peak current command based on voltage offset. The peak
inductor current is sensed from the high-side switch and compared to the peak current to control the ON time of
the high-side switch. The voltage feedback loop is internally compensated, which allows for fewer external
components, makes it easy to design, and provides stable operation with almost any combination of output
capacitors. The regulator operates with fixed switching frequency at normal load condition. At very light load, the
LMR14050 will operate in Sleep-mode to maintain high efficiency and the switching frequency will decrease with
reduced load current.
8.3.2 Slope Compensation
The LMR14050 adds a compensating ramp to the MOSFET switch current sense signal. This slope
compensation prevents sub-harmonic oscillations at duty cycle greater than 50%. The peak current limit of the
high-side switch is not affected by the slope compensation and remains constant over the full duty cycle range.
8.3.3 Sleep-mode
The LMR14050 operates in Sleep-mode at light load currents to improve efficiency by reducing switching and
gate drive losses. If the output voltage is within regulation and the peak switch current at the end of any
switching cycle is below the current threshold of 300 mA, the device enters Sleep-mode. The Sleep-mode current
threshold is the peak switch current level corresponding to a nominal internal COMP voltage of 400 mV.
When in Sleep-mode, the internal COMP voltage is clamped at 400 mV and the high-side MOSFET is inhibited,
and the device draws only 40 μA (typical) input quiescent current. Since the device is not switching, the output
voltage begins to decay. The voltage control loop responds to the falling output voltage by increasing the internal
COMP voltage. The high-side MOSFET is enabled and switching resumes when the error amplifier lifts internal
COMP voltage above 400 mV. The output voltage recovers to the regulated value, and internal COMP voltage
eventually falls below the Sleep-mode threshold at which time the device again enters Sleep-mode.
Copyright © 2015, Texas Instruments Incorporated
9
LMR14050
ZHCSDH4A –FEBRUARY 2015–REVISED MARCH 2015
www.ti.com.cn
Feature Description (continued)
8.3.4 Low Dropout Operation and Bootstrap Voltage (BOOT)
The LMR14050 provides an integrated bootstrap voltage regulator. A small capacitor between the BOOT and
SW pins provides the gate drive voltage for the high-side MOSFET. The BOOT capacitor is refreshed when the
high-side MOSFET is off and the external low side diode conducts. The recommended value of the BOOT
capacitor is 0.1 μF. A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 16 V or
higher is recommended for stable performance over temperature and voltage.
When operating with a low voltage difference from input to output, the high-side MOSFET of the LMR14050 will
operate at approximate 97% duty cycle. When the high-side MOSFET is continuously on for 5 or 6 switching
cycles (5 or 6 switching cycles for frequency lower than 1 MHz, and 10 or 11 switching cycles for frequency
higher than 1MHz) and the voltage from BOOT to SW drops below 3.2 V, the high-side MOSFET is turned off
and an integrated low side MOSFET pulls SW low to recharge the BOOT capacitor.
Since the gate drive current sourced from the BOOT capacitor is small, the high-side MOSFET can remain on for
many switching cycles before the MOSFET is turned off to refresh the capacitor. Thus the effective duty cycle of
the switching regulator can be high, approaching 97%. The effective duty cycle of the converter during dropout is
mainly influenced by the voltage drops across the power MOSFET, the inductor resistance, the low side diode
voltage and the printed circuit board resistance.
8.3.5 Adjustable Output Voltage
The internal voltage reference produces a precise 0.75 V (typical) voltage reference over the operating
temperature. The output voltage is set by a resistor divider from output voltage to the FB pin. It is recommended
to use 1% tolerance or better and temperature coefficient of 100 ppm or lower divider resistors. Select the low
side resistor RFBB for the desired divider current and use Equation 1 to calculate high-side RFBT. Larger value
divider resistors are good for efficiency at light load. However, if the values are too high, the regulator will be
more susceptible to noise and voltage errors from the FB input current may become noticeable. RFBB in the
range from 10 kΩ to 100 kΩ is recommended for most applications.
V
OUT
R
FBT
FBB
FB
R
Figure 14. Output Voltage Setting
VOUT ꢀ 0.75
RFBT
RFBB
0.75
(1)
8.3.6 Enable and Adjustable Under-voltage Lockout
The LMR14050 is enabled when the VIN pin voltage rises above 3.7 V (typical) and the EN pin voltage exceeds
the enable threshold of 1.2 V (typical). The LMR14050 is disabled when the VIN pin voltage falls below 3.52 V
(typical) or when the EN pin voltage is below 1.2 V. The EN pin has an internal pull-up current source (typically
IEN = 1 μA) that enables operation of the LMR14050 when the EN pin is floating.
Many applications will benefit from the employment of an enable divider RENT and RENB in Figure 13 to establish
a precision system UVLO level for the stage. System UVLO can be used for supplies operating from utility power
as well as battery power. It can be used for sequencing, ensuring reliable operation, or supply protection, such
as a battery. An external logic signal can also be used to drive EN input for system sequencing and protection.
When EN terminal voltage exceeds 1.2 V, an additional hysteresis current (typically IHYS = 3.6 μA) is sourced out
of EN terminal. When the EN terminal is pulled below 1.2 V, IHYS current is removed. This additional current
facilitates adjustable input voltage UVLO hysteresis. Use Equation 2 and Equation 3
Equation 3 to calculate RENT and RENB for desired UVLO hysteresis voltage.
10
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Feature Description (continued)
I
I
EN
EN_HYS
VIN
EN
V
IN
R
R
ENT
V
EN
ENB
Figure 15. System UVLO By Enable Dividers
VSTART ꢀ VSTOP
RENT
IHYS
(2)
(3)
VEN
VSTART ꢀ VEN
RENB
ꢁ IEN
RENT
where VSTART is the desired voltage threshold to enable LMR14050, VSTOP is the desired voltage threshold to
disable device.
8.3.7 External Soft-start
The LMR14050 has soft-start pin for programmable output ramp up time. The soft-start feature is used to prevent
inrush current impacting the LMR14050 and its load when power is first applied. The soft-start time can be
programed by connecting an external capacitor CSS from SS pin to GND. An internal current source (typically ISS
= 3 μA) charges CSS and generates a ramp from 0V to VREF. The soft-start time can be calculated by Equation 4:
CSS(nF)u VREF(V)
tSS(ms)
ISS(PA)
(4)
The internal soft-start resets while device is disabled or in thermal shutdown.
8.3.8 Switching Frequency and Synchronization (RT/SYNC)
The switching frequency of the LMR14050 can be programmed by the resistor RT from the RT/SYNC pin and
GND pin. The RT/SYNC pin can’t be left floating or shorted to ground. To determine the timing resistance for a
given switching frequency, use Equation 5 or the curve in Figure 16. Table 1 gives typical RT values for a given
fSW
.
RT(k:) 32537u ¦SW ꢀN+]ꢁꢀ1.045
(5)
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Feature Description (continued)
140
120
100
80
60
40
20
0
0
500
1000
1500
2000
2500
Frequency (kHz)
D008
Figure 16. RT vs Frequency Curve
Table 1. Typical Frequency Setting RT Resistance
fSW (kHz)
RT (kΩ)
127
200
350
71.5
49.9
32.4
23.7
15.8
11.5
10.5
500
750
1000
1500
2000
2200
The LMR14050 switching action can also be synchronized to an external clock from 250 kHz to 2.3 MHz.
Connect a square wave to the RT/SYNC pin through either circuit network shown in Figure 17. Internal oscillator
is synchronized by the falling edge of external clock. The recommendations for the external clock include: high
level no lower than 1.7 V, low level no higher than 0.5 V and have a pulse width greater than 30 ns. When using
a low impedance signal source, the frequency setting resistor RT is connected in parallel with an AC coupling
capacitor CCOUP to a termination resistor RTERM (e.g., 50 Ω). The two resistors in series provide the default
frequency setting resistance when the signal source is turned off. A 10 pF ceramic capacitor can be used for
CCOUP. Figure 18, Figure 19 and Figure 20 show the device synchronized to an external system clock.
C
COUP
PLL
RT/SYNC
PLL
RT/SYNC
R
T
Lo-Z
Clock
Source
Hi-Z
Clock
Source
R
T
R
TERM
Figure 17. Synchronizing to an External Clock
12
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SYNC (2 V/DIV)
SYNC (2 V/DIV)
SW (5 V/DIV)
SW (5 V/DIV)
iL (2 A/DIV)
iL (500 mA/DIV)
Time (4 µs/DIV)
Time (4 µs/DIV)
Figure 18. Synchronizing in CCM
Figure 19. Synchronizing in DCM
SYNC (2 V/DIV)
SW (5 V/DIV)
iL (500 mA/DIV)
Time (4 µs/DIV)
Figure 20. Synchronizing in Sleep-mode Mode
Equation 6 calculates the maximum switching frequency limitation set by the minimum controllable on time and
the input to output step down ratio. Setting the switching frequency above this value will cause the regulator to
skip switching pulses to achieve the low duty cycle required at maximum input voltage.
§
·
IOUT uRIND ꢀ VOUT ꢀ VD
V ꢁIOUT uRDS_ON ꢀ VD
IN_MAX
1
¦
u
¨
¨
©
¸
¸
¹
SW(max)
tON
(6)
where
•
•
•
•
•
•
•
IOUT = Output current
RIND = Inductor series resistance
VIN_MAX = Maximum input voltage
VOUT = Output voltage
VD = Diode voltage drop
RDS_ON = High-side MOSFET switch on resistance
tON = Minimum on time
8.3.9 Over Current and Short Circuit Protection
The LMR14050 is protected from over current condition by cycle-by-cycle current limiting on the peak current of
the high-side MOSFET. High-side MOSFET over-current protection is implemented by the nature of the Peak
Current Mode control. The high-side switch current is compared to the output of the Error Amplifier (EA) minus
slope compensation every switching cycle. Please refer to Functional Block Diagram for more details. The peak
current of high-side switch is limited by a clamped maximum peak current threshold which is constant. So the
peak current limit of the high-side switch is not affected by the slope compensation and remains constant over
the full duty cycle range.
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The LMR14050 also implements a frequency fold-back to protect the converter in severe over-current or short
conditions. The oscillator frequency is divided by 2, 4, and 8 as the FB pin voltage decrease to 75%, 50%, 25%
of VREF. The frequency fold-back increases the off time by increasing the period of the switching cycle, so that it
provides more time for the inductor current to ramp down and leads to a lower average inductor current. Lower
frequency also means lower switching loss. Frequency fold-back reduces power dissipation and prevents
overheating and potential damage to the device.
8.3.10 Overvoltage Protection
The LMR14050 employs an output overvoltage protection (OVP) circuit to minimize voltage overshoot when
recovering from output fault conditions or strong unload transients in designs with low output capacitance. The
OVP feature minimizes output overshoot by turning off high-side switch immediately when FB voltage reaches to
the rising OVP threshold which is nominally 109% of the internal voltage reference VREF. When the FB voltage
drops below the falling OVP threshold which is nominally 107% of VREF, the high-side MOSFET resumes normal
operation.
8.3.11 Thermal Shutdown
The LMR14050 provides an internal thermal shutdown to protect the device when the junction temperature
exceeds 170°C (typical). The high-side MOSFET stops switching when thermal shundown activates. Once the
die temperature falls below 158°C (typical), the device reinitiates the power up sequence controlled by the
internal soft-start circuitry.
14
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The LMR14050 is a step down DC-to-DC regulator. It is typically used to convert a higher DC voltage to a lower
DC voltage with a maximum output current of 5 A. The following design procedure can be used to select
components for the LMR14050. This section presents a simplified discussion of the design process.
9.2 Typical Application
The LMR14050 only requires a few external components to convert from wide voltage range supply to a fixed
output voltage. A schematic of 5 V/5 A application circuit is shown in Figure 21. The external components have
to fulfill the needs of the application, but also the stability criteria of the device’s control loop.
7 V to 36 V
CBOOT
VIN
CIN
BOOT
L
5 V / 5 A
EN
SW
COUT
D
RFBT
RT/SYNC
FB
RFBB
SS
RT
GND
CSS
Figure 21. Application Circuit, 5V Output
9.2.1 Design Requirements
This example details the design of a high frequency switching regulator using ceramic output capacitors. A few
parameters must be known in order to start the design process. These parameters are typically determined at the
system level:
Input Voltage, VIN
Output Voltage, VOUT
7 V to 36 V, Typical 12 V
5.0 V
5 A
Maximum Output Current IO_MAX
Transient Response 0.5 A to 5 A
Output Voltage Ripple
Input Voltage Ripple
5%
50 mV
400 mV
300 kHz
5 ms
Switching Frequency fSW
Soft-start time
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9.2.2 Detailed Design Procedure
9.2.2.1 Output Voltage Set-Point
The output voltage of LMR14050 is externally adjustable using a resistor divider network. The divider network is
comprised of top feedback resistor RFBT and bottom feedback resistor RFBB. Equation 7 is used to determine the
output voltage:
VOUT ꢀ 0.75
RFBT
RFBB
0.75
(7)
Choose the value of RFBT to be 100 kΩ. With the desired output voltage set to 5 V and the VFB = 0.75 V, the RFBB
value can then be calculated using Equation 7. The formula yields to a value 17.65 kΩ. Choose the closest
available value of 17.8 kΩ for RFBB
.
9.2.2.2 Switching Frequency
For desired frequency, use Equation 8 to calculate the required value for RT.
RT(k:) 32537u ¦SW ꢀN+]ꢁꢀ1.045
(8)
For 300 kHz, the calculated RT is 83.9 kΩ and standard value 84.5 kΩ can be used to set the switching
frequency at 300 kHz.
9.2.2.3 Output Inductor Selection
The most critical parameters for the inductor are the inductance, saturation current and the RMS current. The
inductance is based on the desired peak-to-peak ripple current ΔiL. Since the ripple current increases with the
input voltage, the maximum input voltage is always used to calculate the minimum inductance LMIN. Use
Equation 10 to calculate the minimum value of the output inductor. KIND is a coefficient that represents the
amount of inductor ripple current relative to the maximum output current. A reasonable value of KIND should be
20%-40%. During an instantaneous short or over current operation event, the RMS and peak inductor current
can be high. The inductor current rating should be higher than current limit.
VOUT u(V
ꢀ VOUT
)
IN_MAX
'iL
VIN_MAX uL u ¦SW
(9)
V
ꢀ VOUT
VOUT
IN_MAX
LMIN
u
IOUT uKIND
VIN_MAX u ¦SW
(10)
In general, it is preferable to choose lower inductance in switching power supplies, because it usually
corresponds to faster transient response, smaller DCR, and reduced size for more compact designs. But too low
of an inductance can generate too large of an inductor current ripple such that over current protection at the full
load could be falsely trigged. It also generates more conduction loss since the RMS current is slightly higher.
Larger inductor current ripple also implies larger output voltage ripple with same output capacitors. With peak
current mode control, it is not recommended to have too small of an inductor current ripple. A larger peak current
ripple improves the comparator signal to noise ratio.
For this design example, choose KIND = 0.4, the minimum inductor value is calculated to be 7.17 µH, and a
nearest standard value is chosen: 8.2 µH. A standard 8.2 μH ferrite inductor with a capability of 7 A RMS current
and 10A saturation current can be used.
9.2.2.4 Output Capacitor Selection
The output capacitor(s), COUT, should be chosen with care since it directly affects the steady state output voltage
ripple, loop stability and the voltage over/undershoot during load current transients.
The output ripple is essentially composed of two parts. One is caused by the inductor current ripple going
through the Equivalent Series Resistance (ESR) of the output capacitors:
'VOUT_ESR 'iL uESR KIND uIOUT uESR
(11)
The other is caused by the inductor current ripple charging and discharging the output capacitors:
'iL
KIND uIOUT
8u ¦SW uCOUT 8u ¦SW uCOUT
'VOUT_C
(12)
16
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The two components in the voltage ripple are not in phase, so the actual peak-to-peak ripple is smaller than the
sum of two peaks.
Output capacitance is usually limited by transient performance specifications if the system requires tight voltage
regulation with presence of large current steps and fast slew rate. When a fast large load increase happens,
output capacitors provide the required charge before the inductor current can slew up to the appropriate level.
The regulator’s control loop usually needs three or more clock cycles to respond to the output voltage droop. The
output capacitance must be large enough to supply the current difference for three clock cycles to maintain the
output voltage within the specified range. Equation 13 shows the minimum output capacitance needed for
specified output undershoot. When a sudden large load decrease happens, the output capacitors absorb energy
stored in the inductor. The catch diode can’t sink current so the energy stored in the inductor results in an output
voltage overshoot. Equation 14 calculates the minimum capacitance required to keep the voltage overshoot
within a specified range.
3u(IOH ꢀIOL
)
COUT
!
¦
u 9US
SW
(13)
(14)
IO2 H ꢁIO2 L
(VOUT ꢀ VOS )2 ꢁ VO2UT
COUT
!
uL
where
•
•
•
•
•
KIND = Ripple ratio of the inductor ripple current (ΔiL / IOUT
IOL = Low level output current during load transient
IOH = High level output current during load transient
VUS = Target output voltage undershoot
)
VOS = Target output voltage overshoot
For this design example, the target output ripple is 50 mV. Presuppose ΔVOUT_ESR = ΔVOUT_C = 50 mV, and
chose KIND = 0.4. Equation 11 yields ESR no larger than 25 mΩ and Equation 12 yields COUT no smaller than
16.7 μF. For the target over/undershoot range of this design, VUS = VOS = 5% × VOUT = 250 mV. The COUT can
be calculated to be no smaller than 180 μF and 79.2 μF by Equation 13 and Equation 14 respectively. In
summary, the most stringent criteria for the output capacitor is 180 μF. Four 47 μF, 16 V, X7R ceramic
capacitors with 5 mΩ ESR are used in parallel .
9.2.2.5 Schottky Diode Selection
The breakdown voltage rating of the diode is preferred to be 25% higher than the maximum input voltage. The
current rating for the diode should be equal to the maximum output current for best reliability in most
applications. In cases where the input voltage is much greater than the output voltage the average diode current
is lower. In this case it is possible to use a diode with a lower average current rating, approximately (1-D) × IOUT
however the peak current rating should be higher than the maximum load current. A 6 A to 7 A rated diode is a
good starting point.
9.2.2.6 Input Capacitor Selection
The LMR14050 device requires high frequency input decoupling capacitor(s) and a bulk input capacitor,
depending on the application. The typical recommended value for the high frequency decoupling capacitor is 4.7
μF to 10 μF. A high-quality ceramic capacitor type X5R or X7R with sufficiency voltage rating is recommended.
To compensate the derating of ceramic capacitors, a voltage rating of twice the maximum input voltage is
recommended. Additionally, some bulk capacitance can be required, especially if the LMR14050 circuit is not
located within approximately 5 cm from the input voltage source. This capacitor is used to provide damping to the
voltage spike due to the lead inductance of the cable or the trace. For this design, two 2.2 μF, X7R ceramic
capacitors rated for 100 V are used. A 0.1 μF for high-frequency filtering and place it as close as possible to the
device pins.
9.2.2.7 Bootstrap Capacitor Selection
Every LMR14050 design requires a bootstrap capacitor (CBOOT). The recommended capacitor is 0.1 μF and rated
16 V or higher. The bootstrap capacitor is located between the SW pin and the BOOT pin. The bootstrap
capacitor must be a high-quality ceramic type with an X7R or X5R grade dielectric for temperature stability.
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9.2.2.8 Soft-start Capacitor Selection
Use Equation 15 in order to calculate the soft-start capacitor value:
tSS(ms)uISS(PA)
CSS(nF)
VREF(V)
(15)
where
•
•
•
CSS = Soft-start capacitor value
ISS = Soft-start charging current (3 μA)
tSS = Desired soft-start time
For the desired soft-start time of 5 ms and soft-start charging current of 3.0 μA, Equation 15 yields a soft-start
capacitor value of 20 nF, a standard 22 nF ceramic capacitor is used.
18
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9.2.3 Application Curves
Unless otherwise specified the following conditions apply: VIN = 12 V, fSW = 300 kHz, L = 6.5 µH, COUT = 47 µF x 4, TA = 25°C
VIN (5 V/DIV)
VIN (5 V/DIV)
EN (1 V/DIV)
VOUT (1 V/DIV)
VOUT (1 V/DIV)
iL (2 A/DIV)
Time (2 ms/DIV)
Time (2 ms/DIV)
VIN = 12 V
VOUT = 5 V
IOUT = 2 A
IOUT = 0 A
IOUT = 5 A
VIN = 12 V
VOUT = 5 V
IOUT = 2 A
Figure 22. Start-up By EN
Figure 23. Start-up By VIN
SW (5 V/DIV)
SW (5 V/DIV)
iL (500 mA/DIV)
iL (500 mA/DIV)
VOUT(ac) (10 mV/DIV)
VOUT(ac) (10 mV/DIV)
Time (2 ms/DIV)
Time (4 µs/DIV)
VIN = 12 V
VOUT = 5 V
VIN = 12 V
VOUT = 5 V
IOUT = 100 mA
Figure 24. Sleep-mode
Figure 25. DCM Mode
SW (5 V/DIV)
IOUT (2 A/DIV)
iL (2 A/DIV)
VOUT(ac) (200 mV/DIV)
VOUT(ac) (10 mV/DIV)
Time (4 µs/DIV)
Time (100 µs/DIV)
VIN = 12 V
VOUT = 5 V
IOUT: 10% → 100%
Slew rate = 100
of 5 A
mA/μs
Figure 26. CCM Mode
Figure 27. Load Transient
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Unless otherwise specified the following conditions apply: VIN = 12 V, fSW = 300 kHz, L = 6.5 µH, COUT = 47 µF x 4, TA = 25°C
VOUT (2 V/DIV)
VOUT (2 V/DIV)
iL (2 A/DIV)
iL (2 A/DIV)
Time (100 µs/DIV)
Time (1.6 ms/DIV)
VIN = 12 V
VOUT = 5 V
VIN = 12 V
VOUT = 5 V
Figure 28. Output Short
Figure 29. Output Short Recovery
20
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10 Power Supply Recommendations
The LMR14050 is designed to operate from an input voltage supply range between 4 V and 40 V. This input
supply should be able to withstand the maximum input current and maintain a stable voltage. The resistance of
the input supply rail should be low enough that an input current transient does not cause a high enough drop at
the LMR14050 supply voltage that can cause a false UVLO fault triggering and system reset. If the input supply
is located more than a few inches from the LMR14050, additional bulk capacitance may be required in addition to
the ceramic input capacitors. The amount of bulk capacitance is not critical, but a 47 μF or 100 μF electrolytic
capacitor is a typical choice .
11 Layout
11.1 Layout Guidelines
Layout is a critical portion of good power supply design. The following guidelines will help users design a PCB
with the best power conversion performance, thermal performance, and minimized generation of unwanted EMI.
1. The feedback network, resistor RFBT and RFBB, should be kept close to the FB pin. VOUT sense path away
from noisy nodes and preferably through a layer on the other side of a shielding layer .
2. The input bypass capacitor CIN must be placed as close as possible to the VIN pin and ground. Grounding
for both the input and output capacitors should consist of localized top side planes that connect to the GND
pin and PAD .
3. The inductor L should be placed close to the SW pin to reduce magnetic and electrostatic noise.
4. The output capacitor, COUT should be placed close to the junction of L and the diode D. The L, D, and COUT
trace should be as short as possible to reduce conducted and radiated noise and increase overall efficiency.
5. The ground connection for the diode, CIN, and COUT should be as small as possible and tied to the system
ground plane in only one spot (preferably at the COUT ground point) to minimize conducted noise in the
system ground plane
6. For more detail on switching power supply layout considerations see Application Note AN-1149
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11.2 Layout Example
Output Bypass
Capacitor
Output
Inductor
Rectifier Diode
BOOT
Capacitor
Input Bypass
Capacitor
BOOT
VIN
SW
GND
SS
Soft-Start
Capacitor
EN
RT/SYNC
FB
UVLO Adjust
Resistor
Output Voltage
Set Resistor
Thermal VIA
Signal VIA
Frequency
Set Resistor
Figure 30. Layout
22
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12 器件和文档支持
12.1 商标
PowerPAD is a trademark of Texas Instruments.
SIMPLE SWITCHER is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.2 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.3 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、首字母缩略词和定义。
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13 机械封装和可订购信息
以下页中包括机械封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不对
本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
24
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PACKAGE OPTION ADDENDUM
www.ti.com
1-Mar-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMR14050SDDA
LMR14050SDDAR
ACTIVE SO PowerPAD
ACTIVE SO PowerPAD
DDA
DDA
8
8
75
RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR
-40 to 125
-40 to 125
DB5SP
DB5SP
Samples
Samples
2500 RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
1-Mar-2023
OTHER QUALIFIED VERSIONS OF LMR14050 :
Automotive : LMR14050-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
LMR14050SDDA
LMR14050SDDA
DDA
DDA
HSOIC
HSOIC
8
8
75
75
507
517
8
3940
635
4.32
4.25
7.87
Pack Materials-Page 1
PACKAGE OUTLINE
DDA0008B
PowerPADTM SOIC - 1.7 mm max height
S
C
A
L
E
2
.
4
0
0
PLASTIC SMALL OUTLINE
C
6.2
5.8
TYP
SEATING PLANE
A
PIN 1 ID
AREA
0.1 C
6X 1.27
8
1
2X
5.0
4.8
3.81
NOTE 3
4
5
0.51
8X
0.31
4.0
3.8
1.7 MAX
B
0.25
C A B
NOTE 4
0.25
0.10
TYP
SEE DETAIL A
5
4
EXPOSED
THERMAL PAD
0.25
3.4
2.8
9
GAGE PLANE
0.15
0.00
0 - 8
1.27
0.40
1
8
DETAIL A
TYPICAL
2.71
2.11
4214849/A 08/2016
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MS-012.
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EXAMPLE BOARD LAYOUT
DDA0008B
PowerPADTM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
(2.95)
NOTE 9
SOLDER MASK
DEFINED PAD
(2.71)
SOLDER MASK
OPENING
SEE DETAILS
8X (1.55)
1
8
8X (0.6)
(3.4)
SOLDER MASK
OPENING
TYP
9
SYMM
(1.3)
(4.9)
NOTE 9
6X (1.27)
5
4
(R0.05) TYP
METAL COVERED
BY SOLDER MASK
SYMM
(5.4)
(
0.2) TYP
VIA
(1.3) TYP
LAND PATTERN EXAMPLE
SCALE:10X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
PADS 1-8
4214849/A 08/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
DDA0008B
PowerPADTM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
(2.71)
BASED ON
0.125 THICK
STENCIL
8X (1.55)
(R0.05) TYP
8
1
8X (0.6)
(3.4)
BASED ON
0.125 THICK
STENCIL
SYMM
9
6X (1.27)
5
4
METAL COVERED
BY SOLDER MASK
SYMM
(5.4)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
3.03 X 3.80
2.71 X 3.40 (SHOWN)
2.47 X 3.10
0.125
0.150
0.175
2.29 X 2.87
4214849/A 08/2016
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
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