LMR33640 [TI]
采用 SOIC-8 封装的 SIMPLE SWITCHER® 3.8V 至 36V、4A 降压转换器;
| 型号： | LMR33640 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用 SOIC-8 封装的 SIMPLE SWITCHER® 3.8V 至 36V、4A 降压转换器 转换器 |
| 文件： | 总46页 (文件大小：3471K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LMR33640
ZHCSKF5C – OCTOBER 2019 – REVISED NOVEMBER 2020
LMR33640 SIMPLE SWITCHER® 3.8V 至 36V、4A 同步降压转换器
1 特性
3 说明
•
提供功能安全
LMR33640 SIMPLE SWITCHER® 稳压器是一款简单
易用的同步降压直流/直流转换器，可提供出色的效
率，适用于条件严苛的工业应用。LMR33640 能够使
用高达 36V 的输入电压驱动高达 4A 的负载电流。
LMR33640 可提供高轻负载效率和输出精度。电源正
常状态标志和精密使能端等特性有助于实现灵活而又易
用的解决方案，适用于广泛的应用。LMR33640 在轻
负载条件下自动折返频率以提高效率。保护特性包括热
关断、输入欠压锁定、逐周期电流限制和断续短路保
护。通过集成和内部补偿，该器件减少了很多外部组
件，并提供专为实现简单 PCB 布局而设计的引脚排列
方式。该器件的功能集旨在简化各种终端设备的实施。
LMR33640 与 LMR33610、LMR33620、LMR33630
（36V、1A/2A/3A）和 LMR36510（65V、1A）以及
LMR36520（65V、2A）引脚对引脚兼容，完善了可扩
展的 SIMPLE SWITCHER 电源系列。这就降低了成本
并减少了与电路板布局修改相关的工作量。LMR33640
采用 8 引脚 HSOIC 封装。
– 可帮助进行功能安全系统设计的文档
专用于条件严苛的工业应用
– 输入电压范围：3.8V 至 36V
– 输出电压范围：1V 至 24V
– 峰值电流模式控制
•
– 结温范围：–40°C 至 +125°C
– 易于使用的 SOIC 封装
•
非常适合可扩展的工业电源
– 与以下器件引脚兼容：
• LMR33610、LMR33620 和 LMR33630
（36V、1A、2A 或 3A）
• LMR36510 和 LMR36520
（65V、1A 或 2A）
– 400kHz 和 1MHz 频率
– 集成式补偿有助于减小解决方案尺寸、降低成本
和设计复杂性
•
高效解决方案
器件信息
封装(1)
– 峰值效率 > 95%
器件型号
LMR33640
封装尺寸（标称值）
HSOIC (8)
5.00mm × 4.00mm
– 低至 5µA 的关断静态电流
– 24µA 的低工作静态电流
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
•
•
•
灵活的系统接口
– 电源正常状态标志和精密使能端
使用 LMR33640 并借助 WEBENCH® Power
Designer 创建定制设计
使用 TPSM53604 模块缩短产品上市时间
2 应用
•
•
•
电机驱动系统：无人机、交流逆变器、
变频驱动器、伺服系统
工厂和楼宇自动化系统：
PLC、HMI、HVAC 系统、电梯主控板
宽输入电压直流/直流电源
100
95
90
85
80
75
70
BOOT
VIN
CIN
VIN
EN
CBOOT
L1
VOUT
COUT
SW
PGND
VCC
PG
FB
65
RFBT
CVCC
8V
12V
60
24V
36V
55
50
RFBB
AGND
0.001
0.01
0.1
Output Current (A)
1
5
eff_
效率与输出电流间的关系 VOUT = 5V，{7}400kHz，
简化版原理图
HSOIC
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNVSB99
LMR33640
www.ti.com.cn
ZHCSKF5C – OCTOBER 2019 – REVISED NOVEMBER 2020
Table of Contents
8.4 Device Functional Modes..........................................16
9 Application and Implementation..................................19
9.1 Application Information............................................. 19
9.2 Typical Application.................................................... 19
9.3 What to Do and What Not to Do............................... 29
10 Power Supply Recommendations..............................30
11 Layout...........................................................................31
11.1 Layout Guidelines................................................... 31
11.2 Layout Example...................................................... 33
12 Device and Documentation Support..........................34
12.1 Device Support....................................................... 34
12.2 Documentation Support.......................................... 34
12.3 Receiving Notification of Documentation Updates..34
12.4 Support Resources................................................. 34
12.5 Trademarks.............................................................35
12.6 Electrostatic Discharge Caution..............................35
12.7 Glossary..................................................................35
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings........................................ 5
7.2 ESD Ratings............................................................... 5
7.3 Recommended Operating Conditions.........................5
7.4 Thermal Information....................................................6
7.5 Electrical Characteristics.............................................6
7.6 Timing Characteristics.................................................7
7.7 System Characteristics............................................... 8
7.8 Typical Characteristics................................................9
8 Detailed Description......................................................11
8.1 Overview................................................................... 11
8.2 Functional Block Diagram......................................... 11
8.3 Feature Description...................................................12
Information.................................................................... 35
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision B (May 2020) to Revision C (November 2020)
Page
向特性 添加了功能安全项目................................................................................................................................1
更新了整个文档的表、图和交叉参考的编号格式。.............................................................................................1
•
•
Changes from Revision A (October 2019) to Revision B (May 2020)
Page
•
向特性 添加了 TPSM53604 链接........................................................................................................................1
Changes from Revision * (September 2019) to Revision A (October 2019)
Page
•
将产品状态从“预告信息”更改为“量产数据”................................................................................................ 1
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5 Device Comparison Table
DEVICE OPTION
LMR33640ADDA
LMR33640DDDA
RATED CURRENT
SWITCHING FREQUENCY
400 kHz
4 A
4 A
1000 kHz
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6 Pin Configuration and Functions
PGND
VIN
1
2
3
4
8
7
6
5
SW
BOOT
VCC
FB
THERMAL
PAD
EN
PG
Not to scale
图 6-1. 8-Pin HSOIC with PowerPAD™ DDA Package (Top View)
表 6-1. Pin Functions
PIN
I/O
DESCRIPTION
NAME
PGND
NO.
Power ground terminal. Connect to system ground and AGND. Connect to bypass capacitor
with short wide traces.
1
G
P
A
Input supply to regulator. Connect a high-quality bypass capacitor or capacitors directly to this
pin and PGND.
VIN
EN
2
3
Enable input to regulator. High = ON, low = OFF. Can be connected directly to VIN; Do not
float.
Open drain power-good flag output. Connect to suitable voltage supply through a current
limiting resistor. High = power OK, low = power bad. Flag pulls low when EN = Low. Can be left
open when not used.
PG
4
5
6
A
A
P
Feedback input to regulator. Connect to tap point of feedback voltage divider. Do not float. Do
not ground.
FB
Internal 5-V LDO output. Used as supply to internal control circuits. Do not connect to external
loads. Can be used as logic supply for power-good flag. Connect a high-quality 1-µF capacitor
from this pin to PGND.
VCC
Boot-strap supply voltage for internal high-side driver. Connect a high-quality 100-nF capacitor
from this pin to the SW pin.
BOOT
SW
7
8
P
P
Regulator switch node. Connect to power inductor.
Analog ground for regulator and system. Ground reference for internal references and logic. All
electrical parameters are measured with respect to this pin. Connect to system ground on
PCB. For the HSOIC package, the pad on the bottom of the device serves as both the AGND
connection and a thermal connection to the heat sink ground plane. This pad must be soldered
to a ground plane to achieve good electrical and thermal performance.
THERMAL
PAD
AGND
G
A = Analog, P = Power, G = Ground
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7 Specifications
7.1 Absolute Maximum Ratings
Over the recommended operating junction temperature range(1)
PARAMETER
MIN
–0.3
–0.3
–0.3
0
MAX
38
UNIT
VIN to PGND
EN to AGND(2)
FB to AGND
VIN + 0.3
5.5
V
PG to AGND(2)
22
AGND to PGND
0.3
Voltages
–0.3
–0.3
–3.5
–0.3
–0.3
–40
–55
SW to PGND
VIN + 0.3
38
SW to PGND less than 100-ns transients
BOOT to SW
V
5.5
VCC to AGND(4)
5.5
TJ
Junction temperature(3)
Storage temperature
150
°C
°C
Tstg
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) The voltage on this pin must not exceed the voltage on the VIN pin by more than 0.3 V
(3) Operating at junction temperatures greater than 125°C, although possible, degrades the lifetime of the device.
(4) Under some operating conditions the VCC LDO voltage may increase beyond 5.5V.
7.2 ESD Ratings
VALUE
±2500
±750
UNIT
Human-body model (HBM) (1)
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM) (2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
Over the recommended operating temperature range of –40°C to 125°C (unless otherwise noted) (1)
MIN
3.8
0
MAX
UNIT
VIN to PGND
EN (2)
36
VIN
18
24
4
Input voltage
V
PG(2)
0
(3)
Adjustable output voltage
Output current
VOUT
1
V
A
IOUT
0
(1) Recommended operating conditions indicate conditions for which the device is intended to be functional, but do not ensure specific
performance limits. For ensured specifications, see 节 7.5.
(2) The voltage on this pin must not exceed the voltage on the VIN pin by more than 0.3 V.
(3) The maximum output voltage can be extended to 95% of VIN; contact TI for details. Under no conditions should the output voltage be
allowed to fall below zero volts.
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7.4 Thermal Information
The value of RθJA given in this table is only valid for comparison with other packages and can not be used for design
purposes. These values were calculated in accordance with JESD 51-7, and simulated on a 4-layer JEDEC board. They do
not represent the performance obtained in an actual application. For design information, see 节 7.1.
LMR33640
THERMAL METRIC(1) (2)
DDA (HSOIC)
8 PINS
42.9(2)
54
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
13.6
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
4.3
ψJT
13.8
ψJB
RθJC(bot)
4.3
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) The value of RθJA given in this table is only valid for comparison with other packages and can not be used for design purposes. These
values were calculated in accordance with JESD 51-7, and simulated on a 4-layer JEDEC board. They do not represent the
performance obtained in an actual application. For design information see the 节 7.1.
7.5 Electrical Characteristics
Limits apply over the operating junction temperature (TJ) range of –40°C to +125°C, unless otherwise stated. Minimum and
maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric
norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply:
VIN = 12 V, VEN = 4 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE
Minimum operating input
voltage
VIN
3.8
34
10
V
Non-switching input current;
measured at VIN pin (2)
IQ
VFB = 1.2 V
EN = 0
24
5
µA
µA
Shutdown quiescent current;
measured at VIN pin
ISD
ENABLE
VEN-VCC-H
EN input level required to turn
on internal LDO
Rising threshold
Falling threshold
Rising threshold
1
V
V
V
EN input level required to turn
off internal LDO
VEN-VCC-L
VEN-H
0.3
1.2
EN input level required to start
switching
1.231
1.26
VEN-HYS
ILKG-EN
INTERNAL SUPPLIES
Hysteresis below VEN-H
Hysteresis below VEN-H; falling
VEN = 3.3 V
100
0.2
mV
nA
Enable input leakage current
Internal LDO output voltage
appearing at the VCC pin
VCC
4.75
5
5.25
V
V
6 V ≤ VIN ≤ 36 V
Bootstrap voltage
undervoltage lock-out
threshold(3)
VBOOT-UVLO
2.2
VOLTAGE REFERENCE (FB PIN)
VFB Feedback voltage; ADJ option
0.985
1
1.015
50
V
Current into FB pin; ADJ
option
IFB
FB = 1 V
0.2
nA
CURRENT LIMITS
ISC
High-side current limit
Low-side current limit
LMR33640
LMR33640
4.8
3.9
5.5
4.5
6.2
5
A
A
A
ILIMIT
IPEAK-MIN
Minimum peak inductor current LMR33640
0.824
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Limits apply over the operating junction temperature (TJ) range of –40°C to +125°C, unless otherwise stated. Minimum and
maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric
norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply:
VIN = 12 V, VEN = 4 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Zero current detector
threshold
IZC
-0.106
A
SOFT START
tSS
Internal soft-start time
2.9
4
6
ms
POWER GOOD (PG PIN)
Power-good upper threshold -
VPG-HIGH-UP
VPG-HIGH-DN
VPG-LOW-UP
VPG-LOW-DN
tPG
% of FB voltage
105%
103%
92%
90%
60
107%
105%
94%
110%
108%
97%
95%
170
rising
Power-good upper threshold -
falling
% of FB voltage
% of FB voltage
% of FB voltage
Power-good lower threshold -
rising
Power-good lower threshold -
falling
92%
Power-good glitch filter
delay(1)
µs
VIN = 12 V, VEN = 4 V
VEN = 0 V
76
35
150
60
RPG
Power-good flag RDSON
Ω
Minimum input voltage for
proper PG function
VIN-PG
50-µA, EN = 0 V
2
V
V
VPG
PG logic low output
50-µA, EN = 0 V, VIN = 2V
0.2
OSCILLATOR
ƒSW
Switching frequency
Switching frequency
860
340
1000
400
1140
460
kHz
kHz
ƒSW
MOSFETS
High-side MOSFET ON-
resistance
RDS-ON-HS
RDS-ON-LS
DDA package
DDA package
95
66
160
110
mΩ
mΩ
Low-side MOSFET ON-
resistance
(1) See 节 8.3.1 for details.
(2) This is the current used by the device open loop. It does not represent the total input current of the system when in regulation.
(3) When the voltage across the CBOOT capacitor falls below this voltage, the low side MOSFET is turned on to recharge CBOOT
.
7.6 Timing Characteristics
Limits apply over the operating junction temperature (TJ) range of –40°C to +125°C, unless otherwise stated. Minimum and
maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric
norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply: VIN
= 12 V, VEN = 4 V.
MIN
NOM
MAX
108
85
UNIT
tON-MIN
tOFF-MIN
tON-MAX
Minimum switch on-time
Minimum switch off-time
Maximum switch on-time
DDA package
DDA package
75
ns
50
ns
7
9
µs
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7.7 System Characteristics
The following specifications apply to a typical applications circuit, with nominal component values. Specifications in the
typical (TYP) column apply to TJ = 25°C only. Specifications in the minimum (MIN) and maximum (MAX) columns apply to the
case of typical components over the temperature range of TJ = –40°C to 125°C. These specifications are not ensured by
production testing.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIN
Operating input voltage range
VOUT = 3.3 V, IOUT= 0 A
3.8
36
V
VOUT = 5 V, VIN = 7 V to 36 V, IOUT = 0 A to 4
A
2.5%
1.5%
2.5%
1.5%
–1.6%
–1.6%
–1.6%
–1.6%
Output voltage regulation for VOUT = 5
V(1)
VOUT = 5 V, VIN = 7 V to 36 V, IOUT = 1 A to 4
A
VOUT
VOUT = 3.3 V, VIN = 3.8 V to 36 V, IOUT = 0 A
to 4 A
Output voltage regulation for VOUT = 3.3
V(1)
VOUT = 3.3 V, VIN = 3.8 V to 36 V, IOUT = 1 A
to 4 A
VIN = 12 V, VOUT = 3.3 V, IOUT = 0 A,
RFBT = 1 MΩ
ISUPPLY
Input supply current when in regulation
25
µA
VOUT = 5 V, IOUT = 1A
Dropout at –1% of regulation,
ƒSW = 140 kHz
VDROP
150
mV
Dropout voltage; (VIN – VOUT
)
DMAX
VHC
Maximum switch duty cycle(2)
VIN = VOUT = 12 V, IOUT = 1 A
98%
0.4
FB pin voltage required to trip short-circuit
hiccup mode
V
tHC
tD
Time between current-limit hiccup burst
Switch voltage dead time
94
2
ms
ns
°C
°C
Shutdown temperature
Recovery temperature
165
148
TSD
Thermal shutdown temperature
(1) Deviation is with respect to VIN = 12 V, IOUT = 1 A.
(2) In dropout the switching frequency drops to increase the effective duty cycle. The lowest frequency is clamped at approximately: ƒMIN
=
1 / (tON-MAX + tOFF-MIN). DMAX = tON-MAX /(tON-MAX + tOFF-MIN).
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7.8 Typical Characteristics
Unless otherwise specified the following conditions apply: TA = 25°C and VIN = 12 V, ƒSW = 400 kHz
36
34
32
30
28
26
24
22
20
12
11
10
9
8
7
6
5
4
-40C
25C
-40C
25C
3
2
1
125C
125C
0
0
5
10
15
20
25
30
35
40
0
5
10
15
20
25
30
35
40
Input Voltage (V)
Input Voltage (V)
C005
C003
VFB = 1.2 V
EN = 0 V
图 7-1. Non-Switching Input Supply Current
图 7-2. Shutdown Supply Current
1.35
1.30
1.25
1.20
1.15
1.10
1.05
1.00
1
0.95
0.9
0.85
UP
DN
0.8
0
0
20
40
60
80
100 120 140
œ40 œ20
5
10
15
20
25
30
35
40
Temperature (C)
C006
Input Voltage (V)
C004
图 7-4. Precision Enable Thresholds
VOUT = 0 V
ƒS = 400 kHz
See 图 9-21
图 7-3. Short-Circuit Output Current
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1
0.95
0.9
0.85
0.8
0.75
0.7
DN
UP
5V
0.65
0.6
3.3V
0
0
5
10
15
20
25
30
35
40
INPUT VOLTAGE (1V/Div)
Input Voltage (V)
C003
IOUT = 0 A
VOUT = 5 V
See 图 9-21
IOUT = 1 mA
See 图 9-21
ƒSW = 400 kHz
图 7-5. UVLO Thresholds
图 7-6. IPEAK-MIN
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8 Detailed Description
8.1 Overview
The LMR33640 is a synchronous peak-current-mode buck regulator designed for a wide variety of industrial
applications. Advanced high-speed circuitry allows the device to regulate from an input voltage of 36 V, while
providing an output voltage of 3.3 V at a switching frequency of 400 kHz. The innovative architecture allows the
device to regulate a 3.3 V output from an input of only 3.8 V. The regulator automatically switches modes
between PFM and PWM, depending on the load. At heavy loads, the device operates in PWM at a constant
switching frequency. At light loads, the mode changes to PFM with diode emulation, allowing DCM. This reduces
the input supply current and keeps efficiency high. The device features internal loop compensation, which
reduces design time and requires fewer external components than externally compensated regulators.
8.2 Functional Block Diagram
VCC
VIN
Int. Reg.
Bias
Oscillator
BOOT
Enable
Logic
HS Current
Sense
EN
ꢀ
1 V
Reference
PWM
Comp.
Error
Amplifier
Control Logic
Driver
SW
+
+
œ
œ
FB
LS Current
Sense
PFM Mode
Control
PG
Power
Good
Control
AGND
PGND
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8.3 Feature Description
8.3.1 Power-Good Flag Output
The power-good flag function (PG output pin) of the LMR33640 can be used to reset a system microprocessor
whenever the output voltage is out of regulation. This open-drain output goes low under fault conditions, such as
current limit and thermal shutdown, as well as during normal start-up. A glitch filter prevents false flag operation
for short excursions of the output voltage, such as during line and load transients. The timing parameters of the
glitch filter are found in 节 7.5. Output voltage excursions lasting less than tPG do not trip the power-good flag.
Power-good operation can best be understood by reference to 图 8-1 and 图 8-2. During initial power up, a delay
of about 4 ms (typical) is inserted from the time that EN is asserted to the time that the power-good flag goes
high. This delay only occurs during start-up and is not encountered during normal operation of the power-good
function.
The power-good output consists of an open-drain NMOS and requires an external pullup resistor to a suitable
logic supply. It can also be pulled up to either VCC or VOUT through a 100-kΩ resistor, as desired. If this function
is not needed, the PG pin must be left floating. When EN is pulled low, the flag output is also forced low. With EN
low, power good remains valid as long as the input voltage is ≥ 2 V (typical). Limit the current into the power-
good flag pin to less than 5 mA D.C. The maximum current is internally limited to about 35 mA when the device
is enabled and approximately 65 mA when the device is disabled. The internal current limit protects the device
from any transient currents that can occur when discharging a filter capacitor connected to this output.
VOUT
VPG-HIGH_UP (107%)
VPG-HIGH-DN
(105%)
VPG-LOW-UP
(95%)
VPG-LOW-DN (93%)
PG
High = Power Good
Low = Fault
图 8-1. Static Power-Good Operation
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Glitches do not cause false operation nor reset timer
VOUT
VPG-LOW-UP (95%)
PG-LOW-DN (93%)
V
< tPG
PG
tPG
tPG
tPG
图 8-2. Power-Good-Timing Behavior
8.3.2 Enable and Start-up
Start-up and shutdown are controlled by the EN input. This input features precision thresholds, allowing the use
of an external voltage divider to provide an adjustable input UVLO (see 节 9.2.2.9). Applying a voltage greater
than or equal to VEN-VCC_H causes the device to enter standby mode, which powers the internal VCC, but does
not produce an output voltage. Increasing the EN voltage to VEN-H fully enables the device, allowing it to enter
start-up mode and begin the soft-start period. When the EN input is brought below VEN-H by VEN-HYS, the
regulator stops running and enters standby mode. Further decrease in the EN voltage to below VEN-VCC-L
completely shuts down the device. 图 8-3 shows this behavior. The EN input can be connected directly to VIN if
this feature is not needed. This input must not be allowed to float. The values for the various EN thresholds can
be found in 节 7.5.
The LMR33640 uses a reference-based soft start that prevents output voltage overshoots and large inrush
currents as the regulator is starting up. 图 8-4 shows a typical start-up waveform, indicating typical timings. The
rise time of the output voltage is about 4 ms (see 节 7.5).
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EN
VEN-H
VEN-H œ VEN-HYS
VEN-VCC-H
VEN-VCC-L
VCC
5V
0
VOUT
VOUT
0
图 8-3. Precision Enable Behavior
EN
Output
Voltage
2V/div
PG
5V/div
Inductor
Curent
2A/
2ms/div
图 8-4. Typical Start-up Behavior VIN = 12 V, VOUT = 5 V, IOUT = 4 A
8.3.3 Current Limit and Short Circuit
The LMR33640 incorporates both peak and valley inductor current limit to provide protection to the device from
overloads and short circuits and limit the maximum output current. Valley current limit prevents inductor current
run-away during short circuits on the output, while both peak and valley limits work together to limit the maximum
output current of the converter. Cycle-by-cycle current limit is used for overloads while hiccup mode is used for
sustained short circuits. Finally, a zero current detector is used on the low-side power MOSFET to implement
DEM at light loads (see the Glossary). The typical value of this current limit is found under IZC in 节 7.5.
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When the device is overloaded, the valley of the inductor current may not reach below ILIMIT, (see 节 7.5) before
the next clock cycle. When this occurs, the valley current limit control skips that cycle, causing the switching
frequency to drop. Further overload causes the switching frequency to continue to drop and the inductor ripple
current to increase. When the peak of the inductor current reaches the high-side current limit, ISC (see 节 7.5),
the switch duty cycle is reduced and the output voltage falls out of regulation. This represents the maximum
output current from the converter and is given approximately by 方程式 1.
ILIMIT +ISC
IOUT
=
max
2
(1)
If during current limit, the voltage on the FB input falls below about 0.4 V due to a short circuit, the device enters
into hiccup mode. In this mode, the device stops switching for tHC (see the System Characteristics section), or
about 94 ms, and then goes through a normal re-start with soft start. If the short-circuit condition remains, the
device runs in current limit for about 20 ms (typical) and then shuts down again. This cycle repeats, as shown in
图 8-5, as long as the short-circuit condition persists. This mode of operation reduces the temperature rise of the
device during a hard short on the output. The output current is greatly reduced during hiccup mode (see 节 7.8).
Once the output short is removed and the hiccup delay is passed, the output voltage recovers normally as
shown in 图 8-6.
图 8-7 shows the overall output voltage versus the output current characteristic.
Short Released
Short triggered
Output
Voltage
2V/div
Inductor
Curent
2A/
Inductor
Curent
1A/
50ms/div
50ms/div
图 8-5. Inductor Current Burst in Short-Circuit
图 8-6. Short-Circuit Transient and Recovery VIN =
Mode
12 V, VOUT = 5 V
Output
Voltage
VOUT
0.4· VOUT
Output
Current
IOMAX
0.2· IOMAX
图 8-7. Output Voltage versus Output Current in Current Limit
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8.3.4 Undervoltage Lockout and Thermal Shutdown
The LMR33640 incorporates an undervoltage-lockout feature on the output of the internal LDO (at the VCC pin).
When VCC reaches about 3.7 V, the device is ready to receive an EN signal and start up. When VCC falls below
approximately 3 V, the device shuts down, regardless of EN status. Since the LDO is in dropout during these
transitions, the above values roughly represent the input voltage levels during the transitions.
Thermal shutdown is provided to protect the regulator from excessive junction temperature. When the junction
temperature reaches about 165°C, the device shuts down; re-start occurs when the temperature falls to about
148°C .
8.4 Device Functional Modes
8.4.1 Auto Mode
In auto mode, the device moves between PWM and PFM as the load changes. At light loads, the regulator
operates in PFM. At higher loads, the mode changes to PWM. The load current for which the device moves from
PFM to PWM can be found in 节 9.2.3. The output current at which the device changes modes depends on the
input voltage, inductor value, and the output voltage. For output currents above the curve, the device is in PWM
mode. For currents below the curve, the device is in PFM. The curves apply for a nominal switching frequency of
400 kHz and the BOM shown in 表 9-3. For applications where the switching frequency must be known for a
given condition, the transition between PFM and PWM must be carefully tested before the design is finalized.
In PWM mode, the regulator operates as a constant frequency converter using PWM to regulate the output
voltage. While operating in this mode, the output voltage is regulated by switching at a constant frequency and
modulating the duty cycle to control the power to the load. This provides excellent line and load regulation and
low-output voltage ripple.
In PFM, the high-side MOSFET is turned on in a burst of one or more pulses to provide energy to the load. The
duration of the burst depends on how long it takes the inductor current to reach IPEAK-MIN. The periodicity of
these bursts is adjusted to regulate the output, while diode emulation (DEM) is used to maximize efficiency (see
the Glossary). This mode provides high light-load efficiency by reducing the amount of input supply current
required to regulate the output voltage at light loads. PFM results in very good light-load efficiency, but also
yields larger output voltage ripple and variable switching frequency. Also, a small increase in output voltage
occurs at light loads. The actual switching frequency and output voltage ripple depend on the input voltage,
output voltage, and load. 图 8-8 and 图 8-9 show typical switching waveforms in PFM and PWM. See 节 9.2.3 for
output voltage variation with load in auto mode.
SW,
5V/Div
SW
5V/Div
0
VOUT,
10mV/Div
VOUT
10mV/Div
5V
Inductor
Current,
0.5A/Div
Inductor Current
2A/Div
0
2µs/Div
50µs/Div
图 8-9. Typical PWM Switching Waveforms VIN = 12
V, VOUT = 5 V, IOUT = 4 A, ƒS = 400 kHz
图 8-8. Typical PFM Switching Waveforms VIN = 12
V, VOUT = 5 V, IOUT = 10 mA
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8.4.2 Dropout
The dropout performance of any buck regulator is affected by the RDSON of the power MOSFETs, the DC
resistance of the inductor, and the maximum duty cycle that the controller can achieve. As the input voltage level
approaches the output voltage, the off-time of the high-side MOSFET starts to approach the minimum value.
Beyond this point, the switching can become erratic, and the output voltage can fall out of regulation. To avoid
this problem, the LMR33640 automatically reduces the switching frequency to increase the effective duty cycle
and maintain regulation. In this data sheet, the dropout voltage is defined as the difference between the input
and output voltage when the output has dropped by 1% of its nominal value. Under this condition, the switching
frequency has dropped to its minimum value of about 140 kHz. Note that the 0.4 V short circuit detection
threshold is not activated when in dropout mode. Typical dropout characteristics can be found in 图 8-10, 图
8-11, and 图 8-12.
6
5.5
5
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
4.5
4
3.5
3
4
4.5
5
5.5
6
6.5
7
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Input Voltage (V)
Output Current (A)
C005
C007
图 8-10. Overall Dropout Characteristic VOUT = 5 V, 图 8-11. Typical Dropout Voltage vs Output Current
IOUT = 4 A
in Frequency Fold-back ƒSW = 140 kHz
450
400
350
300
250
200
150
100
4
4.5
5
5.5
6
6.5
7
Input Voltage (V)
C006
图 8-12. Typical Switching Frequency in Dropout Mode VOUT = 5 V, fSW = 400 kHz
8.4.3 Minimum Switch On-Time
Every switching regulator has a minimum controllable on-time dictated by the inherent delays and blanking times
associated with the control circuits. This imposes a minimum switch duty cycle and, therefore, a minimum
conversion ratio. The constraint is encountered at high input voltages and low output voltages. To extend the
minimum controllable duty cycle, the LMR33640 automatically reduces the switching frequency when the
minimum on-time limit is reached. This way the converter can regulate the lowest programmable output voltage
at the maximum input voltage. An estimate for the approximate input voltage, for a given output voltage before
frequency foldback occurs is found in 方程式 2. The values of tON and fSW can be found in 节 7.5. As the input
voltage is increased, the switch on-time (duty-cycle) reduces to regulate the output voltage. When the on-time
reaches the limit, the switching frequency drops while the on-time remains fixed.
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VOUT
V
Ç
IN
tON ∂ fSW
(2)
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
The LMR33640 step-down DC-to-DC converter is typically used to convert a higher DC voltage to a lower DC
voltage with a maximum output current of 4 A. The following design procedure can be used to select
components for the LMR33640. Alternately, the WEBENCH design tool can be used to generate a complete
design. This tool uses an iterative design procedure and has access to a comprehensive database of
components. This allows the tool to create an optimized design and allows the user to experiment with various
options.
Note
In this data sheet, the effective value of capacitance is defined as the actual capacitance under D.C.
bias and temperature; not the rated or nameplate values. Use high-quality, low-ESR, ceramic
capacitors with an X5R or better dielectric throughout. All high value ceramic capacitors have a large
voltage coefficient in addition to normal tolerances and temperature effects. Under D.C. bias, the
capacitance drops considerably. Large case sizes and higher voltage ratings are better in this regard.
To help mitigate these effects, multiple capacitors can be used in parallel to bring the minimum
effective capacitance up to the required value. This can also ease the RMS current requirements on a
single capacitor. A careful study of bias and temperature variation of any capacitor bank must be
made to ensure that the minimum value of effective capacitance is provided.
9.2 Typical Application
图 9-1 shows a typical application circuit for the LMR33640. This device is designed to function over a wide
range of external components and system parameters. However, the internal compensation is optimized for a
certain range of external inductance and output capacitance. As a quick-start guide, 表 9-1 provides typical
component values for a range of the most common output voltages. The values given in the table are typical.
Other values can be used to enhance certain performance criterion as required by the application.
L
VOUT
VIN
6 V to 36 V
SW
VIN
EN
6.8 µH
5 V
4 A
CIN
CHF
220 nF
CBOOT
10 µF
COUT
4x 22 µF
BOOT
0.1 µF
RFBT
CFF
PG
100 kΩ
PG
100 kΩ
VCC
FB
CVCC
1 µF
PGND
AGND
RFBB
24.9 kΩ
图 9-1. Example Application Circuit (400 kHz)
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9.2.1 Design Requirements
表 9-1 provides the parameters for our detailed design procedure example.
表 9-1. Detailed Design Parameters
DESIGN PARAMETER
Input voltage
EXAMPLE VALUE
12 V (6 V to 36 V)
5 V
Output voltage
Maximum output current
Switching frequency
0 A to 4 A
400 kHz
表 9-2. Typical External Component Values
f SW(kHz)
400
VOUT (V)
TYPICAL
COUT
MINIMUM
COUT
CIN + CHF
CBOOT
100 nF
100 nF
100 nF
100 nF
CVCC
1 μF
1 μF
1 μF
1 μF
L (μH)
RFBT (Ω)
RFBB (Ω)
3.3
5
6.8
100 k
4.32 k
4 ×22 μF
4 ×22 μF
3 ×22 μF
3 ×22 μF
3 ×22 μF
3 ×22 μF
2 ×22 μF
2 ×22 μF
10 μF + 220
nF
400
6.8
3.3
3.3
100 k
100 k
100 k
24.9 k
43.2 k
24.9 k
10 μF + 220
nF
1000
1000
3.3
5
10 μF + 220
nF
10 μF + 220
nF
9.2.2 Detailed Design Procedure
The following design procedure applies to 图 9-1 and 表 9-1.
9.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LMR33640 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
9.2.2.2 Setting the Output Voltage
The output voltage of LMR33640 is externally adjustable using a resistor divider network. The range of
recommended output voltage is found in 节 7.5. The divider network is comprised of RFBT and RFBB and closes
the loop between the output voltage and the converter. The converter regulates the output voltage by holding the
voltage on the FB pin equal to the internal reference voltage, VREF. The resistance of the divider is a
compromise between excessive noise pickup and excessive loading of the output. Smaller values of resistance
reduce noise sensitivity and reduce the light-load efficiency. The recommended value for RFBT is 100 kΩ with a
maximum value of 1 MΩ. If a 1 MΩ is selected for RFBT, then a feedforward capacitor must be used across this
resistor to provide adequate loop-phase margin (see the 节 9.2.2.8 section). Once RFBT is selected, use 方程式
3 to select RFBB. VREF is nominally 1 V (see 节 7.5 for limits).
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RFBT
RFBB
=
»
…
ÿ
VOUT
-1
Ÿ
⁄
VREF
(3)
For this 5-V example, RFBT = 100 kΩ and RFBB = 24.9 kΩ are chosen.
9.2.2.3 Inductor Selection
The parameters for selecting the inductor are the inductance and saturation current. The inductance is based on
the desired peak-to-peak ripple current and is normally chosen to be in the range of 20% to 40% of the
maximum output current. Experience shows that the best value for inductor ripple current is 30% of the
maximum load current. Note that when selecting the ripple current for applications with much smaller maximum
load than the maximum available from the device, the maximum device current must be used. 方程式 4 can be
used to determine the value of inductance. The constant K is the percentage of inductor current ripple. For this
example, K = 0.3, giving a calculated inductance of 6.08 µH. The next standard value of 6.8 µH is used.
(
V
IN - VOUT
)
VOUT
L =
∂
fSW ∂K ∂IOUTmax
V
IN
(4)
Ideally, the saturation current rating of the inductor must be at least as large as the high-side switch current limit,
ISC. This ensures that the inductor does not saturate, even during a short circuit on the output. When the inductor
core material saturates, the inductance falls to a very low value, causing the inductor current to rise very rapidly.
Although the valley current limit, ILIMIT, is designed to reduce the risk of current run-away, a saturated inductor
can cause the current to rise to high values very rapidly. This can lead to component damage. Do not allow the
inductor to saturate. Inductors with a ferrite core material have very hard saturation characteristics, but usually
have lower core losses than powdered iron cores. Powered iron cores exhibit a soft saturation, allowing some
relaxation in the current rating of the inductor. However, they have more core losses at frequencies typically
above 1 MHz. In any case, the inductor saturation current must not be less than the device low-side current limit,
ILIMIT. To avoid subharmonic oscillation, the inductance value must not be less than that given in 方程式 5. The
maximum inductance is limited by the minimum current ripple required for the current mode control to perform
correctly. As a rule-of-thumb, the minimum inductor ripple current must not be less than about 10% of the device
maximum rated current under nominal conditions.
VOUT
L í 0.23 ∂
FSW
(5)
9.2.2.4 Output Capacitor Selection
The value of the output capacitor and its ESR determine the output voltage ripple and load transient
performance. The output capacitor bank is usually limited by the load transient requirements rather than the
output voltage ripple. Use 方程式 6 to estimate a lower bound on the total output capacitance and an upper
bound on the ESR, which are required to meet a specified load transient.
K2
12
»
…
…
ÿ
DIOUT
fSW ∂ DVOUT ∂K
COUT
í
∂
(
1- D
)
∂
(
1+ K
)
+
∂
(
2 - D
)
Ÿ
Ÿ
⁄
(
2 + K
)
∂ DVOUT
ESR Ç
K2
1
»
ÿ
≈
’
2∂ DIOUT 1+ K +
∂∆1+
÷
÷
…
Ÿ
∆
12
(1- D)
…
«
◊Ÿ
⁄
VOUT
D =
V
IN
(6)
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where
•
•
ΔVOUT = output voltage transient
ΔIOUT = output current transient
• K = ripple factor from 节 9.2.2.3
Once the output capacitor and ESR have been calculated, 方程式 7 can be used to check the peak-to-peak
output voltage ripple, Vr.
1
Vr @ DIL ∂ ESR2 +
2
8∂ fSW ∂COUT
(7)
The output capacitor and ESR can then be adjusted to meet both the load transient and output ripple
requirements.
For this example, a ΔVOUT of ≤ 350 mV for an output current step of ΔIOUT = 4 A is required. 方程式 6 gives a
minimum value of about 80 µF and a maximum ESR of 77 mΩ. Assuming a 20% tolerance and a 10% bias de-
rating, you arrive at a minimum capacitance of about 110 µF. This can be achieved with a bank of 4 × 22-µF, 16-
V, ceramic capacitors in the 1210 case size or 5 × 22-µF for a worst case. More output capacitance can be used
to improve the load transient response. Ceramic capacitors can easily meet the minimum ESR requirements. In
some cases, an aluminum electrolytic capacitor can be placed in parallel with the ceramics to build up the
required value of capacitance. When using a mixture of aluminum and ceramic capacitors, use the minimum
recommended value of ceramics and add aluminum electrolytic capacitors as needed.
In general, use a capacitor of at least 10 V for output voltages of 3.3 V or less, while a capacitor of 16 V or more
must be used for output voltages of 5 V and above.
In practice, the output capacitor has the most influence on the transient response and loop-phase margin. Load
transient testing and bode plots are the best way to validate any given design and must always be completed
before the application goes into production. In addition to the required output capacitance, a small ceramic
placed on the output can help reduce high-frequency noise. Small-case size ceramic capacitors in the range of 1
nF to 100 nF can be very helpful in reducing voltage spikes on the output caused by inductor and board
parasitics.
The maximum value of total output capacitance must be limited to about 10 times the design value, or 1000 µF,
whichever is smaller. Large values of output capacitance can adversely affect the start-up behavior of the
regulator as well as the loop stability. If values larger than noted here must be used, then a careful study of start-
up at full load and loop stability must be performed.
9.2.2.5 Input Capacitor Selection
The ceramic input capacitors provide a low impedance source to the regulator in addition to supplying the ripple
current and isolating switching noise from other circuits. A minimum of 10 µF of ceramic capacitance is required
on the input of the LMR33640. This must be rated for at least the maximum input voltage that the application
requires; preferably twice the maximum input voltage. This capacitance can be increased to reduce input voltage
ripple and maintain the input voltage during load transients. In addition, a small case size 220-nF ceramic
capacitor must be used at the input, as close a possible to the regulator. This provides a high frequency bypass
for the control circuits internal to the device. For this example, a 10-µF, 50-V, X7R (or better) ceramic capacitor is
chosen. The 220 nF must also be rated at 50 V with an X7R dielectric.
Many times, it is desirable to use an electrolytic capacitor on the input in parallel with the ceramics. This is
especially true if long leads or traces are used to connect the input supply to the regulator. The moderate ESR of
this capacitor can help damp any ringing on the input supply caused by the long power leads. The use of this
additional capacitor also helps with momentary voltage dips caused by input supplies with unusually high
impedance.
Most of the input switching current passes through the ceramic input capacitors. The approximate worst case
RMS value of this current can be calculated from 方程式 8 and must be checked against the manufacturers'
maximum ratings.
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IOUT
IRMS
@
2
(8)
9.2.2.6 CBOOT
The LMR33640 requires a boot-strap capacitor connected between the BOOT pin and the SW pin. This
capacitor stores energy that is used to supply the gate drivers for the power MOSFETs. A high-quality ceramic
capacitor of 100 nF and at least 10 V is required.
9.2.2.7 VCC
The VCC pin is the output of the internal LDO used to supply the control circuits of the regulator. This output
requires a 1-µF, 16-V ceramic capacitor connected from VCC to GND for proper operation. In general, avoid
loading this output with any external circuitry. However, this output can be used to supply the pullup for the
power-good function. A value of 100 kΩ is a good choice in this case. The nominal output voltage on VCC is 5
V; see 节 7.5 for limits. Do not short this output to ground or any other external voltage.
9.2.2.8 CFF Selection
In some cases, a feedforward capacitor can be used across RFBT to improve the load transient response or
improve the loop-phase margin. This is especially true when values of RFBT > 100 kΩ are used. Large values of
RFBT in combination with the parasitic capacitance at the FB pin, can create a small signal pole that interferes
with the loop stability. A CFF can help mitigate this effect. Use 方程式 9 to estimate the value of CFF. The value
found with 方程式 9 is a starting point. Use lower values to determine if any advantage is gained by the use of a
CFF capacitor. The Optimizing Transient Response of Internally Compensated DC-DC Converters with Feed-
forward Capacitor Application Report is helpful when experimenting with a feedforward capacitor.
VOUT ∂COUT
CFF
<
VREF
VOUT
120 ∂RFBT
∂
(9)
9.2.2.9 External UVLO
In some cases, an input UVLO level different than that provided internal to the device is needed. This can be
accomplished by using the circuit shown in 图 9-2. The input voltage at which the device turns on is designated
VON while the turnoff voltage is VOFF. First, a value for RENB is chosen in the range of 10 kΩ to 100 kΩ, then 方
程式 10 is used to calculate RENT and VOFF
.
VIN
RENT
EN
RENB
图 9-2. Setup for External UVLO Application
≈
’
VON
∆
∆
÷
RENT
=
- 1 ∂RENB
÷
◊
VEN -H
«
≈
’
VEN -HYS
VEN -H
∆
÷
÷
VOFF = VON ∂ 1-
∆
«
◊
(10)
where
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• VON = VIN turnon voltage
• VOFF = VIN turnoff voltage
9.2.2.10 Maximum Ambient Temperature
As with any power conversion device, the LMR33640 dissipates internal power while operating. The effect of this
power dissipation is to raise the internal temperature of the converter above ambient. The internal die
temperature (TJ) is a function of the ambient temperature, the power loss and the effective thermal resistance,
R
θJA, of the device and PCB combination. The maximum internal die temperature for the LMR33640 must be
limited to 125°C. This establishes a limit on the maximum device power dissipation and, therefore, the load
current. 方程式 11 shows the relationships between the important parameters. It is easy to see that larger
ambient temperatures (TA) and larger values of RθJA reduce the maximum available output current. The
converter efficiency can be estimated by using the curves provided in this data sheet. If the desired operating
conditions cannot be found in one of the curves, then interpolation can be used to estimate the efficiency.
Alternatively, the EVM can be adjusted to match the desired application requirements and the efficiency can be
measured directly. The correct value of RθJA is more difficult to estimate. As stated in the Semiconductor and IC
Package Thermal Metrics Application Report, the value of RθJA given in 节 7.4 is not valid for design purposes
and must not be used to estimate the thermal performance of the application. The values reported in that table
were measured under a specific set of conditions that are rarely obtained in an actual application.
(
TJ - TA
RqJA
)
∂
h
1- h
1
IOUT
=
∂
MAX
VOUT
(11)
where
η = efficiency
•
The effective RθJA is a critical parameter and depends on many factors such as the following:
• Power dissipation
• Air temperature
• Air flow
• PCB area
• Copper heat-sink area
• Number of thermal vias under the package
• Adjacent component placement
The HSOIC (DDA) package uses a die attach paddle or thermal pad (PAD) to provide a place to solder down to
the PCB heat-sinking copper. This provides a good heat conduction path from the regulator junction to the heat
sink and must be properly soldered to the PCB heat sink copper. Typical examples of RθJA versus copper board
area can be found in 图 9-3. The copper area given in the graph is for each layer; the top and bottom layers are
2 oz copper each, while the inner layers are 1 oz. 图 9-4 shows the typical curves of maximum output current
versus ambient temperature This data was taken with a device and PCB combination, giving an RθJA as noted
in the graph. Remember that the data given in these graphs are for illustration purposes only and the actual
performance in any given application depends on all of the previously mentioned factors.
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44
42
40
38
36
34
32
30
28
26
24
22
20
DDA, 4L
0
10
20
30
40
50
60
70
Copper Area (cm2)
C003
图 9-3. Typical RθJA versus Copper Area for a Four-Layer Board
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
0
20
40
60
80
100
120
140
Ambient Temperature (°C)
C010
图 9-4. Maximum Output Current versus Ambient Temperature VIN = 12 V, VOUT = 5 V, RθJA = 30°C/W, ƒSW
= 400 kHz
Use the following resources as a guide to optimal thermal PCB design and to estimate RθJA for a given
application environment:
• Thermal Design by Insight Not Hindsight Application Report
• A Guide to Board Layout for Best Thermal Resistance for Exposed Pad Packages Application Report
• Semiconductor and IC Package Thermal Metrics Application Report
• Thermal Design Made Simple with LM43604 And LM43602 Application Report
• PowerPAD Thermally Enhanced Package Application Report
• PowerPAD Made Easy Application Report
• Using New Thermal Metrics Application Report
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9.2.3 Application Curves
Unless otherwise specified, the following conditions apply: VIN = 12 V, TA = 25°C. 图 9-21 shows the circuit with
the appropriate BOM from 表 9-3.
100
95
90
85
80
75
70
65
60
55
50
100
95
90
85
80
75
70
65
60
55
50
45
8V
8V
12V
24V
36V
12V
24V
36V
0.001
0.01
0.1
Output Current (A)
1
5
0.001
0.01
0.1
Output Current (A)
1
5
eff_
eff_
VOUT = 5 V
VOUT = 3.3 V
ƒSW = 400 kHz
ƒSW = 400 kHz
图 9-5. Efficiency
图 9-6. Efficiency
100
95
90
85
80
75
70
65
60
55
50
45
100
95
90
85
80
75
70
65
60
55
50
45
8V
8V
12V
24V
36V
12V
24V
36V
0.001
0.01
0.1
Output Current (A)
1
5
0.001
0.01
0.1
Output Current (A)
1
5
eff_
eff_
VOUT = 5 V
VOUT = 3.3 V
ƒSW = 1000 kHz
ƒSW = 1000 kHz
图 9-7. Efficiency
图 9-8. Efficiency
5.06
3.35
3.34
3.33
3.32
3.31
8V
8V
12V
24V
36V
12V
24V
36V
5.05
5.04
5.03
5.02
5.01
0
0.5
1
1.5
Output Current (A)
2
2.5
3
3.5
4
0
0.5
1
1.5
Output Current (A)
2
2.5
3
3.5
4
LMR3
LMR3
VOUT = 5 V
VOUT = 3.3 V
图 9-9. Line and Load Regulation
图 9-10. Line and Load Regulation
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Output Voltage
200mV/div
Output Voltage
200mV/div
5V
3.3V
Output Current
2A/div
Output Current
2A/div
100µs/div
100µs/div
0
0
VIN = 12 V
VOUT = 3.3 V
VIN = 12 V
ƒSW = 400 kHz
VOUT = 5 V
IOUT = 0 A to 4 A
IOUT = 0 A to 4 A
ƒSW = 400 kHz
图 9-12. Load Transient
图 9-11. Load Transient
Output Voltage
200mV/div
Output Voltage
200mV/div
3.3V
5V
Output Current
2A/div
Output Current
2A/div
100µs/div
100µs/div
0
0
VIN = 12 V
ƒSW = 400 kHz
VOUT = 5 V
VIN = 12 V
ƒSW = 400 kHz
VOUT = 3.3 V
IOUT = 1 A to 4 A
IOUT = 1 A to 4 A
图 9-13. Load Transient
图 9-14. Load Transient
Output Voltage
200mV/div
Output Voltage
200mV/div
3.3V
5V
Output Current
2A/div
Output Current
2A/div
100µs/div
100µs/div
0
0
VIN = 12 V
ƒSW = 1000 kHz
VOUT = 3.3 V
IOUT = 0 A to 4 A
VIN = 12 V
ƒSW = 1000 kHz
VOUT = 5 V
IOUT = 0 A to 4 A
图 9-16. Load Transient
图 9-15. Load Transient
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Output Voltage
200mV/div
Output Voltage
200mV/div
5V
3.3V
Output Current
2A/div
Output Current
2A/div
100µs/div
100µs/div
0
0
VIN = 12 V
ƒSW = 1000 kHz
VOUT = 3.3 V
IOUT = 1 A to 4 A
VIN = 12 V
ƒSW = 1000 kHz
VOUT = 5 V
IOUT = 1 A to 4 A
图 9-18. Load Transient
图 9-17. Load Transient
0.65
0.55
0.45
0.35
0.25
0.15
0.05
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
PWM
PWM
PFM
PFM
6
9
12
15
18
Input Voltage (V)
21
24
27
30
33
36
mode
6
9
12
15
18
Input Voltage (V)
21
24
27
30
33
36
mode
VOUT = 5 V
VOUT = 5 V
ƒSW = 400 kHz
ƒSW = 1000 kHz
图 9-19. Load Transient
图 9-20. Load Transient
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L
VOUT
VIN
SW
VIN
EN
U1
CBOOT
CIN
CHF
COUT
BOOT
0.1 µF
RFBT
PG
100 kΩ
PG
100 kΩ
VCC
FB
CVCC
1 µF
PGND
AGND
RFBB
图 9-21. Circuit for Application Curves
表 9-3. BOM for Typical Application Curves
(1)
VOUT
FREQUENCY
400 kHz
RFBB
COUT
CIN + CHF
L
U1
3.3 V
5 V
3 × 22 µF
3 × 22 µF
3 × 22 µF
3 × 22 µF
1 × 10 µF + 1 × 220 nF
1 × 10 µF + 1 × 220 nF
1 × 10 µF + 1 × 220 nF
1 × 10 µF + 1 × 220 nF
LMR33640ADDA
LMR33640ADDA
LMR33640DDDA
LMR33640DDDA
43.3 kΩ
24.9 kΩ
43.3 kΩ
24.9 kΩ
6.8 µH, 18 mΩ
6.8 µH, 18 mΩ
3.3 µH, 16 mΩ
3.3 µH, 16 mΩ
400 kHz
3.3 V
5 V
1000 kHz
1000 kHz
(1) The values in this table were selected to enhance certain performance criteria and may not represent typical values.
9.3 What to Do and What Not to Do
• Don't: Exceed the ESD Ratings.
• Don't: Exceed the Absolute Maximum Ratings.
• Don't: Exceed the Recommended Operating Conditions.
• Don't: Allow the EN input to float.
• Don't: Allow the output voltage to exceed the input voltage, nor go below ground.
• Don't: Use the value of RθJA given in the Thermal Information table to design your application. Use the
information in the Maximum Ambient Temperature section.
• Do: Follow all the guidelines and/or suggestions found in this data sheet before committing the design to
production. TI application engineers are ready to help critique your design and PCB layout to help make your
project a success (see the Support Resources).
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10 Power Supply Recommendations
The characteristics of the input supply must be compatible with the recommendations found in this data sheet. In
addition, the input supply must be capable of delivering the required input current to the loaded regulator. The
average input current can be estimated with 方程式 12.
VOUT ∂IOUT
IIN
=
VIN ∂ h
(12)
where
•
η is the efficiency
If the regulator is connected to the input supply through long wires or PCB traces, special care is required to
achieve good performance. The parasitic inductance and resistance of the input cables can have an adverse
effect on the operation of the regulator. The parasitic inductance, in combination with the low-ESR, ceramic input
capacitors, can form an under-damped resonant circuit, resulting in overvoltage transients at the input to the
regulator. The parasitic resistance can cause the voltage at the VIN pin to dip whenever a load transient is
applied to the output. If the application is operating close to the minimum input voltage, this dip can cause the
regulator to momentarily shutdown and reset. The best way to solve these kind of issues is to reduce the
distance from the input supply to the regulator and use an aluminum or tantalum input capacitor in parallel with
the ceramics. The moderate ESR of these types of capacitors help to damp the input resonant circuit and reduce
any overshoots. A value in the range of 20 µF to 100 µF is usually sufficient to provide input damping and help
hold the input voltage steady during large load transients.
Sometimes, for other system considerations, an input filter is used in front of the regulator. This can lead to
instability, as well as some of the effects mentioned above, unless it is designed carefully. The AN-2162 Simple
Success With Conducted EMI From DCDC Converters User Guide provides helpful suggestions when designing
an input filter for any switching regulator.
In some cases, a transient voltage suppressor (TVS) is used on the input of regulators. One class of this device
has a snap-back characteristic (thyristor type). The use of a device with this type of characteristic is not
recommended. When the TVS fires, the clamping voltage falls to a very low value. If this voltage is less than the
output voltage of the regulator, the output capacitors discharge through the device back to the input. This
uncontrolled current flow can damage the device.
The input voltage must not be allowed to fall below the output voltage. In this scenario, such as a shorted input
test, the output capacitors discharges through the internal parasitic diode found between the VIN and SW pins of
the device. During this condition, the current can become uncontrolled, possibly causing damage to the device. If
this scenario is considered likely, then use a Schottky diode between the input supply and the output is
recommended.
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11 Layout
11.1 Layout Guidelines
The PCB layout of any DC/DC converter is critical to the optimal performance of the design. Bad PCB layout can
disrupt the operation of an otherwise good schematic design. Even if the converter regulates correctly, bad PCB
layout can mean the difference between a robust design and one that cannot be mass produced. Furthermore,
the EMI performance of the regulator is dependent on the PCB layout, to a great extent. In a buck converter, the
most critical PCB feature is the loop formed by the input capacitors and power ground, as shown in 图 11-1. This
loop carries large transient currents that can cause large transient voltages when reacting with the trace
inductance. These unwanted transient voltages disrupts the proper operation of the converter. Because of this,
the traces in this loop must be wide and short, and the loop area as small as possible to reduce the parasitic
inductance. 图 11-1 shows the recommended layout for the critical components of the LMR33640.
1. Place the input capacitors as close as possible to the VIN and GND terminals. VIN and GND pins are
adjacent, simplifying the input capacitor placement.
2. Place the bypass capacitor for VCC close to the VCC pin. This capacitor must be placed close to the device
and routed with short, wide traces to the VCC and GND pins.
3. Use wide traces for the CBOOT capacitor. Place CBOOT close to the device with short and wide traces to the
BOOT and SW pins.
4. Place the feedback divider as close as possible to the FB pin of the device. Place RFBB, RFBT, and CFF, if
used, physically close to the device. The connections to FB and GND must be short and close to those pins
on the device. The connection to VOUT can be somewhat longer. However, this latter trace must not be routed
near any noise source (such as the SW node) that can capacitively couple into the feedback path of the
regulator.
5. Use at least one ground plane in one of the middle layers. This plane acts as a noise shield and also a heat
dissipation path.
6. Connect the thermal pad to the ground plane. The SOIC package has a thermal pad (PAD) connection that
must be soldered down to the PCB ground plane. This pad acts as a heat-sink connection and an electrical
ground connection for the regulator. The integrity of this solder connection has a direct bearing on the total
effective RθJA of the application.
7. Provide wide paths for VIN, VOUT, and GND. Making these paths as wide and direct as possible reduces any
voltage drops on the input or output paths of the converter and maximizes efficiency.
8. Provide enough PCB area for proper heat sinking. As stated in 节 9.2.2.10, enough copper area must be
used to ensure a low RθJA, commensurate with the maximum load current and ambient temperature. Make
the top and bottom PCB layers with two-ounce copper and no less than one ounce. With the SOIC package,
use an array of heat-sinking vias to connect the thermal pad (PAD) to the ground plane on the bottom PCB
layer. If the PCB design uses multiple copper layers (recommended), thermal vias can also be connected to
the inner layer heat-spreading ground planes.
9. Keep switch area small. Keep the copper area connecting the SW pin to the inductor as short and wide as
possible. At the same time, the total area of this node must be minimized to help reduce radiated EMI.
See the following PCB layout resources for additional important guidelines:
• Layout Guidelines for Switching Power Supplies Application Report
• Simple Switcher PCB Layout Guidelines Application Report
• Construction Your Power Supply- Layout Considerations Seminar
• Low Radiated EMI Layout Made Simple with LM4360x and LM4600x Application Report
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VIN
KEEP
CURRENT
LOOP
CIN
SW
SMALL
GND
图 11-1. Current Loops with Fast Edges
11.1.1 Ground and Thermal Considerations
As mentioned above, TI recommends using one of the middle layers as a solid ground plane. A ground plane
provides shielding for sensitive circuits and traces. It also provides a quiet reference potential for the control
circuitry. The AGND and PGND pins must be connected to the ground planes using vias next to the bypass
capacitors. PGND pins are connected directly to the source of the low-side MOSFET switch, and also connected
directly to the grounds of the input and output capacitors. The PGND net contains noise at the switching
frequency and can bounce due to load variations. The PGND trace, as well as the VIN and SW traces, must be
constrained to one side of the ground planes. The other side of the ground plane contains much less noise and
must be used for sensitive routes.
TI recommends providing adequate device heat sinking by using the thermal pad (PAD) of the device as the
primary thermal path. Use a minimum 4 × 4 array of 10 mil thermal vias to connect the PAD to the system
ground plane heat sink. The vias must be evenly distributed under the PAD. For the best heat dissipation, use as
much copper as possible for system ground plane and on the top and bottom layers. Use a four-layer board with
the copper thickness for the four layers, starting from the top as: 2 oz / 1 oz / 1 oz / 2 oz. A four-layer board with
enough copper thickness, and proper layout, provides low-current conduction impedance, proper shielding, and
lower thermal resistance.
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11.2 Layout Example
GND
INDUCTOR
HEATSINK
VOUT
COUT
COUT
COUT
CHF
GND
CIN
EN
PGOOD
CVCC
VIN
RFBB
GND
GND
HEATSINK
VIA
Ground Plane
VIA
Bottom
Top Trace
Bottom Trace
图 11-2. Example Layout for HSOIC (DDA) Package
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
12.1.1.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LM33630 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Thermal Design by Insight not Hindsight Application Report
• Texas Instruments, A Guide to Board Layout for Best Thermal Resistance for Exposed Pad Packages
Application Report
• Texas Instruments, Semiconductor and IC Package Thermal Metrics Application Report
• Texas Instruments, Thermal Design Made Simple with LM43604 And LM43602 Application Report
• Texas Instruments, PowerPAD Thermally Enhanced Package Application Report
• Texas Instruments, PowerPAD Made Easy Application Report
• Texas Instruments, Using New Thermal Metrics Application Report
• Texas Instruments, Layout Guidelines for Switching Power Supplies Application Report
• Texas Instruments, Simple Switcher PCB Layout Guidelines Application Report
• Texas Instruments, Construction Your Power Supply- Layout Considerations Seminar
• Texas Instruments, Low Radiated EMI Layout Made Simple with LM4360x and LM4600x Application Report
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
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12.5 Trademarks
PowerPAD™ is a trademark of TI.
TI E2E™ is a trademark of Texas Instruments.
WEBENCH® is a registered trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
12-Jul-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMR33640ADDAR
LMR33640DDDAR
ACTIVE SO PowerPAD
ACTIVE SO PowerPAD
DDA
DDA
8
8
2500 RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR
2500 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR
-40 to 125
-40 to 125
33640A
33640D
Samples
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
12-Jul-2023
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Oct-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
2500
2500
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMR33640ADDAR
LMR33640DDDAR
SO
Power
PAD
DDA
DDA
8
8
330.0
330.0
12.8
12.8
6.4
6.4
5.2
5.2
2.1
2.1
8.0
8.0
12.0
12.0
Q1
Q1
SO
Power
PAD
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Oct-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LMR33640ADDAR
LMR33640DDDAR
SO PowerPAD
SO PowerPAD
DDA
DDA
8
8
2500
2500
366.0
366.0
364.0
364.0
50.0
50.0
Pack Materials-Page 2
PACKAGE OUTLINE
DDA0008J
PowerPADTM SOIC - 1.7 mm max height
S
C
A
L
E
2
.
4
0
0
PLASTIC SMALL OUTLINE
C
6.2
5.8
TYP
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
6X 1.27
8
1
2X
5.0
4.8
3.81
NOTE 3
4
5
0.51
8X
0.31
4.0
3.8
1.7 MAX
B
0.1
C A
B
NOTE 4
0.25
0.10
TYP
SEE DETAIL A
5
4
EXPOSED
THERMAL PAD
0.25
3.1
2.5
GAGE PLANE
0.15
0.00
0 - 8
1.27
0.40
1
8
DETAIL A
TYPICAL
2.6
2.0
4221637/B 03/2016
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MS-012, variation BA.
www.ti.com
EXAMPLE BOARD LAYOUT
DDA0008J
PowerPADTM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
(2.95)
NOTE 9
SOLDER MASK
DEFINED PAD
(2.6)
SOLDER MASK
OPENING
SEE DETAILS
8X (1.55)
1
8
8X (0.6)
(3.1)
SOLDER MASK
SYMM
(1.3)
TYP
OPENING
(4.9)
NOTE 9
6X (1.27)
5
4
(
0.2) TYP
VIA
METAL COVERED
BY SOLDER MASK
SYMM
(5.4)
(1.3) TYP
LAND PATTERN EXAMPLE
SCALE:10X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221637/B 03/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
DDA0008J
PowerPADTM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
(2.6)
BASED ON
0.125 THICK
STENCIL
8X (1.55)
1
8
8X (0.6)
(3.1)
SYMM
BASED ON
0.127 THICK
STENCIL
6X (1.27)
5
4
SEE TABLE FOR
METAL COVERED
BY SOLDER MASK
SYMM
(5.4)
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
2.91 X 3.47
2.6 X 3.1 (SHOWN)
2.37 X 2.83
0.125
0.150
0.175
2.20 X 2.62
4221637/B 03/2016
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DDA0008B
PowerPADTM SOIC - 1.7 mm max height
S
C
A
L
E
2
.
4
0
0
PLASTIC SMALL OUTLINE
C
6.2
5.8
TYP
SEATING PLANE
A
PIN 1 ID
AREA
0.1 C
6X 1.27
8
1
2X
5.0
4.8
3.81
NOTE 3
4
5
0.51
8X
0.31
4.0
3.8
1.7 MAX
B
0.25
C A B
NOTE 4
0.25
0.10
TYP
SEE DETAIL A
5
4
EXPOSED
THERMAL PAD
0.25
3.4
2.8
9
GAGE PLANE
0.15
0.00
0 - 8
1.27
0.40
1
8
DETAIL A
TYPICAL
2.71
2.11
4214849/A 08/2016
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MS-012.
www.ti.com
EXAMPLE BOARD LAYOUT
DDA0008B
PowerPADTM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
(2.95)
NOTE 9
SOLDER MASK
DEFINED PAD
(2.71)
SOLDER MASK
OPENING
SEE DETAILS
8X (1.55)
1
8
8X (0.6)
(3.4)
SOLDER MASK
OPENING
TYP
9
SYMM
(1.3)
(4.9)
NOTE 9
6X (1.27)
5
4
(R0.05) TYP
METAL COVERED
BY SOLDER MASK
SYMM
(5.4)
(
0.2) TYP
VIA
(1.3) TYP
LAND PATTERN EXAMPLE
SCALE:10X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
PADS 1-8
4214849/A 08/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DDA0008B
PowerPADTM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
(2.71)
BASED ON
0.125 THICK
STENCIL
8X (1.55)
(R0.05) TYP
8
1
8X (0.6)
(3.4)
BASED ON
0.125 THICK
STENCIL
SYMM
9
6X (1.27)
5
4
METAL COVERED
BY SOLDER MASK
SYMM
(5.4)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
3.03 X 3.80
2.71 X 3.40 (SHOWN)
2.47 X 3.10
0.125
0.150
0.175
2.29 X 2.87
4214849/A 08/2016
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
www.ti.com
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