LMR54406FDBVR [TI]
LMR544xx SIMPLE SWITCHER® 4-V to 36-V, 0.6-A/1-A Buck Converter in a SOT-23 Package;
| 型号： | LMR54406FDBVR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LMR544xx SIMPLE SWITCHER® 4-V to 36-V, 0.6-A/1-A Buck Converter in a SOT-23 Package |
| 文件： | 总27页 (文件大小：1625K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LMR54410, LMR54406
SLUSEG8 – OCTOBER 2021
LMR544xx SIMPLE SWITCHER® 4-V to 36-V, 0.6-A/1-A Buck Converter
in a SOT-23 Package
1 Features
3 Description
•
Functional Safety-Capable
The LMR544xx is
a
wide-VIN, easy-to-use
synchronous buck converter capable of driving up to
1-A and 0.6-A load current. With a wide input range of
4 V to 36 V, the device is suitable for a wide range of
industrial applications for power conditioning from an
unregulated source.
– Documentation available to aid functional safety
system design
•
Configured for rugged industrial applications
– 4-V to 36-V input voltage range
– 0.6-A/1-A continuous output current
– 60-ns minimum switching on time
– 1.1-MHz fixed switching frequency
– –40°C to 150°C junction temperature range
– 98% maximum duty cycle
– Monotonic start-up with pre-biased output
– Short circuit protection with hiccup mode
– Precision enable
– ±1% tolerance voltage reference
Small solution size and ease of use
– Integrated synchronous rectification
– Internal compensation for ease of use
– SOT-23 package
The LMR544xx operates at 1.1-MHz switching
frequency to support use of relatively small inductors
for an optimized solution size. It has a PFM version
to realize high efficiency at light load and a FPWM
version to achieve constant frequency and small
output voltage ripple over the full load range. Soft-
start and compensation circuits are implemented
internally, which allow the device to be used with
minimal external components.
•
The device has built-in protection features, such as
cycle-by-cycle current limit, hiccup mode short-circuit
protection, and thermal shutdown in case of excessive
power dissipation.
•
•
Pin-to-pin compatible with the LMR14010A,
LMR50410, and TPS560430
Various options in pin-to-pin compatible package
Device Information
PACKAGE(1)
BODY SIZE (NOM)
– PFM and forced PWM (FPWM) options
PART NUMBER
LMR54410
2 Applications
SOT-23
2.90 mm × 1.60 mm
LMR54406
•
•
•
•
Major appliances
PLC, DCS, and PAC
Smart meters
General purpose wide VIN power supplies
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
VIN up to 36 V
CB
VIN
CIN
CBOOT
L
VOUT
SW
FB
EN
RFBT
GND
COUT
RFBB
Simplified Schematic
Efficiency Versus Output Current; VOUT = 5 V, 1100
kHz
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change
without notice.
LMR54410, LMR54406
SLUSEG8 – OCTOBER 2021
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Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 4
7.1 Absolute Maximum Ratings........................................ 4
7.2 ESD Ratings............................................................... 4
7.3 Recommended Operating Conditions.........................4
7.4 Thermal Information....................................................5
7.5 Electrical Characteristics.............................................5
7.6 Timing Requirements..................................................6
7.7 System Characteristics............................................... 6
8 Detailed Description........................................................7
8.1 Overview.....................................................................7
8.2 Functional Block Diagram...........................................8
8.3 Feature Description.....................................................8
8.4 Device Functional Modes..........................................13
9 Application and Implementation..................................14
9.1 Application Information............................................. 14
9.2 Typical Application.................................................... 14
10 Power Supply Recommendations..............................19
11 Layout...........................................................................20
11.1 Layout Guidelines................................................... 20
11.2 Layout Example...................................................... 21
12 Device and Documentation Support..........................22
12.1 Device Support....................................................... 22
12.2 Documentation Support.......................................... 22
12.3 Receiving Notification of Documentation Updates..22
12.4 Support Resources................................................. 22
12.5 Trademarks.............................................................22
12.6 Electrostatic Discharge Caution..............................22
12.7 Glossary..................................................................22
13 Mechanical, Packaging, and Orderable
Information.................................................................... 22
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DATE
REVISION
NOTES
October 2021
*
Advance Information
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5 Device Comparison Table
ORDERABLE PART NUMBER
LMR54410DBVR
OUTPUT CURRENT
FREQUENCY
1100 kHz
PFM OR FPWM
PFM
OUTPUT
Adjustable
Adjustable
Adjustable
Adjustable
1 A
1 A
LMR54410FDBVR
1100 kHz
FPWM
LMR54406DBVR
0.6 A
0.6 A
1100 kHz
PFM
LMR54406FDBVR
1100 kHz
FPWM
6 Pin Configuration and Functions
CB
1
6
SW
VIN
GND
FB
2
3
5
4
EN
Figure 6-1. 6-Pin SOT-23 DBV Package (Top View)
Table 6-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
NO
Bootstrap capacitor connection for high-side FET driver. Connect a high quality 100-nF capacitor from
this pin to the SW pin.
CB
1
P
G
A
A
P
P
Power ground pins. Connected to the source of low-side FET internally. Connect to system ground,
ground side of CIN and COUT. The path to CIN must be as short as possible.
GND
FB
2
3
4
5
6
Feedback input to the converter. Connect a resistor divider to set the output voltage. Never short this
terminal to ground during operation.
Precision enable input to the converter. Do not float. High = on, low = off. Can be tied to VIN.
Precision enable input allows an adjustable UVLO by an external resistor divider.
EN
Supply input pin to the internal bias LDO and high-side FET. Connect to the input supply and input
bypass capacitors CIN. Input bypass capacitors must be directly connected to this pin and GND.
VIN
SW
Switching output of the converter. Internally connected to source of the high-side FET and drain of the
low-side FET. Connect to the power inductor.
(1) A = Analog, P = Power, G = Ground
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7 Specifications
7.1 Absolute Maximum Ratings
Over junction temperature range of –40°C to 150°C (unless otherwise noted)(1)
MIN
MAX
50(3)
UNIT
VIN to GND(2)
–0.3
–0.3
–0.3
–0.3
–3.5
–0.3
–40
V
V
Input voltage
EN to GND(2)
VIN + 0.3
5.5
FB to GND
V
SW to GND(2)
VIN + 0.3
44
V
Output voltage
SW to GND less than 10-ns transients(2)
V
CBOOT to SW
5.5
V
Junction Temperature TJ
Storage temperature, Tstg
150
°C
°C
–65
150
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) Absolute maximum ratings are rated under typical room temperature conditions. Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the device.
(3) A maximum of 50 V can be sustained at this pin at room temperature for a duration of ≤ 1 s at a duty cycle of ≤ 0.01%. In short 100-μS
VIN transient at room temperature.
7.2 ESD Ratings
VALUE
±2500
±750
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
Over the recommended operating junction temperature range of –40°C to 150°C (unless otherwise noted)
MIN
MAX
UNIT
VIN to GND
4
36
VIN
28
V
V
V
A
A
Input voltage
Output voltage
Output current
EN to GND(1)
0
(2)
VOUT
1
LMR54410
LMR54406
0
1
0
0.6
(1) The voltage on this pin must not exceed the voltage on the VIN pin by more than 0.3 V.
(2) Under no conditions should the output voltage be allowed to fall below 0 V.
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7.4 Thermal Information
LMR544XX
THERMAL METRIC(1)
DBV(SOT-23)
UNIT
6 PINS
173
116
31
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
20
ψJB
30
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
Limits apply over operating junction temperature (TJ) range of –40°C to +150°C, unless otherwise stated. Minimum and
Maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric
norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply: VIN
= 4 V to 36 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE (VIN PIN)
Rising threshold
3.55
3.25
3.75
3.45
0.3
4
V
V
V
VIN_UVLO
Undervoltage lockout thresholds
Falling threshold
Hysteresis
3.65
Operating quiescent current
(nonswitching)(1)
VEN = 3.3 V, VFB = 1.1 V (PFM variant
only)
IQ-nonSW
ISD
80
3
120
10
µA
µA
Shutdown quiescent current;
measured at the VIN pin
VEN = 0 V
ENABLE (EN PIN)
VEN-VOUT-H Enable input high-level for VOUT
VEN-VOUT-L Enable input low-level for VOUT
VEN-VOUT-HYS Enable input hysteresis for VOUT
ILKG-EN Enable input leakage current
VOLTAGE REFERENCE (FB PIN)
VENABLE rising
VENABLE falling
Hysteresis
1.1
1.23
1.1
130
10
1.36
1.22
V
V
0.95
mV
nA
VEN = 3.3 V
200
VFB
Feedback voltage
0.78
0.8
0.2
0.82
V
ILKG-FB
Feedback leakage current
FB = 1.2 V
nA
SWITCHING FREQUENCY
FOSC
Internal oscillator frequency
0.935
1.1
1.265
MHz
CURRENT LIMITS AND HICCUP
ISC
High-side current limit(2)
Low-side current limit(2)
High-side current limit(2)
Low-side current limit(2)
Zero cross detector threshold
LMR54410
1.6
1.1
A
A
A
A
A
ILS-LIMIT
ISC
ILS-LIMIT
IL-ZC
LMR54410
LMR54406
1.3
LMR54406
0.9
PFM variants only
–0.02
MOSFETS
High-side MOSFET ON-
resistance
RDS-ON-HS
TJ = 25℃, VIN = 12 V
450
240
mΩ
mΩ
RDS-ON-LS
THERMAL SHUTDOWN
TSD-Rising Thermal shutdown
TSD-Falling Thermal shutdown
Low-side MOSFET ON-resistance TJ = 25℃, VIN = 12 V
Shutdown threshold
Recovery threshold
170
158
°C
°C
(1) This is the current used by the device open loop. It does not represent the total input current of the system when in regulation.
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(2) The current limit values in this table are tested, open loop, in production. They may differ from those found in a closed loop application.
7.6 Timing Requirements
Limits apply over operating junction temperature (TJ ) range of –40°C to +150°C, unless otherwise stated. Minimum and
Maximum limits(1) are specified through test, design or statistical correlation. Typical values represent the most likely
parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following
conditions apply: VIN = 4 V- 36 V.
PARAMETER
TEST CONDTIONS
IOUT = 1 A
IOUT = 1 A
MIN
TYP
MAX
UNIT
tON-MIN
tOFF-MIN
tON-MAX
tSS
Minimum switch on time
Minimum switch off time
Maximum switch on time
Internal soft-start time
60
ns
110
7.5
1.8
ns
µs
ms
(1) MIN and MAX limits are 100% production tested at 25°C. Limits over the operating temperature range verified through correlation
using
Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
7.7 System Characteristics
The following specifications apply to a typical application circuit with nominal component values. Specifications in the typical
(TYP) column apply to TJ = 25°C only. Specifications in the minimum (MIN) and maximum (MAX) columns apply to the
case of typical components over the temperature range of TJ = –40°C to 150°C. These specifications are not ensured by
production testing.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIN
Operating input voltage range
4
36
V
Adjustable output voltage
regulation(1)
VOUT
PFM operation
–1.5%
–1.5%
2.5%
1.5%
Adjustable output voltage
regulation(1)
VOUT
FPWM operation
Input supply current when in
regulation
VIN = 12 V, VOUT = 3.3 V, IOUT = 0 A,
RFBT = 1 MΩ, PFM variant
ISUPPLY
DMAX
VHC
90
98%
µA
V
Maximum switch duty cycle(2)
FB pin voltage required to trip short-
circuit hiccup mode
0.325
tD
Switch voltage dead time
2
170
158
ns
°C
°C
TSD
TSD
Thermal shutdown temperature
Thermal shutdown temperature
Shutdown temperature
Recovery temperature
(1) Deviation in VOUT from nominal output voltage value at VIN = 24 V, IOUT = 0 A to full load
(2) In dropout the switching frequency drops to increase the effective duty cycle. The lowest frequency is clamped at approximately: FMIN
= 1 / (tON-MAX + tOFF-MIN). DMAX = tON-MAX / (tON-MAX + tOFF-MIN).
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8 Detailed Description
8.1 Overview
The LMR544xx converter is an easy-to-use synchronous step-down DC-DC converter operating from a 4-V to
36-V supply voltage. The LMR54410 is capable of delivering up to 1-A DC load current in a very small solution
size while the LMR54406 is capable of delivering up to 0.6-A load current. The family has multiple versions
applicable to various applications. See Section 5 for detailed information.
The LMR544xx employs fixed-frequency peak-current mode control. The PFM version enters PFM mode at light
load to achieve high efficiency. A FPWM version is provided to achieve low output voltage ripple, tight output
voltage regulation, and constant switching frequency at light load. The device is internally compensated, which
reduces design time and requires few external components.
Additional features, such as precision enable and internal soft start, provide a flexible and easy-to-use solution
for a wide range of applications. Protection features include the following:
•
•
•
•
Thermal shutdown
VIN undervoltage lockout
Cycle-by-cycle current limit
Hiccup mode short-circuit protection
This family of devices requires very few external components and has a pinout designed for simple, optimal PCB
layout.
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8.2 Functional Block Diagram
EN
VCC
Enable
LDO
VIN
CB
Precision
Enable
HSI Sense
Internal
SS
EA
REF
RC
CC
TSD
UVLO
FB
PWM CONTROL LOGIC
PFM
Detector
SW
Slope
Comp
Ton_min/Toff_min
Detector
Freq
Foldback
HICCUP
Detector
Zero
Cross
LSI Sense
Oscillator
FB
GND
8.3 Feature Description
8.3.1 Fixed Frequency Peak Current Mode Control
The following operating description of the LMR544xx refers to Section 8.2 and to the waveforms in Figure
8-1. The LMR544xx is a step-down synchronous buck converter with integrated high-side (HS) and low-side
(LS) switches (synchronous rectifier). The LMR544xx supplies a regulated output voltage by turning on the
high-side and low-side NMOS switches with controlled duty cycle. During high-side switch ON time, the SW
pin voltage swings up to approximately VIN, and the inductor current, iL, increases with a linear slope of (VIN
–
VOUT) / L. When the high-side switch is turned off by the control logic, the low-side switch is turned on after an
anti-shoot-through dead time. Inductor current discharges through the low-side switch with a slope of –VOUT / L.
The control parameter of a buck converter is defined as Duty Cycle D = tON / TSW, where tON is the high-side
switch ON time and TSW is the switching period. The converter control loop maintains a constant output voltage
by adjusting the duty cycle D. In an ideal buck converter, where losses are ignored, D is proportional to the
output voltage and inversely proportional to the input voltage: D = VOUT / VIN.
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VSW
VIN
D = tON/ TSW
tON
tOFF
t
0
TSW
iL
ILPK
IOUT
∆iL
t
0
Figure 8-1. SW Node and Inductor Current Waveforms in Continuous Conduction Mode (CCM)
The LMR544xx employs fixed-frequency peak-current mode control. A voltage feedback loop is used to get
accurate DC voltage regulation by adjusting the peak-current command based on voltage offset. The peak
inductor current is sensed from the high-side switch and compared to the peak current threshold to control the
ON time of the high-side switch. The voltage feedback loop is internally compensated, which allows for fewer
external components, making designing easy and providing stable operation when using a variety of output
capacitors. The converter operates with fixed switching frequency at normal load conditions. During light-load
condition, the LMR544xx operates in PFM mode to maintain high efficiency (PFM version) or in FPWM mode for
low output voltage ripple, tight output voltage regulation, and constant switching frequency (FPWM version).
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8.3.2 Adjustable Output Voltage
A precision 0.8-V reference voltage (VREF) is used to maintain a tightly regulated output voltage over the entire
operating temperature range. The output voltage is set by a resistor divider from VOUT to the FB pin. It is
recommended to use 1% tolerance resistors with a low temperature coefficient for the FB divider. Select the
bottom-side resistor, RFBB, for the desired divider current and use Equation 1 to calculate the top-side resistor,
RFBT. The recommended range for RFBT is 10 kΩ to 100 kΩ. A lower RFBT value can be used if pre-loading
is desired to reduce the VOUT offset in PFM operation. Lower RFBT values reduce efficiency at very light load.
Less static current goes through a larger RFBT value and can be more desirable when light-load efficiency is
critical. However, RFBT values larger than 1 MΩ are not recommended because they make the feedback path
more susceptible to noise. Larger RFBT values require a more carefully designed feedback path trace from the
feedback resistors to the feedback pin of the device. The tolerance and temperature variation of the resistor
divider network affect the output voltage regulation.
VOUT
RFBT
FB
RFBB
Figure 8-2. Output Voltage Setting
VOUT - VREF
RFBT
=
× RFBB
VREF
(1)
8.3.3 Enable
The voltage on the EN pin controls the ON/OFF operation of the LMR544xx. A voltage of less than 0.95 V shuts
down the device, while a voltage of greater than 1.36 V is required to start the converter. The EN pin is an input
and cannot be left open or floating. The simplest way to enable the operation of the LMR544xx is to connect EN
to VIN. This allows self-start-up of the LMR544xx when VIN is within the operating range.
Many applications benefit from the employment of an enable divider, RENT and RENB (Figure 8-3) to establish
a precision system UVLO level for the converter. A system UVLO can be used for supplies operating from
utility power as well as battery power. It can be used for sequencing, ensuring reliable operation, or supplying
protection, such as a battery discharge level. An external logic signal can also be used to drive the EN input for
system sequencing and protection.
Note
The EN pin voltage must not to be greater than VIN + 0.3 V. It is not recommended to apply EN
voltage when VIN is 0 V.
VIN
RENT
EN
RENB
Figure 8-3. System UVLO by Enable Divider
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8.3.4 Minimum ON Time, Minimum OFF Time, and Frequency Foldback
The minimum ON time (TON_MIN) is the shortest duration of time that the high-side switch can be turned on.
TON_MIN is typically 60 ns for the LMR544xx. The minimum OFF time (TOFF_MIN) is the shortest duration of time
that the high-side switch can be off. TOFF_MIN is typically 110 ns. In CCM operation, TON_MIN and TOFF_MIN limit
the voltage conversion range without switching frequency foldback.
The minimum duty cycle without frequency foldback allowed is:
DMIN = TON_MIN × fSW
(2)
(3)
The maximum duty cycle without frequency foldback allowed is:
DMAX = 1 - TOFF_MIN × fSW
Given a required output voltage, the maximum VIN without frequency foldback can be found by:
VOUT
VIN_MAX
=
fSW × TON_MIN
(4)
(5)
The minimum VIN without frequency foldback can be calculated by:
VOUT
VIN_MIN
=
1- fSW × TOFF_MIN
In the LMR544xx, a frequency foldback scheme is employed once the TON_MIN or TOFF_MIN is triggered, which
can extend the maximum duty cycle or lower the minimum duty cycle.
The on time decreases while VIN voltage increases. Once the on time decreases to TON_MIN, the switching
frequency starts to decrease while VIN continues to go up, which lowers the duty cycle further to keep VOUT in
regulation according to Equation 2.
The frequency foldback scheme also works once larger duty cycle is needed under a low VIN condition. The
frequency decreases once the device hits its TOFF_MIN, which extends the maximum duty cycle according to
Equation 3. In such condition, the frequency can be as low as approximately 133 kHz. A wide range of frequency
foldback allows for the LMR544xx output voltage to stay in regulation with a much lower supply voltage VIN,
which leads to a lower effective dropout.
With frequency foldback while maintaining a regulated output voltage, VIN_MAX is raised and VIN_MIN is lowered
by decreased fSW
.
8.3.5 Bootstrap Voltage
The LMR544xx provides an integrated bootstrap voltage converter. A small capacitor between the CB and SW
pins provides the gate drive voltage for the high-side MOSFET. The bootstrap capacitor is refreshed when the
high-side MOSFET is off and the low-side switch is on. The recommended value of the bootstrap capacitor
is 0.1 µF. A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 16 V or higher is
recommended for stable performance over temperature and voltage.
8.3.6 Overcurrent and Short Circuit Protection
The LMR544xx incorporates both peak and valley inductor current limit to provide protection to the device from
overloads and short circuits and limit the maximum output current. Valley current limit prevents inductor current
runaway during short circuits on the output, while both peak and valley limits work together to limit the maximum
output current of the converter. Cycle-by-cycle current limit is used for overloads, while hiccup mode is used for
sustained short circuits.
High-side MOSFET overcurrent protection is implemented by the nature of the peak current mode control. The
high-side switch current is sensed when the high-side is turned on after a set blanking time. The high-side switch
current is compared to the output of the Error Amplifier (EA) minus slope compensation every switching cycle.
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See Section 8.2 for more details. The peak current of high-side switch is limited by a clamped maximum peak
current threshold Isc (see Section 7.5), which is constant.
The current going through the low-side MOSFET is also sensed and monitored. When the low-side switch turns
on, the inductor current begins to ramp down. The low-side switch is not turned OFF at the end of a switching
cycle if its current is above the low-side current limit, ILS_LIMIT (see Section 7.5). The low-side switch is kept ON
so that inductor current keeps ramping down until the inductor current ramps below ILS_LIMIT. Then, the low-side
switch is turned OFF and the high-side switch is turned on after a dead time. After ILS_LIMIT is achieved, peak
and valley current limit controls the maximum current delivered and it can be calculated using Equation 6.
ILS_LIMIT +ISC
IOUT
=
max
2
(6)
If the feedback voltage is lower than 40% of the VREF, the current of the low-side switch triggers ILS_LIMIT for
256 consecutive cycles and hiccup current protection mode is activated. In hiccup mode, the converter shuts
down and keeps off for a period of hiccup, THICCUP (135 ms typical) before the LMR544x tries to start again. If
overcurrent or a short-circuit fault condition still exist, hiccup repeats until the fault condition is removed. Hiccup
mode reduces power dissipation under severe overcurrent conditions, preventing overheating and potential
damage to the device.
For the FPWM version, the inductor current is allowed to go negative. When this current exceeds the low-side
negative current limit, ILS_NEG, the low-side switch is turned off and high-side switch is turned on immediately.
This is used to protect the low-side switch from excessive negative current.
8.3.7 Soft Start
The integrated soft-start circuit prevents input inrush current impacting the LMR544xx and the input power
supply. Soft start is achieved by slowly ramping up the internal reference voltage when the device is first enabled
or powered up. The typical soft-start time is 1.8 ms.
The LMR544xx also employs overcurrent protection blanking time, TOCP_BLK (33 ms typical), at the beginning
of power up. Without this feature, in applications with a large amount of output capacitors and high VOUT, the
inrush current is large enough to trigger the current-limit protection, which can cause a false start as the device
enters into hiccup mode. This results in a continuous recycling of soft start without raising up to the programmed
output voltage. The LMR544xx is able to charge the output capacitor to the programmed VOUT by controlling the
average inductor current during the start-up sequence in the blanking time, TOCP_BLK
.
8.3.8 Thermal Shutdown
The LMR544xx provides an internal thermal shutdown to protect the device when the junction temperature
exceeds 170°C. Both high-side and low-side FETs stop switching in thermal shutdown. Once the die
temperature falls below 158°C, the device reinitiates the power-up sequence controlled by the internal soft-start
circuitry.
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8.4 Device Functional Modes
8.4.1 Shutdown Mode
The EN pin provides electrical ON/OFF control for the LMR544xx. When VEN is below 0.95 V, the device is
in shutdown mode. The LMR544xx also employs VIN undervoltage lockout protection (UVLO). If VIN voltage is
below its UVLO threshold of 3.25 V, the converter is turned off.
8.4.2 Active Mode
The LMR544xx is in active mode when both VEN and VIN are above their respective operating threshold. The
simplest way to enable the LMR544xx is to connect the EN pin to VIN pin. This allows self-start-up when the
input voltage is in the operating range of 4.0 V to 36 V. See Section 8.3.3 for details on setting these operating
levels.
In active mode, depending on the load current, the LMR544xx is in one of four modes:
1. Continuous conduction mode (CCM) with fixed switching frequency when load current is greater than half of
the peak-to-peak inductor current ripple (for both PFM and FPWM versions)
2. Discontinuous conduction mode (DCM) with fixed switching frequency when load current is less than half of
the peak-to-peak inductor current ripple(only for PFM version)
3. Pulse frequency modulation mode (PFM) when switching frequency is decreased at very light load (only for
PFM version)
4. Forced pulse width modulation mode (FPWM) with fixed switching frequency even at light load (only for
FPWM version)
8.4.3 CCM Mode
Continuous conduction mode (CCM) operation is employed in the LMR544xx when the load current is greater
than half of the peak-to-peak inductor current. In CCM operation, the frequency of operation is fixed, output
voltage ripple is at a minimum in this mode and the maximum output current of 1 A or 0.6 A can be supplied by
the LMR54410 or LMR54406, respectively.
8.4.4 Light Load Operation (PFM Version)
For PFM version, when the load current is lower than half of the peak-to-peak inductor current in CCM, the
LMR544xx operates in discontinuous conduction mode (DCM), also known as diode emulation mode (DEM). In
DCM operation, the low-side switch is turned off when the inductor current drops to ILS_ZC (20 mA typical) to
improve efficiency. Both switching losses and conduction losses are reduced in DCM, compared to forced PWM
operation at light load.
During light load operation, pulse frequency modulation (PFM) mode is activated to maintain high efficiency
operation. When either the minimum high-side switch ON time tON_MIN or the minimum peak inductor current
IPEAK_MIN (300 mA typical) is reached, the switching frequency decreases to maintain regulation. In PFM mode,
switching frequency is decreased by the control loop to maintain output voltage regulation when load current
reduces. Switching loss is further reduced in PFM operation due to a significant drop in effective switching
frequency.
8.4.5 Light-Load Operation (FPWM Version)
For FPWM version, LMR544xx is locked in PWM mode at full load range. This operation is maintained, even
in no-load condition, by allowing the inductor current to reverse its normal direction. This mode trades off
reduced light load efficiency for low output voltage ripple, tight output voltage regulation, and constant switching
frequency.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The LMR544xx is a step-down DC-to-DC converter. The LMR54410 is typically used to convert a higher input
voltage to a lower output DC voltage with a maximum output current of 1 A. The LMR54406 is typically used
to convert a higher input voltage to a lower output DC voltage with a maximum output current of 0.6 A. The
following design procedure can be used to select components for the LMR544xx.
9.2 Typical Application
The LMR54410 only requires a few external components to convert from a wide voltage range supply to a fixed
output voltage. Figure 9-1 shows a basic schematic.
Figure 9-1. Application Circuit
The external components have to fulfill the needs of the application and the stability criteria of the control loop of
the device. Table 9-1 can be used to simplify the output filter component selection.
Table 9-1. L and COUT Typical Values
fSW (kHz)
VOUT (V)
L (µH)
COUT (µF) (1)
RFBT (kΩ)
69.8
RFBB (kΩ)
3.3
5
10
22 µF / 10 V
22.1
1100
15
33
22 µF / 10 V
118
22.1
22.1
12
22 µF / 25 V + 10 µF / 25 V
309
(1) A ceramic capacitor is used in this table.
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9.2.1 Design Requirements
The detailed design procedure is described based on a design example. For this design example, use the
parameters listed in Table 9-2 as the input parameters.
Table 9-2. Design Example Parameters
PARAMETER
VALUE
Input voltage, VIN
5 V typical, range from 6 V to 36 V
Output voltage, VOUT
5 V ±3%
1 A
Maximum output current, IOUT_MAX
Output overshoot/undershoot (0 A to 1 A)
Output voltage ripple
5%
0.5%
Operating frequency
1100 kHz
9.2.2 Detailed Design Procedure
9.2.2.1 Output Voltage Set-Point
The output voltage of the LMR54410 device is externally adjustable using a resistor divider network. The divider
network is comprised of a top feedback resistor RFBT and bottom feedback resistor RFBB. Equation 7 is used to
determine the output voltage of the converter:
VOUT - VREF
RFBT
=
× RFBB
VREF
(7)
Choose the value of RFBB to be 22.1 kΩ. With the desired output voltage set to 5 V and the VREF = 0.8 V, the
RFBT value can then be calculated using Equation 7. The formula yields to a value 116 kΩ, a standard value of
118 kΩ is selected.
9.2.2.2 Switching Frequency
The higher switching frequency allows for lower value inductors and smaller output capacitors, which results
in smaller solution size and lower component cost. However, higher switching frequency brings more switching
loss, making the solution less efficient and produce more heat. The switching frequency is also limited by the
minimum on time of the integrated power switch, the input voltage, the output voltage, and the frequency shift
limitation as mentioned in Section 8.3.4. For this example, a switching frequency of 1100 kHz is selected.
9.2.2.3 Inductor Selection
The most critical parameters for the inductor are the inductance, saturation current, and the RMS current. The
inductance is based on the desired peak-to-peak ripple current ΔiL. Since the ripple current increases with
the input voltage, the maximum input voltage is always used to calculate the minimum inductance LMIN. Use
Equation 9 to calculate the minimum value of the output inductor. KIND is a coefficient that represents the amount
of inductor ripple current relative to the maximum output current of the device. A reasonable value of KIND must
be 20% to 60% of maximum IOUT supported by converter. During an instantaneous overcurrent operation event,
the RMS and peak inductor current can be high. The inductor saturation current must be higher than peak
current limit level.
VOUT
×
V
- VOUT
IN_MAX
(
)
ûiL =
VIN_MAX × L × fSW
(8)
(9)
VIN_MAX - VOUT
VOUT
LMIN
=
×
IOUT × K IND
VIN_MAX × fSW
In general, it is preferable to choose lower inductance in switching power supplies, because it usually
corresponds to faster transient response, smaller DCR, and reduced size for more compact designs. Too low
of an inductance can generate too large of an inductor current ripple such that overcurrent protection at the
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full load can be falsely triggered. It also generates more inductor core loss since the current ripple is larger.
Larger inductor current ripple also implies larger output voltage ripple with the same output capacitors. With peak
current mode control, it is recommended to have adequate amount of inductor ripple current. A larger inductor
ripple current improves the comparator signal-to-noise ratio.
For this design example, choose KIND = 0.4. The minimum inductor value is calculated to be 15.36 µH. Choose
the nearest standard 15-µH ferrite inductor with a capability of 1.5-A RMS current and 2.5-A saturation current.
9.2.2.4 Output Capacitor Selection
The device is designed to be used with a wide variety of LC filters. It is generally desired to minimize the output
capacitance to keep cost and size down. The output capacitor or capacitors, COUT, must be chosen with care
since it directly affects the steady state output voltage ripple, loop stability, and output voltage overshoot and
undershoot during load current transient. The output voltage ripple is essentially composed of two parts. One
part is caused by the inductor ripple current flowing through the Equivalent Series Resistance (ESR) of the
output capacitors:
ûVOUT_ESR = ûiL × ESR = KIND ×IOUT × ESR
(10)
The other part is caused by the inductor current ripple charging and discharging the output capacitors:
ûiL
KIND ×IOUT
ûVOUT_C
=
=
8×fSW × COUT 8×fSW × COUT
(11)
The two components of the voltage ripple are not in-phase, therefore, the actual peak-to-peak ripple is less than
the sum of the two peaks.
Output capacitance is usually limited by transient performance specifications if the system requires tight voltage
regulation with presence of large current steps and fast slew rates. When a large load step occurs, output
capacitors provide the required charge before the inductor current can slew to an appropriate level. The control
loop of the converter usually requires eight or more clock cycles to regulate the inductor current equal to the
new load level during this time. The output capacitance must be large enough to supply the current difference
for eight clock cycles to maintain the output voltage within the specified range. Equation 12 shows the minimum
output capacitance needed for a specified VOUT overshoot and undershoot.
8 × IOH -IOL
(
)
1
2
COUT
>
×
fSW × ûVOUT_SHOOT
(12)
where
•
•
•
•
KIND = Ripple ratio of the inductor current (ΔiL / IOUT
IOL = Low level output current during load transient
IOH = High level output current during load transient
)
VOUT_SHOOT = Target output voltage overshoot or undershoot
For this design example, the target output ripple is 30 mV. Assuming ΔVOUT_ESR = ΔVOUT_C = 30 mV, choose
KIND = 0.4. Equation 10 yields ESR no larger than 75 mΩ and Equation 11 yields COUT no smaller than 2.38
µF. For the target overshoot and undershoot limitation of this design, ΔVOUT_SHOOT = 8% × VOUT = 400 mV. The
COUT can be calculated to be no less than 14.3 µF by Equation 12. In summary, the most stringent criteria for
the output capacitor is 14.3 µF. Considering derating, one 22-µF, 10-V, X7R ceramic capacitor with 10-mΩ ESR
is used.
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9.2.2.5 Input Capacitor Selection
The LMR54410 device requires a high frequency input decoupling capacitor or capacitor. The typical
recommended value for the high frequency decoupling capacitor is 2.2 µF or higher. A high-quality ceramic
type X5R or X7R with sufficiency voltage rating is recommended. The voltage rating must be greater than
the maximum input voltage. To compensate the derating of ceramic capacitors, a voltage rating of twice the
maximum input voltage is recommended. For this design, one 2.2-µF, X7R dielectric capacitor rated for 50 V is
used for the input decoupling capacitor. The equivalent series resistance (ESR) is approximately 10 mΩ, and the
current rating is 1 A. Include a capacitor with a value of 0.1 µF for high-frequency filtering and place it as close
as possible to the device pins.
9.2.2.6 Bootstrap Capacitor
Every LMR54410 design requires a bootstrap capacitor, CBOOT. The recommended bootstrap capacitor is 0.1
µF and rated at 16 V or higher. The bootstrap capacitor is located between the SW pin and the CB pin.
The bootstrap capacitor must be a high-quality ceramic type with X7R or X5R grade dielectric for temperature
stability.
9.2.2.7 Undervoltage Lockout Set-Point
The system undervoltage lockout (UVLO) is adjusted using the external voltage divider network of RENT and
RENB. The UVLO has two thresholds, one for power up when the input voltage is rising and one for power down
or brown outs when the input voltage is falling. Equation 13 can be used to determine the VIN UVLO level.
RENT + RENB
VIN_RISING = VENH
×
RENB
(13)
The EN rising threshold (VENH) for LMR54410 is set to be 1.23 V (typical). Choose a value of 200 kΩ for RENB to
minimize input current from the supply. If the desired VIN UVLO level is at 6.0 V, then the value of RENT can be
calculated using Equation 14:
≈
’
÷
◊
VIN_RISING
RENT
=
-1 × R
∆
∆
«
÷
ENB
VENH
(14)
The above equation yields a value of 775.6 kΩ, a standard value of 768 kΩ is selected. The resulting falling
UVLO threshold, equal to 5.3 V, can be calculated by Equation 15 where EN hysteresis voltage, VEN_HYS, is 0.13
V (typical).
RENT + RENB
VIN_FALLING = V
(
- VEN_HYS ×
)
ENH
RENB
(15)
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9.2.3 Application Curves
Unless otherwise specified the following conditions apply: VIN = 12 V, VOUT = 5 V, fSW = 1100 kHz, L = 15 µH,
COUT = 22 µF, TA = 25°C.
VEN [2V/div]
VIN [5V/div]
VOUT [2V/div]
VOUT [2V/div]
IL [1A/div]
IOUT = 1 A
IL [1A/div]
IOUT = 1 A
Time [2ms/div]
Time [200us/div]
Time [100ms/div]
Time [2ms/div]
Time [800us/div]
Time [100ms/div]
Figure 9-2. Start-Up by VIN
Figure 9-3. Start-Up by EN
VIN [10V/div]
VOUT(AC) [100mV/div]
VOUT(AC) [50mV/div]
IL [500mA/div]
IOUT [500mA/div]
VIN = 12 to 24 V, 0.1 V / ꢀs
IOUT = 0.5 to 1 A, 80mA / ꢀs
Figure 9-4. Load Transient
Figure 9-5. Line Transient
VOUT [2V/div]
VOUT [2V/div]
IL [1A/div]
IL [1A/div]
IOUT = 0 mA to short
IOUT = short to 0 mA
Figure 9-6. Short Protection
Figure 9-7. Short Recovery
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10 Power Supply Recommendations
The LMR544xx is designed to operate from an input voltage supply range between 4.0 V and 36 V. This input
supply must be well-regulated and able to withstand maximum input current and maintain a stable voltage. The
resistance of the input supply rail must be low enough that an input current transient does not cause a high
enough drop at the LMR544xx supply voltage that can cause a false UVLO fault triggering and system reset.
If the input supply is located more than a few inches from the LMR544xx additional bulk capacitance can be
required in addition to the ceramic bypass capacitors. The amount of bulk capacitance is not critical, but a 10-µF
or 22-µF electrolytic capacitor is a typical choice.
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11 Layout
11.1 Layout Guidelines
Layout is a critical portion of good power supply design. The following guidelines will help users design a PCB
with the best power conversion performance, thermal performance, and minimized generation of unwanted EMI.
1. The input bypass capacitor CIN must be placed as close as possible to the VIN and GND pins. Grounding for
both the input and output capacitors should consist of localized top side planes that connect to the GND pin.
2. Minimize trace length to the FB pin net. Both feedback resistors, RFBT and RFBB, must be located close to
the FB pin. If VOUT accuracy at the load is important, make sure VOUT sense is made at the load. Route VOUT
sense path away from noisy nodes and preferably through a layer on the other side of a shielded layer.
3. Use ground plane in one of the middle layers as noise shielding and heat dissipation path if possible.
4. Make VIN, VOUT, and ground bus connections as wide as possible. This reduces any voltage drops on the
input or output paths of the converter and maximizes efficiency.
5. Provide adequate device heat-sinking. GND, VIN, and SW pins provide the main heat dissipation path, make
the GND, VIN, and SW plane area as large as possible. Use an array of heat-sinking vias to connect the top
side ground plane to the ground plane on the bottom PCB layer. If the PCB has multiple copper layers, these
thermal vias can also be connected to inner layer heat-spreading ground planes. Ensure enough copper
area is used for heat-sinking to keep the junction temperature below 125°C.
11.1.1 Compact Layout for EMI Reduction
Radiated EMI is generated by the high di/dt components in pulsing currents in switching converters. The larger
area covered by the path of a pulsing current, the more EMI is generated. High frequency ceramic bypass
capacitors at the input side provide primary path for the high di/dt components of the pulsing current. Placing
a ceramic bypass capacitor or capacitors as close as possible to the VIN and GND pins is the key to EMI
reduction.
The SW pin connecting to the inductor must be as short as possible, and just wide enough to carry the load
current without excessive heating. Short, thick traces or copper pours (shapes) must be used for high current
conduction path to minimize parasitic resistance. The output capacitors must be placed close to the VOUT end of
the inductor and closely grounded to GND pin.
11.1.2 Feedback Resistors
To reduce noise sensitivity of the output voltage feedback path, it is important to place the resistor divider
close to the FB pin, rather than close to the load. The FB pin is the input to the error amplifier, so it is a high
impedance node and very sensitive to noise. Placing the resistor divider closer to the FB pin reduces the trace
length of FB signal and reduces noise coupling. The output node is a low impedance node, so the trace from
VOUT to the resistor divider can be long if short path is not available.
If voltage accuracy at the load is important, make sure voltage sense is made at the load. Doing so corrects
for voltage drops along the traces and provides the best output accuracy. The voltage sense trace from the
load to the feedback resistor divider must be routed away from the SW node path and the inductor to avoid
contaminating the feedback signal with switch noise, while also minimizing the trace length. This is most
important when high value resistors are used to set the output voltage. It is recommended to route the voltage
sense trace and place the resistor divider on a different layer than the inductor and SW node path, such that
there is a ground plane in between the feedback trace and inductor/SW node polygon. This provides further
shielding for the voltage feedback path from EMI noises.
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11.2 Layout Example
Notes:
1. BOOT capacitor should be
close to CB and SW pins.
VOUT
2. SW area should be small.
3. Output voltage set resistors
should be close to FB pin.
Output Bypass
Capacitor
Output
Inductor
BOOT
Capacitor
4. Input bypass capacitor
should be close to VIN and GND
pins.
5. Use ground plane to keep a
low GND impedance.
GND
SW
CB
GND
FB
VIN
EN
VIN
Input Bypass
Capacitor
Output Voltage
Set Resistors
GND
VIA (Connect to GND Plane)
Figure 11-1. Layout
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
Texas Instruments, AN-1149 Layout Guidelines for Switching Power Supplies
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
27-Oct-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PLMR54410DBVR
ACTIVE
SOT-23
DBV
6
3000
TBD
Call TI
Call TI
-40 to 125
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OUTLINE
DBV0006A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
B
1.45 MAX
A
PIN 1
INDEX AREA
1
2
6
5
2X 0.95
1.9
3.05
2.75
4
3
0.50
6X
0.25
C A B
0.15
0.00
0.2
(1.1)
TYP
0.25
GAGE PLANE
0.22
0.08
TYP
8
TYP
0
0.6
0.3
TYP
SEATING PLANE
4214840/C 06/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.25 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.
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EXAMPLE BOARD LAYOUT
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
5
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214840/C 06/2021
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
5
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214840/C 06/2021
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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