LMS1487EIM/NOPB [TI]
LINE TRANSCEIVER, PDSO8, SOIC-8;
| 型号： | LMS1487EIM/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LINE TRANSCEIVER, PDSO8, SOIC-8 驱动 光电二极管 接口集成电路 驱动器 |
| 文件： | 总13页 (文件大小：249K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
November 2003
LMS1487E
Low Power RS-485 / RS-422 Differential Bus Transceiver
General Description
Features
n Meet ANSI standard RS-485 and RS-422
n Data rate 2.5 Mbps
The LMS1487E is a low power differential bus/line trans-
ceiver designed for high speed bidirectional data communi-
cation on multipoint bus transmission lines. It is designed for
balanced transmission lines. It meets ANSI Standards TIA/
EIA RS422-B, TIA/EIA RS485-A and ITU recommendation
and V.11 and X.27. The driver outputs and receiver inputs
have 15kV ESD protection. The LMS1487E combines a
n Single supply voltage operation, 5V
n Wide input and output voltage range
n Thermal shutdown protection
n Short circuit protection
n Low quiescent current 660µA (max)
n Allows up to 128 transceivers on the bus
n Open circuit fail-safe for receiver
n Extended operating temperature range −40˚C to 85˚C
n Drop-in replacement to MAX1487E
n Available in 8-pin SOIC and 8-pin DIP packages
™
TRI-STATE differential line driver and differential input re-
ceiver, both of which operate from a single 5.0V power
supply. The driver and receiver have an active high and
active low, respectively, that can be externally connected to
function as a direction control. The driver outputs and re-
ceiver inputs are internally connected to form a differential
input/output (I/O) bus port that is designed to offer minimum
loading to bus whenever the driver is disabled or when VCC
= 0V. These ports feature wide positive and negative com-
mon mode voltage ranges, making the device suitable for
multipoint applications in noisy environments. The
LMS1487E is available in 8-Pin SOIC and 8-pin DIP pack-
ages. It is a drop-in replacement to Maxim’s MAX1487E.
Applications
n Low power RS-485 systems
n Network hubs, bridges, and routers
n Point of sales equipment (ATM, barcode scanners,…)
n Local area networks (LAN)
n Integrated service digital network (ISDN)
n Industrial programmable logic controllers
n High speed parallel and serial applications
n Multipoint applications with noisy environment
Typical Application
20085601
A typical multipoint application is shown in the above figure. Terminating resistor, RT are typically required but only located at the two ends of the cable.
Pull-up and pull-down resistors maybe required at the end of the bus to provide fail-safe biasing. The biasing resistors provide a bias to the cable when all
drivers are in TRI-STATE, See National Application Note, AN-847 for further information.
© 2003 National Semiconductor Corporation
DS200856
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Connection Diagram
8-Pin SOIC / DIP
20085602
Top View
Truth Table
DRIVER SECTION
*
RE
X
DE
H
DI
H
L
A
H
L
B
L
X
H
H
Z
X
L
X
Z
RECEIVER SECTION
*
RE
L
DE
L
A-B
RO
H
≥ +0.2V
≤ −0.2V
X
L
L
L
H
L
X
Z
*
L
OPEN
H
*
Note: = Non Terminated, Open Input only
X = Irrelevant
Z = TRI-STATE
H = High level
L = Low level
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2
Pin Descriptions
#
Pin
I/O
Name
Function
>
<
1
O
RO
Receiver Output: If A B by 200 mV, RO will be high; If A B by 200 mV, RO will be low. RO
will be high also if the inputs (A and B) are open (non-terminated).
*
*
*
2
3
I
I
RE
DE
Receiver Output Enable: RO is enabled when RE is low; RO is in TRI-STATEwhen RE is high
Driver Output Enable: The driver outputs (A and B) are enabled when DE is high; they are in
TRI-STATETRI-STATE® when DE is low. Pins A and B also function as the receiver input pins
(see below)
4
I
DI
Driver Input: A low on DI forces A low and B high while a high on DI forces A high and B low
when the driver is enabled
5
6
NA
I/O
GND
A
Ground
Non-inverting Driver Output and Receiver Input pin. Driver output levels conform to RS-485
signaling levels
7
8
I/O
NA
B
Inverting Driver Output and Receiver Input pin. Driver Output levels conform to RS-485 signaling
levels
VCC
Power Supply: 4.75V ≤ VCC ≤ 5.25V
Ordering Information
Package
Part Number
Package Marking
Transport Media
95 Units/Rail
NSC Drawing
LMS1487ECM
LMS1487ECMX
LMS1487EIM
LMS1487ECM
2.5k Units Tape and Reel
95 Units/Rail
8-Pin SOIC
M08A
LMS1487EIM
LMS1487EIMX
LMS1487ECNA
LMS1487EINA
2.5k Units Tape and Reel
40 Units/Rail
LMS1487ECNA
LMS1487EINA
8-Pin DIP
N08E
40 Units/Rail
3
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
ESD Rating (Human Body Model)(Note 4)
Bus Pins
15kV
2kV
Other Pins
Supply Voltage, VCC (Note 2)
Input Voltage, VIN (DI, DE, or RE)
Voltage Range at Bus Terminals (AB)
Receiver Output
6V
ESD Rating (Machine Model)
All Pins
−0.3V to VCC + 0.3V
−7V to 12V
200V
−0.3V to VCC + 0.3V
Operating Ratings
Package Thermal Impedance, θJA
SOIC
Min Nom Max
4.75 5.0 5.25
125˚ C/W
92˚ C/W
150˚C
Supply Voltage, VCC
Voltage at any Bus Terminal
(Separately or Common Mode)
High-Level Input Voltage, VIH
(Note 5)
V
DIP
−7
12
V
V
V
V
Junction Temperature (Note 3)
Operating Free-Air Temperature
Range, TA
2
Commercial
0˚C to 70˚C
−40˚C to 85˚C
−65˚C to 150˚C
Low-Level Input Voltage, VIL
(Note 5)
0.8
12
Industrial
Storage Temperature Range
Soldering Information
Infrared or Convection (20 sec.)
Lead Temperature Range
Differential Input Voltage, VID
(Note 6)
235˚C
+260˚C
Electrical Characteristics
Over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Driver Section
∞
|VOD1
|
|
Differential Output Voltage
Differential Output Voltage
R =
(Figure 1)
5.25
V
V
|VOD2
R = 50Ω (Figure 1) , RS-422
R = 27Ω (Figure 1) , RS-485
R = 27Ω or 50Ω (Figure 1) , (Note 7)
2.0
1.5
5.0
0.2
∆VOD
Change in Magnitude of
Driver Differential Output
Voltage for Complementary
Output States
V
VOC
Common Mode Output
Voltage
R = 27Ω or 50Ω (Figure 1)
3.0
0.2
V
V
∆VOC
Change in Magnitude of
Driver Common-Mode Output
Voltage for Complementary
Output States
R = 27Ω or 50Ω (Figure 1), (Note 7)
VIH
VIL
IIN1
CMOS Input Logic Threshold DE, DI, RE
2.0
V
High
CMOS Input Logic Threshold DE, DI, RE
Low
0.8
2
V
Logic Input Current
DE, DI, RE
µA
Receiver Section
IIN2
Input Current (A, B)
DE = 0V, VCC = 0V or 5.25V
VIN = 12V
0.25
mA
VIN = − 7V
−0.2
+0.2
VTH
Differential Input Threshold
Voltage
−7V ≤ VCM ≤ + 12V
−0.2
3.5
V
∆VTH
VOH
Input Hysteresis
VCM = 0
95
mV
−
(VTH+ VTH−
)
CMOS High-level Output
Voltage
IOH = 4 mA, VID = −200 mV
V
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4
Electrical Characteristics (Continued)
Over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
Symbol
VOL
Parameter
CMOS Low-level Output
Voltage
Conditions
Min
Typ
Max
Units
IOL = −4 mA, VID = 200 mV
0.4
V
IOZR
Tristate Output Leakage
Current
0.4V ≤ VO ≤ + 2.4V
− 7V ≤VCM ≤ +12V
1
µA
kΩ
µA
RIN
Input Resistance
48
Power Supply Current
ICC
Supply Current
DE = VCC, RE = GND or VCC
DE = 0V, RE = GND or VCC
VO = high, −7V ≤ VCM ≤ +12V
400
360
660
560
250
IOSD1
IOSD2
IOSR
Driver Short-circuit Output
Current
mA
mA
mA
Driver Short-circuit Output
Current
VO = low, − 7V ≤VCM ≤ +12V
250
95
Receiver Short-circuit Output 0 V ≤ VO ≤ VCC
Current
Switching Characteristics
Driver
TPLH
,
Propagation Delay Input to
Output
RL = 54Ω, CL = 100 pF
10
3
40
80
ns
TPHL
TSKEW
TR,
Driver Output Skew
Driver Rise and Fall Time
RL = 54Ω, CL = 100 pF
RL = 54Ω, CL = 100 pF
5
10
40
ns
ns
10
TF
TZH
TZL
THZ
TLZ
,
Driver Enable to Ouput Valid CL = 100 pF
Time
25
35
70
70
ns
ns
,
Driver Output Disable Time
CL = 15 pF
Receiver
TPLH
,
Propagation Delay Input to
Output
RL = 54Ω, CL = 100 pF
20
90
200
ns
TPHL
TSKEW
Receiver Output Skew
Receiver Enable Time
RL = 54Ω, CL = 100 pF
5
ns
ns
TZH
TZL
THZ
TLZ
,
CL = 15 pF
20
50
50
,
Receiver Disable Time
Maximum Data Rate
CL = 15 pF
20
ns
FMAX
2.5
Mbps
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test conditions, see the Electrical Characteristics.
Note 2: All voltage values, except differential I/O bus voltage, are with respect to the network ground terminal.
Note 3: The maximum power dissipation is a function of T
, θ , and T . The maximum allowable power dissipation at any ambient temperature, T , is
J(MAX) JA
A
A
P
= (T
- T )/θ . All numbers apply for packages soldered directly into a PC board.
D
J(MAX) A JA
Note 4: ESD rating based upon human body model, 100 pF discharged through 1.5 kΩ.
Note 5: Voltage limits apply to DI, DE, RE pins.
Note 6: Differential input/output bus voltage is measured at the non-inverting terminal A with respect to the inverting terminal B.
Note 7: |∆V | and |∆V | are changes in magnitude of V and V , respectively when the input changes from high to low levels.
OD OC
OD
OC
Note 8: Peak current
5
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Typical Performance Characteristics
Output Current vs. Receiver Output Low Voltage
Output Current vs. Receiver Output High Voltage
20085614
20085613
Receiver Output High Voltage vs. Temperature
Receiver Output Low-Voltage vs. Temperature
20085616
20085615
Driver Output Current vs. Differential Output Voltage
Driver Differential Output Voltage vs. Temperature
20085618
20085617
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6
Typical Performance Characteristics (Continued)
Output Current vs. Driver Output Low Voltage
Output Current vs. Driver Output High Voltage
20085619
20085620
Supply Current vs. Temperature
20085621
7
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Parameter Measuring Information
20085603
FIGURE 1. Test Circuit for VOD and VOC
20085604
FIGURE 2. Test Circuit for VOD3
20085605
FIGURE 3. Test Circuit for Driver Propagation Delay
20085606
FIGURE 4. Test Circuit for Driver Enable / Disable
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8
Parameter Measuring Information (Continued)
20085607
FIGURE 5. Test Circuit for Receiver Propagation Delay
20085608
FIGURE 6. Test Circuit for Receiver Enable / Disable
9
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Switching Characteristics
20085611
20085609
FIGURE 9. Receiver Propagation Delay
FIGURE 7. Driver Propagation Delay, Rise / Fall Time
20085612
20085610
FIGURE 10. Receiver Enable / Disable Time
FIGURE 8. Driver Enable / Disable Time
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10
ideal, they may act more like inductors or resistors over a
specific frequency range. Thus, many times two by-pass
capacitors may be used to filter a wider bandwidth of noise.
It is highly recommended to place a larger capacitor, such as
10µF, between the power supply pin and ground to filter out
low frequencies and a 0.1µF to filter out high frequencies.
Application Information
POWER LINE NOISE FILTERING
A factor to consider in designing power and ground is noise
filtering. A noise filtering circuit is designed to prevent noise
generated by the integrated circuit (IC) as well as noise
entering the IC from other devices. A common filtering
method is to place by-pass capacitors (Cbp) between the
power and ground lines.
By-pass capacitors must be mounted as close as possible to
the IC to be effective. Longs leads produce higher imped-
ance at higher frequencies due to stray inductance. Thus,
this will reduce the by-pass capacitor’s effectiveness. Sur-
face mounted chip capacitors are the best solution because
they have lower inductance.
Placing a by-pass capacitor (Cbp) with the correct value at
the proper location solves many power supply noise prob-
lems. Choosing the correct capacitor value is based upon
the desired noise filtering range. Since capacitors are not
20085622
FIGURE 11. Placement of by-pass Capacitors, Cbp
11
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Physical Dimensions inches (millimeters) unless otherwise noted
8-Pin SOIC
NS Package Number M08A
8-Pin DIP
NS Package Number N08E
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12
Notes
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
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National Semiconductor certifies that the products and packing materials meet the provisions of the Customer Products
Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification
(CSP-9-111S2) and contain no ‘‘Banned Substances’’ as defined in CSP-9-111S2.
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