LMV301MGX/NOPB [TI]
单路 5V 1MHz 低 0.182pA 偏置电流运算放大器 | DCK | 5 | -40 to 85;
| 型号： | LMV301MGX/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 单路 5V 1MHz 低 0.182pA 偏置电流运算放大器 | DCK | 5 | -40 to 85 放大器 光电二极管 运算放大器 |
| 文件： | 总28页 (文件大小：1386K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LMV301
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SNOS968A –MAY 2004–REVISED MAY 2013
LMV301 Low Input Bias Current, 1.8V Op Amp w/ Rail-to-Rail Output
Check for Samples: LMV301
1
FEATURES
DESCRIPTION
The LMV301 CMOS operational amplifier is ideal for
single supply, low voltage operation with an ensured
operating voltage range from 1.8V to 5V. The low
input bias current of less than 0.182pA typical,
eliminates input voltage errors that may originate from
small input signals. This makes the LMV301 ideal for
electrometer applications requiring low input leakage
such as sensitive photodetection transimpedance
amplifiers and sensor amplifiers. The LMV301 also
features a rail-to-rail output voltage swing in addition
to a input common-mode range that includes ground.
The LMV301 will drive a 600Ω resistive load and up
to 1000pF capacitive load in unity gain follower
applications. The low supply voltage also makes the
LMV301 well suited for portable two-cell battery
systems and single cell Li-Ion systems.
2
•
•
•
•
•
Input Bias Current: 0.182 pA
Gain Bandwidth Product: 1 MHz
Supply Voltage at 1.8V: 1.8 to 5 V
Supply Current: 150 µA
Input Referred Voltage Noise at 1kHz:
40nV/√Hz
•
•
•
DC Gain (600Ω Load): 100 dB
Output Voltage Range at 1.8V: 0.024 to 1.77 V
Input Common-Mode Voltage Range: −0.3 to
±1.2 V
APPLICATIONS
•
•
•
•
•
Thermocouple Amplifiers
Photo Current Amplifiers
Transducer Amplifiers
The LMV301 exhibits excellent speed-power ratio,
achieving 1MHz at unity gain with low supply current.
The high DC gain of 100dB makes it ideal for other
low frequency applications.
Sample and Hold Circuits
Low Frequency Active Filters
The LMV301 is offered in a space saving SC70
package, which is only 2.0X2.1X1.0mm. It is also
similar to the LMV321 except the LMV301 has a
CMOS input.
Connection Diagram
Applications Circuit
Top View
Figure 2. Low Leakage Sample and Hold
Figure 1. SC70-5 Package
See Package Number DCK0005A
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2013, Texas Instruments Incorporated
LMV301
SNOS968A –MAY 2004–REVISED MAY 2013
Absolute Maximum Ratings(1)(2)
ESD Tolerance(3)
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Machine Model
200V
2000V
Human Body Model
Differential Input Voltage
Supply Voltage (V+ - V−)
Output Short Circuit to V+(4)
Output Short Circuit to V−(4)
Storage Temperature Range
Mounting Temperature
±Supply Voltage
5.5V
−65°C to 150°C
235°C
Infrared or Convection (20 sec)
Junction Temperature(5)
150°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(3) Human body model, 1.5kΩ in series with 100pF. Machine model, 200Ω in series with 100pF.
(4) Applies to both single supply operation. Continuous short circuit operation at elevated ambient temperature can result in exceeding the
maximum allowed junction temperature of 150°C. Output currents in excess of 45mA over long term may adversely affect reliability.
(5) The maximum power dissipation is a function of TJ(MAX), θJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(MAX) – TA)θJA. All numbers apply for packages soldered directly into a PC board.
(1)
Operating Ratings
Supply Voltage
1.8V to 5.0V
−40°C ≤ TJ ≤ +85°C
478°C/W
Temperature Range
Thermal Resistance (θJA
)
Ultra Tiny SC70-5 Package
5-pin Surface Mount
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics.
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1.8V DC Electrical Characteristics
Unless otherwise specified, all limits ensured for TJ = 25°C. V+ = 1.8V, V− = 0V, VCM = V+/2, VO = V+/2, and RL > 1MΩ.
Boldface limits apply at the temperature extremes.
Parameter
Test Conditions
Min(1)
Typ(2)
Max(1)
Units
VOS
IB
Input Offset Voltage
VCM = 0.4V, V+ = 1.3V, = V− = −0.5V
0.9
8
9
mV
Input Bias Current
Supply Current
0.182
150
35
50
pA
µA
dB
dB
V
IS
VCM = 0.4V, V+ = 1.3V, = V− = −0.5V
250
275
CMRR
PSRR
VCM
AV
Common Mode Rejection Ratio 0.3V ≤ VCM ≤ 0.9V
62
60
108
Power Supply Rejection Ratio
1.8V ≤ V+ ≤ 5V,
0.9 ≤ VCM ≤ 2.5V
67
62
110
Input Common-Mode Voltage
Range
For CMRR ≥ 50dB
−0.3
0
0.6
Large Signal Voltage Gain
Sourcing
RL = 600Ω to 0V, V+ = 1.2V, V− = −0.6V,
VO = −0.2V to 0.8V, VCM = 0V
RL = 2kΩ to 0V, V+ = 1.2V, V− = −0.6V, VO
= −0.2V to 0.8V, VCM = 0V
RL = 600Ω to 0V, V+ = 1.2V, V− = −0.6V,
VO = −0.2V to 0.8V, VCM = 0V
RL = 2kΩ to 0V, V+ = 1.2V, V− = −0.6V, VO
= −0.2V to 0.8V, VCM = 0V
80
75
119
111
94
dB
80
75
Sinking
80
75
dB
V
80
75
96
VO
Output Swing
RL = 600Ω to 0.9V
VOH
1.65
1.72
VIN = ±100mV
1.63
VOL
VOH
0.074
1.77
0.100
V
V
RL = 2kΩ to 0.9V
1.75
VIN = ±100mV
1.74
VOL
0.024
8.4
0.035
0.040
V
IO
Output Short Circuit Current
Sourcing,
4
3.3
mA
mA
VO = 0V, VIN = 100mV
Sinking,
VO = 1.8V, VIN = −100mV
7
9.8
(1) All limits are ensured by testing or statistical analysis.
(2) Typical value represent the most likely parametric norm.
1.8V AC Electrical Characteristics
Unless otherwise specified, all limits ensured for TJ = 25°C. V+ = 1.8V, V− = 0V, VCM = V+/2, VO = V+/2, and RL > 1MΩ.
Boldface limits apply at the temperature extremes.
Parameter
Slew Rate
Test Conditions
Typ(1)
0.57
1
Units
V/µs
SR
GBW
φm
Gm
en
See(2)
Gain Bandwidth Product
Phase Margin
MHz
Deg
60
Gain Margin
10
dB
Input-Referred Voltage Noise
f = 1kHz, VCM = 0.5V
f = 100kHz
40
30
nV/√Hz
THD
Total Harmonic Distortion
f = 1kHz, AV = +1
0.089
%
RL = 600kΩ, VIN = 1VPP
(1) Typical value represent the most likely parametric norm.
(2) V+ = 5V. Connected as voltage follower with 5V step input. Number specified is the slower of the positive and negative slew rates.
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2.7V DC Electrical Characteristics
Unless otherwise specified, all limits ensured for TJ = 25°C. V+ = 2.7V, V− = 0V, VCM = V+/2, VO = V+/2, and RL > 1MΩ.
Boldface limits apply at the temperature extremes.
Parameter
Test Conditions
Min(1)
Typ(2)
Max(1)
Units
VOS
IB
Input Offset Voltage
VCM = 0.35V, V+ = 1.7V, V− = −1V
0.9
8
9
mV
Input Bias Current
Supply Current
0.182
153
35
50
pA
µA
dB
dB
V
IS
VCM = 0.35V, V+ = 1.7V, V− = −1V
250
275
CMRR
PSRR
VCM
AV
Common Mode Rejection Ratio −0.15V ≤ VCM ≤ 1.35V
62
60
115
Power Supply Rejection Ratio
1.8V ≤ V+ ≤ 5V
67
62
110
Input Common-Mode Voltage
Range
For CMRR ≥ 50dB
−0.3
0
1.5
Large Signal Voltage Gain
Sourcing
RL = 600Ω to 0V, V+ = 1.35V, V−
=
80
75
100
114
98
−1.35V, VO = −1V to 1V, VCM = 0V
RL = 2kΩ to 0V, V+ = 1.35V, V− = −1.35V,
VO = −1V to 1V, VCM = 0V
dB
83
77
Sinking
RL = 600Ω to 0V, V+ = 1.35V, V−
=
80
−1.35V, VO = −1V to 1V, VCM = 0V
RL = 2kΩ to 0V, V+ = 1.35V, V− = −1.35V,
VO = −1V to 1V, VCM = 0V
75
dB
V
80
75
99
VO
Output Swing
RL = 600Ω to 1.35V
VOH
2.550
2.62
VIN = ±100mV
2.530
VOL
VOH
0.078
2.675
0.100
0.045
V
V
RL = 2kΩ to 1.35V
VIN = ±100mV
2.650
2.640
VOL
0.024
32
V
IO
Output Short Circuit Current
Sourcing,
20
mA
VO = 0V, VIN = 100mV
15
Sinking,
19
24
mA
VO = 2.7V, VIN = −100mV
12
(1) All limits are ensured by testing or statistical analysis.
(2) Typical value represent the most likely parametric norm.
2.7V AC Electrical Characteristics
Unless otherwise specified, all limits ensured for TJ = 25°C. V+ = 2.7V, V− = 0V, VCM = 1.0V, VO = 1.35V and RL > 1MΩ.
Boldface limits apply at the temperature extremes.
Parameter
Slew Rate
Test Conditions
Typ(1)
0.60
1
Units
V/µs
SR
GBW
φm
Gm
en
See(2)
Gain Bandwidth Product
Phase Margin
MHz
Deg
65
Gain Margin
10
dB
Input-Referred Voltage Noise
f = 1kHz, VCM = 0.5V
f = 100kHz
40
30
nV/√Hz
THD
Total Harmonic Distortion
f = 1kHz, AV = +1
0.077
%
RL = 600kΩ, VIN = 1VPP
(1) Typical value represent the most likely parametric norm.
(2) V+ = 5V. Connected as voltage follower with 5V step input. Number specified is the slower of the positive and negative slew rates.
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5V DC Electrical Characteristics
Unless otherwise specified, all limits ensured for TJ = 25°C. V+ = 5V, V− = 0V, VCM = V+/2, VO = V+/2, and RL > 1MΩ.
Boldface limits apply at the temperature extremes.
Parameter
Test Conditions
Min(1)
Typ(2)
Max(1)
Units
VOS
IB
Input Offset Voltage
VCM = 0.5V, V+ = 3V, V− = −2V
0.9
8
9
mV
Input Bias Current
Supply Current
0.182
163
35
50
pA
µA
dB
dB
V
IS
VCM = 0.5V, V+ = 3V, V− = −2V
260
285
CMRR
PSRR
VCM
AV
Common Mode Rejection Ratio −1.3V ≤ VCM ≤ 2.5V
62
61
111
Power Supply Rejection Ratio
1.8V ≤ V+ ≤ 5V
67
62
110
Input Common-Mode Voltage
Range
For CMRR ≥ 50dB
−0.3
0
3.8
Large Signal Voltage Gain
Sourcing
RL = 600Ω to 0V, V+ = 2.5V, V− = −2.5V,
VO = −2V to 2V, VCM = 0V
RL = 2kΩ to 0V, V+ = 2.5V, V− = −2.5V,
VO = −2V to 2V, VCM = 0V
RL = 600Ω to 0V, V+ = 2.5V, V− = −2.5V,
VO = −2V to 2V, VCM = 0V
RL = 2kΩ to 0V, V+ = 2.5V, V− = −2.5V,
VO = −2V to 2V, VCM = 0V
86
82
117
116
105
107
4.893
0.1
dB
dB
89
85
Sinking
80
75
80
75
VO
Output Swing
RL = 600Ω to 2.5V
VIN = ±100mV
VOH
4.850
4.840
V
V
VOL
0.150
1.160
RL = 2kΩ to 2.5V
VIN = ±100mV
VOH
VOL
4.935
4.966
0.034
V
V
0.065
0.075
IO
Output Short Circuit Current
Sourcing,
VO = 0V, VIN = 100mV
85
68
108
69
mA
mA
Sinking,
60
VO = 5V, VIN = −100mV
45
(1) All limits are ensured by testing or statistical analysis.
(2) Typical value represent the most likely parametric norm.
5V AC Electrical Characteristics
Unless otherwise specified, all limits ensured for TJ = 25°C. V+ = 5V, V− = 0V, VCM = V+/2, VO = 2.5V and RL > 1MΩ.
Boldface limits apply at the temperature extremes.
Parameter
Slew Rate
Test Conditions
Typ(1)
0.66
1
Units
V/µs
SR
GBW
φm
Gm
en
See(2)
Gain Bandwidth Product
Phase Margin
MHz
Deg
70
Gain Margin
15
dB
Input-Referred Voltage Noise
f = 1kHz, VCM = 1V
f = 100kHz
40
30
nV/√Hz
THD
Total Harmonic Distortion
f = 1kHz, AV = +1
0.069
%
RL = 600Ω, VO = 1VPP
(1) Typical value represent the most likely parametric norm.
(2) V+ = 5V. Connected as voltage follower with 5V step input. Number specified is the slower of the positive and negative slew rates.
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Simplified Schematic
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Typical Performance Characteristics
Unless otherwise specified, TA = 25°C.
Supply Current vs. Supply Voltage
Output Negative Swing vs. Supply Voltage
Figure 3.
Figure 4.
Output Negative Swing vs. Supply Voltage
Output Positive Swing vs. Supply Voltage
Figure 5.
Figure 6.
Output Positive Swing vs. Supply Voltage
VOS vs. VCM
Figure 7.
Figure 8.
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Typical Performance Characteristics (continued)
Unless otherwise specified, TA = 25°C.
VOS vs. VCM
VOS vs. VCM
Figure 9.
Figure 10.
Sourcing Current vs. Output Voltage
Sinking Current vs. Output Voltage
Figure 11.
Figure 12.
Sourcing Current vs. Output Voltage
Sinking Current vs. Output Voltage
Figure 13.
Figure 14.
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Typical Performance Characteristics (continued)
Unless otherwise specified, TA = 25°C.
Sourcing Current vs. Output Voltage
Sinking Current vs. Output Voltage
Figure 15.
Figure 16.
IBIAS Current vs. VCM
Open Loop Frequency Response
Figure 17.
Figure 18.
Open Loop Frequency Response
Open Loop Frequency Response
Figure 19.
Figure 20.
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Typical Performance Characteristics (continued)
Unless otherwise specified, TA = 25°C.
Open Loop Frequency Response
Open Loop Frequency Response
Figure 21.
Figure 22.
Open Loop Frequency Response
Noise vs. Frequency Response
Figure 23.
Figure 24.
Noise vs. Frequency Response
Noise vs. Frequency Response
Figure 25.
Figure 26.
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Typical Performance Characteristics (continued)
Unless otherwise specified, TA = 25°C.
Small Signal Response
Large Signal Response
Figure 27.
Figure 28.
Small Signal Response
Large Signal Response
Figure 29.
Figure 30.
Small Signal Response
Large Signal Response
Figure 31.
Figure 32.
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Typical Performance Characteristics (continued)
Unless otherwise specified, TA = 25°C.
Small Signal Response
Large Signal Response
Figure 33.
Figure 34.
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APPLICATION HINTS
Compensating Input Capacitance
The high input resistance of the LMV301 op amp allows the use of large feedback and source resistor values
without losing gain accuracy due to loading. However, the circuit will be especially sensitive to its layout when
these large value resistors are used.
Every amplifier has some capacitance between each input and AC ground, and also some differential
capacitance between the inputs. When the feedback network around an amplifier is resistive, this input
capacitance (along with any additional capacitance due to circuit board traces, the socket, etc.) and the feedback
resistors create a pole in the feedback path. In the following General Operational Amplifier circuit, Figure 35, the
frequency of this pole is
where
•
CS is the total capacitance at the inverting input, including amplifier input capacitance and any stray
capacitance from the IC socket (if one is used), circuit board traces, etc.,
•
RP is the parallel combination of RF and RIN
(1)
This formula, as well as all formulae derived below, apply to inverting and non-inverting op amp configurations.
When the feedback resistors are smaller than a few kΩ, the frequency of the feedback pole will be quite high,
since CS is generally less than 10pF. If the frequency of the feedback pole is much higher than the “ideal” closed-
loop bandwidth (the nominal closed-loop bandwidth in the absence of CS), the pole will have a negligible effect
on stability, as it will add only a small amount of phase shift.
However, if the feedback pole is less than approximately 6 to 10 times the “ideal” −3dB frequency, a feedback
capacitor, CF, should be connected between the output and the inverting input of the op amp. This condition can
also be stated in terms of the amplifier's low frequency noise gain. To maintain stability a feedback capacitor will
probably be needed if
(2)
Where
(3)
is the amplifier's low frequency noise gain and GBW is the amplifier's gain bandwidth product.
An amplifier's low frequency noise gain is represented by the formula
(4)
regardless of whether the amplifier is being used in inverting or non-inverting mode. Note that a feedback
capacitor is more likely to be needed when the noise gain is low and/or the feedback resistor is large.
If the above condition is met (indicating a feedback capacitor will probably be needed), and the noise gain is
large enough that:
(5)
the following value of feedback capacitor is recommended:
(6)
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If
(7)
(8)
the feedback capacitor should be:
Note that these capacitor values are usually significantly smaller than those given by the older, more
conservative formula:
(9)
CS consists of the amplifier's input capacitance plus any stray capacitance from the circuit board and socket. CF
compensates for the pole caused by CS and the feedback resistors.
Figure 35. General Operational Amplifier Circuit
Using the smaller capacitor will give much higher bandwidth with little degradation of transient response. It may
be necessary in any of the above cases to use a somewhat larger feedback capacitor to allow for unexpected
stray capacitance, or to tolerate additional phase shifts in the loop, or excessive capacitive load, or to decrease
the noise or bandwidth, or simply because the particular circuit implementation needs more feedback
capacitance to be sufficiently stable. For example, a printed circuit board's stray capacitance may be larger or
smaller than the breadboard's, so the actual optimum value for CF may be different from the one estimated using
the breadboard. In most cases, the values of CF should be checked on the actual circuit, starting with the
computed value.
Capacitive Load Tolerance
Like many other op amps, the LMV301 may oscillate when its applied load appears capacitive. The threshold of
oscillation varies both with load and circuit gain. The configuration most sensitive to oscillation is a unity gain
follower. The load capacitance interacts with the op amp’s output resistance to create an additional pole. If this
pole frequency is sufficiently low, it will degrade the op amp's phase margin so that the amplifier is no longer
stable. As shown in Figure 36, the addition of a small resistor (50Ω to 100Ω) in series with the op amp's output,
and a capacitor (5pF to 10pF) from inverting input to output pins, returns the phase margin to a safe value
without interfering with lower frequency circuit operation. Thus, larger values of capacitance can be tolerated
without oscillation. Note that in all cases, the output will ring heavily when the load capacitance is near the
threshold for oscillation.
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Figure 36. Rx, Cx Improve Capacitive Load Tolerance
Capacitive load driving capability is enhanced by using a pull up resistor to V+ (Figure 37). Typically a pull up
resistor conducting 500µA or more will significantly improve capacitive load responses. The value of the pull up
resistor must be determined based on the current sinking capability of the amplifier with respect to the desired
output swing. Open loop gain of the amplifier can also be affected by the pull up resistor.
Figure 37. Compensating for Large Capacitive Loads with a Pull Up Resistor
PRINTED-CIRCUIT-BOARD LAYOUT FOR HIGH-IMPEDANCE WORK
It is generally recognized that any circuit which must operate with less than 100pA of leakage current requires
special layout of the PC board. When one wishes to take advantage of the low bias current of the LMV301,
typically less than 0.182pA, it is essential to have an excellent layout. Fortunately, the techniques for obtaining
low leakages are quite simple. First, the user must not ignore the surface leakage of the PC board, even though
it may sometimes appear acceptable low, because under conditions of the high humidity or dust or
contamination, the surface leakage will be appreciable. To minimized the effect of any surface leakage, lay out a
ring of foil completely surrounding the LMV301's inputs and the terminals of capacitors, diodes, conductors,
resistors, relay terminals, etc. connected to the op amp's inputs. See Figure 38. To have a significant effect,
guard rings should be placed on both the top and bottom of the PC board. The PC foil must then be connected
to a voltage which is at the same voltage as the amplifier inputs, since no leakage current can flow between two
points at the same potential. For example, a PC board trace-to-pad resistance of 1012Ω, which is normally
considered a very large resistance, could leak 5pA if the trace were a 5V bus adjacent to the pad of an input.
This would cause a 100 times degradation from the LMV301's actual performance. However, if a guard ring is
held within 5mV of the inputs, then even a resistance of 1011Ω would cause only 0.05pA of leakage current, or
perhaps a minor (2:1) degradation of the amplifier performance. See Figure 39, Figure 40, and Figure 41 for
typical connections of guard rings for standard op amp configurations. If both inputs are active and at high
impedance, the guard can be tied to ground and still provide some protection; see Figure 42.
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Figure 38. Example, using the LMV301,
of Guard Ring in P.C. Board Layout
Guard Ring Connections
Figure 39. Inverting Amplifier
Figure 40. Non-Inverting Amplifier
Figure 41. Follower
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Figure 42. Howland Current Pump
The designer should be aware that when it is inappropriate to lay out a PC board for the sake of just a few
circuits, there is another technique which is even better than a guard ring on a PC board: Don't insert the
amplifier's input pin into the board at all, but bend it up in the air and use only air as an insulator. Air is an
excellent insulator. In this case you may have to forego some of the advantages of PC board construction, but
the advantages are sometimes well worth the effort of using point-to-point up-in-the-air wiring. See Figure 43.
(Input pins are lifted out of PC board and soldered directly to components. All other pins connected to PC board.)
Figure 43. Air Wiring
Typical Single-Supply Applications
(V+ = 5.0 VDC)
Figure 44. Low-Leakage Sample-and-Hold
Copyright © 2004–2013, Texas Instruments Incorporated
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LMV301
SNOS968A –MAY 2004–REVISED MAY 2013
www.ti.com
Figure 45. Sine-Wave Oscillator
Oscillator frequency is determined by R1, R2, C1, and C2:
fosc = 1/2πRC
where
•
•
R = R1 = R2
C = C1 = C2
(10)
This circuit, as shown, oscillates at 2.0kHz with a peak-to-peak output swing of 4.5V.
Figure 46. 1 Hz Square-Wave Oscillator
Figure 47. Power Amplifier
18
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Product Folder Links: LMV301
LMV301
www.ti.com
SNOS968A –MAY 2004–REVISED MAY 2013
fO = 10 Hz
Q = 2.1
Gain = −8.8
Figure 48. 10Hz Bandpass Filter
fc = 10 Hz
d = 0.895
Gain = 1
2 dB passband ripple
Figure 49. 10 Hz High-Pass Filter
fc = 1 Hz
d = 1.414
Gain = 1.57
Figure 50. 1 Hz Low-Pass Filter
(Maximally Flat, Dual Supply Only)
Copyright © 2004–2013, Texas Instruments Incorporated
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LMV301
SNOS968A –MAY 2004–REVISED MAY 2013
www.ti.com
REVISION HISTORY
Changes from Original (May 2013) to Revision A
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 19
20
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Copyright © 2004–2013, Texas Instruments Incorporated
Product Folder Links: LMV301
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMV301MG/NOPB
LMV301MGX/NOPB
ACTIVE
ACTIVE
SC70
SC70
DCK
DCK
5
5
1000 RoHS & Green
3000 RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
A48
A48
SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Oct-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMV301MG/NOPB
LMV301MGX/NOPB
SC70
SC70
DCK
DCK
5
5
1000
3000
178.0
178.0
8.4
8.4
2.25
2.25
2.45
2.45
1.2
1.2
4.0
4.0
8.0
8.0
Q3
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Oct-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LMV301MG/NOPB
LMV301MGX/NOPB
SC70
SC70
DCK
DCK
5
5
1000
3000
208.0
208.0
191.0
191.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DCK0005A
SOT - 1.1 max height
S
C
A
L
E
5
.
6
0
0
SMALL OUTLINE TRANSISTOR
C
2.4
1.8
0.1 C
1.4
1.1
B
1.1 MAX
A
PIN 1
INDEX AREA
1
2
5
NOTE 4
(0.15)
(0.1)
2X 0.65
1.3
2.15
1.85
1.3
4
3
0.33
5X
0.23
0.1
0.0
(0.9)
TYP
0.1
C A B
0.15
0.22
0.08
GAGE PLANE
TYP
0.46
0.26
8
0
TYP
TYP
SEATING PLANE
4214834/C 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-203.
4. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X (0.65)
4
(R0.05) TYP
(2.2)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:18X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214834/C 03/2023
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X(0.65)
4
(R0.05) TYP
(2.2)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:18X
4214834/C 03/2023
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
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