LMV7275-Q1 [TI]
汽车级微功耗单路比较器;
| 型号： | LMV7275-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车级微功耗单路比较器 比较器 |
| 文件： | 总29页 (文件大小：993K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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LMV7275-Q1
ZHCSE55 –SEPTEMBER 2015
LMV7275-Q1 具有轨到轨输入的汽车类单路 1.8V 低功耗比较器
1 特性
3 说明
1
•
适用于汽车电子 应用
具有符合 AEC-Q100 标准的下列结果：
LMV7275-Q1 是一款单路轨到轨输入低功耗比较器，
额定电源电压包括 1.8V、2.7V 和 5V。每条通道的电
源流耗低至 9µA，同时可实现 800ns 的短暂传播延
迟。
•
–
–
–
器件温度 3 级：-40°C 至 85°C
的运行环境温度范围
器件人体放电模式 (HBM) 静电放电 (ESD) 分类
等级 2
LMV7275-Q1 采用 SC-70 封装。这类微型封装可显著
减小印刷电路板 (PCB) 面积，非常适合低电压、低功
耗、对空间要求严格的设计。
器件组件充电模式 (CDM) ESD 分类等级 C6
•
（除非另外注明，否则典型值为 VS = 1.8V，TA =
25°C）。
LMV7275-Q1 特有 一个开漏输出级，支持线或配置。
此外，开漏输出还具备另一项优势，即允许将输出上拉
至 5.5V 及以下的任一电压，与 LMV7275-Q1 的电源
电压无关。该特性有益于电平转换 应用。
•
•
•
•
•
•
•
•
由单电源或双电源供电
开漏输出
超低电源电流：9µA（每通道）
低输入偏置电流：10nA
低输入偏移电流：200pA
低输入偏移电压 (VOS)：4mV
传播延迟：880ns（20mV 过驱电压）
LMV7275-Q1 采用德州仪器 (TI) 先进的亚微米硅栅
BiCMOS 工艺。该器件采用双极输入改善噪声性能，
凭借互补金属氧化物半导体 (CMOS) 输出将负输出摆
幅降至最低。
输入共模电压范围：（负电源轨电压 - 0.1V）至
（正电源轨电压 + 0.1V）
器件信息(1)
器件型号
封装
SC70 (5)
封装尺寸（标称值）
2 应用
LMV7275-Q1
1.25mm × 2.00mm
•
•
•
•
可穿戴式设备
(1) 要了解所有可用封装，请参见数据表末尾的可订购产品附录。
手机和平板电脑
电池供电类电子产品
通用低电压 应用
LMV7275-Q1 用作窗口比较器
低电源电流
VDIGITAL
10
VIN
VTH+
VTH-
VS
9
85°/
RPULLUP
VOUT
VTH+
+
+
85°/
t
t
8
7
6
5
25°/
VOUT
VIN
VS
VDIGITAL
-40°/
VTH-
1.8
2.44
3.08
3.72
4.36
5.0
SUPPLY VOLTAGE (V)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SNOSD09
LMV7275-Q1
ZHCSE55 –SEPTEMBER 2015
www.ti.com.cn
目录
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description................................................. 10
7.4 Device Functional Modes........................................ 11
Application and Implementation ........................ 17
8.1 Application Information............................................ 17
8.2 Typical Applications ................................................ 17
Power Supply Recommendations...................... 22
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 3
6.1 Absolute Maximum Ratings ..................................... 3
6.2 ESD Ratings LMV7275-Q1....................................... 3
6.3 Recommended Operating Conditions....................... 3
6.4 Thermal Information.................................................. 4
6.5 1.8-V Electrical Characteristics ................................. 4
6.6 1.8-V AC Electrical Characteristics........................... 4
6.7 2.7-V Electrical Characteristics ................................. 5
6.8 2.7-V AC Electrical Characteristics........................... 5
6.9 5-V Electrical Characteristics .................................... 5
6.10 5-V AC Electrical Characteristics............................ 6
6.11 Typical Characteristics............................................ 7
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
8
9
10 Layout................................................................... 22
10.1 Layout Guidelines ................................................. 22
10.2 Layout Example .................................................... 23
11 器件和文档支持 ..................................................... 24
11.1 器件支持................................................................ 24
11.2 文档支持................................................................ 24
11.3 社区资源................................................................ 24
11.4 商标....................................................................... 24
11.5 静电放电警告......................................................... 24
11.6 Glossary................................................................ 24
12 机械、封装和可订购信息....................................... 24
7
4 修订历史记录
日期
修订版本
注释
2015 年 9 月
*
最初发布版本。
2
Copyright © 2015, Texas Instruments Incorporated
LMV7275-Q1
www.ti.com.cn
ZHCSE55 –SEPTEMBER 2015
5 Pin Configuration and Functions
DGK Package
5-Pin SC70
Top View
Pin Functions
PIN
I/O
DESCRIPTION
NAME
IN+
V-
SC70
1
2
3
4
5
I
Non-Inverting Input
P
I
Negative Supply Voltage
Inverting Input
IN-
OUT
V+
O
P
Output
Positive Supply Voltage
6 Specifications
(1)
6.1 Absolute Maximum Ratings
MIN
MAX
UNIT
±Supply
Voltage
VIN Differential
V
Supply Voltage (V+ - V−)
Voltage at Input/Output pins
Junction Temperature(2)
Storage Temperature, Tstg
6
V
V
(V−) − 0.1 (V+) + 0.1
150
°C
°C
–65
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The maximum power dissipation is a function of TJ(MAX), RθJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(MAX) - TA)/RθJA. All numbers apply for packages soldered directly into a PCB.
6.2 ESD Ratings LMV7275-Q1
VALUE
±2000
±1000
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
MIN
MAX UNIT
Supply Voltage
Temperature(1)
1.8
5.5
85
V
–40
°C
(1) The maximum power dissipation is a function of TJ(MAX), RθJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(MAX) - TA)/RθJA. All numbers apply for packages soldered directly into a PCB.
Copyright © 2015, Texas Instruments Incorporated
3
LMV7275-Q1
ZHCSE55 –SEPTEMBER 2015
www.ti.com.cn
6.4 Thermal Information
LMV7275-Q1
DGK (SC70)
5 PINS
273.8
THERMAL METRIC(1)
UNIT
(2)
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
106.1
54.9
Junction-to-top characterization parameter
Junction-to-board characterization parameter
3.6
ψJB
54.1
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(2) The maximum power dissipation is a function of TJ(MAX), RθJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(MAX) - TA)/RθJA. All numbers apply for packages soldered directly into a PCB.
6.5 1.8-V Electrical Characteristics
Unless otherwise specified, all limits ensured for TJ = 25°C, V+ = 1.8 V, V− = 0 V.
PARAMETER
CONDITION
MIN(1)
TYP(2)
MAX(1)
UNIT
0.3
4
6
VOS
Input Offset Voltage
mV
At the temperature extremes
(3)
TC VOS Input Offset Temperature Drift
VCM = 0.9 V
20
10
uV/°C
nA
IB
Input Bias Current
Input Offset Current
IOS
200
9
pA
12
14
IS
Supply Current
µA
mA
mV
At the temperature extremes
Sinking, VO = 0.9 V
IO = −0.5 mA
ISC
VOL
Output Short Circuit Current
Output Voltage Low
4
6
52
100
220
IO = −1.5 mA
166
Input Common-Mode Voltage
Range
VCM
CMRR > 45 dB
−0.1
1.9
V
CMRR Common-Mode Rejection Ratio 0 < VCM < 1.8 V
46
55
78
80
dB
dB
PSRR
Power Supply Rejection Ratio
V+ = 1.8 V to 5 V
ILEAKAG Output Leakage Current
E
VO = 1.8 V
2
pA
(1) All limits are ensured by testing or statistical analysis.
(2) Typical values represent the most likely parametric norm.
(3) Offset Voltage average drift determined by dividing the change in VOS at temperature extremes into the total temperature change.
6.6 1.8-V AC Electrical Characteristics
Unless otherwise specified, all limits ensured for TJ = 25°C, V+ = 1.8 V, V− = 0 V, VCM = 0.5 V, VO = V+/2 and RL > 1 MΩ to
V−.
PARAMETER
CONDITION
MIN(1)
TYP(2)
MAX(1)
UNIT
Input Overdrive = 20 mV
Load = 50 pF//5 kΩ
880
ns
Propagation Delay
(High to Low)
tPHL
Input Overdrive = 50 mV
Load = 50 pF//5 kΩ
570
1100
800
ns
ns
ns
Input Overdrive = 20 mV
Load = 50 pF//5 kΩ
Propagation Delay
(Low to High)
tPLH
Input Overdrive = 50 mV
Load = 50 pF//5 kΩ
(1) All limits are ensured by testing or statistical analysis.
(2) Typical values represent the most likely parametric norm.
4
Copyright © 2015, Texas Instruments Incorporated
LMV7275-Q1
www.ti.com.cn
ZHCSE55 –SEPTEMBER 2015
6.7 2.7-V Electrical Characteristics
Unless otherwise specified, all limits ensured for TJ = 25°C, V+ = 2.7 V, V− = 0 V.
PARAMETER
CONDITIONS
MIN(1)
TYP(2) MAX(1) UNIT
0.3
4
6
VOS
Input Offset Voltage
mV
At the temperature extremes
TC VOS
IB
Input Offset Temperature Drift
Input Bias Current
VCM = 1.35 V(3)
20
10
µV/°C
nA
IOS
Input offset Current
200
9
pA
13
15
IS
Supply Current
µA
mA
mV
At the temperature extremes
Sinking, VO = 1.35 V
IO = −0.5 mA
ISC
VOL
Output Short Circuit Current
Output Voltage Low
10
15
50
70
220
2.8
IO = −2 mA
155
VCM
Input Common Voltage Range
CMRR > 45 dB
−0.1
46
V
CMRR
PSRR
Common-Mode Rejection Ratio 0 < VCM < 2.7 V
78
80
2
dB
dB
pA
Power Supply Rejection Ratio
V+ = 1.8 V to 5 V
55
ILEAKAGE Output Leakage Current
VO = 2.7 V
(1) All limits are ensured by testing or statistical analysis.
(2) Typical values represent the most likely parametric norm.
(3) Offset Voltage average drift determined by dividing the change in VOS at temperature extremes into the total temperature change.
6.8 2.7-V AC Electrical Characteristics
Unless otherwise specified, all limits ensured for TJ = 25°C, V+ = 2.7 V, V− = 0 V, VCM = 0.5 V, VO = V+/2 and RL > 1 MΩ to
V−.
PARAMETER
CONDITION
MIN(1)
TYP(2)
MAX(1)
UNIT
Input Overdrive = 20 mV
Load = 50 pF//5 kΩ
1200
ns
Propagation Delay
(High to Low)
tPHL
Input Overdrive = 50 mV
Load = 50 pF//5 kΩ
810
1300
860
ns
ns
ns
tPLH
Propagation Delay
(Low to High)
Input Overdrive = 20 mV
Load = 50 pF//5 kΩ
Input Overdrive = 50 mV
Load = 50 pF//5 kΩ
(1) All limits are ensured by testing or statistical analysis.
(2) Typical values represent the most likely parametric norm.
6.9 5-V Electrical Characteristics
Unless otherwise specified, all limits ensured for TJ = 25°C, V+ = 5 V, V− = 0 V.
PARAMETER
CONDITIONS
MIN(1)
TYP(2) MAX(1) UNIT
0.3
4
6
VOS
Input Offset Voltage
mV
At the temperature extremes
TC VOS
IB
Input Offset Temperature Drift
Input Bias Current
VCM = 2.5 V(3)
20
10
µV/°C
nA
IOS
Input Offset Current
200
10
pA
14
16
IS
Supply Current
µA
At the temperature extremes
Sinking, VO = 2.5 V
IO = −0.5 mA
ISC
Output Short Circuit Current
Output Voltage Low
18
34
27
mA
mV
70
VOL
IO = −4.0 mA
225
315
(1) All limits are ensured by testing or statistical analysis.
(2) Typical values represent the most likely parametric norm.
(3) Offset Voltage average drift determined by dividing the change in VOS at temperature extremes into the total temperature change.
Copyright © 2015, Texas Instruments Incorporated
5
LMV7275-Q1
ZHCSE55 –SEPTEMBER 2015
www.ti.com.cn
5-V Electrical Characteristics (continued)
Unless otherwise specified, all limits ensured for TJ = 25°C, V+ = 5 V, V− = 0 V.
PARAMETER
CONDITIONS
MIN(1)
−0.1
46
TYP(2) MAX(1) UNIT
VCM
Input Common Voltage Range
CMRR > 45 dB
5.1
V
CMRR
PSRR
Common-Mode Rejection Ratio 0 < VCM < 5.0 V
78
80
2
dB
dB
pA
Power Supply Rejection Ratio
V+ = 1.8 V to 5 V
55
ILEAKAGE Output Leakage Current
VO = 5 V
6.10 5-V AC Electrical Characteristics
Unless otherwise specified, all limits ensured for TJ = 25°C, V+ = 5.0 V, V− = 0 V, VCM = 0.5 V, VO = V+/2 and RL > 1 MΩ to
V−.
PARAMETER
CONDITION
MIN(1)
TYP(2)
MAX(1)
UNIT
Input Overdrive = 20 mV
Load = 50 pF//5 kΩ
2100
ns
Propagation Delay
(High to Low)
tPHL
Input Overdrive = 50 mV
Load = 50 pF//5 kΩ
1380
1800
1100
ns
ns
ns
Input Overdrive = 20 mV
Load = 50 pF//5 kΩ
Propagation Delay
(Low to High)
tPLH
Input Overdrive = 50 mV
Load = 50 pF//5 kΩ
(1) All limits are ensured by testing or statistical analysis.
(2) Typical values represent the most likely parametric norm.
6
Copyright © 2015, Texas Instruments Incorporated
LMV7275-Q1
www.ti.com.cn
ZHCSE55 –SEPTEMBER 2015
6.11 Typical Characteristics
TA = 25°C, Unless otherwise specified.
V
= ±0.9V
SUPPLY
V
= ±1.35V
SUPPLY
800
400
0
800
400
0
-40°/
-40°/
25°/
85°/
-400
-800
-400
-800
25°/
85°/
-0.9 -0.7 -0.5 -0.3 -0.1 0.1 0.3 0.5 0.7 0.9
(V)
-1.35 -0.9 -0.45
0
0.45
0.9
1.35
V
V
(V)
CM
CM
Figure 1. VOS vs. VCM
Figure 2. VOS vs. VCM
40
V
= ±2.5V
SUPPLY
800
400
0
30
20
10
-40°/
SINK
-400
-800
25°/
85°/
0
-2.5 -2
-1
0
1
2 2.5
1.8
2.44
3.08
3.72
4.36
5.0
V
(V)
CM
SUPPLY VOLTAGE (V)
Figure 4. Short Circuit vs. Supply Voltage
Figure 3. VOS vs. VCM
600
10
9
I
SINK
500
400
85°/
85°/
4mA
8
7
6
5
300
200
25°/
2mA
1.5mA
-40°/
100
0
0.5mA
1.8
2.3
2.8
3.3
3.8
(V)
4.3
4.8
1.8
2.44
SUPPLY VOLTAGE (V)
Figure 5. Supply Current vs. Supply Voltage
3.08
3.72
4.36
5.0
V
SUPPLY
Figure 6. Output Negative Swing vs. VSUPPLY
Copyright © 2015, Texas Instruments Incorporated
7
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ZHCSE55 –SEPTEMBER 2015
www.ti.com.cn
Typical Characteristics (continued)
TA = 25°C, Unless otherwise specified.
0.8
0.5
0.45
0.4
V
= 2.7V
V
= 1.8V
SUPPLY
SUPPLY
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
85°/
85°/
0.35
0.3
25°/
25°/
0.25
0.2
0.15
0.1
-40°/
-40°/
0.05
0
0
0.5
1
1.5
2
2.5
(mA)
3
3.5
4
0
0.5
1
1.5
2
2.5
(mA)
3
3.5
4
I
I
SINK
SINK
Figure 7. Output Negative Swing vs. ISINK
Figure 8. Output Negative Swing vs. ISINK
0.4
5
V
= 1.8V
V
= 5V
CC
SUPPLY
4
3
2
1
0
TEMP = 25°C
LOAD = 5kW//50pF
85°/
0.3
0.2
20më
50më
25°/
ö
ö
100
0.1
0
0
hë9wꢀwLë9
-40°/
-100
0
0.5
1
1.5
2
2.5
3
3.5
4
0
500 1000 1500 2000 2500 3000
TIME (ns)
I
(mA)
SINK
Figure 10. Propagation Delay (tPLH
)
Figure 9. Output Negative Swing vs. ISINK
5
5
4
3
2
1
0
V = 2.7V
CC
TEMP = 25°C
LOAD = 5kW//50pF
V
= 1.8 V
CC
4
3
2
1
0
TEMP = 25°C
LOAD = 5kW//50pF
50më
20më
50më
20më
ö
ö
ö
ö
100
100
hë9wꢀwLë9
hë9wꢀwLë9
0
0
-100
-100
0
500 1000 1500 2000 2500 3000
TIME (ns)
0
500 1000 1500 2000 2500 3000
TIME (ns)
Figure 11. Propagation Delay (tPHL
)
Figure 12. Propagation Delay (tPLH)
8
Copyright © 2015, Texas Instruments Incorporated
LMV7275-Q1
www.ti.com.cn
ZHCSE55 –SEPTEMBER 2015
Typical Characteristics (continued)
TA = 25°C, Unless otherwise specified.
5
5
4
3
2
1
0
V
= 2.7 V
V
= 5.0V
CC
50më
20më
CC
4
3
2
1
0
TEMP = 25°C
LOAD = 5kW//50pF
TEMP = 25°C
LOAD = 5kW//50pF
50më
20më
ö
ö
ö
ö
100
100
hë9wꢀwLë9
hë9wꢀwLë9
0
0
-100
-100
0
500
1500 2000 2500 3000
1000
TIME (ns)
0
500 1000 1500 2000 2500 3000
TIME (ns)
Figure 13. Propagation Delay (tPHL
)
Figure 14. Propagation Delay (tPLH
)
8
7
6
5
4
3
2
1
0
5
4
3
2
1
0
V
= 5.0 V
CC
TEMP = 25°C
LOAD = 5kW//50pF
V
= 5V
S
50më
20më
V
= 2.7V
S
ö
ö
100
hë9wꢀwLë9
0
-100
V
= 1.8V
S
0
500 1000 1500 2000 2500 3000
TIME (ns)
0
10
OVERDRIVE (mV)
Figure 16. tPHL vs. Overdrive
100
1000
Figure 15. Propagation Delay (tPHL
)
5
V
= 5V
S
4.5
4
3.5
3
2.5
2
V
= 2.7V
S
1.5
1
V
= 1.8V
S
0.5
0
1
10
OVERDRIVE (mV)
Figure 17. tPLH vs. Overdrive
100
1000
Copyright © 2015, Texas Instruments Incorporated
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ZHCSE55 –SEPTEMBER 2015
www.ti.com.cn
7 Detailed Description
7.1 Overview
A comparator is often used to convert an analog signal to a digital signal. As shown in Figure 18, the comparator
compares an input voltage (VIN) to a reference voltage (VREF). If VIN is less than VREF, the output transistor turns
on and pulls the output to V-, and thus the output (VO) goes low.
However, if VIN is greater than VREF, the output transistor turns off and the voltage (VO) is pulled high by the
external pull-up resistor.
ëh[Ç{
V
O
V
REF
ÇLa9
V
IN
Figure 18. Basic Comparator
7.2 Functional Block Diagram
+
V
V
REF
-
V
O
V
IN
+
-
V
7.3 Feature Description
7.3.1 Rail-to-Rail Input Stage
The LMV7275-Q1 has an input common mode voltage range (VCM) of −0.1V below the V− to 0.1 V above V+.
This is achieved by using paralleled PNP and NPN differential input pairs. When the VCM is near V+, the NPN
pair is on and the PNP pair is off. When the VCM is near V−, the NPN pair is off and the PNP pair is on. The
crossover point between the NPN and PNP input stages is around 950mV from V+. Because each input stage
has its own offset voltage (VOS), the VOS of the comparator becomes a function of the VCM. See curves for VOS
vs. VCM in the Typical Characteristics section. In application design, it is recommended to keep the VCM away
from the crossover point to avoid problems. The wide input voltage range makes LMV7275-Q1 ideal in power
supply monitoring circuits, where the comparators are used to sense signals close to ground and power supplies.
10
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LMV7275-Q1
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ZHCSE55 –SEPTEMBER 2015
Feature Description (continued)
7.3.2 Output Stage
Figure 19. LMV7275-Q1 Open-Drain Output
The LMV7275-Q1 has an open-drain output that requires a pull-up resistor to a positive supply voltage for the
output to operate properly. When the internal output transistor is off, the output voltage will be pulled up to the
external positive voltage (V2+) by the external pull-up resistor. This allows the output to be OR'ed with other
open-drain outputs on the same bus.
The output pull-up resistor may be connected to any voltage level between V- and V+ for level shifting
applications.
7.4 Device Functional Modes
7.4.1 Capacitive and Resistive Loads
The propagation delay on the rising edge of the LMV7275-Q1 depends on the load resistance and capacitance
values.
7.4.2 Noise
Most comparators have rather low gain. This allows the output to alternate between high and low when the input
signal changes slowly. The result is the output may oscillate between high and low when the differential input is
near zero and triggers on noise. The high gain of this comparator eliminates this problem. Less than 1 μV of
change on the input will drive the output from one rail to the other rail. If the input signal is noisy, the output
cannot ignore the noise unless some hysteresis is provided by positive feedback. (See Hysteresis.)
7.4.3 Hysteresis
It is a standard procedure to use hysteresis (positive feedback) around a comparator to prevent oscillation due to
the comparator triggering its own noise on slowly ramping signals. The following sections will describe various
ways to apply hysteresis.
7.4.3.1 Non-inverting Comparator With Hysteresis
Non-inverting comparator with hysteresis requires a two resistor network, and a voltage reference (Vref) at the
inverting input. When Vin is low, the output is also low. For the output to switch from low to high, Vin must rise up
to Vin1 where Vin1 is calculated by:
(1)
When Vin is high, the output is also high. To make the comparator switch back to its low state, Vin must equal Vref
before VA will again equal Vref. Vin can be calculated by:
(2)
The hysteresis of this circuit is the difference between Vin1 and Vin2
.
Copyright © 2015, Texas Instruments Incorporated
11
LMV7275-Q1
ZHCSE55 –SEPTEMBER 2015
www.ti.com.cn
Device Functional Modes (continued)
ΔVin = VCCR1/R2
(3)
VCC = +5V
RPULL-UP
5V
3 KΩ
VO
VREF = +2.5V
VO
+
VIN 2
VIN 1
RLOAD
100 KΩ
VIN
VA
R1
R2
0V
330 kΩ
1 MΩ
1.675
3.325
VIN
VO HIGH
VCC
VO LOW
VIN 1
R2
R1
VA = VREF
R1
VA = VREF
R2
VIN 2
Figure 20. Non-Inverting Comparator With Hysteresis
7.4.3.2 Inverting Comparator With Hysteresis
The inverting comparator with hysteresis requires a three resistor network that are referenced to the supply
voltage VCC of the comparator. When Vin at the inverting input is less than Va, the voltage at the non-inverting
node of the comparator (Vin < Va), the output voltage is high (for simplicity assume VO switches as high as VCC).
The three network resistors can be represented as R1//R3 in series with R2. The lower input trip voltage Va1 is
defined as:
(4)
When Vin is greater than Va (Vin > Va), the output voltage is low very close to ground. In this case the three
network resistors can be presented as R2//R3 in series with R1. The upper trip voltage Va2 is defined as:
12
Copyright © 2015, Texas Instruments Incorporated
LMV7275-Q1
www.ti.com.cn
ZHCSE55 –SEPTEMBER 2015
Device Functional Modes (continued)
(5)
(6)
The total hysteresis provided by the network is defined as:
ΔVa = Va1 - Va2
To assure that the comparator will always switch fully to VCC and not be pulled down by the load the resistors
values should be chosen as follow:
RPULL-UP << RLOAD
and R1 > RPULL-UP
(7)
(8)
.
VCC = +5V
R1
RPULL-UP
5
1 MΩ
3 KΩ
VO
VIN
VO
+
VA
VA2
VA1
RLOAD
100 KΩ
R3
1 MΩ
0
1.67
3.33
R2
1 MΩ
VIN
VO HIGH
VCC
VO LOW
VCC
R1
VA1
R2
R3
R1
VA2
R2
R3
Figure 21. Inverting Comparator With Hysteresis
Copyright © 2015, Texas Instruments Incorporated
13
LMV7275-Q1
ZHCSE55 –SEPTEMBER 2015
www.ti.com.cn
Device Functional Modes (continued)
7.4.4 Zero Crossing Detector
VCC
RPULL-UP
VO
RPROT
+
Figure 22. Simple Zero Crossing Detector
In a zero crossing detector circuit, the inverting input is connected to ground and the Non-Inverting input is
connected to a 100 mVPP AC signal. As the signal at the Non-Inverting input crosses 0 V, the output of the
comparator changes state.
RPROT is an optional input protection resistor to limit the current should the input voltage exceed the supply rails.
RPROT should be a minimum of 1 kΩ per volt of expected over-voltage and limit the current to less than ±1mA
under worst case fault conditions.
7.4.4.1 Zero Crossing Detector With Hysteresis
VCC
R3
R4
RPULL-UP
R1
R2
VIN
VO
V2
+
V1
D1
R6
R5
Figure 23. Zero Crossing Detector With Hysteresis
To improve switching times and centering the input threshold to ground a small amount of positive feedback is
added to the circuit. Voltage divider R4 and R5 establishes a reference voltage, V1, at the positive input. By
making the series resistance, R1 plus R2 equal to R5, the switching condition, V1 = V2, will be satisfied when VIN
= 0.
14
Copyright © 2015, Texas Instruments Incorporated
LMV7275-Q1
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ZHCSE55 –SEPTEMBER 2015
Device Functional Modes (continued)
The positive feedback resistor, R6, is made very large (with respect to R5 || R6 = 2000 R5). The resultant
hysteresis established by this network is very small (ΔV1 < 10 mV) but it is sufficient to insure rapid output
voltage transitions.
Diode D1 is used to insure that the inverting input terminal of the comparator never goes below approximately
−100 mV. As the input terminal goes negative, D1 will forward bias, clamping the node between R1 and R2 to
approximately −300 mV. This sets up a voltage divider with R2 and R3 preventing V2 from going below ground.
The maximum negative input overdrive is limited by the current handling ability of D1.
7.4.5 Threshold Detector
VIN
VD
R1
R2
RPULL-UP
+
VOUT
VREF
Figure 24. Threshold Detector
Instead of tying the inverting input to 0 V, the inverting input can be tied to a reference voltage. As the input on
the Non-Inverting input passes the VREF threshold, the output of the comparator changes state. It is important to
use a stable reference voltage to ensure a consistent switching point.
7.4.6 Universal Logic Level Shifter
VA
VCC
VB
10 kΩ
10 kΩ
RPULL-UP
+
Logic
Out
Logic
In
VB ≤ VCC
Figure 25. Logic Level Shifter
The output of LMV7275-Q1 is an unconnected drain of an NMOS device, which can be pulled up, through a
resistor, to any desired output level below the comparators power supply voltage (VB ≤ VCC). Hence, the following
simple circuit works as a universal logic level shifter, pulling up the signal to the desired level.
Copyright © 2015, Texas Instruments Incorporated
15
LMV7275-Q1
ZHCSE55 –SEPTEMBER 2015
www.ti.com.cn
Device Functional Modes (continued)
For example, VA could be the 5-V analog supply voltage, where VB could be the 3.3-V supply of the processor.
The output will now be compatible with the 3.3-V logic.
7.4.7 OR'ING the Output
VD
RPULL-UP
+
VO
+
+
+
Figure 26. OR’ing the Outputs
Open-drain outputs may be tied together, pulled up to VD by a common resistor to provide an output OR'ing
function. If any of the comparator outputs goes low, the output VO goes low.
16
Copyright © 2015, Texas Instruments Incorporated
LMV7275-Q1
www.ti.com.cn
ZHCSE55 –SEPTEMBER 2015
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LMV7275-Q1 is a single-supply comparator with 880 ns of propagation delay and only 12 µA of supply
current.
8.2 Typical Applications
8.2.1 Square Wave Oscillator
+
V
4.3kW
R
4
= 100kW
C
R
= 750pF
1
-
V
C
V
O
+
= 100kW
R
= 100kW
1
3
V
A
+
V
R
2
= 100kW
0
f ö 10KHz
Figure 27. Square Wave Oscillator Application
8.2.1.1 Design Requirements
A typical application for a comparator is as a square wave oscillator. Figure 27 generates a square wave whose
period is set by the RC time constant of the capacitor C1and resistor R4. The maximum frequency is limited by
the large signal propagation delay of the comparator, and by the capacitive loading at the output, which limits the
output slew rate.
8.2.1.2 Detailed Design Procedure
To analyze the circuit, consider it when the output is high. That implies that the inverted input (VC) is lower than
the Non-Inverting input (VA).
Figure 28. Squarewave Oscillator Timing Thresholds
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17
LMV7275-Q1
ZHCSE55 –SEPTEMBER 2015
www.ti.com.cn
Typical Applications (continued)
This causes the C1 to get charged through R4, and the voltage VC increases till it is equal to the Non-Inverting
input. The value of VA at this point is
V
.R
2
CC
V
=
A1
R
2
+ R ||R
1
3
(9)
If R1 = R2 = R3, then VA1 = 2VCC/3
At this point the comparator switches pulling down the output to the negative rail. The value of VA at this point is
V
(R ||R )
2 3
CC
+ (R ||R
3)
V
=
A2
R
1
2
(10)
If R1 = R2 = R3, then VA2 = VCC/3
The capacitor C1 now discharges through R4, and the voltage VC decreases till it is equal to VA2, at which point
the comparator switches again, bringing it back to the initial stage. The time period is equal to twice the time it
takes to discharge C1 from 2VCC/3 to VCC/3, which is given by R4C1.ln2. Hence the formula for the frequency is:
F = 1/(2·R4·C1·ln2)
8.2.1.3 Application Curve
Figure 29 shows the simulated results of an oscillator using the following values:
1. R1 = R2 = R3 = R4 = 100 kΩ
2. C1 = 750 pF, CL = 20 pF
3. V+ = 5 V, V- = GND
4. CSTRAY (not shown) from Va to GND = 10 pF
6
VOUT
5
V
a
4
3
2
1
V
c
0
-1
0
100
200
300
400
500
TIME (µs)
C001
Figure 29. Square Wave Oscillator Output Waveforms
18
Copyright © 2015, Texas Instruments Incorporated
LMV7275-Q1
www.ti.com.cn
ZHCSE55 –SEPTEMBER 2015
Typical Applications (continued)
8.2.2 Positive Peak Detector
V+
R1
10 kΩ
VIN
+
Q1
V
OUT
+
-
R1
1 MΩ
C1
10 µF
Figure 30. Positive Peak Detector
The positive peak detector is basically the comparator operated as a unity gain follower with a large holding
capacitor from the output to ground. A transistor is added to the output to provide a low impedance current
source. The upper output swing is limited by the emitter-base forward voltage. This allows capture of the most
positive input signal between 0 V and (V+) - 0.7V.
When the output of the comparator goes high, current is passed through the transistor to charge up the
capacitor. The only discharge path will be the 1-MΩ resistor shunting C1 and any load that is connected to the
output. The decay time can be altered simply by changing the 1-MΩ resistor.
8.2.3 Negative Peak Detector
VIN
+
V
OUT
-
R1
1 MΩ
C1
10 µF
V-
+
Figure 31. Negative Peak Detector for Negative Supply
The Negative Peak Detector circuit will store the peak negative voltage below ground ( 0 V to V-). For the
negative detector, the output transistor acts as a low-impedance current sink.
When VIN is more negative than VOUT, the output transistor will conduct and pull the output to -VCC, charging C1.
Charging stops when C1 reaches the same level as VIN. Because there is no pull-up resistor, the only discharge
path will be the 1-MΩ resistor and any load impedance applied. Therefore, the decay time is set by varying the 1-
MΩ resistor. Be sure to observe the polarity of C1!
Copyright © 2015, Texas Instruments Incorporated
19
LMV7275-Q1
ZHCSE55 –SEPTEMBER 2015
www.ti.com.cn
Typical Applications (continued)
V+
+
-
R1
1 MΩ
C1
10 µF
VIN
+
V
OUT
Figure 32. Negative Peak Detector for Positive Supply
An alternate positive supply version is shown in Figure 32 that will capture the lowest applied VIN value between
V+ and ground (V+ to 0V).
The output of either version should be buffered by a high-impedance follower stage to prevent loading of the RC
circuit.
8.2.4 Window Detector
+
V
R
1
V
+
-
REF2
OUTPUT A
OUTPUT B
A
B
V
IN
R
2
+
-
V
REF1
R
3
Figure 33. Window Detector
A window detector monitors the input signal to determine if it falls between two voltage levels. Both outputs are
true (high) when VREF1 < VIN < VREF2
20
Copyright © 2015, Texas Instruments Incorporated
LMV7275-Q1
www.ti.com.cn
ZHCSE55 –SEPTEMBER 2015
Typical Applications (continued)
OUTPUT B
V
IN
+
V
V
V
REF2
REF1
OUTPUT A
BOTH OUTPUTS
ARE HIGH
Figure 34. Window Detector Output Signal
The comparator outputs A and B are high only when VREF1 < VIN < VREF2, or within the window, where these are
defined as:
VREF1 = R3 / (R1 + R2 + R3) × V+
(11)
(12)
VREF2 = (R2 + R3) / (R1 + R2 + R3) × V+
To determine if the input signal falls outside of the two voltage levels, both inputs on each comparators can be
reversed to invert the logic.
The outputs should be tied together and use a shared pull-up resistor for a common logic output. If individual limit
outputs are needed, then each output will require it's own pull-up resistor.
Other names for window detectors are: threshold detector, level detector, and amplitude trigger or detector.
Copyright © 2015, Texas Instruments Incorporated
21
LMV7275-Q1
ZHCSE55 –SEPTEMBER 2015
www.ti.com.cn
9 Power Supply Recommendations
To minimize supply noise, power supplies should be decoupled by a 0.01-μF ceramic capacitor in parallel with a
10-μF capacitor.
Due to the nanosecond edges on the output transition, peak supply currents will be drawn during the time the
output is transitioning. Peak current depends on the capacitive loading on the output. The output transition can
cause transients on poorly bypassed power supplies. These transients can cause a poorly bypassed power
supply to ring due to trace inductance and low self-resonance frequency of high ESR bypass capacitors.
Treat the LMV7275-Q1 as a high-speed device. Keep the ground paths short and place small (low-ESR ceramic)
bypass capacitors directly between the V+ and V– pins.
Output capacitive loading and output toggle rate will cause the average supply current to rise over the quiescent
current.
10 Layout
10.1 Layout Guidelines
10.1.1 Circuit Techniques for Avoiding Oscillations in Comparator Applications
Feedback to almost any pin of a comparator can result in oscillation. In addition, when the input signal is a slow
voltage ramp or sine wave, the comparator may also burst into oscillation near the crossing point. To avoid
oscillation or instability, PCB layout should be engineered thoughtfully. Several precautions are recommended:
1. Power supply bypassing is critical, and will improve stability and response time. Resistance and inductance
from power supply wires and board traces increase power supply line impedance. When supply current
changes, the power supply line will move due to its impedance. Large enough supply line shift will cause the
comparator to malfunction. To avoid problems, a small bypass capacitor, such as 0.1-µF ceramic, should be
placed immediately adjacent to the supply pins. An additional 6.8 μF or greater tantalum capacitor should be
placed at the point where the power supply for the comparator is introduced onto the board. These
capacitors act as an energy reservoir and keep the supply impedance low. In a dual-supply application, a
0.1-μF capacitor is recommended to be placed across V+ and V− pins.
2. Keep all leads short to reduce stray capacitance and lead inductance. It will also minimize any unwanted
coupling from any high-level signals (such as the output). The comparators can easily oscillate if the output
lead is inadvertently allowed to capacitively couple to the inputs through stray capacitance. This shows up
only during the output voltage transition intervals as the comparator changes states. Try to avoid a long loop
which could act as an inductor (coil).
3. It is a good practice to use an unbroken ground plane on a printed-circuit-board to provide all components
with a low inductive ground connection. Make sure ground paths are low-impedance where heavier currents
are flowing to avoid ground level shift. Preferably there should be a ground plane under the component.
4. The output trace should be routed away from inputs. The ground plane should extend between the output
and inputs to act as a guard. This can be achieved by running a topside ground plane between the output
and inputs. A typical PCB layout is shown in Figure 35.
5. When the signal source is applied through a resistive network to one input of the comparator, it is usually
advantageous to connect the other input with a resistor with the same value, for both DC and AC
consideration. Input traces should be laid out symmetrically if possible.
22
版权 © 2015, Texas Instruments Incorporated
LMV7275-Q1
www.ti.com.cn
ZHCSE55 –SEPTEMBER 2015
10.2 Layout Example
Figure 35. Typical PCB Layout
版权 © 2015, Texas Instruments Incorporated
23
LMV7275-Q1
ZHCSE55 –SEPTEMBER 2015
www.ti.com.cn
11 器件和文档支持
11.1 器件支持
11.1.1 开发支持
相关开发支持请参阅以下文档：
•
•
•
•
《LMV7275 PSPICE 模型》，SNOM555
TINA-TI 基于 SPICE 的模拟仿真程序，http://www.ti.com.cn/tool/cn/tina-ti
DIP 适配器评估模块，http://www.ti.com.cn/tool/cn/dip-adapter-evm
TI 通用运行放大器评估模块，http://www.ti.com.cn/tool/cn/opampevm
11.2 文档支持
11.2.1 相关文档ꢀ
相关文档如下：
•
AN-74《四个独立运行的比较器》，SNOA654
11.3 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
24
版权 © 2015, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMV7275IDCKRQ1
ACTIVE
SC70
DCK
5
3000 RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 85
SKA
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OUTLINE
DCK0005A
SOT - 1.1 max height
S
C
A
L
E
5
.
6
0
0
SMALL OUTLINE TRANSISTOR
C
2.4
1.8
0.1 C
1.4
1.1
B
1.1 MAX
A
PIN 1
INDEX AREA
1
2
5
NOTE 4
(0.15)
(0.1)
2X 0.65
1.3
2.15
1.85
1.3
4
3
0.33
5X
0.23
0.1
0.0
(0.9)
TYP
0.1
C A B
0.15
0.22
0.08
GAGE PLANE
TYP
0.46
0.26
8
0
TYP
TYP
SEATING PLANE
4214834/C 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-203.
4. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X (0.65)
4
(R0.05) TYP
(2.2)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:18X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214834/C 03/2023
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X(0.65)
4
(R0.05) TYP
(2.2)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:18X
4214834/C 03/2023
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
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