LMV7291MG/NOPB [TI]
具有轨到轨输入的单路 1.8V 低功耗比较器 | DCK | 5 | -40 to 85;
| 型号： | LMV7291MG/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有轨到轨输入的单路 1.8V 低功耗比较器 | DCK | 5 | -40 to 85 放大器 信息通信管理 光电二极管 比较器 |
| 文件： | 总24页 (文件大小：1346K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LMV7291
www.ti.com
SNOSA86E –FEBRUARY 2004–REVISED MARCH 2013
LMV7291 Single 1.8V Low Power Comparator with Rail-to-Rail Input
Check for Samples: LMV7291
1
FEATURES
DESCRIPTION
The LMV7291 is
a rail-to-rail input low power
2
•
(VS = 1.8V, TA = 25°C, Typical
Values unless Specified)
comparator, characterized at supply voltage 1.8V,
2.7V and 5.0V. It consumes only 9uA supply current
per channel while achieving a 800ns propagation
delay.
•
•
•
•
•
•
•
Single Supply
Ultra Low Supply Current 9µA per Channel
Low Input Bias Current 10nA
Low Input Offset Current 200pA
Low ensured VOS 4mV
The LMV7291 is available in SC70 package. With this
tiny package, the PC board area can be significantly
reduced. It is ideal for low voltage, low power and
space critical designs.
Propagation Delay 880ns (20mV Overdrive)
The LMV7291 features a push-pull output stage
which allows operation with minimum power
consumption when driving a load.
Input Common Mode Voltage Range 0.1V
beyond Rails
The LMV7291 is built with Texas Instruments'
advance submicron silicon-gate BiCMOS process. It
has bipolar inputs for improved noise performance
and CMOS outputs for rail-to-rail output swing.
APPLICATIONS
•
•
•
•
Mobile Communications
Laptops and PDA's
Battery Powered Electronics
General Purpose Low Voltage Applications
Typical Circuit
V
IN
V
CC
R
1
C1 =
0.1µF
C2 =
10µF
+
-
V
OUT
R
2
V
REF
Figure 1. Threshold Detector
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2013, Texas Instruments Incorporated
LMV7291
SNOSA86E –FEBRUARY 2004–REVISED MARCH 2013
www.ti.com
(1)(2)
Absolute Maximum Ratings
ESD Tolerance
(3)
2KV
(4)
200V
VIN Differential
±Supply Voltage
5.5V
V+ +0.1V, V− −0.1V
Supply Voltage (V+ - V−)
Voltage at Input/Output pins
Soldering Information
Infrared or Convection (20 sec.)
Wave Soldering (10 sec.)
Storage Temperature Range
235°C
260°C
−65°C to +150°C
+150°C
(5)
Junction Temperature
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) Human body model, 1.5kΩ in series with 100pF.
(4) Machine Model, 0Ω in series with 200pF.
(5) Typical values represent the most likely parametric norm.
(1)
Operating Ratings
(2)
Operating Temperature Range
−40°C to +85°C
(2)
Package Thermal Resistance
SC70
265°C/W
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics.
(2) The maximum power dissipation is a function of TJ(MAX), θJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(MAX) - TA)/θJA. All numbers apply for packages soldered directly into a PC board.
2
Submit Documentation Feedback
Copyright © 2004–2013, Texas Instruments Incorporated
Product Folder Links: LMV7291
LMV7291
www.ti.com
SNOSA86E –FEBRUARY 2004–REVISED MARCH 2013
1.8V Electrical Characteristics
Unless otherwise specified, all limits ensured for TJ = 25°C, V+ = 1.8V, V− = 0V. Boldface limits apply at the temperature
(1)
extremes.
Symbol
VOS
Parameter
Input Offset Voltage
Condition
Min(2)
Typ(3)
Max(2)
Units
0.3
4
mV
6
(4)
TC VOS
Input Offset Temperature Drift
Input Bias Current
VCM = 0.9V
LMV7291
10
10
200
9
uV/C
nA
IB
IOS
IS
Input Offset Current
Supply Current
pA
12
14
µA
ISC
Output Short Circuit Current
Output Voltage High
Sourcing, VO = 0.9V
Sinking, VO = 0.9V
IO = 0.5mA
3.5
4
6
mA
6
VOH
VOL
VCM
1.7
1.58
1.74
1.63
52
V
IO = 1.5mA
Output Voltage Low
IO = −0.5mA
70
220
1.9
mV
IO = −1.5mA
166
Input Common Mode Voltage Range
CMRR > 45 dB
V
−0.1
47
V
CMRR
PSRR
Common Mode Rejection Ratio
Power Supply Rejection Ratio
Output Leakage Current
0 < VCM < 1.8V
V+ = 1.8V to 5V
VO = 1.8V
78
80
2
dB
dB
pA
55
ILEAKAGE
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the electrical
tables under conditions of internal self heating where TJ > TA. Absolute Maximum Ratings indicate junction temperature limits beyond
which the device may be permanently degraded, either mechanically or electrically.
(2) All limits are specified by testing or statistical analysis.
(3) Typical values represent the most likely parametric norm.
(4) Offset Voltage average drift determined by dividing the change in VOS at temperature extremes into the total temperature change.
1.8V AC Electrical Characteristics
Unless otherwise specified, all limits ensured for TJ = 25°C, V+ = 1.8V, V− = 0V, VCM = 0.5V, VO = V+/2 and RL > 1MΩ to V−.
(1)
Boldface limits apply at the temperature extremes.
Symbol
tPHL
Parameter
Condition
Min(2)
Typ(3)
Max(2)
Units
Propagation Delay
Input Overdrive = 20mV
880
ns
(High to Low)
Load = 50pF//5kΩ
Input Overdrive = 50mV
Load = 50pF//5kΩ
570
1100
800
ns
ns
ns
tPLH
Propagation Delay
(Low to High)
Input Overdrive = 20mV
Load = 50pF//5kΩ
Input Overdrive = 50mV
Load = 50pF//5kΩ
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the electrical
tables under conditions of internal self heating where TJ > TA. Absolute Maximum Ratings indicate junction temperature limits beyond
which the device may be permanently degraded, either mechanically or electrically.
(2) All limits are specified by testing or statistical analysis.
(3) Typical values represent the most likely parametric norm.
Copyright © 2004–2013, Texas Instruments Incorporated
Submit Documentation Feedback
3
Product Folder Links: LMV7291
LMV7291
SNOSA86E –FEBRUARY 2004–REVISED MARCH 2013
www.ti.com
2.7V Electrical Characteristics
Unless otherwise specified, all limits ensured for TJ = 25°C, V+ = 2.7V, V− = 0V. Boldface limits apply at the temperature
(1)
extremes.
Symbol
VOS
Parameter
Input Offset Voltage
Conditions
Min(2)
Typ(3)
Max(2)
Units
0.3
4
mV
6
(4)
TC VOS
Input Offset Temperature Drift
Input Bias Current
VCM = 1.35V
10
10
200
9
µV/C
nA
IB
IOS
IS
Input offset Current
Supply Current
pA
LMV7291
13
15
µA
ISC
Output Short Circuit Current
Output Voltage High
Sourcing, VO = 1.35V
Sinking, VO = 1.35V
IO = 0.5mA
12
12
15
15
mA
VOH
VOL
VCM
2.63
2.48
2.66
2.55
50
V
IO = 2.0mA
Output Voltage Low
IO = −0.5mA
70
220
2.8
mV
IO = −2mA
155
Input Common Voltage Range
CMRR > 45dB
V
−0.1
47
V
CMRR
PSRR
Common Mode Rejection Ratio
Power Supply Rejection Ratio
Output Leakage Current
0 < VCM < 2.7V
V+ = 1.8V to 5V
VO = 2.7V
78
80
2
dB
dB
pA
55
ILEAKAGE
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the electrical
tables under conditions of internal self heating where TJ > TA. Absolute Maximum Ratings indicate junction temperature limits beyond
which the device may be permanently degraded, either mechanically or electrically.
(2) All limits are specified by testing or statistical analysis.
(3) Typical values represent the most likely parametric norm.
(4) Offset Voltage average drift determined by dividing the change in VOS at temperature extremes into the total temperature change.
2.7V AC Electrical Characteristics
Unless otherwise specified, all limits ensured for TJ = 25°C, V+ = 2.7V, V− = 0V, VCM = 0.5V, VO = V+/2 and RL > 1MΩ to V−.
(1)
Boldface limits apply at the temperature extremes.
Symbol
tPHL
Parameter
Condition
Min(2)
Typ(3)
Max(2)
Units
Propagation Delay
Input Overdrive = 20mV
1200
ns
(High to Low)
Load = 50pF//5kΩ
Input Overdrive = 50mV
Load = 50pF//5kΩ
810
1300
860
ns
ns
ns
tPLH
Propagation Delay
(Low to High)
Input Overdrive = 20mV
Load = 50pF//5kΩ
Input Overdrive = 50mV
Load = 50pF//5kΩ
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the electrical
tables under conditions of internal self heating where TJ > TA. Absolute Maximum Ratings indicate junction temperature limits beyond
which the device may be permanently degraded, either mechanically or electrically.
(2) All limits are specified by testing or statistical analysis.
(3) Typical values represent the most likely parametric norm.
4
Submit Documentation Feedback
Copyright © 2004–2013, Texas Instruments Incorporated
Product Folder Links: LMV7291
LMV7291
www.ti.com
SNOSA86E –FEBRUARY 2004–REVISED MARCH 2013
5V Electrical Characteristics
Unless otherwise specified, all limits ensured for TJ = 25°C, V+ = 5V, V− = 0V. Boldface limits apply at the temperature
(1)
extremes.
Symbol
VOS
Parameter
Input Offset Voltage
Conditions
Min(2)
Typ(3)
Max(2)
Units
0.3
4
mV
6
(4)
TC VOS
Input Offset Temperature Drift
Input Bias Current
VCM = 2.5V
10
10
µV/C
nA
IB
IOS
IS
Input Offset Current
Supply Current
200
10
pA
LMV7291
14
16
µA
ISC
Output Short Circuit Current
Output Voltage High
Sourcing, VO = 2.5V
Sinking, VO = 2.5V
IO = 0.5mA
28
28
34
34
mA
VOH
VOL
VCM
4.93
4.70
4.96
4.77
27
V
mV
V
IO = 4.0mA
Output Voltage Low
IO = −0.5mA
70
300
5.1
IO = −4.0mA
225
Input Common Voltage Range
CMRR > 45dB
−0.1
47
CMRR
PSRR
Common Mode Rejection Ratio
Power Supply Rejection Ratio
Output Leakage Current
0 < VCM < 5.0V
V+ = 1.8V to 5V
VO = 5V
78
80
2
dB
dB
pA
55
ILEAKAGE
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the electrical
tables under conditions of internal self heating where TJ > TA. Absolute Maximum Ratings indicate junction temperature limits beyond
which the device may be permanently degraded, either mechanically or electrically.
(2) All limits are specified by testing or statistical analysis.
(3) Typical values represent the most likely parametric norm.
(4) Offset Voltage average drift determined by dividing the change in VOS at temperature extremes into the total temperature change.
5.0V AC Electrical Characteristics
Unless otherwise specified, all limits ensured for TJ = 25°C, V+ = 5.0V, V− = 0V, VCM = 0.5V, VO = V+/2 and RL > 1MΩ to V−.
(1)
Boldface limits apply at the temperature extremes.
Symbol
tPHL
Parameter
Condition
Min(2)
Typ(3)
Max(2)
Units
Propagation Delay
Input Overdrive = 20mV
2100
ns
(High to Low)
Load = 50pF//5kΩ
Input Overdrive = 50mV
Load = 50pF//5kΩ
1380
1800
1100
ns
ns
ns
tPLH
Propagation Delay
(Low to High)
Input Overdrive = 20mV
Load = 50pF//5kΩ
Input Overdrive = 50mV
Load = 50pF//5kΩ
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the electrical
tables under conditions of internal self heating where TJ > TA. Absolute Maximum Ratings indicate junction temperature limits beyond
which the device may be permanently degraded, either mechanically or electrically.
(2) All limits are specified by testing or statistical analysis.
(3) Typical values represent the most likely parametric norm.
Copyright © 2004–2013, Texas Instruments Incorporated
Submit Documentation Feedback
5
Product Folder Links: LMV7291
LMV7291
SNOSA86E –FEBRUARY 2004–REVISED MARCH 2013
www.ti.com
Connection Diagram
1
5
+
V
V
OUT
2
GND
+IN
3
4
-IN
Figure 2. 5-Pin SC70 – Top View
See Package Number DCK
6
Submit Documentation Feedback
Copyright © 2004–2013, Texas Instruments Incorporated
Product Folder Links: LMV7291
LMV7291
www.ti.com
SNOSA86E –FEBRUARY 2004–REVISED MARCH 2013
Typical Performance Characteristics
(TA = 25°C, Unless otherwise specified).
VOS
vs.
VCM
VOS
vs.
VCM
V
= ±0.9V
SUPPLY
V
= ±1.35V
SUPPLY
800
400
0
800
400
0
-40°C
-40°C
25°C
85°C
-400
-800
-400
-800
25°C
85°C
-0.9 -0.7 -0.5 -0.3 -0.1 0.1 0.3 0.5 0.7 0.9
(V)
-1.35 -0.9 -0.45
0
0.45
0.9
1.35
V
V
(V)
CM
CM
Figure 3.
Figure 4.
VOS
vs.
VCM
Short Circuit
vs.
Supply Voltage
40
V
= ±2.5V
SUPPLY
800
400
0
SOURCE
30
20
10
-40°C
SINK
-400
-800
25°C
85°C
0
-2.5 -2
-1
0
1
2 2.5
1.8
2.44
3.08
3.72
4.36
5.0
V
(V)
CM
SUPPLY VOLTAGE (V)
Figure 5.
Figure 6.
Supply Current
vs.
Supply Voltage
Supply Current
vs.
Supply Voltage
25
10
9
85°C
20
15
10
5
85°C
85°C
8
7
6
5
25°C
25°C
-40°C
-40°C
V
= HIGH
OUT
0
5
1.5
2
2.5
3
3.5
(V)
4
4.5
1.8
2.44
3.08
3.72
4.36
5.0
V
SUPPLY
SUPPLY VOLTAGE (V)
Figure 7.
Figure 8.
Copyright © 2004–2013, Texas Instruments Incorporated
Submit Documentation Feedback
7
Product Folder Links: LMV7291
LMV7291
SNOSA86E –FEBRUARY 2004–REVISED MARCH 2013
www.ti.com
Typical Performance Characteristics (continued)
(TA = 25°C, Unless otherwise specified).
Supply Current
Output Positive Swing
vs.
vs.
Supply Voltage
VSUPPLY
600
500
400
25
20
I
SOURCE
85°C
15
4mA
300
200
10
2mA
25°C
-40°C
1.5mA
5
100
0
0.5mA
V
= LOW
OUT
4
0
1.8
2.3
2.8
3.3
3.8
(V)
4.3
4.8
5
1.5
2
2.5
3
3.5
(V)
4.5
V
V
SUPPLY
SUPPLY
Figure 9.
Figure 10.
Output Negative Swing
Output Positive Swing
vs.
vs.
VSUPPLY
ISOURCE
600
500
400
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
V
= 1.8V
SUPPLY
I
SINK
85°C
4mA
25°C
300
200
2mA
1.5mA
-40°C
100
0
0.5mA
1.8
2.3
2.8
3.3
3.8
(V)
4.3
4.8
0
0.5
1
1.5
I
2
2.5
3
3.5
4
(mA)
V
SOURCE
SUPPLY
Figure 11.
Figure 12.
Output Negative Swing
Output Positive Swing
vs.
vs.
ISINK
ISOURCE
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.5
0.45
0.4
V
= 1.8V
V
= 2.7V
SUPPLY
SUPPLY
85°C
85°C
0.35
0.3
25°C
25°C
0.25
0.2
0.15
-40°
0.1
-40°C
0.05
0
0
0.5
1
1.5
2
2.5
3
3.5
4
0
0.5
1
1.5
2
2.5
(mA)
3
3.5
4
I
I
(mA)
SINK
SOURCE
Figure 13.
Figure 14.
8
Submit Documentation Feedback
Copyright © 2004–2013, Texas Instruments Incorporated
Product Folder Links: LMV7291
LMV7291
www.ti.com
SNOSA86E –FEBRUARY 2004–REVISED MARCH 2013
Typical Performance Characteristics (continued)
(TA = 25°C, Unless otherwise specified).
Output Negative Swing
Output Negative Swing
vs.
vs.
ISINK
ISINK
0.5
0.4
0.3
0.2
V
= 2.7V
SUPPLY
V
= 5V
SUPPLY
0.45
0.4
85°C
85°C
0.35
0.3
25°C
25°C
0.25
0.2
0.15
0.1
0
0.1
-40°C
-40°C
0.05
0
0
0.5
1
1.5
2
2.5
(mA)
3
3.5
4
0
0.5
1
1.5
2
2.5
3
3.5
4
I
I
(mA)
SINK
SINK
Figure 15.
Figure 16.
Output Positive Swing
vs.
ISOURCE
Propagation Delay (tPLH)
0.4
0.3
0.2
5
4
3
2
1
0
V = 1.8V
CC
TEMP = 25°C
LOAD = 5kW//50pF
V
= 5V
SUPPLY
85°C
20mV
50mV
25°C
ö
ö
100
0.1
0
0
OVERDRIVE
-40°C
-100
0
0.5
1
1.5
2
2.5
3
3.5
4
0
500 1000 1500 2000 2500 3000
TIME (ns)
I
(mA)
SOURCE
Figure 17.
Figure 18.
Propagation Delay (tPHL
)
Propagation Delay (tPLH)
5
4
3
2
1
0
5
4
3
2
1
0
V
= 2.7V
V
= 1.8 V
CC
TEMP = 25°C
LOAD = 5kW//50pF
CC
TEMP = 25°C
LOAD = 5kW//50pF
50mV
20mV
50mV
20mV
ö
ö
ö
ö
100
100
OVERDRIVE
OVERDRIVE
0
0
-100
-100
0
500 1000 1500 2000 2500 3000
TIME (ns)
0
500 1000 1500 2000 2500 3000
TIME (ns)
Figure 19.
Figure 20.
Copyright © 2004–2013, Texas Instruments Incorporated
Submit Documentation Feedback
9
Product Folder Links: LMV7291
LMV7291
SNOSA86E –FEBRUARY 2004–REVISED MARCH 2013
www.ti.com
Typical Performance Characteristics (continued)
(TA = 25°C, Unless otherwise specified).
Propagation Delay (tPHL
)
Propagation Delay (tPLH
)
5
5
4
3
2
1
0
V
= 2.7 V
V
= 5.0V
CC
TEMP = 25°C
LOAD = 5kW//50pF
50mV
CC
4
3
2
1
0
TEMP = 25°C
LOAD = 5kW//50pF
20mV
50mV
20mV
ö
ö
ö
ö
100
100
OVERDRIVE
OVERDRIVE
0
0
-100
-100
0
500
1500 2000 2500 3000
1000
TIME (ns)
0
500 1000 1500 2000 2500 3000
TIME (ns)
Figure 21.
Figure 22.
tPHL
vs.
Overdrive
Propagation Delay (tPHL
)
8
7
6
5
4
3
2
1
0
5
4
3
2
1
0
V
= 5.0 V
CC
TEMP = 25°C
LOAD = 5kW//50pF
V
= 5V
S
50mV
20mV
V
= 2.7V
S
ö
ö
100
OVERDRIVE
0
-100
V
= 1.8V
S
0
500 1000 1500 2000 2500 3000
TIME (ns)
0
10
100
1000
OVERDRIVE (mV)
Figure 23.
Figure 24.
tPLH
vs.
Overdrive
5
V
= 5V
S
4.5
4
3.5
3
2.5
2
V
= 2.7V
S
1.5
1
V
= 1.8V
S
0.5
0
1
10
100
1000
OVERDRIVE (mV)
Figure 25.
10
Submit Documentation Feedback
Copyright © 2004–2013, Texas Instruments Incorporated
Product Folder Links: LMV7291
LMV7291
www.ti.com
SNOSA86E –FEBRUARY 2004–REVISED MARCH 2013
APPLICATION NOTES
BASIC COMPARATOR
A comparator is often used to convert an analog signal to a digital signal. As shown in Figure 26, the comparator
compares an input voltage (VIN) to a reference voltage (VREF). If VIN is less than VREF, the output (VO) is low.
However, if VIN is greater than VREF, the output voltage (VO) is high.
+
V
VOLTS
V
O
V
REF
-
V
O
V
IN
+
V
REF
-
V
TIME
V
IN
Figure 26. LMV7291 Basic Comparator
RAIL-TO-RAIL INPUT STAGE
The LMV7291 has an input common mode voltage range (VCM) of −0.1V below the V− to 0.1V above V+. This is
achieved by using paralleled PNP and NPN differential input pairs. When the VCM is near V+, the NPN pair is on
and the PNP pair is off. When the VCM is near V−, the NPN pair is off and the PNP pair is on. The crossover point
between the NPN and PNP input stages is around 950mV from V+. Since each input stage has its own offset
voltage (VOS), the VOS of the comparator becomes a function of the VCM. See Figure 3, Figure 4, and Figure 5 in
Typical Performance Characteristics. In application design, it is recommended to keep the VCM away from the
crossover point to avoid problems. The wide input voltage range makes LMV7291 ideal in power supply
monitoring circuits, where the comparators are used to sense signals close to gnd and power supplies.
OUTPUT STAGE
The LMV7291 has a push-pull output stage. This output stage keeps the total system power consumption to the
absolute minimum. The only current consumed is the low supply current and the current going directly into the
load. When output switches, both PMOS and NMOS at the output stage are on at the same time for a very short
time. This allows current to flow directly between V+ and V− through output transistors. The result is a short spike
of current (shoot-through current) drawn from the supply and glitches in the supply voltages. The glitches can
spread to other parts of the board as noise. To prevent the glitches in supply lines, power supply bypass
capacitors must be installed. See CIRCUIT TECHNIQUES FOR AVOIDING OSCILLATIONS IN COMPARATOR
APPLICATIONS for details.
HYSTERESIS
It is a standard procedure to use hysteresis (positive feedback) around a comparator, to prevent oscillation, and
to avoid excessive noise on the output because the comparator is a good amplifier of its own noise.
Inverting Comparator with Hysteresis
The inverting comparator with hysteresis requires a three resistor network that are referenced to the supply
voltage VCC of the comparator (Figure 27). When VIN at the inverting input is less than VA, the voltage at the non-
inverting node of the comparator (VIN < VA), the output voltage is high (for simplicity assume VO switches as high
as VCC). The three network resistors can be represented as R1||R3 in series with R2. The lower input trip voltage
VA1 is defined as
Copyright © 2004–2013, Texas Instruments Incorporated
Submit Documentation Feedback
11
Product Folder Links: LMV7291
LMV7291
SNOSA86E –FEBRUARY 2004–REVISED MARCH 2013
www.ti.com
VCC R2
VA1
=
(R1||R3) + R2
(1)
When VIN is greater than VA (VIN > VA), the output voltage is low and very close to ground. In this case the three
network resistors can be presented as R2//R3 in series with R1. The upper trip voltage VA2 is defined as
VCC (R2||R3)
VA2
=
R1 + (R2||R3)
(2)
(3)
The total hysteresis provided by the network is defined as
ΔVA = VA1 - VA2
A good typical value of ΔVA would be in the range of 5 to 50 mV. This is easily obtained by choosing R3 as 1000
to 100 times (R1||R2) for 5V operation, or as 300 to 30 times (R1||R2) for 1.8V operation.
Figure 27. Inverting Comparator with Hysteresis
Non-Inverting Comparator with Hysteresis
A non-inverting comparator with hysteresis requires a two resistor network, and a voltage reference (VREF) at the
inverting input (Figure 28). When VIN is low, the output is also low. For the output to switch from low to high, VIN
must rise up to VIN1, where VIN1 is calculated by
(4)
12
Submit Documentation Feedback
Copyright © 2004–2013, Texas Instruments Incorporated
Product Folder Links: LMV7291
LMV7291
www.ti.com
SNOSA86E –FEBRUARY 2004–REVISED MARCH 2013
When VIN is high, the output is also high. To make the comparator switch back to its low state, VIN must equal
VREF before VA will again equal VREF. VIN can be calculated by:
(5)
The hysteresis of this circuit is the difference between VIN1 and VIN2
.
ΔVIN = VCCR1/R2
(6)
Figure 28. Non-Inverting Comparator with Hysteresis
CIRCUIT TECHNIQUES FOR AVOIDING OSCILLATIONS IN COMPARATOR APPLICATIONS
Feedback to almost any pin of a comparator can result in oscillation. In addition, when the input signal is a slow
voltage ramp or sine wave, the comparator may also burst into oscillation near the crossing point. To avoid
oscillation or instability, PCB layout should be engineered thoughtfully. Several precautions are recommended:
1. Power supply bypassing is critical, and will improve stability and transient response. Resistance and
inductance from power supply wires and board traces increase power supply line impedance. When supply
current changes, the power supply line will move due to its impedance. Large enough supply line shift will
cause the comparator to mis-operate. To avoid problems, a small bypass capacitor, such as 0.1uF ceramic,
should be placed immediately adjacent to the supply pins. An additional 6.8μF or greater tantalum capacitor
should be placed at the point where the power supply for the comparator is introduced onto the board. These
capacitors act as an energy reservoir and keep the supply impedance low. In dual supply application, a
0.1μF capacitor is recommended to be placed across V+ and V− pins.
2. Keep all leads short to reduce stray capacitance and lead inductance. It will also minimize any unwanted
coupling from any high-level signals (such as the output). The comparators can easily oscillate if the output
lead is inadvertently allowed to capacitively couple to the inputs via stray capacitance. This shows up only
during the output voltage transition intervals as the comparator changes states. Try to avoid a long loop
which could act as an inductor (coil).
3. It is a good practice to use an unbroken ground plane on a printed circuit board to provide all components
with a low inductive ground connection. Make sure ground paths are low-impedance where heavier currents
are flowing to avoid ground level shift. Preferably there should be a ground plane under the component.
4. The output trace should be routed away from inputs. The ground plane should extend between the output
and inputs to act as a guard.
Copyright © 2004–2013, Texas Instruments Incorporated
Submit Documentation Feedback
13
Product Folder Links: LMV7291
LMV7291
SNOSA86E –FEBRUARY 2004–REVISED MARCH 2013
www.ti.com
5. When the signal source is applied through a resistive network to one input of the comparator, it is usually
advantageous to connect the other input with a resistor with the same value, for both DC and AC
consideration. Input traces should be laid out symmetrically if possible.
6. All pins of any unused comparators should be tied to the negative supply.
Typical Applications
POSITIVE PEAK DETECTOR
A positive peak detect circuit is basically a comparator operated in a unity gain follower configuration, with a
capacitor as a load to maintain the highest voltage. A diode is added at the output to prevent the capacitor from
discharging through the output, and a 1MΩ resistor added in parallel to the capacitor to provide a high
impedance discharge path. When the input VIN increases, the inverting input of the comparator follows it, thus
charging the capacitor. When it decreases, the cap discharges through the 1MΩ resistor. The decay time can be
modified by changing the resistor. The output should be accessed through a follower circuit to prevent loading.
+V
CC
V
IN
+
-
V
OUT
-
C1
10 mF
R
1 MW
2
+
Figure 29. Positive Peak Detector
NEGATIVE PEAK DETECTOR
For the negative detector, the output transistor of the comparator acts as a low impedance current sink. Since
there is no pull-up resistor, the only discharge path will be the 1MΩ resistor and any load impedance used.
Decay time is changed by varying the 1MΩ resistor.
+V
CC
V
IN
+
V
OUT
-
R
1
1MW
C
10mF
-
1
+
-V
CC
Figure 30. Negative Peak Detector
SQUARE WAVE GENERATOR
A typical application for a comparator is as a square wave oscillator. The circuit below generates a square wave
whose period is set by the RC time constant of the capacitor C1and resistor R4. The maximum frequency is
limited by the large signal propagation delay of the comparator, and by the capacitive loading at the output,
which limits the output slew rate.
14
Submit Documentation Feedback
Copyright © 2004–2013, Texas Instruments Incorporated
Product Folder Links: LMV7291
LMV7291
www.ti.com
SNOSA86E –FEBRUARY 2004–REVISED MARCH 2013
R
= 100 kW
4
C
R
= 750 pF
1
-
V
C
V
O
+
= 100 kW
R
= 100 kW
1
3
V
A
+
V
+
V
R
= 100 kW
2
0
f ö 10 kHz
Figure 31. Squarewave Oscillator
To analyze the circuit, consider it when the output is high. That implies that the inverted input (VC) is lower than
the non-inverting input (VA). This causes the C1 to get charged through R4, and the voltage VC increases till it is
equal to the non-inverting input. The value of VA at this point is
V
.R
2
CC
V
=
A1
R
2
+ R ||R
1 3
(7)
If R1 = R2 = R3 then VA1 = 2VCC/3
At this point the comparator switches pulling down the output to the negative rail. The value of VA at this point is
V
(R ||R )
2 3
CC
V
=
A2
R
1
+ (R ||R
3)
2
(8)
If R1 = R2 = R3 then VA2 = VCC/3
The capacitor C1 now discharges through R4, and the voltage VC decreases till it is equal to VA2, at which point
the comparator switches again, bringing it back to the initial stage. The time period is equal to twice the time it
takes to discharge C1 from 2VCC/3 to VCC/3, which is given by R4C1.ln2. Hence the formula for the frequency is:
F = 1/(2.R4.C1.ln2)
Copyright © 2004–2013, Texas Instruments Incorporated
Submit Documentation Feedback
15
Product Folder Links: LMV7291
LMV7291
SNOSA86E –FEBRUARY 2004–REVISED MARCH 2013
www.ti.com
REVISION HISTORY
Changes from Revision D (March 2013) to Revision E
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 15
16
Submit Documentation Feedback
Copyright © 2004–2013, Texas Instruments Incorporated
Product Folder Links: LMV7291
PACKAGE OPTION ADDENDUM
www.ti.com
23-Jan-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMV7291MG
ACTIVE
SC70
DCK
5
1000
Non-RoHS
& Green
Call TI
Level-1-260C-UNLIM
-40 to 85
C36
Samples
LMV7291MG/NOPB
LMV7291MGX/NOPB
ACTIVE
ACTIVE
SC70
SC70
DCK
DCK
5
5
1000 RoHS & Green
SN
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
C36
C36
Samples
Samples
3000 RoHS & Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
23-Jan-2023
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Oct-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMV7291MG
SC70
SC70
SC70
DCK
DCK
DCK
5
5
5
1000
1000
3000
178.0
178.0
178.0
8.4
8.4
8.4
2.25
2.25
2.25
2.45
2.45
2.45
1.2
1.2
1.2
4.0
4.0
4.0
8.0
8.0
8.0
Q3
Q3
Q3
LMV7291MG/NOPB
LMV7291MGX/NOPB
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Oct-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LMV7291MG
SC70
SC70
SC70
DCK
DCK
DCK
5
5
5
1000
1000
3000
208.0
208.0
208.0
191.0
191.0
191.0
35.0
35.0
35.0
LMV7291MG/NOPB
LMV7291MGX/NOPB
Pack Materials-Page 2
PACKAGE OUTLINE
DCK0005A
SOT - 1.1 max height
S
C
A
L
E
5
.
6
0
0
SMALL OUTLINE TRANSISTOR
C
2.4
1.8
0.1 C
1.4
1.1
B
1.1 MAX
A
PIN 1
INDEX AREA
1
2
5
NOTE 4
(0.15)
(0.1)
2X 0.65
1.3
2.15
1.85
1.3
4
3
0.33
5X
0.23
0.1
0.0
(0.9)
TYP
0.1
C A B
0.15
0.22
0.08
GAGE PLANE
TYP
0.46
0.26
8
0
TYP
TYP
SEATING PLANE
4214834/C 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-203.
4. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X (0.65)
4
(R0.05) TYP
(2.2)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:18X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214834/C 03/2023
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X(0.65)
4
(R0.05) TYP
(2.2)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:18X
4214834/C 03/2023
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023, Texas Instruments Incorporated
相关型号：
LMV751M5
Single, 5.5-V, 5-MHz, low noise (6.5-nV/√Hz), 1-mV offset operational amplifier | DBV | 5 | -40 to 85
TI
LMV751M5/NOPB
IC OP-AMP, 1500 uV OFFSET-MAX, 4.5 MHz BAND WIDTH, PDSO5, SOT-23, 5 PIN, Operational Amplifier
NSC
LMV751M5/NOPB
Single, 5.5-V, 5-MHz, low noise (6.5-nV/√Hz), 1-mV offset operational amplifier | DBV | 5 | -40 to 85
TI
LMV751M5X/NOPB
IC OP-AMP, 1500 uV OFFSET-MAX, 4.5 MHz BAND WIDTH, PDSO5, SOT-23, 5 PIN, Operational Amplifier
NSC
LMV751M5X/NOPB
Single, 5.5-V, 5-MHz, low noise (6.5-nV/√Hz), 1-mV offset operational amplifier | DBV | 5 | -40 to 85
TI
©2020 ICPDF网 联系我们和版权申明