LMX1204RHAT [TI]
支持 JESD204B/C SYSREF 和相位同步的 12.8GHz 射频缓冲器、乘法器和分频器 | RHA | 40 | -40 to 85;
| 型号： | LMX1204RHAT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 支持 JESD204B/C SYSREF 和相位同步的 12.8GHz 射频缓冲器、乘法器和分频器 | RHA | 40 | -40 to 85 射频 |
| 文件： | 总45页 (文件大小：3171K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LMX1204
ZHCSOF2A –JULY 2021 –REVISED AUGUST 2022
LMX1204 低噪声、高频JESD 缓冲器/倍频器/分频器
1 特性
3 说明
• 300MHz 至12.8GHz 输出频率
• 超低噪声
该器件具有高频功能和极低的抖动特性，可在不降低信
噪比的情况下，很好地解决时钟精度、高频数据转换器
的问题。4 个高频时钟输出中的每一个输出以及具有更
大分频器范围的附加 LOGICLK 输出都与 SYSREF 输
出时钟信号配对。JESD 接口的 SYSREF 信号可以在
内部生成，也可以作为输入传入，并重新计时为器件时
钟。对于数据转换器时钟应用，务必使时钟的抖动小于
数据转换器的孔径抖动。在需要对 4 个以上数据转换
器进行时钟控制的应用中，可以使用多个器件开发各种
级联架构，以分配所需的所有高频时钟和 SYSREF 信
号。凭借其低抖动和低本底噪声，该器件可与超低噪声
参考时钟源相结合，是时钟控制型数据转换器的典型解
决方案，尤其是在3GHz 以上采样时。
– 6GHz 输出的本底噪声为-161dBc/Hz
– 6GHz 输出、10kHz 偏移时的1/f 噪声为–
154dBc/Hz
– 在30fs 附加抖动下（直流至fCLK 积分范围）
• 4 个具有相应SYSREF 输出的高频时钟
– 支持÷1（缓冲模式）、÷2、3、4、5、6、7 和
8 的共享分频器
– 支持x1（滤波器模式）、x2、x3 和x4 的基于
PLL 的共享倍频器
• 带有相应SYSREF 输出的LOGICLK 输出
– 基于单独的分频组
– ÷1、2、4 预分频器
封装信息(1)
– ÷1（旁路）、2、…、1023 后分频器
• 8 个可编程输出功率级别
• 同步的SYSREF 时钟输出
器件型号
封装
封装尺寸
LMX1204
VQFN (40)
6.00mm × 6.00mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
– 在12.8GHz 下，508 次延迟步长调整，每次小
于2.5ps
– 发生器和中继器模式
CAL
CLKOUT0
xM
– SYSREFREQ 引脚的窗口化特性，以优化计时
• 针对所有分频和倍频器件的同步功能
• 2.5V 工作电压
SYSREFOUT0
t0
t1
t2
t3
CLKIN
CLKOUT1
÷2,3,..,8
SYSREFOUT1
• –40ºC 至+85ºC 工作温度
CLKOUT2
2 应用
Pulser
÷1,2,4
÷2,3, … , 4095
SYSREFOUT2
SYSREFREQ
RETIME
SYSREF GENERATOR
CLKOUT3
• 通用：
SYSREFOUT3
– 数据转换器时钟
– 时钟分配/倍频/分频
• 测试设备：
SCK
SDI
÷1,2,4
÷1,2,3,...1023
LOGICLKOUT
Digital
Control
CS#
t4
LOGISYSREFOUT
MUXOUT
RETIME
– 示波器
– 宽带数字转换器
– 无线设备测试仪
• 航空航天与国防：
方框图
– 雷达
– 电子战
– 导引头前端
– 军需品
– 相控阵天线/波束形成
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNAS800
LMX1204
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ZHCSOF2A –JULY 2021 –REVISED AUGUST 2022
Table of Contents
7.3 Feature Description...................................................17
7.4 Device Functional Modes..........................................27
8 Application and Implementation..................................28
8.1 Applications Information............................................28
8.2 Typical Application.................................................... 29
8.3 Power Supply Recommendations.............................31
8.4 Layout....................................................................... 31
9 Device and Documentation Support............................33
9.1 Device Support......................................................... 33
9.2 接收文档更新通知..................................................... 33
9.3 支持资源....................................................................33
9.4 Trademarks...............................................................33
9.5 Electrostatic Discharge Caution................................33
9.6 术语表....................................................................... 33
10 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................6
6.6 Timing Requirements..................................................8
6.7 Timing Requirements..................................................8
6.8 Typical Characteristics ...............................................9
7 Detailed Description......................................................15
7.1 Overview...................................................................15
7.2 Functional Block Diagram.........................................16
Information.................................................................... 33
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (July 2021) to Revision A (August 2022)
Page
• 将数据表状态从“预告信息”更改为“生产数据”.............................................................................................1
• 向数据表中添加了滤波器模式信息......................................................................................................................1
• Added descriptions for POR, multiplier, filter mode, common mode voltage, and other topics in the Detailed
Description section........................................................................................................................................... 15
• Changed 表8-1 ............................................................................................................................................... 28
• Moved the Power Supply Recommendations and Layout sections to the Application and Implementation
section.............................................................................................................................................................. 31
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5 Pin Configuration and Functions
MUXOUT
SYSREFREQ_P
SYSREFREQ_N
VCC_CLKIN
GND
1
2
3
4
5
6
7
8
9
10
30
29
28
27
26
25
24
23
22
21
SYSREFOUT2_P
SYSREFOUT2_N
LOGICLKOUT_P
LOGICLKOUT_N
GND
DAP
CLKIN_P
CLKIN_N
SCK
VCC_LOGICLK
LOGISYSREFOUT_P
LOGISYSREFOUT_N
SYSREFOUT1_N
SYSREFOUT1_P
SDI
CS#
Not to scale
图5-1. RHA Package 40-Pin VQFN Top View
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表5-1. Pin Functions
NAME
NO.
TYPE
DESCRIPTION
If not using the multiplier, this pin may be left open. If using the multiplier,
bypass this pin to GND with a 10-nF capacitor for optimal noise performance.
BIAS01
20
BYP
BYP
If not using the multiplier, this pin may be left open. If using the multiplier,
bypass this pin to GND with a 10-µF and 0.1-µF capacitor for optimal noise
performance.
BIAS23
31
CLKIN_N
CLKIN_P
7
6
Differential reference input clock. Internal 50-Ω termination. AC-couple with a
capacitor appropriate to the input frequency (typically 0.1 µF or smaller). If
using single-ended, terminate unused side with a series AC-coupling
capacitor 50-Ω resistor to GND.
I
CLKOUT0_N
CLKOUT0_P
CLKOUT1_N
CLKOUT1_P
CLKOUT2_N
CLKOUT2_P
CLKOUT3_N
CLKOUT3_P
CS#
15
14
19
Differential clock output pairs. Each pin is an open-collector output with
internally integrated 50-Ω resistor with programmable output swing. AC
coupling required.
18
O
32
33
36
37
10
I
SPI chip select. High impedance CMOS input. Accepts up to 3.3 V.
Ground these pins.
DAP
DAP
GND
GND
5,13,17,26,34,38
LOGICLKOUT_N
LOGICLKOUT_P
LOGISYSREFOUT_N
LOGISYSREFOUT_P
MUXOUT
27
28
23
24
1
Differential clock output pair. Selectable CML, LVDS, or LVPECL format.
Programmable common-mode voltage.
O
O
Differential clock output pair. Selectable CML, LVDS, or LVPECL format.
Programmable common-mode voltage.
O
I
Multiplexed pin serial data readback and lock status of the multiplier.
SPI clock. High impedance CMOS input. Accepts up to 3.3 V.
SPI data input. High impedance CMOS input. Accepts up to 3.3 V.
SCK
8
SDI
9
I
SYSREFREQ_N
3
Differential SYSREF request input for JESD204B support. Internal 50-Ω AC
coupled to internal common-mode voltage or capacitor to GND. Supports AC
and DC coupling which can directly accept a common mode voltage of 1.2 to
2 V.
I
SYSREFREQ_P
2
SYSREFOUT0_N
SYSREFOUT0_P
SYSREFOUT1_N
SYSREFOUT1_P
SYSREFOUT2_N
SYSREFOUT2_P
SYSREFOUT3_N
SYSREFOUT3_P
VCC_CLKIN
12
11
22
21
29
30
39
40
4
Differential SYSREF CML output pairs for JESD204B support. Supports AC
and DC coupling with programmable common-mode voltage of 0.6 to 2 volts.
O
Connect to a 2.5-V supply. Recommend a shunt high frequency capacitor
(typically 0.1 µF or smaller) close to the pin in parallel with larger capacitors
(typically 1 µF and 10 µF) farther away.
VCC_LOGICLK
VCC01
25
16
35
PWR
VCC23
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
GND
GND
MAX
2.75
UNIT
V
VDD
VIN
VIN
VIN
TJ
Power supply voltage
DC Input Voltage (SCK, SDI, CSB)
DC Input Voltage (SYSREFREQ)
AC Input Voltage (CLKIN)
Junction temperature
3.6
V
VDD + 0.3
VDD
V
Vpp
°C
°C
150
Tstg
Storage temperature
150
–65
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Recommended Operating Conditions, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC
JS-001, all pins(1)
±2500
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per ANSI/ESDA/
JEDEC JS-002, all pins(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.4
NOM
MAX
2.6
UNIT
V
VDD
TA
Supply voltage
2.5
Ambient temperature
Junction temperature
85
°C
–40
TJ
125
°C
6.4 Thermal Information
RHA (VQFN)
THERMAL METRIC(1)
UNIT
40 PINS
24.8
13.0
6.9
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.1
ΨJT
6.9
ΨJB
RθJC(bot)
0.5
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Current Consumption
Powered up, all outputs and SYSREF on
Powered up, all outputs on, all SYSREF off
Powered up, all outputs and SYSREF off
Powered down(2)
1050
600
265
11
ICC
Supply Current (1)
mA
SYSREF
fSYSREF
Δt
Generator mode
Repeater mode
fCLKIN = 12.8 GHz
SYSREFOUT
CML
200
100
MHz
MHz
ps
SYSREF output frequency
SYSREF delay step size
3
45
ps
120
120
230
45
ps
tRISE
tFALL
VOD
Rise time (20% to 80%)
Fall time (20% to 80%)
Differential output voltage
LOGISYSREFOUT
LVDS
ps
LVPECL
ps
SYSREFOUT
ps
CML
120
120
170
0.85
0.4
ps
LOGISYSREFOUT
SYSREFOUT
LVDS
ps
LVPECL
ps
Vpp
Vp
Vp
Vp
CML
LOGISYSREFOUT
LVDS
0.4
LVPECL
0.8
CML
SYSREFOUTx_PW
R=4
100 ΩDifferential
Load
VSYSREFCM Common mode voltage
SYSREFOUT
0.8
1.3
V
SYSREFREQ Pins
VSYSREFIN Voltage input range
AC differential voltage
0.8
1.2
2
2
Vpp
V
Differential 100 Ω Termination, DC coupled
VCM
Input common mode
Set externally
Clock Input
fIN
Input frequency
Input power
0.3
0
12.8
10
GHz
dBm
Single-ended power at CLKIN_P or
CLKIN_N
PIN
Clock Outputs
fOUT
fOUT
fOUT
fOUT
Output frequency
Divide-by-2
0.15
0.3
3.2
1
6.4
12.8
6.4
Output frequency
Output frequency
Output frequency
Buffer Mode
GHz
x1 (filter mode) , x2, x3, x4
LOGICLK output
800
MHz
Multiplier calibration
time
fIN = 3.2 GHz; x2
fSMCLK = 28 MHz
tCAL
Calibration-time
Output power
750
4
μs
fCLKLOUT= 6 GHz
OUTx_PWR = 7
pOUT
Single-Ended
dBm
tRISE
tFALL
Rise time (20% to 80%)
Fall time (20% to 80%)
fCLKOUT = 300 MHz
fCLKOUT = 300 MHz
45
45
ps
ps
Propagation Delay and Skew
| tSKEW Magnitude of skew between outputs CLKOUTx to CLKOUTy, not LOGICLK
|
1
15
ps
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PARAMETER
Noise, Jitter, and Spurs
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Buffer Mode
5
12
16
21
26
Filter Mode
x2 Multiplier
x3 Multiplier
x4 Multiplier
Additive Jitter. 12k to
100 MHz integration
bandwidth.
JCKx
Additive jitter
fs, rms
Slew Rate > 8 V/ns,
fCLK=6 GHz
Flicker
1/f flicker noise
Noise Floor
Buffer Mode
-154
dBc/Hz
dBc/Hz
NF
NF
Buffer Mode
Divide-by-2
≥
-161
-160.5
fOUT = 6 GHz; fOffset
100 MHz
Multiplier (x1,
x2,x3,x4)
NF
–161.5
NFL
NFL
NFL
CML
-150.5
-151.5
-153.5
-25
LOGICLK output, 300
MHz
Noise Floor
LVDS
dBc/Hz
LVPECL
fOUT = 6 GHz (differential), Buffer Mode
fOUT = 6 GHz (single-ended), Buffer Mode
fOUT = 6 GHz, single-ended, Divide by 2
x2 (fSPUR = 3 GHz)
H2
Second harmonic
-13
dBc
dBc
-16
H1/2
H1/3
-40
fOUT = 6 GHz (single- x3 (fSPUR = 2 GHz)
–50
Input clock leakage spur
LOGICLK to CLKOUT
ended)
x4 (fSPUR = 1.5
GHz)
H1/4
-54
dBc
dBc
ISPUR
fSPUR = 300 MHz (differential)
–70
Digital Interface (SCK, SDI, CS#, MUXOUT)
VIH
VIL
High-level input voltage
Low-level input voltage
SCK, SDI, CS#
1.4
0
3.3
0.4
IOH = 5 mA
IOH = 0.1 mA
IOL = 5 mA
1.4
2.2
Vcc
Vcc
0.45
42
V
VOH
High-level output voltage
VOL
IIH
Low-level output voltage
High-level input current
Low-level input current
-42
uA
IIL
25
–25
(1) Unless Otherwise Stated, fCLKIN=6 GHz, CLK_MUX=Buffer, All clocks on with OUTx_PWR=7, SYSREFREQ_MODE=1
(2) For powered down mode, if the LOGISYSREFOUT field is set to LVPECL mode AND the LVPECL resistors are placed, this
powerdown current increases to about 40 mA.
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6.6 Timing Requirements
MIN
NOM
MAX
UNIT
Timing Requirements
fSPI
tCE
SPI Read/Write Speed
Clock to enable low time
Clock to data wait time
Clock to data hold time
Clock pulse width high
Clock pulse width low
2
20
MHz
ns
tCS
20
ns
tCH
20
ns
tCWH
tCWL
tCES
tEWH
tCD
100
100
20
ns
ns
Enable to clock setup time
Enable pulse width high
Falling clock edge to data wait time
ns
50
ns
100
ns
6.7 Timing Requirements
SDI
(Write)
A5 to A0,
D15 to D2
R/W
A7
A6
D1
D0
tCS
tCH
SCK
tCE
tCES
tCWH
tCWL
D15 to
D2
MUXOUT
(Readback)
D1
D0
tCD
CS#
tEWH
图6-1. Serial Data Input Timing Diagram
There are several other considerations for writing on the SPI:
• The R/W bit must be set to 0.
• The data on SDI pin is clocked into a shift register on each rising edge on the SCK pin.
• The CS# must be held low for data to be clocked. Device will ignore clock pulses if CS# is held high.
• Recommended SPI settings for this device are CPOL=0 and CPHA=0.
• When SCK and SDI lines are shared between devices, TI recommends to hold the CS# line high on the
device that is not to be clocked.
There are several other considerations for SPI readback:
• The R/W bit must be set to 1.
• The MUXOUT pin will always be low for the address portion of the transaction.
• The data on MUXOUT is clocked out at the falling edge of SCK. In other words, the readback data will be
available at the MUXOUT pin tCD after the clock falling edge.
• The data portion of the transition on the SDI line is always ignored.
• The MUXOUT pin does not automatically tri-state after a readback transaction completes. When sharing the
SPI bus readback pin with other devices, set MUXOUT_EN=0 after all readback transactions from device are
complete to manually tri-state the MUXOUT pin, permitting other devices to control the readback line.
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6.8 Typical Characteristics
If not otherwise, the following conditions can be assumed: Temperature = 25°C, Vcc = 2.5 V, OUTx_PWR=5, CLKIN driven
differentially with 8 dBm at each pin. Signal source used was SMA100B with ultra-low noise option B711.
-110
-150
Source
Input Power = -6 dBm
Input Power = 0 dBm
Input Power = +6 dBm
-115
-120
-125
-130
-135
-140
-145
-150
-155
-160
-165
-170
Source+Device
Calculated Device Noise
Modeled Device Noise
-152
-154
-156
-158
-160
-162
-164
-166
-168
-170
0
2000
4000
6000
8000
10000 12000
1x103
1x104
1x105
1x106
1x107
1x108
Output Frequency (MHz)
Offset (Hz)
Stated input power is applied at each pin.
Noise Floor = –161 dBc/Hz, 1/f Noise = –154 dBc/Hz @ 10
.
.
kHz, Integrates to 28 fs jitter from 100 Hz to 6 GHz offset
图6-2. Buffer Phase Noise Plot at 6 GHz Output
图6-3. Noise Floor in Buffer Mode
-110
-150
-151
-152
-153
-154
-155
-156
-157
-158
-159
-160
-161
-162
-163
-164
-165
-166
-167
-168
-169
-170
Source (12 GHz)
Input Power = -6 dBm
Input Power = 0 dBm
Input Power = 6 dBm
-115
-120
-125
-130
-135
-140
-145
-150
-155
-160
-165
-170
Source (Scaled to 6 GHz)
Source+DUT (Includes Div2)
Device (Raw)
Device (Modeled)
1x102
1x103
1x104
1x105
1x106
1x107
1x108
0
500 1000 1500 2000 2500 3000 3500 4000 4500 5000 5500 6000 6500
Offset (Hz)
Output Frequency (MHz)
Stated input power is applied at each pin.
Noise Floor = –160.5 dBc/Hz, 1/f Noise = –154 dBc/Hz @
.
.
10 kHz, Integrates to 30 fs jitter from 100 Hz to 6 GHz offset
图6-4. Divide by 2 Phase Noise Plot at 6 GHz Output
图6-5. Noise Floor with Divide by 2
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6.8 Typical Characteristics (continued)
If not otherwise, the following conditions can be assumed: Temperature = 25°C, Vcc = 2.5 V, OUTx_PWR=5, CLKIN driven
differentially with 8 dBm at each pin. Signal source used was SMA100B with ultra-low noise option B711.
-110
-150
x1 Multiplier
fOUT = 3200 MHz
-115
-120
-125
-130
-135
-140
-145
-150
-155
-160
-165
-170
x2 Multiplier
x3 Multiplier
x4 Multiplier
-152
-154
-156
-158
-160
-162
-164
-166
-168
-170
fOUT = 4200 MHz
fOUT = 5200 MHz
fOUT = 6400 MHz
-10 -8 -6 -4 -2
0
2
4
6
8
10 12 14 16
1x102
1x103
1x104
1x105
Offset (Hz)
1x106
1x107
1x108
Clock Input Power level (dBm)
图6-6. Multiplier Phase Noise Plot at 6 GHz Output
备注
Input power in graph is differential.
图6-7. Noise Floor in Multiply x2 Mode
-150
-150
-152
-154
-156
-158
-160
-162
-164
-166
-168
-170
TA =- 40C
TA = 25C
TA = 85C
-152
-154
-156
-158
-160
-162
-164
-166
-168
-170
TA = -40C
TA = 25C
TA = 85C
3200 3600 4000 4400 4800 5200 5600 6000 6400
0
2000
4000
6000
8000
10000 12000
Output Frequency (MHz)
Output Frequency (MHz)
图6-9. Noise Floor in x2 Multiplier Mode
图6-8. Noise Floor in Buffer Mode
-150
-151
-152
-153
-154
-155
-156
-157
-158
-159
-160
-161
-162
-163
-164
-165
-166
-167
-168
-169
-170
-150
-152
-154
-156
-158
-160
-162
-164
-166
-168
-170
Divide by 2
Divide by 3
Divide by 4
Divide by 5
Divide by 6
Divide by 7
Divide by 8
TA= -40C
TA= 25C
TA= 85C
0
1000
2000
3000
4000
5000
6000
0
500 1000 1500 2000 2500 3000 3500 4000 4500 5000 5500 6000 6500
Output Frequency (MHz)
Output Frequency (MHz)
图6-10. Noise Floor in Divide by 2 Mode
图6-11. Noise Floor in Divider Mode
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6.8 Typical Characteristics (continued)
If not otherwise, the following conditions can be assumed: Temperature = 25°C, Vcc = 2.5 V, OUTx_PWR=5, CLKIN driven
differentially with 8 dBm at each pin. Signal source used was SMA100B with ultra-low noise option B711.
8
7
8
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
-1
-2
-3
-4
-5
-6
-7
-8
-1
-2
-3
-4
-5
-6
-7
-8
OUTx_PWR = 1
OUTx_PWR = 2
OUTx_PWR = 3
OUTx_PWR = 4
OUTx_PWR = 5
OUTx_PWR = 6
OUTx_PWR = 7
TA = -40C
TA = 25C
TA = 85C
0
2000
4000
6000
8000
10000 12000
0
2000
4000
6000
8000
10000 12000
Frequency (MHz)
Output Frequency (MHz)
Applies to all modes except divider mode with odd divide
(which will have slightly lower power).
CLKOUTx_PWR = 7
.
图6-12. Single-Ended Output Power
图6-13. Single-Ended Output Power
0.8
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
CLKOUT_P
CLKOUT_N
CLKOUT_P
CLKOUT_N
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
0
200
400
600
800
1000
0
100
200
300
400
500
600
700
800
900
1000
Time (ps)
Time (ps)
备注
备注
CLKOUTx_PWR=7
CLKOUTx_PWR=7
图6-14. CLKOUT Waveform at 1 GHz
图6-15. CLKOUT Waveform at 3 GHz
-5
-10
-15
-20
-25
-30
-35
-40
-45
-50
-55
-5
-10
-15
-20
-25
-30
-35
-40
-45
-50
-55
Divide=2
Divide=3
Divide=4
Divide=5
Divide=6
Divide=7
Divide=8
Differential, TA=-40C
Differential, TA=25C
Differential, TA=85C
Single-Ended, TA=-40 C
Single-Ended, TA=25 C
Single-Ended, TA=85 C
0
1000
2000
3000
4000
5000
6000
7000
0
2000
4000
6000
8000
10000
12000
Input Frequency (MHz)
Frequency (MHz)
图6-17. Second Harmonic in Divide Mode (Single-Ended)
图6-16. Second Harmonic in Buffer Mode
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6.8 Typical Characteristics (continued)
If not otherwise, the following conditions can be assumed: Temperature = 25°C, Vcc = 2.5 V, OUTx_PWR=5, CLKIN driven
differentially with 8 dBm at each pin. Signal source used was SMA100B with ultra-low noise option B711.
-5
-5
TA=-40C
TA=25C
-10
-10
TA=85C
-15
-15
-20
-20
-25
-25
-30
-30
-35
-35
-40
-45
-50
-55
-40
-45
-50
-55
TA=-40C
TA=25C
TA=85C
0
500 1000 1500 2000 2500 3000 3500 4000 4500 5000 5500 6000 6500
3200 3600 4000 4400 4800 5200 5600 6000 6400
Output Frequency (MHz)
Output Frequency (MHz)
图6-18. Second Harmonic in Divide by 2 Mode (Single-Ended)
图6-19. Second Harmonic in Multiply X2 Mode (Differential)
-40
-40
-42
-44
-46
-48
-50
-52
-54
-56
-58
-60
-62
-64
-66
-68
MULT = x2
MULT = x3
MULT = x4
-42
-44
-46
-48
-50
-52
-54
-56
-58
-60
-62
-64
-66
-68
-70
-72
-74
-76
-78
-80
TA=-40C, Differential
TA=25C, Differential
TA=85C, Differential
TA=-40C, Single-ended
TA=25C, Single-ended
TA=85C, Single-ended
-70
-72
-74
-76
-78
-80
3200
3600
4000
4400
4800
5200
5600
6000
6400
3200
3600
4000
4400
4800
5200
5600
6000
6400
Output Frequency (MHz)
Output Frequency (MHz)
图6-21. Multiplier 1/2 Sub-Harmonic in X2 Mode
备注
Output is differential.
图6-20. Multiplier Sub-Harmonics (Harmonic Frequency =
Output Frequency / M )
-40
-40
-45
-50
-55
-60
-65
-70
-75
-80
Differential, TA=-40C
Differential, TA=25C
Differential, TA=85C
Single-ended, TA=-40C
Single-ended, TA=25C
Single-ended, TA=85C
-45
-50
-55
-60
-65
-70
-75
-80
Differential, MULT=x2
Differential, MULT=x3
Differential, MULT=x4
Single-ended, MULT=x2
Single-ended, MULT=x3
Single-ended, MULT=x4
3200
3600
4000
4400
4800
5200
5600
6000
6400
3200
3600
4000
4400
4800
5200
5600
6000
6400
Output Frequency (MHz)
Output Frequency (MHz)
图6-22. Multiplier Intermodulation Spur (MULT=2)
图6-23. Multiplier Intermodulation (M+1)/M Spur
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6.8 Typical Characteristics (continued)
If not otherwise, the following conditions can be assumed: Temperature = 25°C, Vcc = 2.5 V, OUTx_PWR=5, CLKIN driven
differentially with 8 dBm at each pin. Signal source used was SMA100B with ultra-low noise option B711.
800
775
750
725
700
675
650
625
600
575
550
525
500
475
450
130
129
128
127
126
125
124
123
122
121
120
119
118
Measurement
Trend Line = 0.06*Temperature + 123.5 ps
Trend Line
Slow (Part 1)
Slow Corner (Part 2)
Slow Corner (Part 3)
Nominal Corner (Part 1)
Nominal Corner (Part 2)
Nominal Corner (Part 3)
Fast Corner (Part 1)
Fast Corner (Part 2)
Fast Corner (Part 3)
-50
-30
-10
10
30
50
70
90
110
130
150
-55
-35
-15
5
25
45
65
85
105
Junction Temperature (C)
Temperature (C)
Measured in power-down mode to make Junction
Over 30 devices and 3 corner lots, propagation delay was
Temperature = Ambient temperature.
.
found to vary 1.1 ps over process and 7 ps overall when the
temperature was held at a constant 25°C.
图6-24. Temperature Sensor Readback
图6-25. Propagation Delay
3.5
5
4.5
4
3.5
3
2.5
2
1.5
1
CLKOUT0 to CLKOUT1
CLKOUT0 to CLKOUT2
CLKOUT0 to CLKOUT3
CLKOUT2 to CLKOUT3
3
2.5
2
1.5
1
0.5
0
-0.5
-1
-1.5
-2
0.5
0
-0.5
-1
-2.5
-3
-3.5
-4
-4.5
-5
Fast Corner, TA=-40C
-1.5
-2
Fast Corner, TA=25C
Fast Corner, TA=85C
Nominal Corner, TA=-40C
Nominal Corner, TA=25C
Nominal Corner, TA=85C
Fast Corner, TA=-40C
-2.5
-3
Fast Corner, TA=25C
Fast Corner, TA=85C
0
1000
2000
3000
4000
5000
6000
7000
8000
0
1000
2000
3000
4000
5000
6000
7000
8000
Output Frequency (MHz)
Output Frequency (MHz)
Main source of skew variation is frequency and measurement
error. Other observed sources of variation include about 3 ps
over process corners and 1.5 ps over temperature.
.
.
.
图6-27. Output to Output Skew Variation for CLKOUT0 to
图6-26. Output to Output Skew
CLKout3
200
0
5
4.5
4
TA=-40C
TA=25C
TA=85C
-200
-400
-600
-800
-1000
-1200
-1400
-1600
3.5
3
2.5
2
1.5
1
TA=-40C
0.5
TA=25C
TA=85C
0
0
50
100
150
200
250
300
350
400
450
500
550
0
50
100
150
200
250
300
350
400
450
500
550
SYSREF Phase Shift Code
SYSREF Phase Shift Code
图6-28. SYSREF Delay vs. Temperature and Code (Fout = 10
图6-29. SYSREF Delta Delay vs. Temperature and Code
GHz)
(Fout=10 GHz)
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6.8 Typical Characteristics (continued)
If not otherwise, the following conditions can be assumed: Temperature = 25°C, Vcc = 2.5 V, OUTx_PWR=5, CLKIN driven
differentially with 8 dBm at each pin. Signal source used was SMA100B with ultra-low noise option B711.
0
-2
-4
-6
-8
180
160
140
120
100
80
CLKIN_P
CLKIN_N
CLKIN_P
CLKIN_N
-10
-12
-14
-16
-18
-20
-22
-24
-26
-28
-30
-32
-34
-36
-38
-40
60
40
20
0
-20
-40
-60
-80
-100
-120
-140
-160
-180
0
2000
4000
6000
8000
10000
12000
0
2000
4000
6000
8000
10000
12000
Frequency (MHz)
Frequency (MHz)
图6-30. CLKIN S11 Magnitude
图6-31. CLKIN S11 Phase
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7 Detailed Description
7.1 Overview
The LMX1204 has four main clock outputs and another LOGICLK output. The main clock outputs are all the
same frequency. This frequency can be the same, divided, or multiplied relative to the input clock. Each of these
clock outputs has programmable power level. The LOGICLK output frequency is independent and typically lower
frequency than the other four main clocks and has programmable output format (CML, LVDS, LVPECL) and
power level.
The SYSREF can be generated by either repeating the input from the SYSREFREQ pins, or internally
generated. There is an internal SYSREF windowing feature that allows the internal timing of the device to be
adjusted to optimize setup/hold times of the SYSREFREQ input with respect to the CLKIN input. This feature
assumes that the delay between the SYSREF edge and the next rising clock edge is consistent. Each of the five
outputs has a corresponding SYSREF output that has individual delays and programmable common mode. For
the LOGISYSREF output, the output format is programmable as CML, LVDS, or LVPECL.
7.1.1 Range of Dividers and Multiplier
There are dividers that allow the main and LOGICLK outputs to be a divided value of the input clock. The main
clock outputs also have a multiplier. In addition to this, dividers are used for SYSREF generation in generator
mode as well as generation of the delay block.
表7-1. Range of Dividers and Multiplier
CATEGORY
RANGE
COMMENTS
Buffer
Divider
Main Clocks
LOGICLK
Odd divides (except 1) do not have 50% duty cycle
x1 Multiplier and Filter mode are the same thing.
2, 3, 4, …8
1,2, 3, 4
Multiplier
PreDivide
1, 2, 4
TotalDivide = PreDivide × Divide
Odd divides (except 1) do not have 50% duty cycle
Divide
Divide
1, 2, 3, …1023
1,2, 4
PreDivide
Pre-divides clock for phase interpolator.
TotalDivide = PreDivide×Divide
Odd divides do not have 50% duty cycle
Divide for
frequency
generation
Divide
2, 3, 4,…4095
SYSREF
Divide for
delay
Divide
2, 4, 8, 16
This divide is set according to the input frequency.
generation
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7.2 Functional Block Diagram
CLK_MULT_CAL
CLKOUT0
CLK_MULT
CLKIN
xM
SYSREFOUT0
ꢀꢁ
SYSREFOUT0_DELAY_I
SYSREFOUT0_DELAY_Q
SYSREFOUT0_DELAY_PHASE
SYSREFOUT0_DELAY_SCALE
SYSREF
Windowing
and Capture
CLKOUT1
CLK_DIV
SYSREFREQ
VCC_CLKIN
÷2,3,..,8
ꢀ
SYSREFOUT1
SYSREFOUT1_DELAY_I
SYSREFOUT1_DELAY_Q
SYSREFOUT1_DELAY_PHASE
SYSREFOUT1_DELAY_SCALE
VCC01
VCC23
SYSREF_DELAY_DIV
CLKOUT2
VBIAS01
VBIAS23
÷2,4,8,16
GND (x6)
ꢀ!
SYSREFOUT2
SYSREF_PULSE_COUNT
SYSREFOUT2_DELAY_I
SYSREFOUT2_DELAY_Q
SYSREFOUT2_DELAY_PHASE
SYSREFOUT2_DELAY_SCALE
Pulser
SCK
SDI
÷1,2,4
÷2,3,..4095
Digital
Control
CLKOUT3
CS#
MUXOUT
ꢀ"
SYSREFOUT3
SYSREFOUT3_DELAY_I
SYSREFOUT3_DELAY_Q
SYSREFOUT3_DELAY_PHASE
SYSREFOUT3_DELAY_SCALE
÷1,2,4
÷1,2,3,...1023
LOGICLKOUT
LOGICLK_DIV_PRE
LOGICLK_DIV
LOGICLK_DIV_BYP
ꢀ#
LOGISYSREFOUT
LOGISYSREFOUT_DELAY_I
LOGISYSREFOUT_DELAY_Q
LOGISYSREFOUT_DELAY_PHASE
LOGISYSREFOUT_DELAY_SCALE
图7-1. Functional Block Diagram
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7.3 Feature Description
7.3.1 Power On Reset
When the device is powered up, the power on reset (POR) resets all registers to a default state as well as resets
all state machines and dividers. For the power on reset state, all SYSREF outputs are disabled and all the
dividers are bypassed; the device performs as a 4-output buffer. One should wait 100 µs after the power supply
rails before programming other registers to ensure that this RESET is finished. If the power on reset happens
when there is no device clock present, it will function properly, however, the current will change once an input
clock is presented.
It is also possible and generally good practice to do a software power on reset by writing RESET=1 in the SPI
bus. The RESET bit will self-clear once any other register is written to. The SPI bus can be used to override
these states to the desired settings.
Although the device does have an automatic power on reset, it can be impacted by different ramp rates on the
different supply pins, especially in the presence of a strong input clock signal.. It is therefore recommended to do
a software reset after POR. This can be done by programming RESET=1. The reset bit can be cleared by
programming any other register or setting RESET back to zero. Even at maximum allowed SPI bus speed, the
software reset event always completes before the subsequent SPI write.
7.3.2 Temperature Sensor
The junction temperature can be read back for purposes such as characterization or to make adjustments based
on temperature. Such adjustments might include adjusting CLKOUTx_PWR to make the output power more
stable or using external or digital delays to compensate for changes in propagation delay over temperature.
The junction temperature is typically higher than the ambient temperature due to power dissipation from the
outputs and other functions on the device. 方程式 1 shows the relationship between the code read back and the
junction temperature.
Temperature = 0.65 × Code –351
(1)
方程式 1 is based on a best-fit line created from three devices from slow, nominal, and fast corner lots (9 parts
total),. The worst-case variation of the actual temperature from the temperature predicted by the best-fit line was
13°C, which works out to 20 codes.
7.3.3 Clock Outputs
This device has four main output clocks which share a common frequency. This does not include the additional
lower frequency LOGICLK output.
7.3.3.1 Clock Output Buffers
The output buffers have a format that is open collector with an integrated pullup resistor, similar to CML.
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VCC
50 ꢀ
CLKOUTx
CLKOUTx_PWR
图7-2. CLKOUT Output Buffer
The output buffers can be enabled with CLKOUTx_EN bits. In addition to this, their output power can be
individually set with the CLKOUTx_PWR field. However, these fields only control the output buffer, not the
internal channel path that drives this buffer, the SYSREF generator, or the SYSREF output. To power down the
entire path, disable the CHx_EN bit.
表7-2. Clock Output Power
INTERNAL CHANNEL
CHx_EN
CLKOUTx_EN
CLKOUTx_PWR
OUTPUT BUFFER
PATH
0
Powered Down
Don't Care
0
Don't Care
Powered Down
Powered Down
Minimum
Don't Care
0
1
1
Powered Up
1
...
7
Maximum
7.3.3.2 Clock MUX
The four main clocks must be the same frequency, but this frequency can be bypassed, multiplied, or divided.
This is determined by the CLK_MUX word.
表7-3. Clock MUX
CLK_MUX
OPTION
VALUES SUPPORTED
÷1 (bypass)
0
1
2
Buffer Mode
Divider Mode
Multiplier Mode
÷2, 3, 4, 5, 6, 7, and 8
x1 (filter mode), x2, x3, x4
7.3.3.3 Clock Divider
Setting the CLK_MUX to Divided allows a divide value of 2, 3, 4, 5, 6, 7, and 8. This is set by the CLK_DIV word.
When using the clock divider, any change to the input frequency requires the CLK_DIV_RST bit to be toggled
from 1 to 0.
表7-4. Clock Divider
CLK_DIV
DIVIDE
DUTY CYCLE
0
1
2
Reserved
n/a
2
3
50%
33%
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表7-4. Clock Divider (continued)
CLK_DIV
DIVIDE
DUTY CYCLE
50%
3
4
5
6
7
4
5
6
7
8
40%
50%
43%
50%
7.3.3.4 Clock Multiplier and Filter Modes
General Information about the Clock Multiplier
The clock multiplier is can be used to multiply up the input clock frequency by a factor of x1, x2, x3, or x4. The
multiply value is set by the CLK_MULT field. As the multiplier is PLL-based and includes an integrated VCO, it
has a state machine clock, requires calibration, has a lock detect feature, and can be used as a tunable filter.
Note that if the multiplier is not being used, there is no need for the state machine clock or the lock detect
feature.
State Machine Clock for the Clock Multiplier
The state machine clock frequency ,fSMCLK, is derived by dividing down the input clock frequency by a
programmed divider value. The state machine clock is also necessary for the multiplier calibration and lock
detect. If there are concerns about the state machine clock creating spurs, then it can be shut off provided that
the multiplier calibration is not running and the lock detect feature is not being used.
Calibration for the Clock Multiplier
For optimal phase noise, the VCO in the multiplier divides up the frequency range into many different bands and
cores and has optimized amplitude settings for each one of these. For this reason, upon initial use, or whenever
the frequency is changed, a calibration routine needs to be run in order to determine the correct core, frequency
band, and amplitude setting. Calibration is performed by programming the R0 register with a valid input signal.
Increasing the speed of the state machine clock speeds up the multiplier calibration time. To ensure reliable
multiplier calibration, the state machine clock frequency needs to be at least twice the SPI write speed, but no
more than 30 MHz. Whenever the CLK_MUX mode is changed or the multiplier is calibrated for the first time, the
calibration time will be substantially longer, on the order of 5 ms.
Using the x1 Clock Multiplier as a Filter
As the multiplier is PLL based, it acts as a programmable filter that attenuates noise, spurs, harmonics, and sub-
harmonics that are outside the PLL loop bandwidth (about 10 MHz). In some situations, one may want to filter
the clock without multiplying this up. Filter mode (x1 multiplier) allows one to use the clock multiplier as a tunable
filter with 10 MHz bandwidth that has lower additive noise than the higher multiply values. In this filter mode,
spurs of lower offsets tend to get amplified by the multiplier, so it is typically most effective for spurs that are 100
MHz or farther offset from the carrier where the multiplier PLL loop filter is able to roll these spurs off. Note that
filter mode is different than buffer mode in that it filters the input frequency, but adds more close in phase noise.
Lock Detect for the Clock Multiplier
The lock detect status of the multiplier can be read back through the rb_LD field or from the MUXOUT pin. The
state machine clock must be running for the lock detect to work properly. Lock detect is not supported in x1
(filter) mode.
7.3.3.4.1 State Machine Clock
If not using the clock multiplier, the state machine clock should be disabled by setting SMCLK_EN=0 to minimize
crosstalk and spurs. However, when using the clock multiplier, the state machine clock is required to run the
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calibration engine when the frequency is changed and also used to have the lock detect continuously monitor if
the PLL-based clock multiplier is in lock. The state machine clock must be less than 30 MHz. Consult the register
map document for more details.
7.3.4 LOGICLK Output
The LOGICLK output can be used to drive devices using lower frequency clocks, such as FPGAs. It has
programmable output format and a corresponding SYSREF output.
7.3.4.1 LOGICLK Output Format
The LOGICLK output format can be programmed to LVDS, LVPECL, and CML modes. Depending on the format,
the common mode may be programmable or external components may be required (see 表7-5).
表7-5. LOGICLK Formats and Properties
EXTERNAL COMPONENTS
LOGICLKOUT_FMT
FORMAT
OUTPUT LEVEL
COMMON MODE
REQUIRED
Programmable through
LOGICLKOUT_VCM
0
1
LVDS
None
Fixed
Fixed
LVPECL
Emitter Resistors
Not programmable
Pullup Resistors
Programmable through
LOGICLKOUT_PWR
2
3
CML
Not programmable
50 Ω to VCC
Invalid
7.3.4.2 LOGICLK_DIV_PRE and LOGICLK_DIV Dividers
The LOGICLK_DIV_PRE divider and LOGICLK_DIV dividers are used for the LOGICLK output. The
LOGICLK_DIV_PRE divider is necessary to divide the frequency down to ensure that the input to the
LOGICLK_DIV divider is 3.2 GHz or less. When LOGICLK_DIV is not even and not bypassed, the duty cycle will
not be 50%. Both the LOGICLK dividers are synchronized by the SYNC feature, which allows synchronization
across multiple devices.
表7-6. Minimum N-Divider Restrictions
fCLKIN (MHz)
LOGICLK_DIV_PRE
LOGICLK_DIV
TOTAL DIVIDE RANGE
[1, 2, ...1023]
[2, 4, ... 2046]
[4, 8, 4092]
÷1,2,4
f
CLKIN ≤3.2 GHz
÷1,2 ,3 ,…1023
[4, ... 2046]
[4, 8, 4092]
÷2,4
÷4
3.2 GHz < fCLKIN≤6.4 GHz
÷1, 2 ,3 ,…1023
1, 2, 3 ,…1023
fCLKIN > 6.4 GHz
[8, 4092]
7.3.5 SYSREF
SYSREF allows a low frequency JESD204B/C compliant signal to be produced that is reclocked to a main or
LOGICLK output. The delays between the CLKOUT and SYSREF outputs are adjustable with software. The
SYSREF output can be configured as a generator using the internal SYSREF divider, or as a repeater
duplicating the signal on the SYSREFREQ pins. The SYSREF generator for both the main clocks and the
LOGICLK output are the same.
7.3.5.1 SYSREF Output Buffers
7.3.5.1.1 SYSREF Output Buffers for Main Clocks (SYSREFOUT)
The SYSREF outputs within the clock output channels have the same output buffer structure as the clock output
buffer, with the addition of circuitry to adjust the common-mode voltage. The SYSREF outputs are CML outputs
with a common-mode voltage that can be adjusted with the SYSREFOUTx_VCM field, and the output level that
can be programmed with the SYSREFOUTx_PWR field. This is to allow DC coupling. Note that the CLKOUT
outputs do not have adjustable common-mode voltage and must be AC coupled; this is for optimal noise
performance.
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VCC
SYSREFOUTx_VCM
Bias Adjust
50
SYSREFOUTx
SYSREFOUTx_PWR
图7-3. SYSREF Output Buffer
The common-mode voltage and output power are interrelated and can be simulated assuming a 100-Ω
differential load and no DC path to ground. The common mode voltage and output are interrelated as shown in
表7-7. Realize that for reasons of long-term reliability reasons it is required that VCM - VOD/2 ≥0.5 V.
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表7-7. Single-Ended Voltage (VOD) and Common Mode Voltage (VCM
)
Check:
SYSREFOUT_PWR
SYSREFOUT_VCM
VOD
VCM - VOL/2 ≥0.5 V. ?
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0.22
0.22
0.22
0.22
0.22
0.23
0.23
0.23
0.27
0.27
0.27
0.27
0.28
0.28
0.28
0.29
0.32
0.32
0.32
0.33
0.33
0.33
0.34
0.34
0.36
0.37
0.37
0.38
0.38
0.38
0.39
0.39
0.40
0.41
0.42
0.42
0.43
0.44
0.44
0.45
1.22
1.34
1.48
1.63
1.77
1.91
2.06
2.20
0.94
1.08
1.25
1.44
1.61
1.78
1.96
2.13
0.70
0.83
1.03
1.25
1.45
1.64
1.86
2.06
0.55
0.66
0.82
1.07
1.30
1.52
1.77
2.00
0.44
0.53
0.68
0.89
1.15
1.39
1.67
1.93
0
1
2
3
4
Valid State
Invalid State
Valid State
Invalid State
Valid State
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表7-7. Single-Ended Voltage (VOD) and Common Mode Voltage (VCM) (continued)
Check:
VCM - VOL/2 ≥0.5 V. ?
SYSREFOUT_PWR
SYSREFOUT_VCM
VOD
VCM
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0.41
0.44
0.46
0.47
0.48
0.49
0.49
0.50
0.42
0.45
0.50
0.52
0.53
0.54
0.54
0.55
0.42
0.46
0.51
0.56
0.57
0.58
0.60
0.61
0.40
0.45
0.57
0.76
1.00
1.27
1.58
1.87
0.38
0.42
0.49
0.66
0.86
1.15
1.49
1.81
0.36
0.40
0.45
0.58
0.77
1.03
1.40
1.75
Invalid State
Valid State
5
6
7
Invalid State
Valid State
Invalid State
Valid State
7.3.5.1.2 SYSREF Output Buffer for LOGICLK
The LOGISYSREFOUT output supports the three formats of LVDS, LVPECL, and CML. The
LOGISYSREFOUT_EN enables the output buffer and LOGISYSREF_FMT sets the format. LVDS mode allows
programmable common mode, LVPECL and CML require external components, and CML allows programmable
output power (see 表7-8).
表7-8. LOGISYSREFOUT Output Buffer Configuration
EXTERNAL
TERMINIATION
REQUIRED
LOGISYSREFOUT_E
N
LOGISYSREF
FORMAT
OUTPUT COMMON
MODE
LOGISYSREF_FMT
OUTPUT POWER
0
Powered Down
None
Programmable with
LOGISYSREF_VCM
0
1
LVDS
Fixed
Fixed
LVPECL
Emitter Resistors
Fixed
LOGISYSREF_VCM
has no impact, but
this changes with
1
Pullup resistors
Controlled by
LOGISYSREF_PWR
2
3
CML
50 Ω to VCC
LOGISYSREF_PWR.
Reserved
7.3.5.2 SYSREF Frequency and Delay Generation
The SYSREF circuitry can produce an output signal that is synchronized to fCLKIN. This output can be a single
pulse, series of pulses, or a continuous stream of pulses. In generator mode, the SYSREF_DIV_PRE and
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SYSREF_DIV values are used to divide the CLKIN frequency to a lower frequency that is reclocked to the
output. In repeater mode, this signal is instead input at the SYSREFREQ pins. For each of the outputs, there is
an independent delay control.
表7-9. SYSREF Modes
SYSREF_MODE
DESCRIPTION
Generator Mode (Continuous)
Internal generator creates a continuous stream of SYSREF pulses. The SYSREFREQ pins or the
SYSREFREQ_SPI field can be used to gate the SYSREF divider from the channels for improved noise
isolation without disrupting the synchronization of the SYSREF dividers. The SYSREFREQ pins or the
SYSREFREQ_SPI field must be high for a SYSREF output to come out.
0
Generator Mode (Pulser)
Internal generator generates a burst of 1 - 16 pulses that is set by SYSREF_PULSE_COUNT that occurs after
1
2
a rising edge on the SYSREFREQ pins
Repeater Mode
SYSREFREQ pins are reclocked to clock outputs and then delayed in accordance to the
SYSREF_DELAY_BYPASS field before being sent to the SYSREFOUT outputs.
SYSREFOUTx_DELAY_I
SYSREFOUTx_DELAY_Q
SYSREFOUTx_PHASE
SYSREFOUTx_SCALE
SYSREF_DELAY_DIV
fINTERPOLATOR
Programmable
Delay
Re-clocking
Circuit
÷2,4,8,16
CLKIN_P
CLKIN_N
SYSREFOUTx_P
SYSREFOUTx_N
SYSREF_DIV_PRE
÷1, 2, 4
SYSREF_DIV
÷2, … 4095
SysRef Pulse Generator
SYSREF_PULSE_COUNT
SYSREFREQ_P
SYSREFREQ_N
SYSREF_DELAY_BYPASS
SYSREF_MODE
图7-4. SYSREF Generator Diagram
For the frequency of the SYSREF output in generator mode, the SYSREF_DIV_PRE divider is necessary to
ensure that the input of the SYSREF_DIV divider is not more than 3.2 GHz.
表7-10. SYSREF_DIV_PRE Setup
fCLKIN
SYSREF_DIV_PRE
÷1, 2, or 4
÷2 or 4
TOTAL SYSREF DIVIDE RANGE
÷2,3,4,...16380
3.2 GHz or Less
3.2 GHz < fCLKIN ≤6.4 GHz
fCLKIN > 6.4 GHz
÷4,6,8, …16380
÷4
÷8,12,16, …16380
For the delay, the input clock frequency is divided by SYSREF_DELAY_DIV to generate fINTERPOLATOR. This has
a restricted range as shown in 表 7-11. Note also that when SYSREF_DELAY_BYPASS=0 or 2 (delaygen
engaged for generator mode), and SYSREF_MODE = 0 or 1 (a generator mode) the SYSREF output frequency
must be a multiple of the phase interpolator frequency.
fINTERPOLATOR % fSYSREF = 0.
表7-11. SYSREF Delay Setup
fCLKIN
SYSREF_DELAY_DIV
SYSREFx_DELAY_SCALE
fINTERPOLATOR
0.4 to 0.8 GHz
0.4 to 0.8 GHz
0.4 to 0.8 GHz
0.4 to 0.8 GHz
0.2 to 0.4 GHz
16
8
0
0
0
0
1
6.4 GHz < fCLKIN ≤12.8GHz
3.2 GHz < fCLKIN ≤6.4 GHz
1.6 GHz < fCLKIN ≤3.2 GHz
0.8 GHz < fCLKIN ≤1.6 GHz
0.4 GHz < fCLKIN ≤0.8 GHz
4
2
2
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表7-11. SYSREF Delay Setup (continued)
fCLKIN
0.3 GHz < fCLKIN ≤0.4 GHz
SYSREF_DELAY_DIV
SYSREFx_DELAY_SCALE
fINTERPOLATOR
2
2
0.15 to 0.2 GHz
The maximum delay is equal to the phase interpolator period and there are 4x127 = 508 different delay steps.
Use 方程式2 to calculate the size of each step.
DelayStepSize = 1/( fINTERPOLATOR × 508) = SYSREF_DELAY_DIV/( fCLKIN × 508)
(2)
(3)
Use 方程式3 to calculate the total delay.
TotalDelay=DelayStepSize × StepNumber
表7-12 shows the number of steps for each delay.
表7-12. Calculation of StepNumber
SYSREFx_DELAY_PHASE
STEPNUMBER
3
2
0
1
127 - SYSREFx_DELAY_I
254 - SYSREFx_DELAY_Q
381 - SYSREFx_DELAY_I
508 - SYSREFx_DELAY_Q
The SYSREF_DELAY_BYPASS field selects between the delay generator output and the repeater mode bypass
signal. When SYSREF_MODE is set to continuous or pulser mode, TI recommends to set
SYSREF_DELAY_BYPASS to generator mode. If SYSREF_MODE is set to repeater mode, TI recommends to
set SYSREF_DELAY_BYPASS to bypass mode.
7.3.5.3 SYSREFREQ pins and SYSREFREQ_SPI Field
The SYSREFREQ pins are multipurpose and can be used for SYNC, SYSREF requests, and SYSREF
Windowing. These pins can be DC or AC coupled and have dual 50-Ω, single-ended termination with
programmable common-mode support.
In addition to these pins, the SYSREFREQ_SPI field can be set to 1 to emulate the same effect as forcing these
pins high, simplifying hardware in some cases.
7.3.5.3.1 SYSREFREQ Pins Common-Mode Voltage
The SYSREFREQ_P and SYSREFREQ_N pins can be driven either AC or DC coupled. When driven AC
coupled, the common-mode voltage can be adjusted with the SRREQ_VCM bit.
表7-13. SYSREFREQ Pin Common-Mode Voltage
SRREQ_VCM
COMMON-MODE VOLTAGE
0
1
2
3
1.3 V AC-coupled
1.1 V AC-coupled
1.5 V AC-coupled
No Bias (DC Coupled)
7.3.5.3.2 SYSREFREQ Pin Windowing Feature
The SYSREF windowing can be used to internally calibrate the timing between the SYSREFREQ and CLKIN
pins in order to optimize setup and hold timing and trim out any mismatches between SYSREFREQ and CLKIN
paths. This feature requires that the timing from the SYSREFREQ rising edge to the CLKIN rising edge is
consistent. The timing from the SYSREFREQ rising edge to the CLKIN rising edges can be tracked with the
rb_CLKPOS field. Once the timing to the rising edge of the CLKIN pin is found, then the SYSREFREQ rising
edge can be internally adjusted with the SYSREFREQ_DELAY_STEP and SYSREF_DELAY_STEPSIZE fields
to optimize setup/hold times.
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tSYSREFREQ_DELAY_STEPSIZE
CLKIN
10001100000000000000000110000001
rb_CLKPOS[0:31] (bit order reversed LSB rst, MSB last)
t
tO
set
SYSREFREQ
Pin Input
SYSREFREQ_DELAY
_STEP=13
Adjusted
SYSREFREQ
图7-5. SYSREFREQ Internal Timing Adjustment
General Procedure
• While programming the windowing feature for the first time, SYSREFREQ needs to be low.
• Set CLKPOS_CAPTURE_EN=1
• Set SYSREFREQ_DELAY_STEPSIZE according to 表7-14. If the input frequency is at the boundary of two
possible settings, it is recommended to choose the lowest one for optimal temperature stability.
• Program SYSREFREQ_CLR=1 and then SYSREFREQ_CLR=0
• Send a rising edge to the SYSREFREQ pin(s)
• Read back position with rb_CLKPOS field to determine timing from the SYSREFREQ rising edge to the next
CLKIN rising edge. The number of 0's between the LSB '1' bit and the first series of '11' can be multiplied by
the delay determined by SYSREFREQ_DELAY_STEPSIZE to determine the approximate timing to the first
rising clock edge.
• Program SYSREFREQ_DELAY_STEP field in delay steps to maximize margin between left and right rising
edges of CLKIN
表7-14. SYSREFREQ_DELAY_STEPSIZE
RECOMMENDED
SYSREFREQ_DELAY_STEPSIZE
INPUT FREQUENCY
DELAY (ps)
0
1
2
3
28
15
11
8
1.4GHz < fCLKIN ≤2.7 GHz
2.4 GHz < fCLKIN ≤4.7 GHz
3.1 GHz < fCLKIN ≤5.7 GHz
f
CLKIN ≥4.5 GHz
For glitch-free output
• Keep the same state for the SYSREFREQ pin when switching from request mode to windowing mode and
back to request mode. For example, if the SYSREFREQ pin is high (or low) when windowing mode starts,
make sure the pin state is high (or low) again after windowing mode ends before programing
CLKPOS_CAPTURE_EN.
• The SYSREFREQ pin must be set low when switching from or to SYNC mode.
Other pointers with SYSREF windowing
• The SYSREFREQ pins need to be held high for a minimum time of 3/fCLKIN + 1.6 ns and only after this time
rb_CLKPOS field is valid.
• If the user infers multiple valid SYSREFREQ_DELAY_STEP values from rb_CLKPOS registers to avoid
setup-hold violations, choosing the lowest valid SYSREFREQ_DELAY_STEP is recommended to minimize
variation over temperature.
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If using SYNC feature
• Only one SYSREFREQ pin rising edge is permitted per 75 input clock cycles
• SYSREFREQ has to stay high for >6 clock cycles
7.3.5.4 SYNC Feature
The SYNC feature allows the user to synchronize the CLK_DIV, LOGICLK_DIV, LOGICLK_DIV_PRE,
SYSREF_DIV, SYSREF_DIV_PRE, and SYSREF_DELAY_DIV dividers so that the phase offset can be made
consistent between power cycles. This allows multiple devices to be synchronized. This synchronization dividers
can only be done through the SYSREFREQ pin, not the software.
7.4 Device Functional Modes
表 7-15 shows the different modes for the device. The CLK_MUX field allows the user to configure the device as
a buffer, divider, or multiplier. The SYSREF can also be enabled as well for applications that need this feature.
表7-15. Device Configurations
CLK_MUX
CLK_MULT
SYSREF_EN
FUNCTIONAL MODE
Buffer
0
1
0
1
0
1
0
1
1
x
Buffer w/SYSREF
Divider
2
3
x
1
Divider w/SYSREF
Filter
Filter w/SYSREF
Multiplier
2,3,4
Multiplier w/SYSREF
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8 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Applications Information
8.1.1 Current Consumption
The current consumption varies as a function of the setup condition. By adding up all the block currents shown in
表8-1, a reasonable estimate of the current for any setup condition can be obtained.
表8-1. Current Consumption per Block
BLOCK
Device Core
Core
CONDITION (s)
CURRENT (mA)
CLK_MUX = Buffer Mode
CLK_MUX = Divide Mode
294
260
SMCLK_EN=0
SMCLK_EN=1
540
CLK_MUX = Multiply Mode
560
SYSREF_EN=1
80
Generator Mode (SYSREF_MODE=0,1)
Repeater Mode (SYSREF_MODE=2)
53
Delay Generator
SYSREF
SYNC
40
SYSREF_MODE=0,1
113
Windowing Circuitry
Windowing
Windowing Circuitry
SYSREF Pulser
(CLKPOS_CAPTURE_EN=1)
SYSREF_MODE=2
0
SYSREF_MODE=1
SYSREF_EN=0
7
25
CLKOUT
(Per active clock
Core
Delay Not Used
Delay Used
30
40
SYSREF_EN = 1
channel)
Output Buffer
Core
CHx_EN = CLKOUTx_EN=1
4+6*CLKOUTx_PWR
74 +
SYSREFOUT_EN = CHx_EN = 1
SYSREFOUT_EN = CHx_EN = 1
SYSREFOUTx_PWR*5
SYSREFOUT
(SYSREFOUTx_PWR and SYSREFOUTx_VCM can
interact which would make the output buffer current lower
than the formula predicts in some cases)
2*SYSREFOUTx_PWR +
2*SYSREFOUTx_VCM
Output Buffer
SYSREF_EN=0
SYSREF_EN=1
49
Core
59
LOGIC_EN=1
LOGICLKOUT_EN=1
LOGICLKOUT
16+1*LOGICLKOUT_PWR
CML(RP=50Ω)
Output Buffer
Core
LVDS
12
LVPECL
30
SYSREF_EN=0
SYSREF_EN=1
CML(RP=50Ω)
LVDS
0
LOGIC_EN=1
LOGISYSREFOUT_EN=1
55
LOGISYSREFOUT
16+1*LOGICLKOUT_PWR
LOGIC_EN=1
LOGISYSREFOUT_EN=1
Output Buffer
12
30
LVPECL
If all the output clocks, LOGICLK, multiplier, and multiplier are all enabled, it is possible for this device to
consume a significant amount of current. In order to mitigate this, It is recommended to turn off the SYSREF
output buffers when not actively sending SYSREF pulses to conserve current.
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8.1.2 Treatment of Unused Pins
In many cases, not all pins will be needed. 表8-2 gives recommendation on handling of these unused pins.
表8-2. Treatment of Unused or Partially Used Pins
PIN(S)
TREATMENT
These pins must always be connected to the supply. If the block that this powers (as implied by the pin
name) is not used, then the bypassing can be minimized or eliminated.
All Vcc Pins
If driving single-ended, the complimentary input should have a AC-coupling capacitor and 50 Ω to ground. If
using continuous SYSREF Generator mode, these pins can be either used to turn the output buffers on and
off or they can be left floating. If left floating, use SRREQ_SPI to control the output gating. If not using
SYSREF at all, pins can be left open.
SYSREFREQ
CLKIN Complementary Input
BIAS01 and BIAS23
If driving single-ended, the complementary input should have a AC-coupling capacitor and 50 Ω to ground.
These pins can be left open if multiplier is not used.
CLKOUT
SYSREFOUT
These pins can be left open if not used.
LOGICLKOUT
LOGISYSREFOUT
8.2 Typical Application
For this application, the additive noise impact of using the LMX1204 as a x2 multiplier is exported when added to
the LMX2820 3-GHz output clock. This particular setup used a single-ended clock to drive the LMX1204 for the
sake of simplicity of hooking up two EVMs together, but driving it differentially is generally recommended.
0.01
F
RFOUTAP
RFOUTAN
CLKIN_P
CLKIN_N
3 GHz
0.1
0.01
50
F
100 MHz
+10
dBm
Limiter
OSCIN
F
0.1
F
0.1 F
LMX2820
LMX1204
50
Wenzel
0.01
0.01
F
Oscillator
To Phase
Noise Analyzer
CLKOUT0_P
CLKOUT0_N
CPOUT
VTUNE
6 GHz
18.2
OSCIN#
0.1
F
50
F
68 nF
68.1
470 pF
50
2.2 nF
Bandwidth = 439 kHz
图8-1. Typical Application Schematic
8.2.1 Design Requirements
表8-3 shows the design parameters for this example.
If not all outputs or SYSREF are used, TI recommends to compress the layout to minimize trace lengths,
especially that of the input trace.
表8-3. Design Parameters
PARAMETER
VALUE
100 MHz
3 GHz
3 GHz
6 GHz
x2
LMX2820 Input Frequency
LMX2820 Output Frequency
LMX1204 Input Clock Frequency
LMX1204 Output Clock Frequency
Multiplier Value
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8.2.2 Detailed Design Procedure
In this example, a 3-GHz input clock is being multiplied up to a 6-GHz input clock. The external components do
not change that much based on internal configuration. The TICS Pro software is very useful in calculating the
necessary register values and configuring the device.
图8-2. LMX1204 TICS Pro Setup
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8.2.3 Application Curve
In 图 8-3, the total plot is the sum of the noise of the LMX1204 multiplier noise and the LMX2820 3-GHz output
(scaled to 6 GHz by adding 6 dB). Note that the LMX1204 does increase the phase noise in the 1-MHz to 20-
MHz range, but beyond 20 MHz, the input multiplier actually filters the output noise floor.
-80
LMX2820 Noise Scaled to 6 GHz
LMX1204 Multiplier Noise
LMX2820 + LMX1204
-100
-120
-140
-160
1x102
1x103
1x104
1x105
1x106
1x107
1x108
Offset (Hz)
图8-3. Multiplier Output Frequency
8.3 Power Supply Recommendations
This devices uses a 2.5-V supply for the whole device. A direct connection to a switching power supply will likely
result in unwanted spurs at the output. Bypassing can be done individually at all the power pins. TI recommends
placing smaller capacitors with higher frequency of minimum impedance on the same layer as the device, as
close to the pins as possible. Since the frequencies of nearly all signals in the device are 100 MHz or greater,
larger value bypass capacitors with low frequency of minimum impedance are only used for internal LDO
stability, and their distance to the device (and the loop inductance of the bypass path) can be larger. The supply
pins for the clocks and the LOGICLK should be isolated with a small resistor or ferrite bead if both are being
used simultaneously. See the Pin Configuration and Functions section for additional recommendations for each
pin.
备注
This device has minimal PSRR due to the low operating voltage and internal filtering by LDOs;
it is important that this device is connected to a low noise supply that does not have excessive
spurious noise.
8.4 Layout
8.4.1 Layout Guidelines
• If using an output single-ended, terminate the complementary side so that the impedance as seen looking out
from this is similar to side that is used.
• GND pins on the outer perimeter of the package may be routed on the package back to the DAP.
• Minimize the length of the CLKIN trace for optimal phase noise. Poor matching may degrade the noise floor.
• Ensure the DAP on device is well-grounded with many vias.
• Use a low loss dielectric material, such as Rogers 4350B, for optimal output power.
• Be aware that if all the outputs and SYSREF are operating, the current consumption may be high enough to
exceed the recommended internal junction temperature of 125°C; a heat sink may be necessary.
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8.4.2 Layout Example
AC coupling capacitors
required on all CLKOUT
outputs, but can be
placed far away
Power supply circuitry
can be placed farther
away from the chip
LMX1204
Di eren al Output
Rou ng
Large and small shunt
capacitors. Large
capacitor is not always
necessary. Smaller
capacitor needs to be
as close to the chip as
possible for high
frequency noise.
图8-4. Layout Example
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9 Device and Documentation Support
9.1 Device Support
TI offers an extensive line of development tools and software to simulate the device performance and program
the device.
表9-1. Development Tools and Software
TOOL
TYPE
DESCRIPTION
Simulates phase noise in all modes and filter
transfer function in multiplier mode.
PLLatinum™ Sim
Software
Programs the device with a user-friendly GUI
with interactive feedback and hex register
export.
TICS Pro
Software
Register Map Description
Document
Detailed description of all registers.
9.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
9.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
9.4 Trademarks
PLLatinum™ and TI E2E™ are trademarks of Texas Instruments.
所有商标均为其各自所有者的财产。
9.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
9.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OUTLINE
RHA0040C
VQFN - 1 mm max height
S
C
A
L
E
2
.
2
0
0
PLASTIC QUAD FLATPACK - NO LEAD
6.1
5.9
B
A
0.5
0.3
PIN 1 INDEX AREA
6.1
5.9
0.3
0.2
DETAIL
OPTIONAL TERMINAL
TYPICAL
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
4.7 0.1
2X 4.5
(0.2) TYP
11
20
36X 0.5
10
21
EXPOSED
THERMAL PAD
2X
41
SYMM
4.5
SEE TERMINAL
DETAIL
1
30
0.3
0.2
40X
40
PIN 1 ID
(OPTIONAL)
31
0.1
0.05
C A B
SYMM
0.5
0.3
40X
4219053/A 09/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
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EXAMPLE BOARD LAYOUT
RHA0040C
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
4.7)
SYMM
40
31
40X (0.6)
1
30
40X (0.25)
4X
(1.35)
(
0.2) TYP
VIA
(0.75)
TYP
41
(5.8)
SYMM
4X
(1.5)
36X (0.5)
10
21
(R0.05)
TYP
11
(0.75) TYP
20
4X (1.5)
(5.8)
4X (1.35)
LAND PATTERN EXAMPLE
SCALE:12X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4219053/A 09/2016
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
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EXAMPLE STENCIL DESIGN
RHA0040C
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(1.5) TYP
9X ( 1.3)
(R0.05) TYP
40
31
40X (0.6)
1
30
40X (0.25)
41
(1.5)
TYP
SYMM
(5.8)
36X (0.5)
10
21
METAL
TYP
11
20
SYMM
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 41:
69% PRINTED SOLDER COVERAGE BY AREA
SCALE:15X
4219053/A 09/2016
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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PACKAGE OPTION ADDENDUM
www.ti.com
21-Dec-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMX1204RHAR
LMX1204RHAT
ACTIVE
ACTIVE
VQFN
VQFN
RHA
RHA
40
40
2500 RoHS & Green
250 RoHS & Green
NIPDAUAG
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
LMX1204
LMX1204
Samples
Samples
NIPDAUAG
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
21-Dec-2022
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Sep-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMX1204RHAR
LMX1204RHAT
VQFN
VQFN
RHA
RHA
40
40
2500
250
330.0
180.0
16.4
16.4
6.3
6.3
6.3
6.3
1.1
1.1
12.0
12.0
16.0
16.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Sep-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LMX1204RHAR
LMX1204RHAT
VQFN
VQFN
RHA
RHA
40
40
2500
250
367.0
210.0
367.0
185.0
38.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RHA 40
6 x 6, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225870/A
www.ti.com
PACKAGE OUTLINE
RHA0040C
VQFN - 1 mm max height
S
C
A
L
E
2
.
2
0
0
PLASTIC QUAD FLATPACK - NO LEAD
6.1
5.9
B
A
0.5
0.3
PIN 1 INDEX AREA
6.1
5.9
0.3
0.2
DETAIL
OPTIONAL TERMINAL
TYPICAL
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
4.7 0.1
2X 4.5
(0.2) TYP
11
20
36X 0.5
10
21
EXPOSED
THERMAL PAD
2X
41
SYMM
4.5
SEE TERMINAL
DETAIL
1
30
0.3
0.2
40X
40
31
PIN 1 ID
(OPTIONAL)
0.1
0.05
C A B
SYMM
0.5
0.3
40X
4219053/B 03/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RHA0040C
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
4.7)
SYMM
40
31
40X (0.6)
1
30
40X (0.25)
4X
(1.35)
(
0.2) TYP
VIA
(0.75)
TYP
41
(5.8)
SYMM
4X
(1.5)
36X (0.5)
10
21
(R0.05)
TYP
11
(0.75) TYP
20
4X (1.5)
(5.8)
4X (1.35)
LAND PATTERN EXAMPLE
SCALE:12X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219053/B 03/2021
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RHA0040C
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(1.5) TYP
9X ( 1.3)
(R0.05) TYP
40
31
40X (0.6)
1
30
40X (0.25)
41
(1.5)
TYP
SYMM
(5.8)
36X (0.5)
10
21
METAL
TYP
11
20
SYMM
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 41:
69% PRINTED SOLDER COVERAGE BY AREA
SCALE:15X
4219053/B 03/2021
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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