LMX2332LSLBX/NOPB [TI]
IC,FREQUENCY SYNTHESIZER,BICMOS,LLCC,24PIN,PLASTIC;
| 型号： | LMX2332LSLBX/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | IC,FREQUENCY SYNTHESIZER,BICMOS,LLCC,24PIN,PLASTIC 信息通信管理 |
| 文件： | 总22页 (文件大小：1082K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
OBSOLETE
LMX2330L, LMX2331L, LMX2332L
www.ti.com
SNAS111C –JUNE 1999–REVISED MARCH 2013
PLLatinum™ Low Power Dual Frequency Synthesizer for RF Personal Communications
LMX2330L 2.5 GHz/510 MHz
LMX2331L 2.0 GHz/510 MHz
LMX2332L 1.2 GHz/510 MHz
Check for Samples: LMX2330L, LMX2331L, LMX2332L
1
FEATURES
DESCRIPTION
The LMX233XL family of monolithic, integrated dual
frequency synthesizers, including prescalers, is to be
used as a local oscillator for RF and first IF of a dual
conversion transceiver. It is fabricated using TI's 0.5μ
ABiC V silicon BiCMOS process.
23
•
Ultra Low Current Consumption
2.7V to 5.5V Operation
•
•
Selectable Synchronous or Asynchronous
Powerdown Mode:
–
ICC = 1 μA Typical at 3V
The LMX233XL contains dual modulus prescalers. A
64/65 or a 128/129 prescaler (32/33 or 64/65 in the
2.5 GHz LMX2330L) can be selected for the RF
synthesizer and a 8/9 or a 16/17 prescaler can be
selected for the IF synthesizer. LMX233XL, which
employs a digital phase locked loop technique,
combined with a high quality reference oscillator,
provides the tuning voltages for voltage controlled
oscillators to generate very stable, low noise signals
for RF and IF local oscillators. Serial data is
transferred into the LMX233XL via a three wire
interface (Data, Enable, Clock). Supply voltage can
range from 2.7V to 5.5V. The LMX233XL family
features very low current consumption;
•
Dual Modulus Prescaler:
–
–
–
LMX2330L
(RF) 32/33 or 64/65
LMX2331L/32L
(RF) 64/65 or 128/129
LMX2330L/31L/32L (IF) 8/9 or 16/17
•
•
•
•
Selectable Charge Pump TRI-STATE mode
Selectable Charge Pump Current Levels
Selectable Fastlock Mode
Upgrade and Compatible to LMX233XA Family
APPLICATIONS
•
Portable Wireless Communications
(PCS/PCN, Cordless)
LMX2330L—5.0 mA at 3V, LMX2331L—4.0 mA at
3V, LMX2332L—3.0 mA at 3V.
–
•
•
•
•
Cordless and Cellular Telephone Systems
Wireless Local Area Networks (WLANs)
Cable TV Tuners (CATV)
The LMX233XL are available in a TSSOP 20-pin,
LGA 24-pin surface mount plastic package, and thin
LGA 20-pin surface mount plastic package.
Other Wireless Communication Systems
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
PLLatinum is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1999–2013, Texas Instruments Incorporated
OBSOLETE
LMX2330L, LMX2331L, LMX2332L
SNAS111C –JUNE 1999–REVISED MARCH 2013
www.ti.com
Functional Block Diagram
Connection Diagrams
Figure 1. Chip Scale Package (NPH)
(Top View)
See Package Number NPH0024A
Figure 2. Thin Shrink Small Outline Package (PW)
(Top View)
See Package Number PW0020A
2
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SNAS111C –JUNE 1999–REVISED MARCH 2013
Figure 3. 20-Pin Thin Chipscale Package (NPJ)
(Top View)
See Package Number NPJ0020A
PIN DESCRIPTIONS
Pin No.
Pin No.
Pin No.
LMX233XLNPJ LMX233XLNPH LMX233XLPW
Pin
Name
I/O
Description
20-pin Thin
24-pin LGA
Package
20-pin TSSOP
Package
LGA Package
20
24
1
VCC1
—
Power supply voltage input for RF analog and RF digital circuits.
Input may range from 2.7V to 5.5V. VCC1 must equal VCC2. Bypass
capacitors should be placed as close as possible to this pin and be
connected directly to the ground plane.
1
2
2
3
2
3
VP1
—
O
Power Supply for RF charge pump. Must be ≥ VCC.
Do RF
Internal charge pump output. For connection to a loop filter for
driving the input of an external VCO.
3
4
5
4
5
6
4
5
6
GND
—
Ground for RF digital circuitry.
fIN RF
fIN RF
I
I
RF prescaler input. Small signal input from the VCO.
RF prescaler complementary input. A bypass capacitor should be
placed as close as possible to this pin and be connected directly to
the ground plane. Capacitor is optional with some loss of sensitivity.
6
7
7
8
7
8
GND
—
I
Ground for RF analog circuitry.
OSCin
Oscillator input. The input has a VCC/2 input threshold and can be
driven from an external CMOS or TTL logic gate.
8
9
10
11
9
GND
FoLD
—
O
Ground for IF digital, MICROWIRE, FoLD, and oscillator circuits.
10
Multiplexed output of the RF/IF programmable or reference dividers,
RF/IF lock detect signals and Fastlock mode. CMOS output (see
PROGRAMMABLE MODES).
10
11
12
12
14
15
11
12
13
Clock
Data
LE
I
I
I
High impedance CMOS Clock input. Data for the various counters is
clocked in on the rising edge, into the 22-bit shift register.
Binary serial data input. Data entered MSB first. The last two bits
are the control bits. High impedance CMOS input.
Load enable high impedance CMOS input. When LE goes HIGH,
data stored in the shift registers is loaded into one of the 4
appropriate latches (control bit dependent).
13
14
16
17
14
15
GND
fIN IF
—
I
Ground for IF analog circuitry.
IF prescaler complementary input. A bypass capacitor should be
placed as close as possible to this pin and be connected directly to
the ground plane. Capacitor is optional with some loss of sensitivity.
15
16
17
18
19
20
16
17
18
fIN RF
GND
Do IF
I
IF prescaler input. Small signal input from the VCO.
—
O
Ground for IF digital, MICROWIRE, FoLD, and oscillator circuits.
IF charge pump output. For connection to a loop filter for driving the
input of an external VCO.
18
22
19
VP2
—
Power Supply for IF charge pump. Must be ≥ VCC.
Copyright © 1999–2013, Texas Instruments Incorporated
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SNAS111C –JUNE 1999–REVISED MARCH 2013
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PIN DESCRIPTIONS (continued)
Pin No.
Pin No.
Pin No.
LMX233XLNPJ LMX233XLNPH LMX233XLPW
Pin
Name
I/O
Description
20-pin Thin
24-pin LGA
Package
20-pin TSSOP
Package
LGA Package
19
23
20
VCC2
—
Power supply voltage input for IF analog, IF digital, MICROWIRE,
FoLD, and oscillator circuits. Input may range from 2.7V to 5.5V.
VCC2 must equal VCC1. Bypass capacitors should be placed as
close as possible to this pin and be connected directly to the ground
plane.
X
1, 9, 13, 21
X
NC
—
No connect.
Block Diagram
Note: The RF prescaler for the LMX2331L/32L is either 64/65 or 128/129, while the prescaler for the LMX2330L is
32/33 or 64/65.
Note: VCC1 supplies power to the RF prescaler, N-counter, R-counter and phase detector. VCC2 supplies power to
the IF prescaler, N-counter, phase detector, R-counter along with the OSCin buffer, MICROWIRE, and FoLD. VCC
1
and VCC2 are clamped to each other by diodes and must be run at the same voltage level.
Note: VP1 and VP2 can be run separately as long as VP ≥ VCC
.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
4
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SNAS111C –JUNE 1999–REVISED MARCH 2013
(1)(2)(3)
Absolute Maximum Ratings
Power Supply Voltage
VCC
−0.3V to +6.5V
−0.3V to +6.5V
VP
Voltage on Any Pin
with GND = 0V (VI)
−0.3V to VCC+0.3V
−65°C to +150°C
+260°C
Storage Temperature Range (TS)
Lead Temperature (solder 4 sec.) (TL)
(1) This device is a high performance RF integrated circuit with an ESD rating <2 keV and is ESD sensitive. Handling and assembly of this
device should only be done at ESD protected work stations.
(2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Recommended Operating Conditions indicate
conditions for which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications
and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed.
(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
Recommended Operating Conditions(1)(2)
Power Supply Voltage
VCC
2.7V to 5.5V
VCC to +5.5V
VP
Operating Temperature (TA)
−40°C to +85°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Recommended Operating Conditions indicate
conditions for which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications
and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed.
(2) This device is a high performance RF integrated circuit with an ESD rating <2 keV and is ESD sensitive. Handling and assembly of this
device should only be done at ESD protected work stations.
Electrical Characteristics
VCC = 3.0V, VP = 3.0V; −40°C < TA < 85°C, except as specified
Value
Symbol
ICC
Parameter
Conditions
Units
Min
Typ
5.0
4.0
4.0
3.0
3.0
2.0
1.0
1
Max
6.6
5.2
5.4
4.0
4.1
2.7
1.4
10
Power
Supply
Current
LMX2330L RF + IF
LMX2330L RF Only
LMX2331L RF + IF
LMX2331L RF Only
LMX2332L IF + RF
LMX2332L RF Only
LMX233xL IF Only
VCC = 2.7V to 5.5V
mA
(1)
ICC-PWDN Powerdown Current
μA
fIN RF
Operating Frequency
LMX2330L
LMX2331L
LMX2332L
LMX233xL
0.5
0.2
0.1
45
2.5
2.0
1.2
510
GHz
MHz
fIN IF
Operating Frequency
Oscillator Frequency
fOSC
fφ
5
40
MHz
MHz
Maximum Phase Detector Frequency
RF Input Sensitivity
10
PfIN RF
VCC = 3.0V
−15
−10
0
0
0
dBm
dBm
dBm
VPP
V
VCC = 5.0V
PfIN IF
VOSC
VIH
IF Input Sensitivity
VCC = 2.7V to 5.5V
−10
Oscillator Sensitivity
High-Level Input Voltage
OSCin
(2)
0.5
0.8 VCC
(1) Clock, Data and LE = GND or Vcc
.
(2) Clock, Data and LE does not include fIN RF, fIN IF and OSCIN
.
Copyright © 1999–2013, Texas Instruments Incorporated
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Electrical Characteristics (continued)
VCC = 3.0V, VP = 3.0V; −40°C < TA < 85°C, except as specified
Value
Typ
Symbol
Parameter
Conditions
Units
Min
Max
(2)
VIL
Low-Level Input Voltage
0.2 VCC
1.0
V
μA
μA
μA
μA
V
(2)
IIH
High-Level Input Current
VIH = VCC = 5.5V
VIL = 0V, VCC = 5.5V
VIH = VCC = 5.5V
VIL = 0V, VCC = 5.5V
IOH = −500 μA
−1.0
−1.0
(2)
IIL
Low-Level Input Current
1.0
IIH
Oscillator Input Current
100
IIL
Oscillator Input Current
−100
VOH
VOL
tCS
High-Level Output Voltage (for FoLD, pin number 10)
Low-Level Output Voltage (for FoLD, pin number 10)
Data to Clock Set Up Time
V
CC − 0.4
IOL = 500 μA
0.4
V
See SERIAL DATA
INPUT TIMING
50
10
50
50
50
50
ns
tCH
Data to Clock Hold Time
Clock Pulse Width High
See SERIAL DATA
INPUT TIMING
ns
ns
ns
ns
ns
tCWH
tCWL
tES
See SERIAL DATA
INPUT TIMING
Clock Pulse Width Low
See SERIAL DATA
INPUT TIMING
Clock to Load Enable Set Up Time
Load Enable Pulse Width
See SERIAL DATA
INPUT TIMING
tEW
See SERIAL DATA
INPUT TIMING
Charge Pump Characteristics
VCC = 3.0V, VP = 3.0V; −40°C < TA ≤ 85°C, except as specified
Value
Typ
−4.0
4.0
Symbol
Parameter
Conditions
Units
Min
Max
(1)
IDo-SOURCE
IDo-SINK
Charge Pump Output
Current
VDo = VP/2, ICPo = HIGH
mA
mA
mA
mA
(1)
(1)
(1)
VDo = VP/2, ICPo = HIGH
VDo = VP/2, ICPo = LOW
VDo = VP/2, ICPo = LOW
0.5V ≤ VDo ≤ VP − 0.5V
−40°C < TA < 85°C
VDo = VP/2
IDo-SOURCE
IDo-SINK
−1
1
IDo-TRI
Charge Pump
TRI-STATE Current
CP Sink vs
−2.5
2.5
10
15
nA
%
IDo-SINK vs
IDo-SOURCE
IDo vs VDo
3
(2)
Source Mismatch
TA = 25°C
(3)
CP Current vs Voltage
0.5 ≤ VDo ≤ VP − 0.5V
TA = 25°C
10
10
%
%
IDo vs TA
CP Current vs
VDo = VP/2
(4)
Temperature
−40°C ≤ TA ≤ 85°C
(1) See PROGRAMMABLE MODES for ICPo description.
(2) IDo-sink vs IDo-source Charge Pump Output Current Sink vs Source Mismatch = [|I2| - |I5|]/[½ * {|I2| + |I5|}] * 100%
(3) IDo vs VDo Charge Pump Output Current magnitude variation vs Voltage = [½ * {|I1| - |I3|}]/[½ * {|I1| + |I3|}] * 100% and [½ * {|I4| -
|I6|}]/[½ * {|I4| + |I6|}] * 100%
=
=
(4) IDo vs TA
=
Charge Pump Output Current magnitude variation vs Temperature = [|I2 @ temp| - |I2 @ 25°C|]/|I2 @ 25°C| * 100% and
[|I5 @ temp| - |I5 @ 25°c|]/|I5 @ 25°C| * 100%
6
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SNAS111C –JUNE 1999–REVISED MARCH 2013
Charge Pump Current Specification Definitions
I1 = CP sink current at VDo = VP − ΔV
I2 = CP sink current at VDo = VP/2
I3 = CP sink current at VDo = ΔV
I4 = CP source current at VDo = VP − ΔV
I5 = CP source current at VDo = VP/2
I6 = CP source current at VDo = ΔV
ΔV = Voltage offset from positive and negative rails. Dependent on VCO tuning range relative to VCC and ground.
Typical values are between 0.5V and 1.0V.
RF Sensitivity Test Block Diagram
Note 1: N = 10,000
R = 50
P = 64
Note 2: Sensitivity limit is reached when the error of the divided RF output, FoLD, is ≥ 1 Hz.
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Typical Performance Characteristics
ICC
vs
ICC
vs
VCC
VCC
LMX2330L
LMX2331L
Figure 4.
Figure 5.
ICC
vs
VCC
IDo TRI-STATE
vs Do Voltage
LMX2332L
Figure 6.
Figure 7.
Charge Pump Current
vs
Charge Pump Current
vs
Do Voltage
ICP = HIGH
Do Voltage
ICP = LOW
Figure 8.
Figure 9.
8
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SNAS111C –JUNE 1999–REVISED MARCH 2013
Typical Performance Characteristics (continued)
Sink
vs
Charge Pump Current Variation
(See (1) under Charge Pump Current
Specification Definitions)
Source Mismatch
(See (2) under Charge Pump Current
Specification Definitions)
Figure 10.
Figure 11.
RF Input Impedance
VCC = 2.7V to 5.5V, fIN = 50 MHz to 3 GHz
IF Input Impedance
VCC = 2.7V to 5.5V, fIN = 50 MHz to 1000 MHz
Figure 12.
Figure 13.
(1) IDo vs VDo
= Charge Pump Output Current magnitude variation vs Voltage = [½ * {|I1| - |I3|}]/[½ * {|I1| + |I3|}] * 100% and [½ * {|I4| -
|I6|}]/[½ * {|I4| + |I6|}] * 100%
(2) IDo-sink vs IDo-source Charge Pump Output Current Sink vs Source Mismatch = [|I2| - |I5|]/[½ * {|I2| + |I5|}] * 100%
=
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Typical Performance Characteristics (continued)
LMX233xNPJ RF Input Impedance
VCC = 2.7V to 5.5V, fIN = 500 MHz to 3 GHz, fINRF CAP = 100
pF
LMX233xNPJ IF Input Impedance
VCC = 2.7V to 5.5V, fINIF = 100 MHz to 400 MHz, fINIF CAP =
100 pF
Marker 1 = 500 MHz, Real = 202.98, Imaginary = −200.09
Marker 2 = 1.8 GHz, Real = 32.36, Imaginary = −91.42
Marker 3 = 2.5 GHz, Real = 25.51, Imaginary = −46.41
Marker 1 = 100 MHz, Real = 374.33, Imaginary = −301.45
Marker 2 = 200 MHz, Real = 257.14, Imaginary = −245.79
Marker 3 = 300 MHz, Real = 194.08, Imaginary = −224.24224.24
Marker 4 = 3.0 GHz, Real = 30.46, Imaginary = −9.50
Marker 4 = 400 MHz, Real = 89.03, Imaginary = −131.21
Figure 14.
Figure 15.
LMX2330L RF Sensitivity
LMX2331L RF Sensitivity
vs
vs
Frequency
Frequency
Figure 16.
Figure 17.
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SNAS111C –JUNE 1999–REVISED MARCH 2013
Typical Performance Characteristics (continued)
LMX2332L RF Sensitivity
IF Input Sensitivity
vs
vs
Frequency
Frequency
Figure 18.
Figure 19.
Oscillator Input Sensitivity
vs
Frequency
Figure 20.
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FUNCTIONAL DESCRIPTION
The simplified block diagram below shows the 22-bit data register, two 15-bit R Counters and the 15- and 18-bit
N Counters (intermediate latches are not shown). The data stream is clocked (on the rising edge of Clock) into
the DATA register, MSB first. The data stored in the shift register is loaded into one of 4 appropriate latches on
the rising edge of LE. The last two bits are the Control Bits. The DATA is transferred into the counters as follows:
Control Bits
DATA Location
C1
0
C2
0
IF R Counter
RF R Counter
IF N Counter
RF N Counter
0
1
1
0
1
1
PROGRAMMABLE REFERENCE DIVIDERS (IF AND RF R COUNTERS)
If the Control Bits are 00 or 01 (00 for IF and 01 for RF) data is transferred from the 22-bit shift register into a
latch which sets the 15-bit R Counter. Serial data format is shown below.
15-BIT PROGRAMMABLE REFERENCE DIVIDER RATIO (R COUNTER)
Divide
R
15
0
R
14
0
R
13
0
R
12
0
R
11
0
R
10
0
R
9
0
0
•
R
8
0
0
•
R
7
0
0
•
R
6
0
0
•
R
5
0
0
•
R
4
0
0
•
R
3
0
1
•
R
2
1
0
•
R
1
1
0
•
Ratio
3
4
•
0
0
0
0
0
0
•
•
•
•
•
•
32767
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
12
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PROGRAMMABLE DIVIDER (N COUNTER)
The N counter consists of the 7-bit swallow counter (A counter) and the 11-bit programmable counter (B
counter). If the Control Bits are 10 or 11 (10 for IF counter and 11 for RF counter) data is transferred from the 22-
bit shift register into a 4-bit or 7-bit latch (which sets the Swallow (A) Counter) and an 11-bit latch (which sets the
11-bit programmable (B) Counter), MSB first. Serial data format is shown below. For the IF N counter bits 5, 6,
and 7 are don't care bits. The RF N counter does not have don't care bits.
7-BIT SWALLOW COUNTER DIVIDE RATIO (A COUNTER)
Table 1. RF
Divide
N
7
N
6
N
5
N
4
N
3
N
2
N
1
Ratio
A
0
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
1
•
1
•
127
1
1
1
1
1
1
1
Table 2. IF
Divide
N
7
N
6
N
5
N
4
N
3
N
2
N
1
Ratio
A
0
X
X
•
X
X
•
X
X
•
0
0
•
0
0
•
0
0
•
0
1
•
1
•
15
X
X
X
1
1
1
1
Table 3. 11-BIT PROGRAMMABLE COUNTER DIVIDE RATIO (B COUNTER)
Divide
N
18
N
17
N
16
N
15
N
14
N
13
N
12
N
11
N
10
N
9
N
8
Ratio
B
3
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
1
•
1
0
•
1
0
•
4
•
2047
1
1
1
1
1
1
1
1
1
1
1
PULSE SWALLOW FUNCTION
fVCO = [(P × B) + A] × fOSC/R
fVCO: Output frequency of external voltage controlled oscillator (VCO)
B: Preset divide ratio of binary 11-bit programmable counter (3 to 2047)
A: Preset divide ratio of binary 7-bit swallow counter
(0 ≤ A ≤ 127 {RF}, 0 ≤ A ≤ 15 {IF}, A ≤ B)
fOSC: Output frequency of the external reference frequency oscillator
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R: Preset divide ratio of binary 15-bit programmable reference counter (3 to 32767)
P: Preset modulus of dual moduIus prescaler (for IF; P = 8 or 16;
for RF; LMX2330L: P = 32 or 64
LMX2331L/32L: P = 64 or 128)
PROGRAMMABLE MODES
Several modes of operation can be programmed with bits R16–R20 including the phase detector polarity, charge
pump TRI-STATE and the output of the FoLD pin. The prescaler and powerdown modes are selected with bits
N19 and N20. The programmable modes are shown in Table 4. Truth table for the programmable modes and
FoLD output are shown in Table 5 and Table 6.
Table 4. Programmable Modes
C1
C2
R16
R17
R18
IF Do
R19
R20
0
0
IF Phase
IF ICPo
IF LD
IF Fo
Detector Polarity
RF Phase
TRI-STATE
RF Do
0
1
RF ICPo
RF LD
RF Fo
Detector Polarity
TRI-STATE
C1
1
C2
0
N19
N20
IF Prescaler
RF Prescaler
Pwdn IF
Pwdn RF
1
1
Table 5. Mode Select Truth Table
Phase Detector Polarity
Do TRI-STATE
ICPo
(3)
IF
Prescaler
8/9
2330L RF
Prescaler
32/33
2331L/32L RF
Prescaler
64/65
Pwdn
(2)
(1)
(2)
0
1
Negative
Positive
Normal Operation
TRI-STATE
LOW
HIGH
Pwrd Up
Pwrd Dn
16/17
64/65
128/129
(1) PHASE DETECTOR POLARITY, Depending upon VCO characteristics, R16 bit should be set accordingly: (see Figure 21) When VCO
characteristics are positive like (1), R16 should be set HIGH; When VCO characteristics are negative like (2), R16 should be se LOW.
(2) Refer to POWERDOWN OPERATION.
(3) The ICPo LOW current state = 1/4 × ICPo HIGH current.
Figure 21. VCO Characteristics
Table 6. The FoLD (Pin 10) Output Truth Table(1)
RF R[19]
IF R[19]
RF R[20]
IF R[20]
Fo Output State
(RF LD)
(IF LD)
(RF Fo)
(IF Fo)
(2)
0
0
1
0
1
0
0
0
0
0
0
0
Disabled
(3)
IF Lock Detect
RF Lock Detect
(3)
(1) X = don't care condition
(2) When the FoLD output is disabled, it is actively pulled to a low logic state.
(3) Lock detect output provided to indicate when the VCO frequency is in “lock.” When the loop is locked and a lock detect mode is
selected, the pins output is HIGH, with narrow pulses LOW. In the RF/IF lock detect mode a locked condition is indicated when RF and
IF are both locked.
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Table 6. The FoLD (Pin 10) Output Truth Table(1) (continued)
RF R[19]
IF R[19]
RF R[20]
IF R[20]
Fo Output State
(RF LD)
(IF LD)
(RF Fo)
(IF Fo)
(3)
1
X
X
X
X
0
0
1
1
1
0
0
1
1
0
1
0
1
0
0
1
0
1
1
1
1
1
0
1
0
1
0
1
1
1
1
RF/IF Lock Detect
IF Reference Divider Output
RF Reference Divider Output
IF Programmable Divider Output
RF Programmable Divider Output
(4)
Fastlock
(5)
IF Counter Reset
(5)
RF Counter Reset
(5)
IF and RF Counter Reset
(4) The Fastlock mode utilizes the FoLD output pin to switch a second loop filter damping resistor to ground during fastlock operation.
Activation of Fastlock occurs whenever the RF loop's lcpo magnitude bit #17 is selected HIGH (while the #19 and #20 mode bits are set
for Fastlock).
(5) The IF Counter Reset mode resets IF PLL's R and N counters and brings IF charge pump output to a TRI-STATE condition. The RF
Counter Reset mode resets RF PLL's R and N counters and brings RF charge pump output to a TRI-STATE condition. The IF and RF
Counter Reset mode resets all counters and brings both charge pump outputs to a TRI-STATE condition. Upon removal of the Reset
bits then N counter resumes counting in “close” alignment with the R counter. (The maximum error is one prescaler cycle.)
POWERDOWN OPERATION
Synchronous and asynchronous powerdown modes are both available by MICROWIRE selection. Synchronously
powerdown occurs if the respective loop's R18 bit (Do TRI-STATE) is LOW when its N20 bit (Pwdn) becomes HI.
Asynchronous powerdown occurs if the loop's R18 bit is HI when its N20 bit becomes HI.
In the synchronous powerdown mode, the powerdown function is gated by the charge pump to prevent unwanted
frequency jumps. Once the powerdown program bit N20 is loaded, the part will go into powerdown mode when
the charge pump reaches a TRI-STATE condition.
In the asynchronous powerdown mode, the device powers down immediately after the LE pin latches in a HI
condition on the powerdown bit N20.
Activation of either the IF or RF PLL powerdown conditions in either synchronous or asynchronous modes forces
the respective loop's R and N dividers to their load state condition and debiasing of its respective fIN input to a
high impedance state. The oscillator circuitry function does not become disabled until both IF and RF powerdown
bits are activated. The MICROWIRE control register remains active and capable of loading and latching data
during all of the powerdown modes.
The device returns to an actively powered up condition in either synchronous or asynchronous modes
immediately upon LE latching LOW data into bit N20.
Table 7. Powerdown Mode Select Table
R18
0
N20
0
Powerdown Status
PLL Active
1
0
PLL Active
(Charge Pump Output TRI-STATE)
0
1
1
1
Synchronous Powerdown Initiated
Asynchronous Powerdown Initiated
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SERIAL DATA INPUT TIMING
Note 1: Parenthesis data indicates programmable reference divider data.
Data shifted into register on clock rising edge.
Data is shifted in MSB first.
Note 2: tcs = Data to Clock Set-Up Time
tCH = Data to Clock Hold Time
tCWH = Clock Pulse Width High
tCWL = Clock Pulse Width Low
tES = Clock to Load Enable Set-Up Time
tEW = Load Enable Pulse Width
Test Conditions: The Serial Data Input Timing is tested using a symmetrical waveform around VCC/2. The test
waveform has an edge rate of 0.6 V/ns with amplitudes of 2.2V @ VCC = 2.7V and 2.6V @ VCC = 5.5V.
PHASE COMPARATOR AND INTERNAL CHARGE PUMP CHARACTERISTICS
Notes: Phase difference detection range: −2π to +2π
The minimum width pump up and pump down current pulses occur at the Do pin when the loop is locked.
R16 = HIGH
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Typical Application Example
Operational Notes:
*
VCO is assumed AC coupled.
** RIN increases impedance so that VCO output power is provided to the load rather than the PLL. Typical values
are 10Ω to 200Ω depending on the VCO power level. fIN RF impedance ranges from 40Ω to 100Ω. fIN IF impedances
are higher.
*** Adding RC filters to the VCC lines is recommended to reduce loop-to-loop noise coupling.
Application Hints:
Proper use of grounds and bypass capacitors is essential to achieve a high level of performance. Crosstalk
between pins can be reduced by careful
board layout.
This is an electrostatic sensitive device. It should be handled only at static free work stations.
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Application Information
A block diagram of the basic phase locked loop is shown in Figure 22.
Figure 22. Basic Charge Pump Phase Locked Loop
LOOP GAIN EQUATIONS
A linear control system model of the phase feedback for a PLL in the locked state is shown in Figure 23. The
open loop gain is the product of the phase comparator gain (Kφ), the VCO gain (KVCO/s), and the loop filter gain
Z(s) divided by the gain of the feedback counter modulus (N). The passive loop filter configuration used is
displayed in Figure 24, while the complex impedance of the filter is given in Equation 1.
Figure 23. PLL Linear Model
Figure 24. Passive Loop Filter
(1)
The time constants which determine the pole and zero frequencies of the filter transfer function can be defined
as
(2)
and
T2 = R2 • C2
(3)
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The 3rd order PLL Open Loop Gain can be calculated in terms of frequency, ω, the filter time constants T1 and
T2, and the design constants Kφ, KVCO, and N.
(4)
From Equation 2 and Equation 3 we can see that the phase term will be dependent on the single pole and zero
such that the phase margin is determined in Equation 5.
φ(ω) = tan −1 (ω • T2) − tan−1 (ω • T1) + 180°
(5)
A plot of the magnitude and phase of G(s)H(s) for a stable loop, is shown in Figure 25 with a solid trace. The
parameter φp shows the amount of phase margin that exists at the point the gain drops below zero (the cutoff
frequency wp of the loop). In a critically damped system, the amount of phase margin would be approximately 45
degrees.
If we were now to redefine the cut off frequency, wp', as double the frequency which gave us our original loop
bandwidth, wp, the loop response time would be approximately halved. Because the filter attenuation at the
comparison frequency also diminishes, the spurs would have increased by approximately 6 dB. In the proposed
Fastlock scheme, the higher spur levels and wider loop filter conditions would exist only during the initial lock-on
phase—just long enough to reap the benefits of locking faster. The objective would be to open up the loop
bandwidth but not introduce any additional complications or compromises related to our original design criteria.
We would ideally like to momentarily shift the curve of Figure 25 over to a different cutoff frequency, illustrated by
the dotted line, without affecting the relative open loop gain and phase relationships. To maintain the same
gain/phase relationship at twice the original cutoff frequency, other terms in the gain and phase Equation 4 and
Equation 5 will have to compensate by the corresponding “1/w” or “1/w2” factor. Examination of equations
Equation 2, Equation 3, and Equation 5 indicates the damping resistor variable R2 could be chosen to
compensate the “w”' terms for the phase margin. This implies that another resistor of equal value to R2 will need
to be switched in parallel with R2 during the initial lock period. We must also insure that the magnitude of the
open loop gain, H(s)G(s) is equal to zero at wp' = 2wp. Kvco, Kφ, N, or the net product of these terms can be
changed by a factor of 4, to counteract the w2 term present in the denominator of Equation 2 and Equation 3.
The Kφ term was chosen to complete the transformation because it can readily be switched between 1X and 4X
values. This is accomplished by increasing the charge pump output current from 1 mA in the standard mode to 4
mA in Fastlock.
Figure 25. Open Loop Response Bode Plot
FASTLOCK CIRCUIT IMPLEMENTATION
A diagram of the Fastlock scheme as implemented in Texas Instruments LMX233XL PLL is shown in Figure 26.
When a new frequency is loaded, and the RF Icpo bit is set high the charge pump circuit receives an input to
deliver 4 times the normal current per unit phase error while an open drain NMOS on chip device switches in a
second R2 resistor element to ground. The user calculates the loop filter component values for the normal steady
state considerations. The device configuration ensures that as long as a second identical damping resistor is
wired in appropriately, the loop will lock faster without any additional stability considerations to account for. Once
locked on the correct frequency, the user can return the PLL to standard low noise operation by sending a
MICROWIRE instruction with the RF Icpo bit set low. This transition does not affect the charge on the loop filter
capacitors and is enacted synchronous with the charge pump output. This creates a nearly seamless change
between Fastlock and standard mode.
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Figure 26. Fastlock PLL Architecture
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REVISION HISTORY
Changes from Revision B (March 2013) to Revision C
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 20
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