LMX2541SQE2690E [TI]
LMX2541 Ultra-Low Noise PLLatinum Frequency Synthesizer with Integrated VCO; LMX2541超低噪声半导体PLLatinum频率合成器集成VCO
| 型号： | LMX2541SQE2690E |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LMX2541 Ultra-Low Noise PLLatinum Frequency Synthesizer with Integrated VCO |
| 文件： | 总64页 (文件大小：1169K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LMX2541SQ2060E, LMX2541SQ2380E
LMX2541SQ2690E, LMX2541SQ3030E
LMX2541SQ3320E, LMX2541SQ3740E
www.ti.com
SNOSB31I –JULY 2009–REVISED FEBRUARY 2013
LMX2541 Ultra-Low Noise PLLatinum Frequency Synthesizer with Integrated VCO
Check for
Samples: LMX2541SQ2060E, LMX2541SQ2380E, LMX2541SQ2690E, LMX2541SQ3030E, LMX2541SQ3320E, LMX2541SQ3740E
1
FEATURES
DESCRIPTION
2
•
Very Low RMS Noise and Spurs
The LMX2541 is an ultra low noise frequency
synthesizer which integrates a high performance
delta-sigma fractional N PLL, a VCO with fully
integrated tank circuit, and an optional frequency
divider. The PLL offers an unprecedented normalized
noise floor of -225 dBc/Hz and can be operated with
up to 104 MHz of phase-detector rate (comparison
frequency) in both integer and fractional modes. The
PLL can also be configured to work with an external
VCO.
–
–
-225 dBc/Hz Normalized PLL Phase Noise
Integrated RMS Noise (100 Hz - 20 MHz)
–
–
2 mrad (100 Hz - 20 MHz) at 2.1 GHz
3.5 mrad (100 Hz - 20 MHz) at 3.5 GHz
•
•
•
•
•
•
•
•
•
Ultra Low-Noise Integrated VCO
External VCO Option (Internal VCO Bypassed)
VCO Frequency Divider 1 to 63 (all values)
Programmable Output Power
The LMX2541 integrates several low-noise, high
precision LDOs and output driver matching network to
provide higher supply noise immunity and more
consistent performance, while reducing the number of
external components. When combined with a high
quality reference oscillator, the LMX2541 generates a
very stable, ultra low noise signal.
Up to 104 MHz Phase Detector Frequency
Integrated Low-Noise LDOs
Programmable Charge Pump Output
Partially Integrated Loop Filter
Digital Frequency Shift Keying (FSK)
Modulation Pin
The LMX2541 is offered in a family of 6 devices with
varying VCO frequency range from 1990 MHz up to 4
GHz. Using a flexible divider, the LMX2541 can
generate frequencies as low as 31.6 MHz. The
LMX2541 is a monolithic integrated circuit, fabricated
•
•
•
Integrated Reference Crystal Oscillator Circuit
Hardware and Software Power Down
FastLock Mode and VCO-Based Cycle Slip
Reduction
in
a
proprietary BiCMOS process. Device
three-wire
•
•
Analog and Digital Lock Detect
1.6 V Logic Compatibility
programming is facilitated using
a
MICROWIRE interface that can operate down to 1.6
volts. Supply voltage ranges from 3.15 to 3.45 volts.
The LMX2541 is available in a 36 pin 6x6x0.8 mm
WQFN Package.
TARGET APPLICATIONS
•
•
•
•
Wireless Infrastructure (UMTS, LTE, WiMax)
Broadband Wireless
Wireless Meter Reading
Test and Measurement
Device
VCO Frequency
1990 - 2240
2200 - 2530
2490 - 2865
2810 - 3230
3130 - 3600
3480 - 4000
LMX2541SQ2060E
LMX2541SQ2380E
LMX2541SQ2690E
LMX2541SQ3030E
LMX2541SQ3320E
LMX2541SQ3740E
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009–2013, Texas Instruments Incorporated
LMX2541SQ2060E, LMX2541SQ2380E
LMX2541SQ2690E, LMX2541SQ3030E
LMX2541SQ3320E, LMX2541SQ3740E
SNOSB31I –JULY 2009–REVISED FEBRUARY 2013
www.ti.com
System Diagram
Clean
Reference
Clock
Ultra-Clean
Local Oscillator
Dirty Input
Clock
PLL
PLL
LMK04000
(Clock Jitter Cleaner)
LMX2541
(RF Synthesizer)
LMX2541 Frequency Coverage
2060E
Start
2380E
Start
2690E
Stop
3030E
3320E
Start
3740E
VCO
_DIV
Stop
2240.0
1120.0
746.7
560.0
448.0
373.3
320.0
280.0
…
Stop
2530.0
1265.0
843.3
632.5
506.0
421.7
361.4
316.3
…
Start
2490.0
1245.0
830.0
622.5
498.0
415.0
355.7
311.3
…
Start
Stop
3230.0
1615.0
1076.7
807.5
646.0
538.3
461.4
403.8
…
Stop
3600.0
1800.0
1200.0
900.0
720.0
600.0
514.3
450.0
…
Start
3480.0
1740.0
1160.0
870.0
696.0
580.0
497.1
435.0
…
Stop
4000.0
2000.0
1333.3
1000.0
800.0
666.7
571.4
500.0
…
1
2
1990.0
995.0
663.3
497.5
398.0
331.7
284.3
248.8
…
2200.0
1100.0
733.3
550.0
440.0
366.7
314.3
275.0
…
2865.0
1432.5
955.0
716.3
573.0
477.5
409.3
358.1
…
2810.0
1405.0
936.7
702.5
562.0
468.3
401.4
351.3
…
3130.0
1565.0
1043.3
782.5
626.0
521.7
447.1
391.3
…
3
4
5
6
7
8
…
63
31.6
35.6
34.9
40.2
39.5
45.5
44.6
51.3
49.7
57.1
55.2
63.5
All devices have continuous frequency coverage below a divide value of 8 (7 for most devices) down to their
minimum frequency achievable with divide by 63. The numbers in bold show the upper end of this minimum
continuous frequency range. For instance, the LMX2541SQ3740E option offers continuous frequency coverage
from 55.2 MHz to 571.4 MHz and LMX2541SQ2060E offers continuous frequency coverage from 31.6 MHz to
280 MHz. If using the part in External VCO mode, all parts have roughly the same performance and any option
will do.
Determining the Best Frequency Option of the LMX2541 to Use
When there are multiple devices that can satisfy the frequency requirement, performance characteristics can
sometimes be used to make a decision. Consider the following example of where an output frequency of 1200 to
1250 MHz is desired with a channel spacing of 100 kHz. From the frequency table, the LMX2541SQ2380E could
be used with a divide value of 2, or the LMX2541SQ3740E option could be used with a divide value of 3. This
raises the question: Which one has better performance? The following table is helpful in comparing the
performance.
Performance
Characteristic
What Makes it
Better
Why
Fractional spurs at the VCO are independent of VCO frequency, but when the VCO frequency is
divided down by a factor of VCO_DIV, the fractional spurs improve by a factor of 20·log(VCO_DIV).
Also, the fractional channel spacing can be made wider at the VCO, which makes the fractional spurs
farther from the carrier.
The fractional noise of the modulator is divided down in a similar way as fractional spurs. In
applications where this is dominant, this larger division can have an impact. Consult the applications
section for more information on the fractional phase noise.
Fractional Spurs
and
Fraction Noise
Larger Value
of VCO_DIV
2
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Product Folder Links: LMX2541SQ2060E LMX2541SQ2380E LMX2541SQ2690E LMX2541SQ3030E
LMX2541SQ3320E LMX2541SQ3740E
LMX2541SQ2060E, LMX2541SQ2380E
LMX2541SQ2690E, LMX2541SQ3030E
LMX2541SQ3320E, LMX2541SQ3740E
www.ti.com
SNOSB31I –JULY 2009–REVISED FEBRUARY 2013
Performance
Characteristic
What Makes it
Better
Why
Operating in
the lower
frequency
range of the
VCO
VCO Phase
Noise
At the lower end of the tuning range, the VCO phase noise is less because the tuning gain is less. This
provides better phase noise, even accounting for the difference in frequency.
Considering the fractional spurs and phase noise, the channel spacing at the 2380E VCO would be 200 kHz.
When this is divided by two, the offset of these spurs does not change and the spurs at the VCO output would be
reduced by a factor of 20·log(2) = 6 dB. The channel spacing at the 3740E VCO would be 300 kHz and these
spurs would be reduced by a factor of 20·log(3) = 9.5 dB. So the spurs of the 3740E option would probably be
better by virtue of the fact that they are farther from the carrier and easier to filter and also that they are divided
down more by the VCO divider. The fractional phase noise would also be (9.5 - 6) = 3.5 dB better by the same
reasoning.
Now consider the VCO phase noise. For the 3740E option, 1200 - 1250 MHz corresponds to a VCO frequency of
3600 - 3750 MHz, which is closer to the lower end of the tuning range for this device. For the 2380E option, this
would correspond to 2400 - 2500 MHz, which is closer to the higher end of the tuning range. To verify this, take
the phase noise numbers from the electrical specifications, extrapolate them to the actual frequencies, and then
subtract a factor of 20·log(VCO_DIV). For the 2380E option, this works out to -116 dBc/Hz at 1200 MHz and -
115.4 dBc/Hz at 1250 MHz. For the 3740E option, this works out to -117.4 dBc/Hz at 1200 MHz and -116.9
dBc/Hz at 1250 MHz.
Functional Block Diagram
Vtune
VregVCO
CPout
Charge
Pump
VCO
VREG
VrefVCO
N Divider
4/5
ExtVCOin
Prescaler
FLout
Fast
Lock
f
2-63
Divider
Modulus
Control
Comp
Ftest/LD
RFout
VREG
RFout
VregFRAC
MUX
FRAC
VREG
RFoutEN
2X
DATA
CLK
LE
OSCin
MUX
Serial Interface
Control
OSCin*
R
Divider
CE
Copyright © 2009–2013, Texas Instruments Incorporated
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Product Folder Links: LMX2541SQ2060E LMX2541SQ2380E LMX2541SQ2690E LMX2541SQ3030E
LMX2541SQ3320E LMX2541SQ3740E
LMX2541SQ2060E, LMX2541SQ2380E
LMX2541SQ2690E, LMX2541SQ3030E
LMX2541SQ3320E, LMX2541SQ3740E
SNOSB31I –JULY 2009–REVISED FEBRUARY 2013
www.ti.com
Connection Diagram
33
36
35
34
32
31
30
29
28
GND
VregRFout
VccRFout
L1
GND
1
2
3
4
5
27
26
25
24
23
VregFRAC
VccFRAC
RFoutEN
VccOSCin
OSCin*
0
GND
Lmid
L2
6
7
8
9
22
21
20
19
VccVCO
VregVCO
VrefVCO
OSCin
Ftest/LD
VccPLL2
11
12
13
14
15
16
17
18
10
Figure 1. 36-Pin NJK0036A Package (Top View)
PIN DESCRIPTIONS
Pin #
Name
GND
Type
Description
0
1
2
GND
GND
The DAP pad must be grounded.
GND
VregRFout
LDO Output
LDO Output for RF output buffer.
Supply for the RF output buffer.
Supply
(LDO Input)
3
VccRFout
4
5
6
L1
Lmid
L2
NC
NC
NC
Do not connect this pin.
Do not connect this pin.
Do not connect this pin.
Supply
(LDO Input)
7
VccVCO
Supply for the VCO.
8
9
VregVCO
VrefVCO
GND
LDO Output
LDO Bypass
GND
LDO Output for VCO
LDO Bypass
10
Chip Enable.
11
12
CE
CMOS
The device needs to be programmed for this pin to properly power down the device.
Optional input for use with an external VCO.
This pin should be AC coupled if used or left open if not used.
ExtVCOin
RF Input
13
14
15
16
17
18
19
VccPLL1
VccCP1
Vtune
Supply
Supply
Power supply for PLL.
Power supply for PLL charge pump.
Tuning voltage input to the VCO.
Charge pump output.
High-Z Input
Output
CPout
FLout
Output
Fastlock output.
VccCP2
VccPLL2
Supply
Power supply for PLL charge pump.
Power supply for PLL.
Supply
4
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Copyright © 2009–2013, Texas Instruments Incorporated
Product Folder Links: LMX2541SQ2060E LMX2541SQ2380E LMX2541SQ2690E LMX2541SQ3030E
LMX2541SQ3320E LMX2541SQ3740E
LMX2541SQ2060E, LMX2541SQ2380E
LMX2541SQ2690E, LMX2541SQ3030E
LMX2541SQ3320E, LMX2541SQ3740E
www.ti.com
SNOSB31I –JULY 2009–REVISED FEBRUARY 2013
PIN DESCRIPTIONS (continued)
Pin #
Name
Type
Description
Software controllable multiplexed CMOS output.
Can be used to monitor PLL lock condition.
20
Ftest/LD
Output
Oscillator input signal. If not being used with an external crystal, this input should be AC
coupled.
21
22
OSCin
High-Z Input
High-Z Input
Complementary oscillator input signal. Can also be used with an external crystal. If not
being used with an external crystal, this input should be AC coupled.
OSCin*
23
24
VccOSCin
RFoutEN
Supply
Input
Supply for the OSCin buffer.
Software programmable output enable pin.
Supply
(LDO Input)
25
VccFRAC
Power Supply for the PLL fractional circuitry.
26
27
28
29
30
31
32
VregFRAC
GND
LDO Output
GND
Regulated power supply used for the fractional delta-sigma circuitry.
VccDig
VccBias
Bypass
VccDiv
DATA
Supply
Supply for digital circuitry, such the MICROWIRE.
Supply for Bias circuitry that is for the whole chip.
Put a cap to the VccBias pin.
Supply
Bypass
Supply
Supply for the output divider
High-Z Input
MICROWIRE serial data input. High impedance CMOS input.
MICROWIRE clock input. High impedance CMOS input.
This pin is used for the digital FSK modulation feature.
33
CLK
High-Z Input
34
35
36
LE
NC
High-Z Input
NC
MICROWIRE Latch Enable input. High impedance CMOS input.
No connect.
RFout
RF Output
RF output. Must be AC coupled if used.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
(1)(2)(3)(4)
Absolute Maximum Ratings
Parameter
Symbol
Ratings
Units
Power Supply Voltage
Vcc
-0.3 to 3.6
V
Input Voltage to pins other than Vcc Pins
VIN
-0.3 to (Vcc+0.3)
VIN
(5)
Storage Temperature
Range
TSTG
TL
-65 to 150
+ 260
°C
°C
Lead Temperature (solder 4 sec.)
(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test
conditions, see the Electrical Characteristics. The guaranteed specifications apply only to for the test conditions listed.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(3) This device is has a ESD rating of ≥ 2500 V Human Body Model (HBM), ≥ 1750 V Charged Device Model (CDM), and ≥400 V Machine
Model (MM). It should only be assembled and handled in ESD-free workstations.
(4) Stresses in excess of the absolute maximum ratings can cause permanent or latent damage to the device. These are absolute stress
ratings only. Functional operation of the device is only implied at these or any other conditions in excess of those given in the
(5) Never to exceed 3.6 V.
Recommended Operating Conditions
Parameter
Symbol
Min
3.15
-40
Typ
Max
3.45
+85
Units
V
Power Supply Voltage
Vcc
3.3
(All Vcc Pins)
Ambient Temperature
TA
°C
Copyright © 2009–2013, Texas Instruments Incorporated
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Product Folder Links: LMX2541SQ2060E LMX2541SQ2380E LMX2541SQ2690E LMX2541SQ3030E
LMX2541SQ3320E LMX2541SQ3740E
LMX2541SQ2060E, LMX2541SQ2380E
LMX2541SQ2690E, LMX2541SQ3030E
LMX2541SQ3320E, LMX2541SQ3740E
SNOSB31I –JULY 2009–REVISED FEBRUARY 2013
www.ti.com
Package Thermal Resistance
Package
θJA
θJC
9 Thermal Vias
(Recommended for Most Reliable Solderability)
31.7 °C/W
7.3 °C/W
13 Thermal Vias
(Compromise Between Solderability, Heat Dissipation, and
Fractional Spurs)
30.3 °C/W
29.8 °C/W
7.3 °C/W
7.3 °C/W
16 Thermal Vias
(Recommended for Optimal Heat Dissipation and Fractional Spurs)
Electrical Characteristics
(3.15 V ≤ VCC ≤ 3.45 V, -40°C ≤ TA ≤ 85 °C; except as specified. Typical values are at Vcc = 3.3 V, 25 C.)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Current Consumption
Default Power VCO_DIV>1
Mode
170
130
72
204
156
94
Entire Chip Supply Current with
all blocks enabled
ICC
mA
mA
mA
µA
(1)
VCO_DIV=1
IPLL
Current for External VCO Mode
Current for Divider Only Mode
Power Down Current
RFoutEN = LOW
VCO_DIV >1
IDIV
Default Power Mode
84
110
250
(1)
ICCPD
CE = 0 V, Device Initialized
100
Oscillator (Normal Mode Operation with XO=0)
Oscillator Input High Current for
OSCin and OSCin*
IIHOSC in
IILOSCin
VIH = 2.75 V
300
µA
µA
Oscillator Input Low Current for
OSCin and OSCin* pins
VIL = 0
-100
OSC_2X = 1
5
5
52
OSCin Frequency Range
fOSCin
MODE = 0
700
900
MHz
(2)
OSC_2X = 0
MODE = 1
5
(2)
dvOSCin
vOSCin
Slew Rate
150
0.2
0.4
V/µs
Vpp
Single-Ended
dvOSCin ≥ 150 V/µs
2.0
3.1
Oscillator Sensitivity
Differential
Oscillator (Crystal Mode with XO=1)
fXTAL
Crystal Frequency Range
VIH = 2.75 V
5
20
MHz
Crystal Equivalent Series
Resistance
This a requirement for the crystal, not a characteristic
of the LMX2541.
ESRXTAL
100
Ω
This requirement is for the crystal, not a
characteristic of the LMX2541.
PXTAL
Power Dissipation in Crystal
Input Capacitance of OSCin
200
6
µW
pF
COSCin
PLL
fPD
Phase Detector Frequency
104
MHz
µA
CPG = 1X
100
200
300
...
CPG = 2X
Charge Pump
Output Current Magnitude
ICPout
CPG = 3X
...
CPG=32X
3200
1
ICPoutTRI CP TRI-STATE Current
0.4 V < VCPout < Vcc - 0.4
5
nA
%
Charge Pump
ICPoutMM
VCPout = Vcc / 2
TA = 25°C
3
10
Sink vs. Source Mismatch
(1) The LMX2541 RFout power level is programmable with the program words of VCOGAIN, OUTTERM, and DIVGAIN. Changing these
words can change the output power of the VCO as well as the current consumption of the output buffer. For the purpose of consistency
in electrical specifications, "Default Power Mode" is defined to be the settings of VCOGAIN = OUTTERM = DIVGAIN = 12.
(2) Not tested in production. Guaranteed by characterization. OSCin is tested only to 400 MHz.
6
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Product Folder Links: LMX2541SQ2060E LMX2541SQ2380E LMX2541SQ2690E LMX2541SQ3030E
LMX2541SQ3320E LMX2541SQ3740E
LMX2541SQ2060E, LMX2541SQ2380E
LMX2541SQ2690E, LMX2541SQ3030E
LMX2541SQ3320E, LMX2541SQ3740E
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SNOSB31I –JULY 2009–REVISED FEBRUARY 2013
Electrical Characteristics (continued)
(3.15 V ≤ VCC ≤ 3.45 V, -40°C ≤ TA ≤ 85 °C; except as specified. Typical values are at Vcc = 3.3 V, 25 C.)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Charge Pump
Current vs. CP Voltage Variation TA = 25°C
CP Current vs. Temperature
0.4 V < VCPout < Vcc - 0.4
ICPout
V
T
4
%
ICPout
VCPout = Vcc / 2
8
%
Variation
CPG = 1X
CPG = 32X
CPG = 1X
CPG = 32X
-116
Normalized PLL 1/f Noise
LNPLL_flicker(10 kHz)
dBc/Hz
-124.5
-220.8
-225.4
LN(f)
(3)
Normalized PLL Noise Floor
LNPLL_flat(1 Hz)
dBc/Hz
MHz
RFout Buffer Enabled and VCO_DIV > 1
RFout Buffer Disabled and VCO_DIV = 1
400
400
-15
-5
4000
6000
10
fExtVCOin PLL Input Frequency
f
ExtVCOin ≤ 4 GHz
fExtVCOin > 4 GHz
VCO Specifications
PLL Input Sensitivity
pExtVCOin
dBm
(
(2) applies to Max Limit Only)
10
2060E
2380E
2690E
3030E
3320E
3740E
1990
2200
2490
2810
3130
3480
2240
2530
2865
3230
3600
4000
Mode = Full Chip Mode
This is the frequency before the
VCO divider.
fVCO
Internal VCO Frequency Range
MHz
°C
Maximum Allowable Temperature
Drift for Continuous Lock
(4) (5)
ΔTCL
,
125
2060E
2380E
2690E
3030E
3320E
3740E
3.5
2.8
Maximum Frequency
Default Power Mode
VCO_DIV=1
1.6
RF Output Power
pRFout
dBm
(6)
1.2
0.2
- 0.3
Fixed Temperature with 100 MHz frequency change
at the output
0.3
0.4
ΔPRFout
Change in Output Power
dB
Fixed frequency with a change over the entire
temperature range
(3) Consult the Applications Information for more details on these parameters.
(4) Not tested in production. Guaranteed by characterization. OSCin is tested only to 400 MHz.
(5) Maximum Allowable Temperature Drift for Continuous Lock is how far the temperature can drift in either direction from the value it was
at the time that the R0 register was last programmed, and still have the device stay in lock. The action of programming the R0 register,
even to the same value, activates a frequency calibration routine. This implies that the device will work over the entire frequency range,
but if the temperature drifts more than the maximum allowable drift for continuous lock, then it will be necessary to reload the R0 register
to ensure that it stays in lock. Regardless of what temperature the device was initially programmed at, the temperature can never drift
outside the frequency range of -40°C ≤TA≤ 85°C without violating specifications.
(6) The measurement of the output power is sensitive to the test circuit. All the numbers in the electrical specifications and typical
performance curves were obtained from a characterization setup that accommodate temperature testing and changing of parts. In a
more optimized setup the measured RF output power is typically on the order of 1.5 to 2.4 dB higher.
Copyright © 2009–2013, Texas Instruments Incorporated
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Product Folder Links: LMX2541SQ2060E LMX2541SQ2380E LMX2541SQ2690E LMX2541SQ3030E
LMX2541SQ3320E LMX2541SQ3740E
LMX2541SQ2060E, LMX2541SQ2380E
LMX2541SQ2690E, LMX2541SQ3030E
LMX2541SQ3320E, LMX2541SQ3740E
SNOSB31I –JULY 2009–REVISED FEBRUARY 2013
www.ti.com
Units
Electrical Characteristics (continued)
(3.15 V ≤ VCC ≤ 3.45 V, -40°C ≤ TA ≤ 85 °C; except as specified. Typical values are at Vcc = 3.3 V, 25 C.)
Symbol
Parameter
Conditions
Min
Typ
Max
13 -
23
2060E
2380E
2690E
3030E
3320E
3740E
16 -
30
The lower number in the range
applies when the VCO is at its
lowest frequency and the higher
number applies when the VCO
is at its highest frequency. A
linear approximation can be
used for frequencies between
these two cases.
17 -
32
KVtune
Fine Tuning Sensitivity
MHz/V
20 -
37
21 -
37
24 -
42
Default Power Mode
VCO_DIV = 2
VCO_DIV = 3
VCO_DIV = 2
VCO_DIV = 3
-20
-20
3
Second Harmonic
(8)
HSRFout
dBc
%
(7)
50 Ω Load
Default Power Mode
Duty Cycle Error
(8)
DERFout
(7)
3
50 Ω Load
PSHVCO VCO Frequency Pushing
PULVCO VCO Frequency Pulling
CVregVCO = 4.7 µF, Open Loop
600
±800
±60
1.6
kHz/V
kHz
VCO_DIV = 1
VCO_DIV > 1
2060E
VSWR 1.7 to 1
(6 dB Pad)
Integration Bandwidth
= 100 Hz to 20 MHz
Middle VCO Frequency
100 MHz Wenzel Crystal
Reference
2380E
1.8
2690E
2.1
σΦ
RMS Phase Error
mRad
3030E
2.1
Integer Mode
Optimized Loop Bandwidth
3320E
2.3
3740E
2.6
(9)
VCO Phase Noise
10 kHz Offset
-89.7
-113.7
-134.9
-155.4
-160.3
-86.5
100 kHz Offset
1 MHz Offset
10 MHz Offset
20 MHz Offset
10 kHz Offset
100 kHz Offset
1 MHz Offset
10 MHz Offset
20 MHz Offset
fRFout
=
Min VCO
Frequency
Phase Noise
2060E
L(f)Fout
dBc/Hz
-111.4
-132.8
-153.4
-158.5
fRFout
=
Max VCO
Frequency
(7) The duty cycle error (DE) and second harmonic (HS) are theoretically related by the equation HS = 10·log| 2π·DE | - 6 dB. A square
wave with 3% duty cycle theoretically has a second harmonic of -20 dBc.
(8) The LMX2541 RFout power level is programmable with the program words of VCOGAIN, OUTTERM, and DIVGAIN. Changing these
words can change the output power of the VCO as well as the current consumption of the output buffer. For the purpose of consistency
in electrical specifications, "Default Power Mode" is defined to be the settings of VCOGAIN = OUTTERM = DIVGAIN = 12.
(9) The VCO phase noise is measured assuming that the loop bandwidth is sufficiently narrow that the VCO noise dominates. The phase
noise is measured with AC_TEMP_COMP = 5 and the device is reloaded at each test frequency. The typical performance
characteristics section shows how the VCO phase noise varies over temperature and frequency.
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SNOSB31I –JULY 2009–REVISED FEBRUARY 2013
Electrical Characteristics (continued)
(3.15 V ≤ VCC ≤ 3.45 V, -40°C ≤ TA ≤ 85 °C; except as specified. Typical values are at Vcc = 3.3 V, 25 C.)
Symbol
Parameter
Conditions
10 kHz Offset
Min
Typ
Max
Units
-87.9
100 kHz Offset
1 MHz Offset
10 MHz Offset
20 MHz Offset
10 kHz Offset
100 kHz Offset
1 MHz Offset
10 MHz Offset
20 MHz Offset
10 kHz Offset
100 kHz Offset
1 MHz Offset
10 MHz Offset
20 MHz Offset
10 kHz Offset
100 kHz Offset
1 MHz Offset
10 MHz Offset
20 MHz Offset
10 kHz Offset
100 kHz Offset
1 MHz Offset
10 MHz Offset
20 MHz Offset
10 kHz Offset
100 kHz Offset
1 MHz Offset
10 MHz Offset
20 MHz Offset
10 kHz Offset
100 kHz Offset
1 MHz Offset
10 MHz Offset
20 MHz Offset
10 kHz Offset
100 kHz Offset
1 MHz Offset
10 MHz Offset
20 MHz Offset
-112.7
-133.8
-154.2
-159.5
-83.4
fRFout
Min VCO
Frequency
=
Phase Noise
2380E
L(f)Fout
dBc/Hz
-109.1
-130.8
-151.8
-157.5
-86.9
fRFout
Max VCO
Frequency
=
-111.8
-133.3
-154.2
-159.4
-82.3
fRFout
Min VCO
Frequency
=
Phase Noise
2690E
L(f)Fout
L(f)Fout
L(f)Fout
dBc/Hz
dBc/Hz
dBc/Hz
-108.4
-130.3
-151.1
-156.7
-86.1
fRFout
Max VCO
Frequency
=
-110.5
-132.0
-152.2
-157.1
-82.2
fRFout
Min VCO
Frequency
=
Phase Noise
3030E
-107.7
-129.4
-150.5
-156.1
-84.1
fRFout
Max VCO
Frequency
=
-109.1
-130.7
-151.6
-156.9
-82.0
fRFout
Min VCO
Frequency
=
Phase Noise
3320E
-107.0
-128.5
-149.6
-155.2
fRFout
Max VCO
Frequency
=
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LMX2541SQ2690E, LMX2541SQ3030E
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Units
Electrical Characteristics (continued)
(3.15 V ≤ VCC ≤ 3.45 V, -40°C ≤ TA ≤ 85 °C; except as specified. Typical values are at Vcc = 3.3 V, 25 C.)
Symbol
Parameter
Conditions
10 kHz Offset
Min
Typ
Max
-83.9
100 kHz Offset
1 MHz Offset
10 MHz offset
20 MHz Offset
10 kHz Offset
100 kHz Offset
1 MHz Offset
10 MHz Offset
20 MHz Offset
-108.3
-129.9
-150.6
-156.5
-81.6
fRFout
Min VCO
Frequency
=
Phase Noise
3740E
L(f)Fout
dBc/Hz
-106.5
-127.7
-148.6
-154.2
fRFout
Max VCO
Frequency
=
Digital Interface (DATA, CLK, LE, CE, Ftest/LD, FLout,RFoutEN)
VIH
VIL
High-Level Input Voltage
Low-Level Input Voltage
High-Level Input Current
Low-Level Input Current
High-Level Output Voltage
Low-Level Output Voltage
Leakage Current
1.6
Vcc
0.4
5
V
V
IIH
VIH = 1.75, XO = 0
-5
-5
µA
µA
V
IIL
VIL = 0 V , XO = 0
5
VOH
VOL
ILeak
IOH = 500 µA
2.0
IOL = -500 µA
0.0
0.4
5
V
Ftest/LD and FLout Pins Only
MICROWIRE Timing
See Data Input Timing
See Data Input Timing
See Data Input Timing
See Data Input Timing
See Data Input Timing
-5
µA
tCE
Clock to Enable Low Time
Data to Clock Set Up Time
Data to Clock Hold Time
Clock Pulse Width High
Clock Pulse Width Low
25
25
20
25
25
25
25
ns
ns
ns
ns
ns
ns
ns
tCS
tCH
tCWH
tCWL
tCES
tEWH
Enable to Clock Set Up Time
Enable Pulse Width High
See Data Input Timing
See Data Input Timing
Serial Data Timing Diagram
MSB
LSB
C0
DATA
CLK
LE
D19
D18
D17
D16
D15
D0
C3
C2
C1
t
t
CWH
CS
t
ES
t
t
CH
CES
t
CWL
t
EWH
There are several other considerations for programming:
•
The DATA is clocked into a shift register on each rising edge of the CLK signal. On the rising edge of the LE
signal, the data is sent from the shift registers to an actual counter.
•
•
•
A slew rate of at least 30 V/μs is recommended for the CLK, DATA, and LE signals.
After the programming is complete, the CLK, DATA, and LE signals should be returned to a low state.
When using the part in Full Chip Mode with the Integrated VCO, LE should be kept high no more than 1 us
after the programming of the R0 register. Failure to do so may interfere with the digital VCO calibration.
•
If the CLK and DATA lines are toggled while the in VCO is in lock , as is sometimes the case when these
lines are shared with other parts, the phase noise may be degraded during the time of this programming.
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LMX2541SQ2690E, LMX2541SQ3030E
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SNOSB31I –JULY 2009–REVISED FEBRUARY 2013
Typical Performance Characteristics (Not Guaranteed)
LMX2541SQ3740E Raw Phase Noise Measurement
-80
-85
-90
-95
-100
-105
-110
Measured Noise
1/f Noise
-115
-120
Noise Floor
1.E+05
1.E+02
1.E+03
1.E+04
OFFSET (Hz)
1.E+06
1.E+07
The above plot demonstrates the PLL phase noise of the LMX2541SQ3700E operating at 3700 MHz output frequency, phase detector
frequency of 100 MHz, and charge pump gain of 32X. The loop bandwidth was made as wide as possible to fully expose the PLL phase
noise and reference source was a 100 MHz Wenzel crystal. This measurement was done in integer mode. To better understand the impact of
using fractional mode, consult the applications section.
The measured noise is the sum of the PLL 1/f noise and noise floor. At offsets below 1 kHz, the PLL 1/f noise dominates and changes at a
rate of 10 dB/decade. The noise at 1 kHz is dominated by this 1/f noise and has a value of -103 dBc/Hz. In the 100 - 200 kHz offset range,
the noise is -113.7 dBc/Hz and is dominated by the PLL noise floor. It can be shown that if the effects of the loop filter peaking and the 1/f
noise are subtracted away from this measurement, it would be about 0.6 dB better.
If the phase detector frequency is changed with the VCO frequency held constant, the PLL noise floor will change, but the 1/f noise will
remain the same. If the VCO frequency is changed, both the 1/f noise and PLL noise floor change at a rate of 20 dB/decade.
Figure 2.
LMX2541SQ2690 System Phase Noise
-70
sf = 4.7 mRad
(FPD = 50 MHz)
-80
-90
-100
-110
sf = 4.2 mRad
(OSCin Scaled to Freq.)
-120
-130
-140
sf = 4.4 mRad
(FPD = 100 MHz)
-150
-160
1.E+02
1.E+03
1.E+04
1.E+05
1.E+06
1.E+07
1.E+08
OFFSET (Hz)
For this plot, a third order modulator with dithering disabled was used with a fractional denominator of 500000. The charge pump gain was
32X and the loop filter components were C1 = 2.2 nF, C2 = 22 nF, R2 = 470 Ω. The internal loop filter components were C3_LF = 20 pF,
C4_LF = 100 pF, R3_LF = 1 kΩ, R4_LF = 200 Ω. The VCO frequency is 2720.1 MHz. The OSCin signal was a 500 MHz differential LVPECL
output of the LMK04033.
Figure 3.
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LMX2541SQ2060E, LMX2541SQ2380E
LMX2541SQ2690E, LMX2541SQ3030E
LMX2541SQ3320E, LMX2541SQ3740E
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Typical Performance Characteristics (Not Guaranteed) (continued)
LMX2541SQ3320E System Phase Noise
-70
-80
sf = 5.8 mRad
(FPD = 50 MHz)
-90
-100
-110
sf = 5.1 mRad
(OSCin Scaled to Freq.)
-120
-130
-140
sf = 5.1 mRad
(FPD = 100 MHz)
-150
-160
1.E+02
1.E+03
1.E+04
1.E+05
1.E+06
1.E+07
1.E+08
OFFSET (Hz)
For this plot, a third order modulator with dithering disabled was used with a fractional denominator of 500000. The charge pump gain was
32X and the loop filter components were C1 = 2.2 nF, C2 = 22 nF, R2 = 470 Ω. The internal loop filter components were C3_LF = 20 pF,
C4_LF = 100 pF, R3_LF = 1 kΩ, R4_LF = 200 Ω. The VCO frequency is 3320.1 MHz. The OSCin signal was a 500 MHz differential LVPECL
output of the LMK04033.
Figure 4.
LMX2541SQ3740E System Phase Noise
-70
s = 3.3 mRad
(FPD = 50 MHz)
f
-80
-90
-100
-110
s = 3.0 mRad
(OSCin Scaled to Freq.)
f
-120
-130
-140
s = 2.8 mRad
(FPD = 100 MHz)
f
-150
-160
1.E+02
1.E+03
1.E+04
1.E+05
1.E+06
1.E+07
1.E+08
OFFSET (Hz)
For this plot, a third order modulator with dithering disabled was used with a fractional denominator of 500000. The charge pump gain was
32X and the loop filter components were C1 = 2.2 nF, C2 = 22 nF, R2 = 470 Ω. The internal loop filter components were C3_LF = 20 pF,
C4_LF = 100 pF, R3_LF = 1 kΩ, R4_LF = 200 Ω. The VCO frequency is 3840.2 MHz, but the VCO Divider is set to two, so the RFout
frequency is 1720.1 MHz. The OSCin signal was a 500 MHz differential LVPECL output of the LMK04033.
Figure 5.
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LMX2541SQ2060E, LMX2541SQ2380E
LMX2541SQ2690E, LMX2541SQ3030E
LMX2541SQ3320E, LMX2541SQ3740E
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SNOSB31I –JULY 2009–REVISED FEBRUARY 2013
Typical Performance Characteristics (Not Guaranteed) (continued)
Divider Noise Floor
vs.
Divider Value
(fVCO = 3700 MHz, Various values for VCO_DIV)
-90
-100
-110
-120
-130
-140
VCO_DIV = 1
VCO_DIV = 2
VCO_DIV = 3
VCO_DIV = 4
VCO_DIV = 5
VCO_DIV = 6
1.E+05
-150
-160
1.E+02
1.E+03
1.E+04
1.E+06
1.E+07
1.E+08
OFFSET (Hz)
When the divider is engaged (VCO_DIV >0), then the entire system phase noise is reduced by a factor of 20 × log(VCO_DIV). However, the
noise floor of the divider will also add to this noise as is visible at far offsets. Note that the noise floor for Bypass mode is lower because the
VCO divider is not engaged.
Figure 6.
Divider Noise Floor
vs.
Frequency
-146
-150
-154
-158
-162
10
100
1000
FREQUENCY (MHz)
Provided the VCO divider is not bypassed, the actual value of it does not impact the divider noise floor; it is the frequency at the RFout pin
that impacts the divider noise floor. The above plot shows how this noise floor changes as a function of the frequency of the RFout pin.
Figure 7.
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LMX2541SQ2690E, LMX2541SQ3030E
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Typical Performance Characteristics (Not Guaranteed) (continued)
PLL Normalized Noise Floor
vs.
PLL Normalized Noise Floor
vs.
Charge Pump Gain
(Slew Rate = 2000 V/μs)
OSCin Slew Rate
(KPD = 32X)
-216
-206
-210
-214
-218
-222
-226
-218
-220
-222
-224
-226
1
2
3
4
1X
2X
4X
8X
16X
32X
10
10
10
10
CHARGE PUMP GAIN
SLEW RATE (V/ms)
Figure 8.
Figure 9.
PLL Normalized 1/f Noise
vs.
PLL Normalized 1/f Noise
vs.
Charge Pump Gain
(Slew Rate = 2000 V/μs)
OSCin Slew Rate
(KPD = 32X)
-115
-105
-109
-113
-117
-121
-125
-117
-119
-121
-123
-125
1
2
3
4
1X
2X
4X
8X
16X
32X
10
10
10
10
CHARGE PUMP GAIN
SLEW RATE (V/ms)
Figure 10.
Figure 11.
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LMX2541SQ2690E, LMX2541SQ3030E
LMX2541SQ3320E, LMX2541SQ3740E
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SNOSB31I –JULY 2009–REVISED FEBRUARY 2013
Typical Performance Characteristics (Not Guaranteed) (continued)
VCO Phase Noise Degradation
vs.
Temperature and Offset
(VCO Relocked at Each Temperature
Vcc = 3.3 V, AC_TEMP_COMP = 5)
3
2
10 kHz
20 MHz
1 MHz
1
0
10 MHz
-1
100 kHz
-2
-3
-40
-20
0
20
40
60
80
100
TEMPERATURE (oC)
The above plot shows how much the VCO phase noise typically change over temperature relative to room temperature. The typical values for
represent an average over all frequencies and part options and therefore there are some small variations over part options and frequencies
that are not shown. VCO phase noise numbers room temperature are reported in the electrical specifications. A negative value indicates a
phase noise improvement.
Figure 12.
Table 1. Relative VCO Phase Noise Over Temperature Drift
(AC_TEMP_COMP = 24, Vcc = 3.3 V)(1)
Temperature
Current
Phase Noise Change in Celsius for Various Offsets
Lock
-40
-40
-40
25
10 kHz
+0.4
100 kHz
-2.0
1 MHz
-1.6
10 MHz
-1.8
20 MHz
-1.6
-40
25
85
-40
25
85
-40
25
85
+0.3
+0.5
+0.5
+2.4
-1.7
+0.5
+0.4
+0.9
+2.0
+2.5
+2.3
+0.2
-2.2
-2.0
-1.8
25
This is the default condition to which these other numbers are normalized to.
25
+0.6
+0.2
+0.2
+0.6
+1.5
-2.2
+2.0
-1.7
+2.0
-1.9
+1.9
-1.8
85
85
+0.2
+1.8
+0.3
+2.2
+0.2
+2.3
+0.2
+2.1
85
(1) The table shows the typical degradation for VCO phase noise when the VCO is locked at one temperature and the temperature is
allowed to drift to another temperature. A negative value indicates a phase noise improvement.
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LMX2541SQ2690E, LMX2541SQ3030E
LMX2541SQ3320E, LMX2541SQ3740E
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The following plots show the trends in output power as a function of temperature, voltage, and frequency. For
states where VCOGAIN and OUTTERM are not 12, the table below shows how the output power is modified
based on these programmable settings.
Output Power
vs.
Voltage
Output Power
vs.
(VCO_DIV = 1, VCOGAIN = 12, OUTTERM = 12,
OUTTERM and FREQUENCY
TA = 25°C(2)
)
(VCO_DIV = 1, TA = 25 °C, Vcc = 3.3 V, VCOGAIN = 12(2)
)
5
4
6
OUTTERM=12
Vcc = 3.3V
OUTTERM=15
2
3
Vcc = 3.45V
2
-2
1
OUTTERM=9
OUTTERM=6
0
-6
Vcc = 3.15V
-1
OUTTERM=3
-10
-2
1750
1750
2250
2750
3250
3750
4250
2250
2750
3250
3750
4250
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 13.
Figure 14.
Output Power
vs.
Output Power
vs.
Temperature
(VCO_DIV = 1, VCOGAIN = 12, OUTTERM = 12,
VCOGAIN and FREQUENCY
Vcc = 3.3 V(2)
)
(VCO_DIV = 1, TA = 25 °C, Vcc = 3.3 V, OUTTERM = 12(2)
)
5
4
6
T
= 25o C
VCOGAIN=12
A
T
= -40o C
VCOGAIN=15
A
2
3
VCOGAIN=9
2
-2
1
VCOGAIN=6
T
A
= 85o C
0
-6
VCOGAIN=3
-1
-2
1750
-10
1750
2250
2750
3250
3750
4250
2250
2750
3250
3750
4250
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 15.
Figure 16.
(2) The measurement of the output power is sensitive to the test circuit. All the numbers in the electrical specifications and typical
performance curves were obtained from a characterization setup that accommodate temperature testing and changing of parts. In a
more optimized setup the measured RF output power is typically on the order of 1.5 to 2.4 dB higher.
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LMX2541SQ2690E, LMX2541SQ3030E
LMX2541SQ3320E, LMX2541SQ3740E
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SNOSB31I –JULY 2009–REVISED FEBRUARY 2013
Table 2. Change in Output Power in Bypass Mode as a Function of VCOGAIN and OUTTERM
VCOGAIN
3
6
9
12
15
3
6
-9.7
-6.6
-5.7
-5.4
-5.3
-8.4
-4.5
-3.1
-2.5
-2.2
-7.9
-3.6
-1.7
-0.8
-0.3
-7.8
-3.4
-1.3
+0.0
+0.8
-7.9
-3.6
-1.3
+0.1
+1.1
OUTTERM
9
12
15
Output Power
vs.
Output Power
vs.
Voltage
(VCO_DIV > 1, DIVGAIN = 12, OUTTERM = 12,
TA = 25°C
OUTTERM and FREQUENCY
(VCO_DIV > 1, TA = 25 °C, Vcc = 3.3 V, DIVGAIN = 12
(1)
(1)
)
)
10
9
OUTTERM=15
Vcc = 3.3 V
8
8
OUTTERM=12
6
7
4
6
Vcc = 3.45 V
OUTTERM=6
2
5
4
3
0
OUTTERM=9
-2
-4
2
-6
1
Vcc = 3.15 V
OUTTERM=3
-8
0
-10
-1
0
500
1000
1500
2000
2500
0
500
1000
1500
2000
2500
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 17.
Figure 18.
Output Power
vs.
Temperature
Output Power
vs.
( VCO_DIV > 1, DIVGAIN = OUTTERM = 12,
Vcc(=1) 3.3 V
DIVGAIN and FREQUENCY
)
(1)(VCO_DIV > 1, TA = 25 °C, Vcc = 3.3 V, OUTTERM = 12 )
10
9
DIVGAIN=15
8
8
DIVGAIN=12
6
4
2
0
7
6
T
= -40o C
A
5
4
3
T
A
= 25o C
DIVGAIN=6
-2
-4
2
1
DIVGAIN=9
-6
-8
T
= 85o C
A
0
DIVGAIN=3
-10
-1
0
500
1000
1500
2000
2500
0
500
1000
1500
2000
2500
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 19.
Figure 20.
Table 3. Change in Output Power in Divided Mode as a Function of DIVGAIN and OUTTERM(1)
DIVGAIN
3
6
9
12
15
(1) The measurement of the output power is sensitive to the test circuit. All the numbers in the electrical specifications and typical
performance curves were obtained from a characterization setup that accommodate temperature testing and changing of parts. In a
more optimized setup the measured RF output power is typically on the order of 1.5 to 2.4 dB higher.
(1) The table shows the RELATIVE output power to the case of VCOGAIN = OUTTERM = 12.
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Table 3. Change in Output Power in Divided Mode as a Function of DIVGAIN and OUTTERM(1) (continued)
3
6
-10.2
-9.8
-9.8
-9.9
-9.9
-6.1
-4.4
-4.3
-4.3
-4.4
-5.7
-2.4
-1.5
-1.4
-1.4
-5.5
-2.1
-0.7
+0.0
+0.3
-5.5
-2.0
-0.5
+0.2
+0.7
OUTTERM
9
12
15
The impedance of the RFout pin varies as a function of frequency, VCO_DIV, OUTTERM, VCOGAIN, DIVGAIN, and
frequency. When in bypass mode (VCO_DIV = 1), the DIVGAIN word has no impact on the output impedance. When
in divided mode (VCO_DIV>1), the VCOGAIN has no impact on the output impedance. This graphic shows how the
input impedance varies as a function of frequency for both the bypass and divided cases.
4
2
1
3
Marker 1:
1 GHz
1
VCO_DIV
= 1
2
Marker 2:
2 GHz
VCO_DIV > 1
Marker 3:
3 GHz
Marker 4:
4 GHz
Start 30 MHz
Stop 5 GHz
Figure 21. RFout Output Impedance
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LMX2541SQ2690E, LMX2541SQ3030E
LMX2541SQ3320E, LMX2541SQ3740E
www.ti.com
SNOSB31I –JULY 2009–REVISED FEBRUARY 2013
Table 4. RFout Output Impedance vs. VCOGAIN (Bypass Mode)(1)
VCOGAIN=3
VCOGAIN=6
VCOGAIN=9
VCOGAIN=12
VCOGAIN=15
Freq.
(MHz)
Real
Imaginary
2.1
Real
Imaginary
1.9
Real
Imaginary
1.8
Real
Imaginary
1.7
Real
Imaginary
1.7
50
3.8
4.8
5.5
6.1
7.3
7.8
9.5
9.8
10.1
10.3
11.4
13.1
14.5
16.7
19.8
20.0
20.2
20.5
20.7
19.8
20.4
19.2
17.3
17.1
16.4
18.4
21.5
29.8
33.4
34.8
36.0
40.8
52.3
74.0
102.4
100
4.1
3.9
3.7
3.6
3.6
200
5.4
5.7
6.8
6.0
8.7
6.3
10.9
12.4
13.7
15.8
19.0
19.3
19.7
20.1
20.5
19.6
20.3
19.0
17.2
17.0
16.3
18.4
21.7
30.2
34.1
35.5
37.2
42.3
54.3
76.7
105.4
6.5
6.6
400
5.5
9.4
7.5
10.0
15.4
20.8
26.1
27.9
29.7
31.5
33.3
37.4
40.7
45.3
48.7
55.3
64.0
73.2
82.8
90.2
94.4
99.0
109.8
126.6
138.1
145.6
135.5
9.8
10.6
15.7
20.8
25.6
26.9
28.2
29.5
30.8
35.0
38.2
42.8
46.5
52.4
60.5
69.0
77.4
83.6
87.3
92.0
101.9
117.6
129.5
140.1
138.0
11.0
15.7
20.3
24.6
25.5
26.4
27.4
28.3
32.5
35.6
40.1
43.5
49.0
56.5
64.2
71.8
76.7
80.5
85.1
94.2
109.5
122.2
135.9
141.1
11.0
15.6
20.1
24.1
25.0
25.9
26.8
27.7
31.9
35.0
39.4
42.5
48.3
55.7
63.3
70.8
75.6
79.4
83.7
93.0
108.3
121.2
135.5
141.9
600
5.8
15.1
20.7
26.3
28.6
30.9
33.2
35.5
39.5
42.9
47.6
51.3
57.9
67.1
77.3
88.1
96.0
99.4
106.0
119.3
137.9
149.4
153.7
134.7
8.1
10.7
12.6
15.4
16.3
17.1
18.0
18.8
17.9
18.7
17.4
15.6
15.3
14.8
17.3
21.1
30.9
36.4
38.9
43.1
49.8
65.4
93.0
124.9
800
7.0
9.6
1000
1200
1400
1600
1800
2000
2200
2400
2600
2800
3000
3200
3400
3600
3800
4000
4200
4400
4600
4800
5000
9.2
12.1
13.4
14.7
15.9
17.2
16.4
17.4
16.0
14.1
13.7
13.1
15.7
20.0
30.6
38.0
41.6
45.9
56.4
76.0
109.7
145.4
10.7
12.2
13.7
15.2
14.5
15.6
14.2
12.2
11.5
10.6
13.1
17.6
29.0
38.2
43.5
48.0
62.4
87.0
128.1
168.1
(1) This is for the VCO divider in bypass mode (VCO_DIV=1) and the RFout pin powered up. OUTTERM was set to 12.
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Table 5. RFout Output Impedance vs. OUTTERM (Bypass Mode)(1)
OUTTERM=3
OUTTERM=6
OUTTERM=9
OUTTERM=12
Real Imaginary
9.5 1.7
TERM=15
Freq.
(MHz)
Real
Imaginary
1.6
Real
Imaginary
1.9
Real
Imaginary
1.8
Real
7.8
Imaginary
1.7
50
27.9
28.5
29.2
28.8
28.8
29.1
28.6
28.0
27.5
27.0
26.4
25.9
25.3
23.1
20.1
18.5
16.6
16.5
17.1
20.8
22.0
23.0
23.7
23.7
27.3
40.1
61.4
16.2
16.7
18.1
19.2
20.4
22.5
22.8
23.1
23.3
23.6
23.9
24.1
24.4
22.9
20.5
19.6
18.1
18.9
20.4
25.4
27.3
28.1
28.6
30.1
36.6
52.2
76.2
12.3
12.7
14.0
15.3
16.5
18.7
19.3
19.8
20.4
20.9
21.4
22.0
22.5
21.3
19.3
18.8
17.8
19.3
21.8
28.3
31.1
32.1
32.8
35.4
44.8
63.3
89.5
100
2.8
3.6
3.6
9.8
10.9
12.4
13.7
15.8
16.5
17.1
17.7
18.4
19.0
19.6
20.3
19.0
17.2
17.0
16.3
18.4
21.7
30.2
34.1
35.5
37.0
42.3
54.3
76.7
105.5
3.6
6.5
8.0
3.5
200
3.8
5.9
6.3
9.0
6.6
400
5.7
9.5
10.3
14.9
19.2
21.2
23.2
25.2
27.2
29.2
31.1
33.1
37.1
39.6
45.0
51.9
58.9
65.8
70.5
74.6
80.0
87.7
102.9
116.3
132.3
142.3
11.0
15.7
20.3
22.5
24.7
26.9
29.0
31.2
33.4
35.6
40.1
42.9
49.0
56.5
64.2
71.8
76.8
80.5
86.4
94.2
109.4
122.2
135.9
141.0
10.6
11.9
14.0
14.6
15.2
15.8
16.5
17.1
17.7
18.3
17.0
15.1
14.8
14.3
16.7
20.4
30.3
35.4
37.6
39.9
47.8
62.6
89.3
121.0
11.2
16.0
20.8
23.1
25.4
27.7
30.0
32.3
34.6
36.9
41.8
44.9
51.6
59.7
68.2
76.6
82.5
86.1
92.0
100.9
116.6
128.9
140.5
140.5
600
8.8
13.7
17.5
19.2
20.9
22.7
24.4
26.1
27.9
29.6
33.2
35.4
40.4
46.9
53.4
60.1
65.0
69.7
74.9
82.8
98.0
112.0
129.8
143.3
800
11.7
13.4
15.0
16.7
18.4
20.1
21.8
23.5
26.9
29.3
34.2
40.6
47.0
53.8
59.4
64.9
70.0
77.9
93.2
107.4
126.6
142.8
1000
1200
1400
1600
1800
2000
2200
2400
2600
2800
3000
3200
3400
3600
3800
4000
4200
4400
4600
4800
5000
(1) The VCO divider was bypassed (VCO_DIV = 1) and the RFout pin was enabled. The VCOGAIN word was set to 12.
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LMX2541SQ3320E, LMX2541SQ3740E
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SNOSB31I –JULY 2009–REVISED FEBRUARY 2013
Table 6. RFout Output Impedance vs. DIVGAIN (Divided Mode)(1)
DIVGAIN=3
DIVGAIN=6
DIVGAIN=9
DIVGAIN=12
DIVGAIN=15
Freq.
(MHz)
Real
Imaginary
2.2
Real
Imaginary
2.1
Real
Imaginary
2.0
Real
Imaginary
1.9
Real
Imaginary
1.6
50
3.2
4.5
3.6
4.6
5.8
6.6
13.9
14.7
15.0
15.6
15.9
16.9
18.7
21.4
22.5
22.5
21.6
20.9
21.7
20.4
18.2
17.0
15.2
16.5
19.4
26.1
28.9
32.3
26.6
37.8
49.9
73.7
107.1
22.3
23.2
23.0
22.8
22.2
22.3
22.9
24.3
23.9
23.1
21.7
20.6
20.9
19.3
16.8
15.3
13.0
13.8
16.0
21.7
24.0
27.1
20.7
30.0
40.3
61.7
94.5
100
4.1
4.0
3.8
3.2
2.3
200
5.7
5.3
6.4
5.7
7.0
5.9
4.7
2.7
400
5.0
9.2
5.6
9.4
7.7
9.5
7.7
4.4
600
5.2
14.6
20.2
25.7
29.9
32.3
34.4
37.2
41.1
45.1
49.4
52.1
59.3
68.3
78.6
89.6
98.6
105.8
101.4
122.9
143.0
155.3
159.1
135.1
5.7
14.6
20.2
25.7
30.0
32.3
34.3
37.0
40.9
44.7
49.0
51.6
58.7
67.6
77.6
88.4
96.9
103.9
99.5
120.3
139.6
151.4
155.7
133.9
7.8
14.6
20.2
25.5
29.5
31.7
33.5
36.2
39.9
43.6
47.7
50.1
56.8
65.2
74.5
84.4
91.6
97.5
92.9
111.8
128.6
139.6
145.5
131.4
12.1
16.5
20.5
23.1
24.3
25.8
28.2
31.4
34.5
38.1
40.4
46.2
53.4
61.1
69.2
75.4
81.1
78.8
94.7
111.4
125.8
142.1
147.7
7.9
800
6.0
6.5
8.7
11.4
14.6
16.8
18.2
20.1
22.9
26.4
29.7
33.5
36.2
42.0
49.2
56.9
65.1
71.6
77.8
76.3
91.8
109.2
124.9
144.0
155.2
1000
1200
1400
1600
1800
2000
2200
2400
2600
2800
3000
3200
3400
3600
3800
4000
4200
4400
4600
4800
5000
7.9
8.4
10.7
13.9
16.1
17.1
16.7
16.4
17.8
17.1
15.5
15.0
14.0
16.7
21.6
31.9
37.8
43.7
40.6
59.9
81.1
116.3
153.3
11.0
13.2
14.2
13.9
13.5
14.8
14.1
12.4
11.8
10.7
13.1
18.1
29.2
36.0
43.6
40.6
63.6
90.9
135.8
179.4
11.6
13.9
15.0
14.6
14.3
15.6
14.9
13.2
12.5
11.5
14.0
18.9
29.8
36.5
43.7
40.8
62.9
88.8
131.2
173.2
(1) This was done with RFout buffer powered up and with OUTTERM=12. VCO_DIV was set to 50.
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Table 7. RFout Output Impedance vs. OUTTERM (Divided Mode)(1)
OUTTERM=3
OUTTERM=6
OUTTERM=9
OUTTERM=12
Imaginary
OUTTERM=15
Freq.(MHz)
Real
Imaginary
-0.3
Real
Imaginary
1.0
Real
Imaginary
1.7
Real
14.0
14.8
16.1
15.7
15.9
16.9
18.7
21.4
22.5
22.5
21.6
20.9
21.7
20.4
18.2
17.0
15.2
16.5
19.4
26.1
28.9
32.3
26.6
37.8
49.8
73.7
107.2
Real
9.3
Imaginary
2.0
50
44.1
44.9
43.2
33.2
28.0
25.1
23.7
23.5
22.6
21.5
20.2
19.1
19.4
17.9
15.7
14.5
12.7
13.5
15.5
20.9
22.7
25.4
19.0
26.6
34.9
52.1
78.5
31.8
32.8
33.2
28.5
25.7
24.0
23.3
23.7
22.9
21.8
20.5
19.4
19.7
18.2
15.9
14.5
12.6
13.3
15.4
21.1
23.1
26.2
19.8
28.3
37.8
57.4
87.4
21.2
22.1
23.3
21.9
21.4
21.7
22.4
23.8
23.5
22.6
21.3
20.1
20.5
18.9
16.5
15.1
12.9
13.8
15.9
21.7
23.9
27.1
20.7
29.9
40.1
61.1
93.3
1.9
3.2
100
-2.2
0.7
2.5
10.0
11.3
11.2
11.4
12.5
14.6
17.7
19.5
20.2
19.7
19.3
20.6
19.8
17.9
17.2
15.8
18.0
22.0
30.5
34.7
39.0
34.6
49.4
65.3
93.8
129.0
3.5
200
-7.2
-1.2
2.8
4.7
5.6
400
-8.1
-1.5
4.5
7.7
9.1
600
-3.8
1.8
8.0
12.1
16.5
20.5
23.1
24.3
25.8
28.2
31.4
34.5
38.1
40.4
46.2
53.4
61.1
69.2
75.4
81.1
78.8
94.7
111.4
125.9
141.9
148.0
13.9
19.0
23.8
27.2
28.9
30.5
33.0
36.4
39.8
43.6
45.7
51.9
59.5
67.8
76.5
82.8
88.2
84.7
101.8
118.0
130.6
141.8
138.6
800
1.1
5.6
11.5
14.7
16.7
18.1
20.0
22.8
26.3
29.6
33.4
36.1
42.0
49.2
56.9
65.0
71.5
77.6
76.1
91.4
108.7
124.1
143.1
154.0
1000
1200
1400
1600
1800
2000
2200
2400
2600
2800
3000
3200
3400
3600
3800
4000
4200
4400
4600
4800
5000
5.8
9.6
9.3
12.4
14.8
17.4
20.7
24.5
28.0
32.0
34.9
40.7
47.9
55.5
63.5
70.0
76.0
74.5
89.5
106.3
121.5
140.3
152.0
12.3
15.3
18.8
22.9
26.4
30.4
33.3
39.0
46.1
53.5
61.3
67.5
73.3
71.7
86.1
102.0
116.4
134.8
147.4
(1) This was done in divided mode (VCO_DIV=50) with VCOGAIN=12.
22
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LMX2541SQ2060E, LMX2541SQ2380E
LMX2541SQ2690E, LMX2541SQ3030E
LMX2541SQ3320E, LMX2541SQ3740E
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SNOSB31I –JULY 2009–REVISED FEBRUARY 2013
OSCin Sensitivity for Single-Ended SINE Wave
20
10
0
Guaranteed
Operating
Range
-10
-20
-30
-40
1
10
100
1000
f
(MHz)
OSCin
The above chart shows the typical sensitivity for a sine wave. Note that at lower frequencies, there is a constant slope that
suggests that the part fails when the slew rate falls below 27 V/us. The electrical specifications call for a minimum of 150 V/us to
ensure margin. Also, as some of the other performance graphs show, the OSCin slew rate has an impact on fractional spurs and
phase noise as well. It is recommended to design to the electrical specifications, not the typical performance plots.
Variation over voltage and temperature is typically very small and on the order than less ±1 dB.
Figure 22.
SINE wave ExtVCOin Sensitivity
20
10
T
= 25oC
A
Guaranteed Operating
Range
0
-10
-20
-30
-40
T
= 85oC
A
T
A
= -40oC
1000
2000
4000
6000
0
3000
5000
7000
8000
fExtVCOin (MHz)
The above plot shows the ExtVCOin sensitivity which applies only when the device is being used in External VCO mode.
Variation over voltage is typically very small and on the order of less than ± 1 dB.
Figure 23.
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LMX2541SQ2060E, LMX2541SQ2380E
LMX2541SQ2690E, LMX2541SQ3030E
LMX2541SQ3320E, LMX2541SQ3740E
SNOSB31I –JULY 2009–REVISED FEBRUARY 2013
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OSCin Input Impedance
Marker 1:
50 MHz
Marker 2:
100 MHz
Marker 3:
500 MHz
1
XO = 1
4
2
Marker 4:
1000 MHz
3
2
XO = 0
4
Start 50 MHz
Stop 1000 MHz
3
Figure 24.
OSCin (Normal Mode)
OSCin (XO Mode)
OSCin# (Normal Mode)
Frequency (MHz)
Real
3945.3
4846.0
4253.4
2295.3
1290.0
847.9
581.3
439.2
337.9
269.4
223.4
179.2
52.4
Imaginary
2261.6
-189.6
-1850.1
-2366.9
-2087.0
-1716.1
-1464.9
-1254.1
-1105.7
-983.6
-869.9
-776.8
-379.8
-247.0
-181.7
-140.5
-110.2
-88.0
Real
9452.3
2397.9
428.2
248.4
187.1
163.5
147.9
138.3
131.1
127.0
119.7
114.5
93.9
Imaginary
2182.1
-916.7
-1105.7
-591.8
-410.1
-313.3
-257.1
-219.0
-192.0
-171.8
-158.0
-143.9
-85.1
Real
3975.5
4890.1
4297.4
2288.6
1304.3
855.5
590.7
449.4
349.0
276.3
231.9
186.9
54.3
Imaginary
2287.0
-150.1
-1886.7
-2383.8
-2079.1
-1718.0
-1471.6
-1264.2
-1115.4
-989.1
-876.2
-783.9
-382.5
-247.4
-180.5
-138.4
-107.6
-85.3
1
5
10
20
30
40
50
60
70
80
90
100
200
300
400
500
600
700
800
900
1000
31.2
80.9
-68.9
31.9
23.5
72.3
-58.1
23.8
20.4
65.1
-49.4
20.4
18.4
58.1
-42.1
18.2
17.0
51.9
-35.6
16.7
15.8
-71.2
47.4
-29.5
15.7
-68.4
15.2
-57.6
43.6
-23.4
14.7
-56.3
15.1
-45.2
40.9
-17.2
14.3
-44.7
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LMX2541SQ3320E LMX2541SQ3740E
LMX2541SQ2060E, LMX2541SQ2380E
LMX2541SQ2690E, LMX2541SQ3030E
LMX2541SQ3320E, LMX2541SQ3740E
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SNOSB31I –JULY 2009–REVISED FEBRUARY 2013
ExtVCOin Input Impedance
Marker 1:
100 MHz
7
8
Marker 2:
1 GHz
Marker 3:
2 GHz
6
5
Marker 4:
3 GHz
Marker 5:
4 GHz
1
Marker 6:
5 GHz
Marker 7:
6 GHz
2
Marker 8:
7 GHz
3
4
Start 100 MHz
Stop 7000 MHz
Figure 25.
Frequency
100
Real
627.9
193.8
56.4
31.3
23.2
17.8
15.4
14.0
12.8
11.8
11.2
10.7
10.2
10.5
9.1
Imaginary
-1532.3
-852.6
-434.5
-287.4
-212.9
-167.0
-134.9
-111.4
-93.7
-79.5
-67.5
-57.4
-48.6
-42.0
-35.5
-29.0
-23.4
-18.3
-13.3
-8.5
200
400
600
800
1000
1200
1400
1600
1800
2000
2200
2400
2600
2800
3000
3200
3400
3600
3800
4000
4200
4400
4600
4800
5000
6000
7000
7.8
7.2
6.6
5.9
5.3
5.0
-3.7
4.5
-1.4
4.0
0.9
3.5
3.1
2.6
7.7
1.7
12.1
0.9
26.7
2.3
51.9
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LMX2541SQ2060E, LMX2541SQ2380E
LMX2541SQ2690E, LMX2541SQ3030E
LMX2541SQ3320E, LMX2541SQ3740E
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BENCH TEST SETUPS
Charge Pump Currents Test Setup
DC
Blocking
Capacitor
10 MHz
SMA Cable
OSCin
Signal Generator
Device
Under
Test
Semiconductor
Parameter
Analyzer
SMA Cable
CPout
Pin
3.3 V
Evaluation Board
Power Supply
The charge pump is tested in external VCO mode (MODE=1), although it is no external VCO hooked up. The
CPout pin should be disconnected from the any external VCO tuning pin, external loop filter, and also the Vtune
pin on the device. A signal is then applied to the OSCin pin to ensure that the R counter is oscillating. This signal
does not have to be clean and the frequency is very critical. These currents at the CPout pin are typically
measured with a semiconductor parameter analyzer.
Charge Pump Current Measurements
In order to test the TRI-STATE current, the CPT bit is set to one and the current is measured. Aside from having
no other sources of leakage attached to this pin, it is also important that the board be well cleaned before doing
this test. The temperature and voltage at the charge pump can then be varied and the resulting leakage current
is then recorded. Typically, the leakage currents are worst at higher temperatures and higher charge pump
voltages.
In order to test the source and sink currents, the CPT bit is set to active mode and the frequency is programmed
to something much higher than can be achieved in order to force the charge pump to rail. The reason why this is
necessary is that the duty cycle of the charge pump is not 100% unless it is forced against one of the rails. If the
charge pump polarity bit (CPP) is set to positive, then the charge pump source current is measured. To measure
the sink current, the CPT bit is set to negative. The part is then programmed and the charge pump will rail in one
direction. The semiconductor parameter analyzer measures the current at a particular charge pump voltage. The
phase detector polarity bit, CPP, can be toggled to test between the negative and positive charge pump gains. In
order to test leakage, set the TRI-STATE bit, CPT, to 1 so that this can be measured. For the most accurate
measurements, it is desirable that the CPout and Vtune pin are not shorted together for these measurements.
Once these currents are measured, then the datasheet parameters can be calculated.
A summary of these charge pump tests is given in the table below.
Measurement
Leakage Current
Source Current
Sink Current
PLL_R
PLL_N
X
CPG
X
CPT
CPP
X
X
1
1
1 (TRI-STATE)
0 (Active)
4000
4000
0 - 31
0 - 31
1 (Positive)
0 (Negative)
0 (Active)
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LMX2541SQ2060E, LMX2541SQ2380E
LMX2541SQ2690E, LMX2541SQ3030E
LMX2541SQ3320E, LMX2541SQ3740E
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SNOSB31I –JULY 2009–REVISED FEBRUARY 2013
Charge Pump Current Definitions
Figure 26. Charge Pump Current Definitions
I1 = Charge Pump Sink Current at VCPout = Vcc - ΔV
I2 = Charge Pump Sink Current at VCPout = Vcc/2
I3 = Charge Pump Sink Current at VCPout = ΔV
I4 = Charge Pump Source Current at VCPout = Vcc - ΔV
I5 = Charge Pump Source Current at VCPout = Vcc/2
I6 = Charge Pump Source Current at VCPout = ΔV
ΔV = Voltage offset from the positive and negative supply rails. Defined to be 0.4 volts for this part.
Figure 27. Variation of Charge Pump Current Magnitude vs. Charge Pump Voltage
Figure 28. Variation of Charge Pump Current Magnitude vs. Temperature
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LMX2541SQ2060E, LMX2541SQ2380E
LMX2541SQ2690E, LMX2541SQ3030E
LMX2541SQ3320E, LMX2541SQ3740E
SNOSB31I –JULY 2009–REVISED FEBRUARY 2013
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Figure 29. Charge Pump Sink vs. Source Current Mismatch
RFout Output Power Test Setup(1)
100 MHz
SMA Cable
OSCin
Signal Generator
Device
Under
Test
SMA Cable
Matching
Network
RFout Pin
Spectrum Analyzer
DC
Blocking
Capacitor
3.3 V
Evaluation Board
Power Supply
The output power is tested by programming the VCO output to a desired frequency and measuring with a
spectrum analyzer. A 3 dB pad is used and this gain as well as any losses from the cable are added to the actual
measurement. As for the DC blocking capacitor, typically 100 pF is used for frequencies above 2 GHz and 0.1 uF
are used for frequencies below 2 GHz. It turns out that the measurement is not as sensitive as one would expect
to this blocking capacitor value. The output power is mainly a function of the frequency of the output buffer and
the settings of the VCO_DIV (1 or >1), OUTTERM, VCOGAIN, and DIVGAIN bits. It is not very sensitive to the
actual frequency option of the part. For instance, the LMX2541SQ2060E and the LMX2541SQ2380E both should
have similar output power at 2.2 GHz. Note that this same test setup can also be used to measure harmonics.
Phase Noise Measurement Test Setup
The basic setup technique for all noise tests is to measure the noise at the output of the RFout pin in Internal
VCO Mode (MODE=0) with a phase noise analyzer. For all measurements, the internal loop filter components
(LF_R3, LF_R4, LF_C3, and LF_C4) should be set to their minimum values. There are some special
considerations depending on what kind of noise is being measured.
PLL Phase Noise Measurement
To get an accurate measurement of the PLL phase noise, one needs to ensure four things.
•
•
•
•
The PLL loop bandwidth is sufficiently wide so that the VCO noise does not degrade the measurement
The measurement is not corrupted by peaking in the loop filter response.
The reference source is sufficiently clean so that this does not degrade the measurement.
A distinction is made between the PLL flat noise and the PLL 1/f noise
If the PLL loop bandwidth is made as wide as possible, then this helps keep the peaking of the loop filter
response and the VCO noise from degrading the measurement. For the ultimate accuracy, this loop filter
response can be factored into the measurement. As for the cleanliness of the reference source, the best sources
tend to be those that are fixed, such as a 100 MHz Wenzel oscillator. Signal generators tend to be noisy, but if
that is all that is available, then there are a few things that can help compensate for this. One technique is to use
a higher frequency and divide this down to a lower frequency. For instance, a 500 MHz signal divided down to 20
(1) The measurement of the output power is sensitive to the test circuit. All the numbers in the electrical specifications and typical
performance curves were obtained from a characterization setup that accommodate temperature testing and changing of parts. In a
more optimized setup the measured RF output power is typically on the order of 1.5 to 2.4 dB higher.
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LMX2541SQ2060E, LMX2541SQ2380E
LMX2541SQ2690E, LMX2541SQ3030E
LMX2541SQ3320E, LMX2541SQ3740E
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MHz typically has much better phase noise than a direct 20 MHz signal, if it comes from a signal generator.
Another technique is to measure the noise of the reference source and then multiply it up and then subtract it
from the measurement. For instance, if the signal source was 500 MHz and the output frequency was 4 GHz, this
signal source noise would be multiplied up by a factor of 20·log(4 GHz / 500 MHz) = 18 dB. Once that is done,
the 1/f noise and the flat noise can be measured.
PLL Phase Noise Measurement - 1/f Noise
The 1/f noise dominates closer to the carrier. Special care should be taken to ensure that this is not the noise of
the reference source. The noise contribution of the reference source at the RFout pin can be calculating by
measuring what is coming into the OSCin pin and then adding a correction factor of 20·log( fRFout / fOSCin) . A
characteristic of this noise is that it follows a 10 dB/decade slope. If the slope of the measured noise looks more
than 10 dB/decade, it is likely to be the reference source, not the LMX2541 device. Another characteristic of the
1/f noise is that it is independent of phase detector frequency. So to fully expose the 1/f noise, raise the phase
detector frequency as high as possible, since this lowers the flat noise, but not the 1/f noise.
PLL Phase Noise Measurement - Flat Noise
The PLL flat noise is measured at an offset that is not too close to the PLL 1/f noise, but also well inside the loop
bandwidth. Many phase noise profiles have a point where the PLL noise flattens to a minimum value between
the carrier and the loop bandwidth. This is where the flat noise should be measured. To measure the 1 Hz
normalized phase noise, it is often easier to measure this with a lower phase detector frequency so that this flat
noise is higher and easier to measure.
VCO Phase Noise Measurement
In order to measure the VCO phase noise, the loop filter resistors should be set to their minimum value to reduce
their noise contribution. The loop bandwidth should also be made as narrow as possible. Because the loop
bandwidth is very narrow, the cleanliness of the OSCin signal is therefore not as important. The phase noise is
measured outside the loop bandwidth of the system.
An alternative way that might not be as accurate, but is much easier to do is to lock the device to a frequency
and then set the CPT bit to 1 to disable the charge pump. The VCO will drift a little, the averaging on the
equipment should be reset after this bit is changed and one can not take to long to take this measurement. Test
equipment that tracks the signal source is better if using this open loop technique.
Divider Phase Noise Measurement
The basic method for measuring the divider noise is to drive the divider with a noise source of known value and
then subtract away this noise. The divider noise floor tends to be flat, whereas the VCO phase noise decreases
with offset frequency, so this measurement is made at as far of an offset that is possible. When using Internal
VCO Mode (MODE=0), the raw VCO phase noise with VCO_DIV=1 can be measured. Then the VCO divider can
be programmed to get close to the desired frequency. For example, the VCO frequency can be set to 4 GHz and
the phase noise measured. This phase noise data can be saved or downloaded. Suppose then that one was
interested in the divider noise at 400 MHz. The VCO divider could be set to 10 and then 20 dB is subtracted from
the VCO phase noise to figure its contribution at 400 MHz. Provided that the actual phase noise measured at
400 MHz with VCO_DIV is above this, then one can assume that this is the noise of the divider.
An alternative way to measure this is to drive the OSCin pin and use Divider Only (MODE=2) to measure the
phase noise. This gives direct control of the frequency, but one should be sure that the noise being measured is
the device and not the frequency source.
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LMX2541SQ2060E, LMX2541SQ2380E
LMX2541SQ2690E, LMX2541SQ3030E
LMX2541SQ3320E, LMX2541SQ3740E
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Input and Output Impedance Test Setup
Calibrate for Open,
Short, Load Here
Frequency
Device
Under
Test
Pin
Network Analyzer
Evaluation Board
Power Supply
A network analyzer can be used to measure the input impedance of the OSCin and ExtVCOin pin as well as the
output impedance of the RFout pin. The general technique is to connect the desired pin with no DC blocking
capacitor to a network analyzer and measure the impedance directly. The part needs to be programmed to
ensure that it is in a known state. There are some special considerations that should be taken for different
measurements of the three different impedances.
OSCin Input Impedance Measurement
For this pin, the provided calibration standards are typically good enough for a decent measurement. A single-
ended measurement at the OSCin or OSCin* pins can be made For a differential measurement, this needs to be
treated by the instrument as a two port network.
ExtVCOin Input Impedance Measurement
Because this pin goes higher in frequency, it is often difficult get a good measurement at higher frequencies
because of the effects of the board and SMA connector. One technique that can be used is instead of using the
provided calibration standards that come with the equipment, solder resistors directly to the board in order to
calibrate out the effects of the board as well. A 0 ohm resistor functions as a short, no resistor functions as an
open, and two parallel 100 ohm resistors serve as a load. These should be soldered as close to the part as
possible. Once this calibration is done, the measurement can be done as normal.
RFout Output Impedance Measurement
Although output and input impedance are not the same thing, they can be measured in a similar way. Because
this pin is a higher frequency, it is better to use the same method for calibration as used for the ExtVCOin pin.
The other consideration for the RFout pin is that there are many different settings that impact this input
impedance. When in bypass mode (VCO_DIV=1), the VCOGAIN and OUTTERM words can change the
impedance. When in divided mode (VCO_DIV>1), the DIVGAIN and OUTTERM words can impact the
impedance.
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LMX2541SQ2060E, LMX2541SQ2380E
LMX2541SQ2690E, LMX2541SQ3030E
LMX2541SQ3320E, LMX2541SQ3740E
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SNOSB31I –JULY 2009–REVISED FEBRUARY 2013
ExtVCOin (NOT OSCin) Input Sensitivity Test Setup
SMA Cable
Matching
ExtVCOin
Signal Generator
Network
DC
Blocking
Capacitor
Device
Under
Test
SMA Cable
Ftest/LD
Pin
Frequency Counter
Evaluation Board
Power Supply
In order to measure the ExtVCOin Input sensitivity, the part is put in External VCO mode and a signal is applied
to the ExtVCOin pin. A matching network, which is typically a 3 dB pad, is used and this loss is added to the
measured numbers as well as any potential cable losses (on the order of 1 dB). A signal is applied at a known
frequency and power and the output of the N counter is monitored using the Ftest/LD pin and setting it to look at
the N counter output divided by 2. Typically, the divide by 2 function is better because if it is not used, the duty
cycle from the Ftest/LD pin is not 50% and this can sometimes confuse frequency counters. The part is set in
fractional mode with a large fraction of 502 + 2097150/4194301 to ensure that the fractional circuitry gets fully
tested. Accounting for the extra divide by 2 from the Ftest/LD pin, the divided output frequency should be the
input frequency divided by 1005 to a 1 ppm tolerance.
OSCin Input Sensitivity Test Setup
SMA Cable
OSCin
Signal Generator
Device
Under
Test
SMA Cable
RFout Pin
Frequency Counter
Evaluation Board
Power Supply
Input Sensitivity Test Procedure
There are two things that are important to consider when measuring the OSCin sensitivity.
•
•
The action of setting the Ftest/LD pin to monitor the R divider output degrades the OSCin sensitivity.
The internal VCO frequency calibration is based on the OSCin signal
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LMX2541SQ2060E, LMX2541SQ2380E
LMX2541SQ2690E, LMX2541SQ3030E
LMX2541SQ3320E, LMX2541SQ3740E
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Because of these considerations, the OSCin sensitivity needs to be measured in a closed loop test in such a way
that the internal frequency calibration is not distorting the measurement. To do this, a known frequency and
power level are set at the OSCin pin and the power level is changed until the PLL becomes more than 1 ppm off
frequency. The PLL_R divider is varied to maintain a phase detector frequency of 1 MHz to ensure that the PLL
loop does not become unstable. The frequency counter needs to be synchronized in frequency to the signal
generator. It is better to use a narrower loop bandwidth for this test because the phase noise of the PLL might
degrade when the OSCin power level gets to close to the sensitivity limits. Typically, a 0.1 uF capacitor is used
as a DC block for the signal at the OSCin pin. The sensitivity at the OSCin pin is measured with a single-ended
input.
This test can be run in internal VCO mode (MODE=0) or external VCO mode (MODE=1). When doing the test in
internal VCO mode, the part needs to be initially locked and then the R counter is programmed to adjust for the
OSCin frequency. However, in internal VCO mode, the PLL_N counter can not be programmed, because the
action of programming this counter activates the internal VCO frequecy calibration, which can interfere with the
test.
OSCin Slew Rate Tests
There are two methods that can be used to test the OSCin slew rate. One method is to use test equipment that
actually allows the user to vary the slew rate directly, but this type of equipment typically does not give the user
enough range of adjustability. Another method is to calculate the slew rate based on the slope of a sine wave of
known frequency and amplitude. For this method, the slew rate can be calculated from the frequency and peak
to peak amplitude of the OSCin signal as follows: SlewOSCin = 2 × π × fOSCin × VppOSCin
FUNCTIONAL DESCRIPTION
The LMX2541 is a low power, high performance frequency synthesizer system which includes a PLL, Partially
Integrated Loop Filter, VCO, VCO Divider, and Programmable Output Buffer. There are three basic modes that
the device can be configured in: Full Chip Mode, External VCO Mode, and Divider Only Mode. Full chip mode is
intended to be used with the internal VCO and PLL. There is also the option of External VCO mode, which allows
the user to connect their own external VCO. Finally, there is Divider only, which is just the VCO divider and
output buffer. The active blocks for these modes are described below:
Available Blocks
Mode
Loop
Filter
VCO
Divider
Output
Buffer
PLL
Yes
Yes
No
VCO
Yes
No
Full
Chip
Yes
No
Yes
Yes
Yes
Yes
Yes
Yes
External
VCO
Divider
Only
No
No
PLL Reference Oscillator Input Pins
There are three basic ways that the OSCin/OSCin* pins may be configured as shown in the table below:
Mode
Description
Device is used with a crystal oscillator
XO Bit
Crystal
1
Single
Ended
Device is driven with a single-ended source, such as a TCXO.
0
0
Use this mode when driving with a differential signal, such as an LVDS
signal.
Differential
In addition to the way that the OSCin/OSCin* pins are driven, there are also bits that effect the frequency that the
chip uses. The OSC_FREQ word needs to be programmed correctly, or the VCO may have issues locking to the
proper frequency, since the VCO frequency calibration is based on this word.
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LMX2541SQ2060E, LMX2541SQ2380E
LMX2541SQ2690E, LMX2541SQ3030E
LMX2541SQ3320E, LMX2541SQ3740E
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SNOSB31I –JULY 2009–REVISED FEBRUARY 2013
Word Name
Function
This needs to be set correctly if the internal VCO is used for proper
calibration.
OSC_FREQ
This allows the oscillator frequency to be doubled. The R divider is
bypassed in this case.
OSC2X
Higher slew rates tend to yield the best fractional spurs and phase noise, so a square wave signal is best for
OSCin. Single ended mode and differential mode have similar results if a square wave is used to drive the
OSCin pin. If using a sine wave, higher frequencies tend to work better due to their higher slew rates.
PLL R Divider
The R divider divides the OSCin frequency down to the phase detector frequency. If the doubler is enabled, then
the R divider is bypassed.
PLL Phase Detector and Charge Pump
The phase detector compares the outputs of the R and N dividers and generates a correction current
corresponding to the phase error. This charge pump current is software programmable to 32 different levels. The
phase detector frequency, fPD, can be calculated as follows:
fPD = fOSCin / R
(1)
PLL N Divider and Fractional Circuitry
The N divider in the LMX2541 includes fractional compensation and can achieve any fractional denominator
(PLL_DEN) from 1 to 4,194,303. The integer portion, PLL_N, is the whole part of the N divider value and the
fractional portion, PLL_NUM / PLL_DEN, is the remaining fraction. PLL_N, PLL_NUM, and PLL_DEN are
software programmable. So in general, the total N divider value, N, is determined by:
N = PLL_N + PLL_NUM / PLL_DEN
(2)
The order of the delta sigma modulator is programmable from integer mode to fourth order. There are also
several dithering modes that are also programmable. In order to make the fractional spurs consistent, the
modulator is reset any time that the R0 register is programmed.
Partially Integrated Loop Filter
The LMX2541 integrates the third pole (formed by R3_LF and C3_LF) and fourth pole (formed by R4_LF and
C4_LF) of the loop filter. The values for these integrated components can be programmed independently through
the MICROWIRE interface. The larger the values of these components, the stronger the attenuation of the
internal loop filter. The maximum attenuation can be achieved by setting the internal resistors and capacitors to
their maximum value and the minimum attenuation can be attained by setting all of these to their minimum
setting. This partially integrated loop filter can only be used in full chip mode.
Charge
CPout
Pump
R4_LF
R3_LF
Vtune
C2_LF
C1_LF
R2_LF
Low Noise, Fully Integrated VCO
The LMX2541 includes a fully integrated VCO, including the inductors. The VCO (Voltage Controlled Oscillator)
takes the voltage from the loop filter and converts this into a frequency. The VCO frequency is related to the
other frequencies and divider values as follows:
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fVCO = fPD × N = fOSCin × N / R
(3)
In order to the reduce the VCO tuning gain and therefore improve the VCO phase noise performance, the VCO
frequency range is divided into many different frequency bands. This creates the need for frequency calibration in
order to determine the correct frequency band given a desired output frequency. The frequency calibration
routine is activated any time that the R0 register is programmed. It is important that the OSC_FREQ word is set
correctly to have this work correctly.
The VCO also has an internal amplitude calibration algorithm to optimize the phase noise which is also activated
any time the R0 register is programmed. The optimum internal settings for this are temperature dependent. If the
temperature is allowed to drift too much without being re-calibrated, some minor phase noise degradation could
result. For applications where this is an issue, the AC_TEMP_COMP word can be used to sacrifice phase noise
at room temperature in order to improve the VCO phase noise over all temperatures. The maximum allowable
drift for continuous lock, ΔTCL, is stated in the electrical specifications. For this part, a number of +125 C means
the part will never lose lock if the part is operated under recommended operating conditions.
Programmable VCO Divider
The VCO divider can be programmed to any value from 2 to 63 as well as bypass mode if device is in full chip
mode. In external VCO mode or divider mode, all values except bypass mode can be used for the VCO divider.
The VCO divider is not in the feedback path between the VCO and the PLL and therefore has no impact on the
PLL loop dynamics. After this programmable divider is changed, it may be beneficial to reprogram the R0 register
to recallibrate the VCO . The frequency at the RFout pin is related to the VCO frequency and divider value,
VCO_DIV, as follows:
fRFout = fVCO / VCO_DIV
(4)
When this divider is enabled, there will be some far-out phase noise contribution to the VCO noise. Also, it may
be beneficial for VCO phase noise to reprogram the R0 register to recalibrate the VCO if the VCO_DIV value is
changed from bypass to divided, or vice-versa.
The duty cycle for this divider is always 50%, even for odd divide values. Because of the architecture of this
divider that allows it to work to high frequencies and always have a 50% duty cycle, there are a few extra
considerations:
•
In divider only mode, there must be 5 clock cycles on the ExtVCOin pin after the divide value is programmed
in order to cause the divide value to properly changed. It is fine to use more than 5 clock cycles for this
purpose.
•
For a divide of 4 or 5 ONLY, the R4 register needs to be programmed one more time after the device is fully
programmed in order synchronize the divider. Failure to do so will cause the VCO divider to divide by the
wrong value. Furthermore, if the VCO signal ever goes away, as is the case when the part is powered down,
it is necessary to reprogram the R4 register again to re-synchronize the divider. Furthermore, if the R0
register is ever programmed in full chip mode, it is also necessary to reprogram the R4 register.
Programmable RF Output Buffer
The output power at the RFout pin can be programmed to various levels as well as on and off states. The output
state of this pin is controlled by the RFoutEN pin as well as the RFOUT word. The RF output buffer can be
disabled while still keeping the PLL in lock. In addition to this, the actual output power level of this pin can be
adjusted using the VCOGAIN, DIVGAIN, and OUTTERM programming words. The reader should note that
VCOGAIN controls the gain of the VCO buffer, not the tuning constant in of the VCO.
Powerdown Modes
The LMX2541 can be powered up and down using the CE pin or the POWERDOWN bit. When the device is
powered down, the programming and VCO calibration information is retained, so it is not necessary to re-
program the device when the device comes out of the powered down state (The one exception is when the
VCO_DIV value is 4 or 5, which has already been discussed.). The following table shows how to use the bit and
pin.
CE Pin
POWERDOWN Bit
Device State
Low
Don't Care
Powered Down
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CE Pin
POWERDOWN Bit
Device State
Powered Up
0
1
High
Powered Down
The device can be programmed in the powerdown state. However, the VCO frequency needs to be changed
when the device is powered up because the VCO calibration does not run in the powerdown state. Also, the
special programming for VCO_DIV = 4 or 5 has to be done when the part is powered up. In order for the CE pin
to properly power the device down when it is held low, the all registers in the device need to have been
programmed at least one time.
Fastlock
The LMX2541 includes the Fastlock feature that can be used to improve the lock times. When the frequency is
changed, a timeout counter is used to engage the fastlock for a programmable amount of time. During the time
that the device is in Fastlock, the FLout pin changes from high impedance to low, thus switching in the external
resistor R2pLF with R2_LF as well as changing the internal loop filter values for R3_LF and R4_LF.
R4_LF
R3_LF
Vtune
Charge
Pump
CPout
FLout
C2_LF
Fastlock
Control
C1_LF
R2_LF
R2pLF
The following table shows the charge pump gain, loop filter resistors, and FLout pin change between normal
operation and Fastlock.
Normal
Operation
Parameter
Fastlock
Charge Pump Gain
CPG
FL_CPG
FL_R3_LF
FL_R4_LF
Loop Filter Resistor R3_LF
Loop Filter Resistor R4_LF
R3_LF
R4_LF
High
Impedance
FLout Pin
Low
Once the loop filter values and charge pump gain are known for normal mode operation, they can be determined
for fastlock operation as well. In normal operation, one can not use the highest charge pump gain and still use
fastlock because there will be no larger current to switch in. If the resistors and the charge pump current are
done simultaneously, then the phase margin can be preserved while increasing the loop bandwidth by a factor of
K as shown in the following table:
Parameter
Symbol
Calculation
Charge pump gain in Fastlock
FL_CPG
Typically choose to be the largest value.
K =
Loop Bandwidth Multiplier
Internal Loop Filter Resistor
Internal Loop Filter Resistor
K
sqrt (FL_CPG/CPG)
FL_R3_LF =
R3_LF / K
FL_R3_LF
FL_R4_LF
FL_R4_LF =
R4_LF / K
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Parameter
Symbol
Calculation
R2pLF =
R2_LF / (K - 1)
External Loop Filter Resistor
R2pLF
Lock Detect
The Ftest/LD pin of the LMX2541 can be configured to output a signal that gives an indication for the PLL being
locked. There are two styles of lock detect; analog and digital. The analog lock detect signal is more of a legacy
feature and consists a series of narrow pulses that correspond to when the charge pump comes on. These
pulses can be integrated with an external RC filter to create generate a lock detect signal. Analog lock detect can
be configured in a push-pull output or an open drain output. The analog open drain lock detect signal can be
integrated with a similar RC filter and requires an additional pull-up resistor. This pull-up resistor can be much
larger than the resistor in the RC filter in order to make unbalanced time constants for improved sensitivity.
The digital lock detect function can also be selected for the Ftest/LD pin to give a logic level indication of lock or
unlock. The digital lock detect circuitry works by comparing the difference between the phase of the inputs to the
phase detector with a RC generated delay of ε. To indicate a locked state (Lock = HIGH) the phase error must
be less than ε for 5 consecutive phase detector cycles. Once in lock (Lock = HIGH), the RC delay is changed to
δ. To indicate an out of lock state (Lock = LOW), the phase error must become greater than δ. The values of ε
and δ are programmable with the DLOCK word.
START
LD = LOW
(Not Locked)
NO
Phase Error < e
YES
NO
Phase Error < e
YES
NO
Phase Error < e
YES
NO
Phase Error < e
YES
NO
Phase Error < e
YES
LD = HIGH
(Locked)
NO
YES
Phase Error > d
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General Programming Information
The LMX2541 is programmed using several 32-bit registers used to control the LMX2541 operation. A 32-bit shift
register is used as a temporary register to indirectly program the on-chip registers. The shift register consists of a
data field and an address field. The last 4 register bits, CTRL[3:0] form the address field, which is used to
decode the internal register address. The remaining 28 bits form the data field DATA[27:0]. While LE is low,
serial data is clocked into the shift register upon the rising edge of clock (data is programmed MSB first). When
LE goes high, data is transferred from the data field into the selected register bank. For initial device
programming the register programming sequence must be done in the order as shown in the register map. The
action of programming register R7 and bringing LE low resets all the registers to default values, including hidden
registers. The programming of register R0 is also special for the device when operating in full chip mode
because the action of programming either one of these registers activates the VCO calibration.
In addition to changing the values of various words, the programming of certain registers triggers certain events
as described in the table below:
Configurations
Programming Event Event Triggered
Where it Has an Significance
Impact
Resets all registers,
Action of
programming register
ones, to a default
R7 and bring LE low
state
This needs to be the first programming step for all configurations. If
register R7 is ever programmed again, all programming information
will be reset to the default state.
including hidden
All
The VCO calibration tunes the VCO to the correct frequency band
and optimizes the phase noise. It is necessary whenever the
internal VCO frequency is changed. Also, if the temperature drifts
considerably, then this calibration can better optimize the phase
noise.
Action of
programming register Activates the VCO
R0 and bringing LE
low
Only in Full Chip
Mode
calibration
Only when the RFout
pin ins enabled and
the VCO divider is set
to 4 or 5
Action of
programming register
R4
Synchronizes the
VCO Divider
Consult the Functional Description for more details.
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Table 8. Register Map
The following table lists the registers as well as the order that they should be programmed. Register 7 is programmed first and the action of programming register R7 resets all the registers
after the LE pin is pulled to a low state. Register R0 is programmed last because it activates the VCO calibration. The one exception to this is when the VCO_DIV value is 4 or 5. Consult the
programming section on VCO_DIV for more details.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
DATA[27:0]
9
8
7
6
5
4
3
2
1
0
C3 C2 C1 C0
R7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
1
1
1
VCO_DIV_OPT
[2:0]
R13
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
R12
R9
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
1
0
0
0
0
1
0
0
0
1
0
1
1
0
0
1
0
0
0
0
0
0
0
0
1
0
1
1
1
1
0
0
0
0
0
0
1
0
R8
AC_TEMP_COMP[4:0]
RFOUT[1
R6
0
1
0
0
0
0
0
0
0
0
0
0
1
1
1
VCOGAIN[3:0]
OUTTERM[3:0]
DIVGAIN[3:0]
0
1
1
0
:0]
R5
R4
0
1
FL_CPG[4:0]
C3_LF[3:0]
FL_RF_LF[2:0] FL_R3_LF[2:0]
R4_LF[2:0] R3_LF[2:0]
FL_TOC[13:0]
CPG[4:0]
0
0
1
1
0
0
1
0
C4_LF[3:0]
VCO_DIV[5:0]
MUX[3:0]
OSC_FREQ[7:0]
PO
OS
C
_2X
WE
R
DO
WN
FS
K
CP
T
FD
M
CP
P
MODE[1:
0]
R3
0
0
DLOCK[2:0]
DITH[1:0]
ORDER[2:0]
XO
0
0
1
1
R2
R1
R0
0
0
0
0
0
0
0
0
0
1
DEN[21:0]
0
0
0
0
0
0
1
0
0
0
1
0
PLL_NUM[21:16]
PLL_NUM[15:0]
PLL_N[17:12]
PLL_R[11:0]
PLL_N[11:0]
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Register R7
Although Register 7 has no elective bits to program, it is very important to program this register because the
action of doing so with the bit sequence shown in the register map resets all the registers, including hidden
registers with test bits that are not disclosed. Register 7 should always be programmed first, because it will reset
all other programming information. The register reset occurs only after the LE signal has transitioned from low to
high and back to low again.
Register R13
This register needs to be programmed only in the event that the RFout pin is being used and VCO_DIV = 1.
VCO_DIV_OPT[2:0]
This word optimizes the RFout power level based on the VCO_DIV and VCO_GAIN words.
Condition
VCO_DIV_OPT
Comments
RFout Pin Disabled
OR
Register R13 Does Not need to be
programmed, since 0 is the default.
VCO_DIV>1
OR
0
VCO_GAIN<13
RFout Pin Enabled
AND
VCO_DIV=1
VCO_GAIN>12
4
Register R12
This register needs to be programmed as shown in the register map in the event that the internal VCO is being
used. When using external VCO mode, this register does not need to be programmed.
Register R9
Program this register as shown in the register map.
Register R8
AC_TEMP_COMP[4:0]
This word optimizes the VCO phase noise for possible temperature drift. When the VCO frequency is changed,
the internal tuning algorithm optimizes the phase noise for the current temperature. In fixed frequency
applications, temperature drift may lead to sub-optimal phase noise over time. In dynamic frequency applications,
the re-tuning of the VCO frequency overcomes this problem because the phase noise is re-optimized each time
the VCO frequency is changed. The AC_TEMP_COMP word can be used to optimize the VCO phase noise for
temperature drift for these different scenarios. The following table indicates which values of this word should be
used for each scenario.
AC_TEMP_COMP
Application Type
Dynamic Frequency
Fixed Frequency
Invalid
5
24
All Other States
Register R6
Register R6 has words that impact the output power of the RFout pin.
RFOUT[1:0] - RFout enable pin
This word works in combination with the RFoutEN Pin to control the state of the RFout pin.
RFOUT
RFoutEN Pin
RFout Pin State
0
Don't Care
Disabled
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RFOUT
RFoutEN Pin
Don't Care
Low
RFout Pin State
Enabled
2
Disabled
1 or 3
High
Enabled
DIVGAIN[3:0], VCOGAIN[3:0], and OUTTERM[3:0] - Power Controls for RFout
These three words may be programmed in a value from 0 to 15 and work in conjunction to control the output
power level of the RFout pin. Increasing any of these values increases the output power at the expense of higher
current consumption of the buffer. Although there may be more than one way to get the same output power,
some combinations may have lower current. The typical performance characteristics show these trade-offs. The
default setting for all these bits is 12. The value of VCO_DIV determines which two of these three words have an
impact.
VCO_DIV
1 (Bypass)
Bits that Impact Power
OUTTERM, VCOGAIN
OUTTERM, DIVGAIN
>1 (Not Bypass)
Register R5
This register controls the fastlock mode which enables a wider loop bandwidth when the device is changing
frequencies.
FL_TOC[13:0] -- Time Out Counter for FastLock
When the value of this word is 3 or less, FastLock time out counter is disabled, and the FLout pin can be used
for general purpose I/O. When this value is 4 or greater, the time out counter is engaged for the amount of phase
detector cycles shown in the table below.
TOC Value
FLout Pin State
Fastlock Engagement Time
Disabled
0
1
2
3
High Impedance
Low
Low
High
Always Engaged
Disabled
Disabled
Engaged for
4 × 2 Phase Detector Cycles
4
.
Low
.
.
Engaged for
16383 × 2 Phase Detector Cycles
16383
Low
When this count is active, the FLout Pin is grounded, the FastLock current is engaged, and the resistors R3 and
R4 are also potentially changed. The table below summarizes the bits that control various values in and out of
FastLock.
FastLock State
Not Engaged
Engaged
FLout
Charge Pump Current
CPG
R3_LF Value
R3_LF
R4_LF Value
R4_LF
High Impedance
Grounded
FL_CPG
FL_R3_LF
FL_R4_LF
FL_R3_LF[2:0] -- Value for Internal Loop Filter Resistor R3 During Fastlock
FL_R3_LF Value
R3 Resistor During Fastlock (kΩ)
0
1
2
3
4
Low ( 200 Ω )
1
2
4
16
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FL_R3_LF Value
R3 Resistor During Fastlock (kΩ)
5-7
Reserved
FL_R4_LF[2:0] -- Value for Internal Loop Filter Resistor R4 During Fastlock
FL_R4_LF Value
R3 Resistor During Fastlock (kΩ)
0
1
Low ( 200 Ω )
1
2
2
3
4
16
4
5-7
Reserved
FL_CPG[4:0] -- Charge Pump Current for Fastlock
When FastLock is enabled, this is the charge pump current that is used for faster lock time.
Typical Fastlock Charge Pump Current at 3.3
Volts (µA)
FL_CPG
Fastlock Charge Pump State
0
1
1X
2X
3X
4X
...
100
200
300
400
...
2
3
...
31
32X
3200
Register R4
This register controls miscellaneous functions of the device. The action of programming the R4 register also
synchronizes the VCO divider, which is necessary when VCO_DIV = 4 or 5.
OSC_FREQ [7:0] -- OSCin Frequency for VCO Calibration Clocking
This word is used for the VCO frequency calibration. This word should be set to the OSCin frequency rounded to
the nearest MHz.
OSC_FREQ
OSCin Frequency
Illegal State
1 MHz
0
1
2
2 MHz
...
...
255 MHz
and higher
255
VCO_DIV[5:0] - VCO Divider
The output of the VCO is divided by the value of VCO_DIV, which can range from 1 (Bypass Mode) to 63 and all
values in between with the limitation that the VCO divider can only be set to bypass mode when the device is
operating in full chip mode. When the VCO divider is set to 4 or 5 ONLY, there is one extra programming step
required to synchronize the VCO divider. Consult the Functional Description for more details.
VCO_DIV
VCO Output Divide
n/a
Comments
Illegal State
0
1
2
3
Bypass Mode
Divide by 2
Divide by 3
This state only available for MODE=Full Chip Mode
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VCO_DIV
VCO Output Divide
Divide by 4
Divide by 5
Divide by 6
...
Comments
4
5
Extra programming is required for divide by 4 and divide by 5 only. Refer to the
Functional Description for more details.
6
...
62
63
Divide by 62
Divide by 63
R3_LF[2:0] -- Value for Internal Loop Filter Resistor R3
This word controls the state of the internal loop filter resistor R3_LF when the device is in Full Chip Mode and
Fastlock is not active.
R3_LF Value
R3 Resistor During Fastlock (kΩ)
0
1
Low ( 200 Ω )
1
2
2
3
4
16
4
5-7
Reserved
R4_LF[2:0] -- Value for Internal Loop Filter Resistor R4
This word controls the state of the internal loop filter resistor R4_LF when the device is in Full Chip Mode and
Fastlock is not active.
R4_LF Value
R3 Resistor During Fastlock (kΩ)
0
1
Low ( 200 Ω )
1
2
2
3
4
16
4
5-7
Reserved
C3_LF[3:0] -- Value for C3 in the Internal Loop Filter
This word controls the state of the internal loop filter resistor C3_LF when the device is Full Chip Mode.
C3_LF
C3 (pF)
0
0
1
1
2
5
3
6
4
10
11
15
16
20
21
25
26
30
31
5
6
7
8
9
10
11
12
13
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C3_LF
14
C3 (pF)
35
15
36
C4_LF[3:0] -- Value for C4 in the Internal Loop Filter
This word controls the state of the internal loop filter resistor C4_LF when the device is Full Chip Mode.
C4_LF
C4 (pF)
0
0
1
5
2
20
3
25
4
40
5
45
6
60
7
65
8
100
105
120
125
140
145
160
165
9
10
11
12
13
14
15
Register R3
This register controls miscellaneous features of the device.
MODE[1:0] -- Operational Mode
The LMX2541 can be run in several operational modes as listed in the table below:
MODE
Name
Full
Divider
Enabled
Enabled
Enabled
Enabled
PLL
VCO
0
1
2
3
Enabled
Enabled
Disabled
Enabled
Enabled
Disabled
Disabled
Enabled
External VCO
Divider Only
Test (Reserved)
Powerdown -- Powerdown Bit
Enabling this bit powers down the entire device, although register and VCO calibration information is retained.
XO - Crystal Oscillator Mode Select
When this bit is enabled, a crystal with appropriate load capacitors can be attached between the OSCin and
OSCin* pins in order to form a crystal oscillator.
CPG[4:0] -- Charge Pump Current
This word programs the charge pump current gain. The current is programmable between 100 uA and 3.2 mA in
100 uA steps.
CPG
Charge Pump State
Typical Charge Pump Current (µA)
0
1X
100
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CPG
1
Charge Pump State
Typical Charge Pump Current (µA)
2X
3X
4X
...
200
300
...
2
3
...
31
32X
3200
MUX[3:0] -- Multiplexed Output for Ftest/LD Pin
The MUX[3:0] word is used to program the output of the Ftest/LD Pin. This pin can be used for a general
purpose I/O pin, a lock detect pin, and for diagnostic purposes. When programmed to the digital lock detect
state, the output of the Ftest/LD pin will be high when the device is in lock, and low otherwise. The output voltage
level of the Ftest/LD is not equal to the supply voltage of the device, but rather is given by VOH and VOL in the
electrical characteristics specification.
Because the Ftest/LD pin is close to the OSCin pin, the state of this pin can have an impact on the performance
of the device. If any of the diagnostic modes (8-13) are used, the OSCin sensitivity can be severely degraded, so
these should only be used for diagnostic purposes. The fractional spurs can also be impacted a little by the MUX
programming word. The Push-Pull digital lock detect modes, like mode 3, tend to have the best fractional spurs,
so these states are recommended, even if the digital lock detect function is not needed.
MUX
Output Type
High Impedance
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Open Drain
Open Drain
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
N/A
Function
Disabled
Comments
0
1
Logical High State
Logical Low State
Digital Lock Detect
Inverse Digital Lock Detect
Digital Lock Detect
Analog Lock Detect
Analog Lock Detect
N Divider
General Purpose I/O Modes
2
3
4
Lock Detect Modes
Consult Functional Description for more details
State 3 is recommended for optimal spurious performance.
5
6
7
8
Diagnostic Modes
9
N Divider / 2
These allow the user to view the outputs of the N divider,
R divider, and phase frequency detector (PFD) and are
intended only for diagnostic purposes. Typically, the output
is narrow pulses, but when the output is divided by 2, there
is a 50% duty cycle. The use of these modes (including R
Divider) can degrade the OSCin sensitivity.
10
11
12
13
14-15
R Divider
R Divider / 2
PFD Up
PFD Down
Reserved
CPP - Charge Pump Polarity
This bit sets the polarity of the phase detector.
CPP
Charge Pump Polarity
Typical Applications
Full Chip Mode
External VCO Mode with an inverting active loop filter.
0
1
Negative
Positive
External VCO Mode with a passive loop filter.
OSC2X-- OSCin Frequency Doubler
Enabling this bit doubles the OSCin frequency. This is useful in achieving a higher phase detector frequency to
improve PLL phase noise, push out noise from the delta sigma modulator, and sometimes reduce fractional
spurs . Note that when this bit is enabled, the R divider is bypassed.
OSC_2X
State
Normal
0
1
OSCin frequency is doubled
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FDM - Extended Fractional Denominator Mode Enable
Enabling this bit allows the fractional numerator and denominator to be expanded from 10 bits to 22 bits. In 10-bit
mode, only the first 10 bits of the fractional numerator and denominator are considered. When using FSK mode,
this bit has to be disabled.
FDM
0
Fractional Mode
10-bit
1 (Default)
22-bit
ORDER[2:0] -- Delta Sigma Modulator Order
This word determines the order of the delta sigma modulator in the PLL. In general, higher order fractional
modulators tend to reduce the primary fractional spurs that occur at increments of the channel spacing, but can
also create spurs that are at a fraction of the channel spacing. The optimal choice of modulator order is very
application specific, however, a third order modulator is a good starting point. The first order modulator has no
analog compensation or dithering
Delta Sigma
Modulator
ORDER
Mode
Comments
0
1
Disabled
Integer
Allows larger N Counter
First Order
This has no analog compensation or dithering
2
Second Order
Third Order
Fourth Order
Illegal States
Fractional
n/a
3
Traditional Delta Sigma Operation
n/a
4
5-7
DITH[1:0] -- Dithering
Dithering randomizes the delta sigma modulator output. This reduces sub-fractional spurs at the expense of
adding phase noise. In general, it is recommended to keep the dithering strength at None or Weak for most
applications. Dithering should never be used when the device is used in integer mode or a first order modulator.
When using dithering with the other delta sigma modulator orders, it is beneficial to disable it in the case where
the fractional numerator is zero, since it can actually create sub-fractional spurs.
DITH
Dithering Strength
Weak
0
1
2
3
Medium
Strong
Disabled
CPT - Charge Pump TRI-STATE
When this bit is enabled, the charge pump is at TRI-STATE. The TRI-STATE mode could be useful for open loop
modulation applications or as diagnostic tool for measuring the VCO noise, but is generally not used.
CPT
Charge Pump
Normal Operation
TRI-STATE
0
1
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DLOCK[2:0] - Controls for Digital Lock detect
This word controls operation of the digital lock detect function through selection of the window sizes (ε and δ). In
order to indicate the PLL is locked, there must be 5 consecutive phase detector output cycles in which the time
offset between the R and N counter outputs is less than ε. This will cause the Ftest/LD pin output to go high.
Once lock is indicated, it will remain in this state until the time offset between the R and N counter outputs
exceeds δ. For this device, ε and δ are the same. If the OSCin signal goes away, the digital lock detect circuit will
reliably indicate an unlocked condition. Consult the Functional Description for more details. A larger window size
makes the lock detect circuit less sensitive, but may be necessary in some situations to reduce chattering.
Window Size
(ε and δ)
DLOCK
0
3.5
(Default)
1
2
5.5
7.5
3
9.5
4
11.5
5
13.5
6 -7
Reserved
There are restrictions when using digital lock detect, based on the phase detector frequency (fPD), Modulator
Order (ORDER), and VCO frequency (fVCO). The first restriction involves a minimum window size (εmin), the
second one involves a maximum window size (εmax), and the third involves further restrictions on the maximum
phase detector frequency that are implied by the window size that is selected.
The first restriction involves the minimum window size (εmin). This minimum window size can not be greater than
the maximum programmable value of 13.5 ns for valid operation of the digital lock detect. Possible remedies for
this solution would be reducing the delta sigma order, using a higher VCO frequency and using a larger
VCO_DIV value, or using analog lock detect.
13.5 ns ≥ εmin = 2ORDER-1 / fVCO
(5)
The second restriction is the maximum window size (εmax). If the calculated maximum window size is less than
the minimum programmable window size of 3.5 ns, then this indicates that the digital lock detect can not be used
in this condition. Possible remedies for this could be to decrease the phase detector frequency, use analog lock
detect, decrease the delta sigma order, or decrease the VCO frequency.
3.5 ns ≤ εmax = 1/fPD - εmin - 2 ns
(6)
The third restriction comes from rearranging the equation for εmax
.
fPD ≤ 1 / ( εmin + εmax + 2 ns )
(7)
In addition to this restriction on the maximum phase detector rate, recall that there are also restrictions on the
maximum phase detector rate implied by the electrical specifications ( fPD≤ 104 MHz ) and by the minimum
continuous N divider value (fPD ≤ fVCO / NMin).
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SNOSB31I –JULY 2009–REVISED FEBRUARY 2013
Maximum Possible Phase Detector Frequency (MHz)
fVCO
(MHz)
εmin
(ns)
ORDER
ε = 3.5 ns
ε = 5.5 ns
ε = 7.5 ns
ε = 9.5 ns
ε = 11.5 ns
ε = 13.5 ns
Min
(104, fVCO
12)
Min
(104, fVCO
12)
Min
(104, fVCO
12)
Min
(87.0, fVCO
12)
Min
(74.1, fVCO
12)
Min
(64.5, fVCO
12)
All
0
0.0
/
/
/
/
/
/
400
400
4
3
2
4
3
2
4
3
2
4
3
2
4
3
2
4
3
2
4
3
2
4
3
2
4
3
2
20.0
10.0
5.0
16.0
8.0
4.0
13.3
6.7
3.3
6.7
3.3
1.7
5.2
2.6
1.3
4.4
2.2
1.1
4.0
2.0
1.0
2.7
1.3
0.7
2.0
1.0
0.5
FAIL
FAIL
FAIL
FAIL
FAIL
FAIL
FAIL
FAIL
46.2
FAIL
FAIL
30.8
FAIL
FAIL
30.8
FAIL
FAIL
30.8
FAIL
33.3
38.5
FAIL
40.0
46.2
63.2
80.0
87.0
80.3
87.0
87.0
87.0
87.0
87.0
87.0
87.0
87.0
87.0
87.0
87.0
87.0
87.0
87.0
FAIL
26.7
30.8
FAIL
33.3
38.5
FAIL
40.0
46.2
63.2
74.1
74.1
74.1
74.1
74.1
74.1
74.1
74.1
74.1
74.1
74.1
74.1
74.1
74.1
74.1
74.1
74.1
FAIL
26.7
30.8
FAIL
33.3
38.5
31.6
40.0
46.2
63.2
64.5
64.5
64.5
64.5
64.5
64.5
64.5
64.5
64.5
64.5
64.5
64.5
64.5
64.5
64.5
64.5
64.5
400
500
FAIL
FAIL
38.5
FAIL
FAIL
38.5
500
500
600
FAIL
FAIL
46.2
FAIL
40.0
600
600
46.2
1200
1200
1200
1530
1530
1530
1800
1800
1800
2000
2000
2000
3000
3000
3000
4000
4000
4000
FAIL
80.0
FAIL
80.0
63.2
80.0
92.3
92.3
92.3
FAIL
102.0
104.0
FAIL
104.0
104.0
FAIL
104.0
104.0
104.0
104.0
104.0
104.0
104.0
104.0
80.3
80.3
102.0
104.0
91.8
102.0
104.0
91.8
104.0
104.0
100.0
104.0
104.0
104.0
104.0
104.0
104.0
104.0
104.0
104.0
104.0
100.0
104.0
104.0
104.0
104.0
104.0
104.0
104.0
104.0
In the previous table, consider the case of operating in integer mode with ORDER=0. For this case, lock detect
can theoretically work for all VCO frequencies provided that the phase detector frequency does not violate the
maximum possible value. For instance, it would be an invalid condition to operate in integer mode with a VCO
frequency of 900 MHz and a phase detector frequency of 100 MHz because 100 MHz exceeds the limit of 900
MHz/12 = 75 MHz. If the phase detector was lowered to 75 MHz to meet this restriction, then this condition would
be valid provided that the window size was programmed to be 9.5 ns or less.
Consider another example of a 400 MHz VCO frequency with a fourth order modulator. Because the minimum
window size of 20 ns is above the maximum programmable value of 13.5 ns, digital lock detect can not be used
in this configuration. If the modulator order was reduced to 2nd order, then it would function provided that the
phase detector frequency was less 30.8 MHz.
FSK - Frequency Shift Keying
This bit enables a binary FSK modulation mode using the PLL N counter. Consult the applications section for
more details.
FSK
FSK Mode
Disabled
Enabled
0
1
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Register R2
This word contains all the bits of the fractional denominator. These bits apply if the device is being used
fractional mode.
PLL_DEN[21:0] -- Fractional Denominator
These bits determine the fractional denominator.
PLL_DEN[21:0]
Fractional
Denominator
0
...
0
.
0
.
0
.
0
.
0
.
0
.
0
.
0
.
0
.
0
.
0
.
0
.
0
.
0
.
0
.
0
.
0
.
0
.
0
.
0
.
0
.
0
.
4194303
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Registers R1 and R0
Both registers R1 and R0 contain information for the PLL R counter, N counter, and fractional numerator. The
action of programming register R0, even to the same value, runs the VCO calibration when the device has the
internal VCO operating. There are some programming words that are split across these two registers.
PLL_R[11:0] -- PLL R Divider Value
The R divider divides the OSCin signal. Note that if the doubler is enabled, the R divider is bypassed.
PLL_R[11:0]
0
1
Illegal State
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
2
3
0
0
0
0
0
0
0
0
0
0
1
1
...
...
1
...
1
...
1
...
1
...
1
...
1
...
1
...
1
...
1
...
1
...
1
...
1
4095
PLL_N[17:0] PLL N Divider Value
When using integer mode, the PLL N divider value is split up into two different locations. In fractional mode, only
the 12 LSB bits of the N counter are used. Based on the order of the modulator, the range is shown in the table
below.
PLL_N[17:12]
PLL_N[11:0]
Divide Values below 12 are prohibited
<12
12
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
1
1
.
1
1
.
0
0
.
0
1
.
Intege
r
Mode
13
...
262143
12
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Possible with first order modulator only
13-14
15-18
19
Possible with first or second order modulator
Possible with first, second, or third order modulators only
x
.
x
.
x
.
x
.
x
.
x
.
0
.
0
.
0
.
0
.
0
.
0
.
0
.
1
.
0
.
0
.
1
.
1
.
...
Fracti
onal
Mode
4087
x
x
x
x
x
x
1
1
1
1
1
1
1
1
0
1
1
1
4088
-4091
Possible with a first, second, or third order modulator only
Possible with a first or second order modulator only
Possible with a first order modulator only
4092-
4093
4094
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SNOSB31I –JULY 2009–REVISED FEBRUARY 2013
Note that the N divider value has a minimum value, NMin, which is implied by the modulator order. NMin is 12 for
integer mode and a first order modulator, 13 for a 2nd order modulator,15 for a third order modulator, and 19 for
a fourth order modulator. The maximum phase detector frequency given the electrical specifications, modulator
order, and VCO frequency is shown below.
fPD ≤ Min( 104 MHz, fVCO / NMin
)
(8)
PLL_NUM[21:0] -- Fractional Numerator
The fractional numerator is formed by the NUM word that is split between two registers and applies in fractional
mode only. The fractional numerator, PLL_NUM must be less than or equal to the fractional denominator,
PLL_DEN.
Fractional
Numerator
PLL_NUM[21:16]
PLL_NUM[15:0]
0
...
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
4194303
APPLICATIONS INFORMATION
Typical Connections
Figure 30. Full Chip Mode, Differential OSCin
Microcontroller
+3.3 V
+3.3 V
100 W
+3.3V
Ferrite
+3.3V
Ferrite
+3.3V
Ferrite
+3.3V
Ferrite
+3.3V
Ferrite
+3.3V
VccPLL1
VccPLL2
1 mF
VregFRAC
+3.3V
Ferrite
4.7W
VccFRAC
0.1 mF
VccCP1
VccCP2
VrefVCO
VregVCO
LMX2541
+3.3V
+3.3V
4.7 mF
4.7W
VccVCO
1 mF
10W
VregRFout
VccRFout
VccDig
VccDiv
330W
330W
R2pLF
To Circuit
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LMX2541SQ2690E, LMX2541SQ3030E
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Figure 31. External VCO Mode, Single-Ended OSCin, RFout Pin not Used
51W
51W
+3.3V
+3.3V
Microcontroller
+3.3V
+3.3V
+3.3V
+3.3V
VccPLL1
VccPLL2
Ferrite
Ferrite
Ferrite
Ferrite
Ferrite
1 mF
VregFRAC
+3.3V
4.7W
VccFRAC
Ferrite
0.1 mF
VccCP1
VccCP2
VrefVCO
VregVCO
LMX2541
+3.3V
+3.3V
1 mF
4.7W
VccVCO
+3.3V
+3.3V
VregRFout
VccRFout
VccDig
VccDiv
R2pLF
R4_LF
To
Circuit
18W
18W
For both of the able connection diagrams, L1, L2, and Lmid should be left open, but the pads should be placed
on these pins for optimal solderability. The GND pins should have separate vias to ground and the GND DAP
also needs to be grounded with 9 vias. The VccVCO, VccRFout, and VccDiv pins can be shorted to the power
plane, but need to be connected. For the other Vcc pins, ferrite beads and bypass capacitors may be added in
order to improve spurious performance. VregVCO and VrefVCO need to be connected even if the internal VCO
is not being used. The VregRFout pin only needs to be connected if the RFout pin is being used. When a block is
not used, it is always still necessary to connect the corresponding Vcc pin, but the bypassing is not necessary,
as shown in the above diagram for the external VCO mode.
OSCin/OSCin* Connections
For single-ended operation, the signal is driven into the OSCin pin. The OSCin* pin is terminated the same as
the OSCin pin. This is a typical case if the device is driven by a TCXO. For both single-ended and differential
operation, the input is AC coupled because the OSCin/OSCin* pins self-bias to an optimal DC operating point.
Better performance for both phase noise and fractional spurs is obtained for signals with a higher slew rate, such
as a square wave. This is especially important for lower frequency signals, since slower frequency sine waves
have lower slew rates. Fractional spurs are typically about four dB better when running in differential mode as
opposed to single-ended mode.
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SNOSB31I –JULY 2009–REVISED FEBRUARY 2013
Figure 32. Single-Ended Operation
LMX2541
OSCin
0.1 mF
0.1 mF
OSCin*
For differential operation, as is the case when using an LVDS or LVPECL driver, a 100 Ω resistor is placed
across the OSCin/OSCin* traces
Figure 33. Differential Operation
LMX2541
0.1 mF
OSCin
OSCin*
0.1 mF
A third way to configure the device is in crystal mode (XO = 1). For this, the crystal is placed across the
OSCin/OSCin* pins. Crystals are specified for a specific load capacitance, CLoad. The load capacitors shown in
the figure each have a value of CLoad/2.
Figure 34. Crystal Mode Operation
LMX2541
OSCin
OSCin*
Current Consumption
The current consumption of the LMX2541 has many factors that influence it. Determining the current
consumption for the entire device involves knowing which blocks are powered up and adding their currents
together. The current in the electrical specifications gives some typical cases, but there could be some variation
over factors such as the phase detector frequency. Also, the output buffer current can be impacted by the
software controllable settings. By subtracting or adding combinations of the currents for the RFout buffer and
VCO divider, the current consumption for the device can be estimated for any usable configuration. The currents
for the buffer and VCO divider are as follows:
Block
Current (mA)
~ 40
RF Output Buffer
VCO Divider
(See Programmable Output Power with On/Off)
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Fractional Spurs
Primary Fractional Spurs
The primary fractional spurs occur at multiples of the channel spacing and can change based on the fraction. For
instance, if the phase detector frequency is 10 MHz, and the channel spacing is 100 kHz, then this could be
achieved using a fraction of 1/100. The fractional spurs would be at offsets that are multiples 100 kHz.
Sub-Fractional Spurs
Sub-fractional spurs occur at sub-multiples of the channel spacing, Fch. For instance, in the above example,
there could be a sub-fractional spur at 50 kHz. The occurrence of these spurs is dependent on the modulator
order. Integer mode and the first order modulator never have sub-fractional spurs. If the fractional denominator
can be chosen to avoid factors of 2 or 3, then there will also be no sub-fractional spurs. Sub-fractional spurs get
worse for higher order modulators. Dithering tends to reduce sub-fractional spurs at the expense of increasing
PLL phase noise. The following table provides guidance on predicting sub-fractional spur offset frequencies.
Table 9. Sub-Fractional Spur Offset Frequencies vs. Modulator Order and Fractional Denominator Factors
Fractional Denominator Factors
ORDER
No Factor of 2 or 3
Factor of 2 but not 3
Factor of 3 but not 2
Factor of 2 and 3
None
Integer Mode
None
None
None
None
None
None
None
Fch/2
Fch/2
Fch/4
None
None
None
Fch/3
Fch/3
1st Order Modulator
2nd Order Modulator
3rd Order Modulator
4th Order Modulator
None
Fch/2
Fch/6
Fch/12
Impact of VCO_DIV on Fractional spurs
Because the fractional and sub-fractional spur levels do not depend on output frequency, there is a big benefit to
division. In general, every factor of 2 gives a 6 dB improvement to fractional spurs. Also, since the spur offset
frequency is not divided, the channel spacing at the VCO can be also increased to improve the spurs. However,
if the on-chip VCO is used, crosstalk can cause spurs at a frequency of fRFout mod fPD. Consider the following
example of a 50 MHz phase detector frequency and VCO_DIV = 2. If the VCO is at 3000.1 MHz and divided by 2
to get 1500.05 MHz, there will be a spur at an offset of 50 kHz (1500.05 MHz mod 50 MHz). However, if the
VCO frequency is at 3050.1 MHz, the output will be at 1525.05 MHz, but the spur will be at a much farther offset
that can easily be filtered by the loop filter of 25.05 MHz (1525.05 MHz mod 50 MHz).
PLL Phase Noise
Disregarding the impact of reference oscillator noise, loop filter resistor thermal noise, and loop filter shaping, the
phase noise of the PLL can be decomposed into three components: flicker noise, flat noise, and fractional noise.
These noise sources add in an RMS sense to produce the total PLL noise. In other words:.
LPLL(f) =
(f) / 10 )
10·log(10(L
(f) / 10 ) + 10(L
(f) / 10 )+ 10(L
PLL_flat
PLL_flicker
PLL_fractional
Potential Influencing Factors
Symbol
f
fVCO
Yes
Yes
No
fPD
Yes
No
KPD
Yes
Yes
No
FRAC
No
LPLL_flat(f)
LPLL_flicker(f)
LPLL_fractional(f)
No
Yes
Yes
No
Yes
Yes
The preceding table shows which factors of offset frequency (f), VCO frequency (fVCO), phase detector frequency
(fPD), charge pump gain (KPD), and the fractional settings (FRAC) can potentially influence each phase noise
component. The fractional settings include the fraction, modulator order, and dithering.
For the flat noise and flicker noise, it is possible to normalize each of these noise sources into a single index. By
normalizing these noise sources to an index, it makes it possible to calculate the flicker and flat noise for an
arbitrary condition. These indices are reported in the electrical characteristics section and in the typical
performance curves.
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Noise Component
Index
Relationship
LPLL_flat(f) =
LNPLL_flat(1 Hz)
+ 20·log(N) + 10·log(fPD
LNPLL_flat
(1 Hz)
LPLL_flat(f)
)
LPLL_flicker(f) =
LNPLL_flicker(10 kHz)
- 10·log(10 kHz / f) + 20·log( fVCO / 1 GHz )
LNPLL_flicker
(10 kHz)
LPLL_flicker(f)
The flat noise is dependent on the PLL N divider value (N) and the phase detector frequency (fPD) and the 1 Hz
Normalized phase noise ( LNPLL_flat(1 ). The 1 Hz normalized phase noise can also depend on the charge
Hz)
pump gain as well. In order to make an accurate measurement of just the flat noise component, the offset
frequency must be chosen sufficiently smaller then the loop bandwidth of the PLL, and yet large enough to avoid
a substantial noise contribution from the reference and PLL flicker noise. This becomes easier to measure for
lower phase detector frequencies.
The flicker noise, also known as 1/f noise, can be normalized to 1 GHz carrier frequency and 10 kHz offset,
LNPLL_flicker(10 kHz). Flicker noise can dominate at low offsets from the carrier and has a 10 dB/decade slope and
improves with higher charge pump currents and at higher offset frequencies . To accurately measure the flicker
noise it is important to use a high phase detector frequency and a clean crystal to make it such that this
measurement is on the 10 dB/decade slope close to the carrier. LPLL_flicker(f) can be masked by the reference
oscillator performance if a low power or noisy source is used.
An alternative way to interpret the flicker noise is the 1/f noise corner, fcorner. This would be the offset frequency
where the flat noise and flicker noise are equal. This corner frequency changes as a function of the phase
detector frequency and can be related to the flat and flicker noise indices as shown below.
(10 kHz) - LN
fcorner = 10( (LN
(1 Hz) - 140) / 10 ) × fPD
PLL_flicker
PLL_flat
Based on the values for LNPLL_flicker(10 kHz) and LNPLL_flat(1Hz) as reported in the electrical specifications,
the corner frequency can be calculated. For example, one of the plots in the typical performance characteristics
shows the phase noise with a 100 MHz phase detector frequency and 32X charge pump gain. In this case, this
corner frequency works out to be 0.000123 × 100 MHz = 12.3 kHz.
KPD
1X
LNPLL_flicker(10 kHz)
-116.0 dBc/Hz
LNPLL_flat(1 Hz)
-220.8 dBc/Hz
-225.4 dBc/Hz
fcorner
0.000302 × fPD
0.000123 × fPD
32X
-124.5 dBc/Hz
For integer mode or a first order modulator, there is no fractional noise (disregarding fractional spurs). For higher
order modulators, the fractional engine may or may not add significant phase noise depending on the fraction
and choice of dithering.
Impact of Modulator Order, Dithering, and Larger Equivalent Fractions on Spurs and Phase
Noise
To achieve a fractional N value, an integer N divider is modulated between different values. This gives rise to
three main degrees of freedom with the LMX2541 delta sigma engine: the modulator order, dithering, and the
way that the fractional portion is expressed. The first degree of freedom, the modulator order, can be selected as
zero (integer mode), one, two, three, or four. One simple technique to better understand the impact of the delta
sigma fractional engine on noise and spurs is to tune the VCO to an integer channel and observe the impact of
changing the modulator order from integer mode to a higher order. A higher fractional modulator order in theory
yields lower primary fractional spurs. However, this can also give rise to sub-fractional spurs in some
applications. The second degree of freedom is dithering. Dithering seeks to improve the sub-fractional spurs by
randomizing the sequence of N divider values. In theory, a perfectly randomized sequence would eliminate all
sub-fractional spurs, but add phase noise by spreading the energy that would otherwise be contained in the
spurs. The third degree of freedom is the way that the fraction is expressed. For example, 1/10 can be expressed
as a larger equivalent fraction of 100000/1000000. Using larger equivalent fractions tends to increase
randomization similar to dithering. In general, the very low phase noise of the LMX2541 exposes the modulator
noise when dithering and large fractions are used, so use these with caution. The avid reader is highly
encouraged to read application note 1879 for more details on fractional spurs. The following table summarizes
the relationships between spur types, phase noise, modulator order, dithering and fractional expression.
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Action
Using
Larger
Equivalent
Fractions
Increase
Modulator
Order
Noise/Spur Type
Increase
Dithering
WORSE
Phase Noise
(But only for larger fractions or
more dithering)
WORSE
NO IMPACT
BETTER
WORSE
NO IMPACT
BETTER
Primary Fractional Spur
Sub-Fractional Spurs
BETTER
WORSE
(Creates more sub-fractional
spurs)
Modulator Order
In general, the fractional mode of the PLL enables the use of a higher phase detector frequency relative to the
channel spacing, which enables the in-band noise of the PLL to be lower. The choice of modulator order to be
used in fractional mode is based on how much higher fPD can be made relative to the channel spacing and the
acceptable spur levels. The LMX2541 has a programmable modulator order which allows the user to make a
trade-off between PLL noise and primary and sub-fractional spur performance. The following table provides some
general guidelines for choosing modulator order: Note that the spurs due to crosstalk will not be impacted by
modulator order.
ORDER
Guidelines for use
•
•
Use if fPD can be made very high without using a fractional N value.
Use if it is not desired to make fPD higher using a fractional N value. This could be the
case if the loop bandwidth is very narrow and smaller loop filter capacitors are desired.
Integer Mode
•
•
Use 1st order if fPD can be increased by at least a factor of four over the integer case
and fractional spur frequencies and levels are acceptable.
If the channel spacing is 5 MHz or greater, the 1st order modulator may provide better
spur performance than integer mode.
1st Order Modulator
•
If the spurs of the 1st order modulator are unacceptable, use a higher order modulator. If
the spurious components are due to crosstalk they will not be improved by increasing
modulator order. In this case , use the lowest order modulator that gives acceptable
performance.
2nd Order Modulator
3rd Order Modulator
4th Order Modulator
•
•
Use if the spurs of the 1st order modulator are unacceptable.
In general, use the lowest order modulator unless a higher order modulator yields an
improvement in primary fractional spurs. If the spurious components are due to crosstalk,
they will not be improved by increasing the modulator order.
Programmable Output Power with On/Off
The power level of the RFout pin is programmable, including on/off controls. The RFoutEN pin and RFOUT word
can be used to turn the RFout pin on and off while still keeping the VCO running and in lock. In addition to on/off
states, the power level can also be programmed in various steps using the VCOGAIN, DIVGAIN, and OUTTERM
programming words. There are tables in the Typical Performance Characteristics (Not Guaranteed) section that
discuss the impact of these words on the output power. In addition to impacting the output power, these words
also impact the current consumption of the device. This data was obtained as an average over all frequencies. In
general, it is desirable to find the combination of programming words that gives the lowest current consumption
for a given output power level. All numbers reported are relative to the case of VCOGAIN = OUTTERM = 12.
According to this data, using a VCOGAIN or OUTTERM value of 12 or greater yields only a small increase in
output power, but a large increase in current consumption.
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Table 10. Change in Current Consumption in Bypass Mode as a Function of VCOGAIN and OUTTERM
VCOGAIN
3
6
9
12
15
3
6
-26.0
-18.5
-11.1
-3.8
-22.3
-15.5
-9.0
-18.6
-12.6
-6.9
-15.1
-9.7
-11.8
-6.9
OUTTERM
9
-4.7
-2.5
12
15
-2.6
-1.4
+0.0
+4.5
+1.5
+5.3
+3.3
+3.7
+4.0
Table 11. Change in Current Consumption in Divided Mode as a Function of DIVGAIN and OUTTERM
DIVGAIN
3
6
9
12
15
3
6
-24.4
-16.2
-8.3
-21.7
-14.6
-7.6
-18.7
-12.6
-6.8
-15.9
-10.1
-5.0
-13.3
-8.0
OUTTERM
9
-3.2
12
15
-0.5
-0.7
-0.7
+0.0
+4.9
+1.3
+5.6
+7.1
+6.0
+5.2
Loop Filter
Loop filter design can be rather complicated, but there are design tools and references available at www.ti.com.
The loop bandwidth can impact the size of loop filter capacitors and also how the phase noise is filtered. For
optimal integrated phase noise, choose the bandwidth to be about 20% wider than the frequency where the in-
band PLL phase noise (as described in PLL Phase Noise) and open loop VCO noise cross. This optimal loop
bandwidth may need adjustment depending on the application requirements. Reduction of spurs can be achieved
by reducing the loop bandwidth. On the other hand, a wider loop bandwidth may be required for faster lock time.
Note that using the integrated loop filter components can lead to a significant restriction on the loop bandwidth
and should be used with care. 2 kΩ for R3_LF and R4_LF is a good starting point. If the integrated loop filter
restricts the loop bandwidth, then first try to relieve this restriction by reducing the integrated loop filter resistors
and then reduce the capacitors only if necessary.
Configuring the LMX2541 for Optimal Performance
1. Determine the Channel Spacing (fCH
)
–
For a system that has a VCO that tunes over several frequencies, the channel spacing is the tuning
increment. In the case that the VCO frequency is fixed, this channel spacing is the greatest number that
divides both the VCO frequency and the OSCin frequency.
2. Determine OSCin Frequency (fOSCin
)
–
If the OSCin frequency is not already determined, then there are several considerations. A higher
frequency is generally, but not always, preferable. One reason for this is that it has a higher slew rate if it
is a sine wave. Another reason is that the clock for the VCO frequency calibration is based on the OSCin
frequency and in general will run faster for higher OSCin frequencies.
–
Although a higher OSCin frequency is desirable, there are also reasons to use a lower frequency. If the
OSCin frequency is strategically chosen, the worst case fractional spur channels might fall out of band.
Also, if the OSCin frequency can be chosen such that the fractional denominator can avoid factors of 2
and/or 3, the sub-fractional spurs can be reduced.
3. Determine the Phase Detector Frequency (fPD) , Charge Pump Gain (KPD) and Fractional Denominator
(FDEN)
–
In general, choose the highest phase detector frequency and charge pump gain, unless it leads to loop
filter capacitor values that are unrealistically large for a given loop bandwidth. In this case, reducing either
the phase detector frequency or the charge pump gain can yield more feasible capacitor values. Other
reasons for not using the highest charge pump gain is to allow some adjustment margin to compensate
for changes in the VCO gain or allow the use of Fastlock.
–
For choosing the fractional denominator, start with FDEN = fPD/fCH. As discussed previously, there might
be reasons to choose larger equivalent fractions.
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4. Design the Loop Filter
5. Determine the Modulator Order
6. Determine Dithering and Potential Larger Equivalent Fractional Value
External VCO Mode
The LMX2541 also has provisions to be driven with an external VCO as well. In this mode, the user has the
option of using the RFout pin output, although if this pin is used, the VCO input frequency is restricted to 4 GHz.
If not used, the RFout pin should be left open. The VCO input is connected to the ExtVCOin pin. Because the
internal VCO is not being used, the part option that is being used does not have a large impact on phase noise
or spur performance. It is also possible to switch between both Full Chip mode and External VCO mode.
Internal VCO Digital Calibration Time
When the LMX2541 is used in full chip mode, the integrated VCO can impact the lock time of the system. This
digital calibration chooses the closest VCO frequency band, which typically gets the device within a frequency
error 10 MHz or less of the final settling frequency, although this final frequency error can change slightly
between the different options of the LMX2541. Once this digital calibration is finished, this remaining frequency
error must settle out, and this remaining lock time is dictated by the loop bandwidth.
Based on measured data, this digital calibration time can be approximated by the following formula:
LockTime = A + B/CLK + C·ΔF + D·( ΔF/CLK )
(9)
Symbo1
Value
Varies
30
Units
µs
Locktime
A
B
μs
3800
0.1
None
us/MHz
µs
C
D
2
ΔF
Varies
MHz
fOSCin / 2
for 0 ≤ OSC_FREQ ≤ 63
fOSCin / 4
for 64 ≤ OSC_FREQ ≤ 127
fOSCin / 8
CLK
None
for 128 ≤ OSC_FREQ
For example, consider the LMX2541SQ3320E changing from 3600 to 3400 with an OSCin frequency of 100
MHz. In this case, ΔF = 200 (direction of frequency change does not matter), fOSCin = 100 MHz, and
OSC_FREQ=100. The calibration circuitry is run at a clock speed of CLK = 100 MHz / 4 = 25 MHz. When this
values are substituted in the formula, the resulting lock time is 218 μs. After this time, the VCO will be within
about 10 MHz of the final frequency and this final frequency error will settle out in an analog fashion. This final
frequency error can be slightly different depending on which option of the LMX2541 is being used.
Digital FSK Mode
The LMX2541 supports 2-level digital frequency shift keying (FSK) modulation. The bit rate is limited by the loop
bandwidth of the PLL loop. As a general rule of thumb, it is desirable to have the loop bandwidth at least twice
the bit rate. This is achieved by changing the N counter rapidly between two states. The fractional numerator and
denominator are restricted to a length of 12 bits. The 12 LSB’s of the numerator and denominator set the center
frequency, Fcenter, and the 10 MSB’s of the numerator set the frequency deviation, Fdev. The LMX2541 has the
ability to switch between two different numerator values based on the voltage at the DATA pin. When DATA is
low, the output frequency will be Fcenter – Fdev and when the DATA pin is high the output frequency will be
Fcenter + Fdev. A limitation of the FSK mode is the frequency deviation can not cause the N counter to cross
integer boundaries. When using FSK mode, the FDM bit needs to be set to zero.
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LMX2541SQ2690E, LMX2541SQ3030E
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SNOSB31I –JULY 2009–REVISED FEBRUARY 2013
REVISION HISTORY
Changes from Revision H (February 2013) to Revision I
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 56
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PACKAGE OPTION ADDENDUM
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11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
LMX2541SQ2060E/NOPB
LMX2541SQ2380E/NOPB
LMX2541SQ2690E/NOPB
LMX2541SQ3030E/NOPB
LMX2541SQ3320E/NOPB
LMX2541SQ3740E/NOPB
LMX2541SQE2060E/NOPB
LMX2541SQE2380E/NOPB
LMX2541SQE2690E/NOPB
LMX2541SQE3030E/NOPB
LMX2541SQE3320E/NOPB
LMX2541SQE3740E/NOPB
LMX2541SQX2060E/NOPB
LMX2541SQX2380E/NOPB
LMX2541SQX2690E/NOPB
LMX2541SQX3030E/NOPB
LMX2541SQX3320E/NOPB
ACTIVE
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
NJK
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
1000
Green (RoHS
& no Sb/Br)
CU SN
CU SN
CU SN
CU SN
CU SN
CU SN
CU SN
CU SN
CU SN
CU SN
CU SN
CU SN
CU SN
CU SN
CU SN
CU SN
CU SN
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
412060E
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
NJK
NJK
NJK
NJK
NJK
NJK
NJK
NJK
NJK
NJK
NJK
NJK
NJK
NJK
NJK
NJK
1000
1000
1000
1000
1000
250
Green (RoHS
& no Sb/Br)
412380E
412690E
413030E
413320E
413740E
412060E
412380E
412690E
413030E
413320E
413740E
412060E
412380E
412690E
413030E
413320E
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
250
Green (RoHS
& no Sb/Br)
250
Green (RoHS
& no Sb/Br)
250
Green (RoHS
& no Sb/Br)
250
Green (RoHS
& no Sb/Br)
250
Green (RoHS
& no Sb/Br)
2500
2500
2500
2500
2500
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Orderable Device
LMX2541SQX3740E/NOPB
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
ACTIVE
WQFN
NJK
36
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 85
413740E
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Mar-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMX2541SQ2060E/NOPB WQFN
LMX2541SQ2380E/NOPB WQFN
LMX2541SQ2690E/NOPB WQFN
LMX2541SQ3030E/NOPB WQFN
LMX2541SQ3320E/NOPB WQFN
LMX2541SQ3740E/NOPB WQFN
NJK
NJK
NJK
NJK
NJK
NJK
NJK
36
36
36
36
36
36
36
1000
1000
1000
1000
1000
1000
250
330.0
330.0
330.0
330.0
330.0
330.0
178.0
16.4
16.4
16.4
16.4
16.4
16.4
16.4
6.3
6.3
6.3
6.3
6.3
6.3
6.3
6.3
6.3
6.3
6.3
6.3
6.3
6.3
1.5
1.5
1.5
1.5
1.5
1.5
1.5
12.0
12.0
12.0
12.0
12.0
12.0
12.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
LMX2541SQE2060E/NOP WQFN
B
LMX2541SQE2380E/NOP WQFN
B
NJK
NJK
NJK
NJK
NJK
NJK
36
36
36
36
36
36
250
250
250
250
250
2500
178.0
178.0
178.0
178.0
178.0
330.0
16.4
16.4
16.4
16.4
16.4
16.4
6.3
6.3
6.3
6.3
6.3
6.3
6.3
6.3
6.3
6.3
6.3
6.3
1.5
1.5
1.5
1.5
1.5
1.5
12.0
12.0
12.0
12.0
12.0
12.0
16.0
16.0
16.0
16.0
16.0
16.0
Q1
Q1
Q1
Q1
Q1
Q1
LMX2541SQE2690E/NOP WQFN
B
LMX2541SQE3030E/NOP WQFN
B
LMX2541SQE3320E/NOP WQFN
B
LMX2541SQE3740E/NOP WQFN
B
LMX2541SQX2060E/NOP WQFN
B
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Mar-2013
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMX2541SQX2380E/NOP WQFN
B
NJK
NJK
NJK
NJK
NJK
36
36
36
36
36
2500
2500
2500
2500
2500
330.0
330.0
330.0
330.0
330.0
16.4
16.4
16.4
16.4
16.4
6.3
6.3
6.3
6.3
6.3
6.3
6.3
6.3
6.3
6.3
1.5
1.5
1.5
1.5
1.5
12.0
12.0
12.0
12.0
12.0
16.0
16.0
16.0
16.0
16.0
Q1
Q1
Q1
Q1
Q1
LMX2541SQX2690E/NOP WQFN
B
LMX2541SQX3030E/NOP WQFN
B
LMX2541SQX3320E/NOP WQFN
B
LMX2541SQX3740E/NOP WQFN
B
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LMX2541SQ2060E/NOPB
LMX2541SQ2380E/NOPB
LMX2541SQ2690E/NOPB
LMX2541SQ3030E/NOPB
LMX2541SQ3320E/NOPB
LMX2541SQ3740E/NOPB
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
NJK
NJK
NJK
NJK
NJK
NJK
NJK
36
36
36
36
36
36
36
1000
1000
1000
1000
1000
1000
250
367.0
367.0
367.0
367.0
367.0
367.0
213.0
367.0
367.0
367.0
367.0
367.0
367.0
191.0
38.0
38.0
38.0
38.0
38.0
38.0
55.0
LMX2541SQE2060E/NOP
B
LMX2541SQE2380E/NOP
WQFN
NJK
36
250
213.0
191.0
55.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Mar-2013
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
B
LMX2541SQE2690E/NOP
B
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
NJK
NJK
NJK
NJK
NJK
NJK
NJK
NJK
NJK
NJK
36
36
36
36
36
36
36
36
36
36
250
250
213.0
213.0
213.0
213.0
367.0
367.0
367.0
367.0
367.0
367.0
191.0
191.0
191.0
191.0
367.0
367.0
367.0
367.0
367.0
367.0
55.0
55.0
55.0
55.0
38.0
38.0
38.0
38.0
38.0
38.0
LMX2541SQE3030E/NOP
B
LMX2541SQE3320E/NOP
B
250
LMX2541SQE3740E/NOP
B
250
LMX2541SQX2060E/NOP
B
2500
2500
2500
2500
2500
2500
LMX2541SQX2380E/NOP
B
LMX2541SQX2690E/NOP
B
LMX2541SQX3030E/NOP
B
LMX2541SQX3320E/NOP
B
LMX2541SQX3740E/NOP
B
Pack Materials-Page 3
MECHANICAL DATA
NJK0036A
SQA36A (Rev A)
www.ti.com
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相关型号：
LMX2541SQE3740E/NOPB
Ultra-Low Noise PLLatinum Frequency Synthesizer with Integrated VCO 36-WQFN -40 to 85
TI
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