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LMX2572LP

ZHCSIA2 –MAY 2018

具有 FSK 调制功能的 LMX2572LP 2GHz 低功耗宽带射频合成器

1 特性

3 说明

1

•

输出频率：12.5MHz 至 2GHz

低功耗：70mA，3.3V 电源供电

LMX2572LP 是一款低功耗、高性能宽带合成器，可生

成从 12.5MHz 到 2GHz 之间的一个频率，而无需使用

内部倍频器。该 PLL 可提供优异的性能，而 3.3V 单

电源中的电流消耗仅为 70mA。

•

在 100kHz 偏移和 800MHz 载波的情况下具有

–124dBc/Hz 的相位噪声

•

PLL 品质因数：–232dBc/Hz

PLL 标称 1/f 噪声：–123.5dBc/Hz

32 位分数 N 分频器

对于数字移动无线电 (DMR) 和无线麦克风等应用

，LMX2572LP 支持 FSK 调制。它支持离散电平 FSK

和脉冲整形 FSK。离散数字 FSK 调制可通过编程或引

脚实现。

用可编程输入乘法器消除整数边界杂散

跨多个设备实现输出相位同步

支持斜升和线性调频脉冲函数

支持 FSK 直接数字调制

LMX2572LP 允许用户同步多个器件的输出，并可支持

需要输入和输出之间具有确定延迟的应用。

LMX2572LP 提供了一个可精准调节相位的选项，以解

决电路板上或器件内的延迟不匹配问题。频率斜升发生

器可在自动斜坡生成选项或手动选项中最多合成 2 段

斜坡，以实现最大的灵活性。通过快速校准算法，用户

可在不到 20μs 的时间内改变频率。

两个可编程输出功率水平差动输出

较快的 VCO 校准速度：< 20µs

3V 至 3.5V 单电源

2 应用

•

测试和测量设备

LMX2572LP 集成了通过 3.3V 单电源供电的 LDO，无

需再配备板载低噪声 LDO。

双线制数字音频广播

低功耗无线电通信系统

卫星通信

器件信息⁽¹⁾

器件型号

LMX2572LP

封装

VQFN (40)

封装尺寸（标称值）

无线耳机

6.00mm × 6.00mm

专有无线连接

MIMO

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

高速数据转换器计时

功能方框图

CPout

Vtune

OSCinP

OSCinM

Pre-R

Divider

Post-R

Divider

Charge

Pump

RFoutAP

RFoutAM

,

x2

MULT

CSB

SCK

SDI

N-Divider

÷2/4/8…/256

Serial Interface

LDOs

RFoutBP

RFoutBM

Lock Detect or

Register Readback

Phase

Sync

Ramp Generator

FSK Generator

ꢀû

Modulator

MUXout

Enable

SYNC

CE

RampClk RampDir SysRefReq

1

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。 TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SNAS764

LMX2572LP

ZHCSIA2 –MAY 2018

www.ti.com.cn

7.5 Programming........................................................... 17

7.6 Register Maps......................................................... 20

Application and Implementation ........................ 59

8.1 Application Information............................................ 59

8.2 Typical Application .................................................. 69

8.3 Do's and Don'ts....................................................... 70

Power Supply Recommendations...................... 72

1

2

3

4

5

6

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 5

6.5 Electrical Characteristics........................................... 5

6.6 Timing Requirements................................................ 7

6.7 Timing Diagrams....................................................... 8

6.8 Typical Characteristics.............................................. 9

Detailed Description ............................................ 12

7.1 Overview ................................................................. 12

7.2 Functional Block Diagram ....................................... 12

7.3 Feature Description................................................. 12

7.4 Device Functional Modes........................................ 17

8

9

10 Layout................................................................... 73

10.1 Layout Guidelines ................................................. 73

10.2 Layout Example .................................................... 73

11 器件和文档支持 ..................................................... 74

11.1 器件支持................................................................ 74

11.2 文档支持................................................................ 74

11.3 接收文档更新通知 ................................................. 74

11.4 社区资源................................................................ 74

11.5 商标....................................................................... 74

11.6 静电放电警告......................................................... 74

11.7 术语表 ................................................................... 74

12 机械、封装和可订购信息....................................... 74

7

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

日期

版本

注释

2018 年 5 月

*

初始发行版

2

LMX2572LP

www.ti.com.cn

ZHCSIA2 –MAY 2018

5 Pin Configuration and Functions

RHA Package

40-Pin VQFN

Top View

CE

GND

1

2

3

4

5

6

7

8

9

10

30

29

28

27

26

25

24

23

22

21

RampClk

VrefVCO2

SysRefReq

VbiasVCO2

VccVCO2

GND

VbiasVCO

GND

SYNC

DAP

GND

VccDIG

OSCinP

OSCinM

VregIN

CSB

RFoutAP

RFoutAM

VccBUF

Not to scale

Pin Functions

I/O

DESCRIPTION

NAME

NO.

Chip enable. High impedance CMOS input. 1.8-V to 3.3-V logic. Active HIGH powers on the

device.

CE

1

Input

CPout

CSB

12

24

—

Output

Input

Charge pump output. Place C1 of loop filter close to this pin.

SPI latch. High impedance CMOS input. 1.8-V to 3.3-V logic.

RF ground.

DAP

Ground

2, 4, 25, 31,

34, 39

Ground

VCO ground.

GND

6, 14, 40

Ground

Output

Input

Digital ground.

13

20

9

Charge pump ground.

MUXout

OSCinM

OSCinP

Multiplexed output pin. Configurable between lock detect and register readback.

Reference input clock (–). High impedance self-biasing pin. Requires AC-coupling.

Reference input clock (+). High impedance self-biasing pin. Requires AC-coupling.

8

Input

Ramp trigger in automatic ramping mode or ramp clock in manual ramping mode. Can also

be used as FSK I2S clock input. High impedance CMOS input. 1.8-V to 3.3-V logic.

RampClk

30

Input

Ramp trigger in automatic ramping mode or ramp segment selection in manual ramping

mode. Can also be used as FSK I2S data input. High impedance CMOS input. 1.8-V to 3.3-V

logic.

RampDir

32

Input

RFoutAM

RFoutAP

RFoutBM

RFoutBP

SCK

22

23

18

19

16

Output

Input

Differential output A (–). Low impedance output. Requires AC-coupling.

Differential output A (+). Low impedance output. Requires AC-coupling.

Differential output B (–). Low impedance output. Requires AC-coupling.

Differential output B (+). Low impedance output. Requires AC-coupling.

SPI clock. High impedance CMOS input. 1.8-V to 3.3-V logic.

3

LMX2572LP

ZHCSIA2 –MAY 2018

www.ti.com.cn

Pin Functions (continued)

NAME

I/O

DESCRIPTION

NO.

SDI

17

Input

SPI data. High impedance CMOS input. 1.8-V to 3.3-V logic.

Phase synchronization trigger. Configurable to accept CMOS input (1.8-V to 3.3-V logic) or

differential input.

SYNC

5

SysRefReq

28

33

Input

FSK I2S Frame Sync input. High impedance CMOS input. 1.8-V to 3.3-V logic.

VCO Varactor bias. Connect a 10-µF decoupling capacitor to VCO ground.

VbiasVARAC

Bypass

VCO bias. Connect a 470-nF (X7R) decoupling capacitor to VCO ground as close to this pin

as possible.

VbiasVCO

3

Bypass

VbiasVCO2

VccBUF

27

21

11

7

Bypass

Supply

Bypass

VCO bias. Connect a 100-nF (X7R) decoupling capacitor to VCO ground.

Supply for output buffers. Connect a 0.1-µF decoupling capacitor to RF ground.

Supply for charge pump. Connect a 0.1-µF decoupling capacitor to charge pump ground.

Digital power supply. Connect a 0.1-µF decoupling capacitor to digital ground.

Digital power supply. Connect a 1-µF decoupling capacitor to digital ground.

Supply for VCO. Connect a 1-µF decoupling capacitor to VCO ground.

VCO supply reference. Connect a 10-µF decoupling capacitor to VCO ground.

VccCP

VccDIG

VccMASH

VccVCO

VccVCO2

VrefVCO

VrefVCO2

15

37

26

36

29

Input reference path regulator output. Connect a 1-µF decoupling capacitor to RF ground as

close to this pin as possible.

VregIN

VregVCO

Vtune

10

38

35

Bypass

Input

VCO regulator node. Connect a 10-nF decoupling capacitor to VCO ground.

VCO tuning voltage input. Connect a 1.5-nF or more capacitor to VCO ground. See External

Loop Filter for details.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

MAX

3.6

UNIT

V

V_CC

V_IN

T_J

Power supply voltage

IO input voltage

–0.3

V_CC+ 0.3

150

V

Junction temperature

Storage temperature

°C

T_stg

–65

150

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per

±2000

ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾

V_(ESD)

Electrostatic discharge

V

Charged device model (CDM), per JEDEC

specification JESD22-C101, all pins⁽²⁾

±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

85

UNIT

°C

T_A

T_J

Ambient temperature

Junction temperature

–40

125

°C

4

LMX2572LP

www.ti.com.cn

ZHCSIA2 –MAY 2018

6.4 Thermal Information

LMX2572LP

THERMAL METRIC⁽¹⁾

RHA (VQFN)

UNIT

40 PINS

25.5

14.4

8

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

Ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.2

Ψ_JB

7.9

R_θJC(bot)

1.2

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.5 Electrical Characteristics

3.0 V ≤ V_CC≤ 3.5 V, –40°C ≤ T_A≤ 85°C. Typical values are at V_CC= 3.3 V, 25°C (unless otherwise noted).

PARAMETER

POWER SUPPLY

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V

V_CC

Supply voltage

3

3.3

70

3.5

f_OSCin= 20 MHz; f_PD= 40 MHz⁽¹⁾

f_OSCin= 100 MHz; f_PD= 100 MHz⁽²⁾

I_CC

Supply current

74.5

2.5

mA

I_CCPD

Power down current

INPUT SIGNAL PATH

OSC_2X = 0 (Doubler bypassed)

OSC_2X = 1 (Doubler enabled)

Single-ended input buffer

5

250

125

3.6

1

f_OSCin

OSCin input frequency

MHz

V

0.3

0.15

10

V_OSCin

OSCin input voltage⁽³⁾

Differential input buffer

f_MULTin

f_MULTout

PLL

Multiplier input frequency

Multiplier output frequency

40

MULT ≥ 3

MHz

60

150

Integer channel

1^stand 2^ndorder modulator

3^rdorder modulator

4^thorder modulator

CPG = 1

0.25

250

200

160

120

5

f_PD

Phase detector frequency⁽⁴⁾

MHz

µA

625

1250

1875

…

CPG = 2

I_CPout

Charge pump current

CPG = 3

···

CPG = 15

6875

–123.5

–232

PN_{PLL_1/f}

Normalized PLL 1/f noise⁽⁵⁾

Normalized PLL noise floor⁽⁵⁾

Integer channel⁽⁶⁾

Fractional channel⁽⁷⁾

dBc/Hz

MHz

PN_{PLL_Flat}

VCO

f_VCO

VCO frequency

3200

6400

(1) I_CP= 2.5 mA; f_VCO= 3.2 GHz; f_OUT= 400 MHz; P_OUT= −3 dBm; OSC_2X = 1; MULT = 1; one RF output.

(2) I_CP= 2.5 mA; f_VCO= 3.2 GHz; f_OUT= 400 MHz; P_OUT= −3 dBm; OSC_2X = 0; MULT = 1; one RF output.

(3) See OSCin Configuration for definition of OSCin input voltage.

(4) For lower VCO frequencies, the N-divider minimum value can limit the phase detector frequency.

(5) Measured with a clean OSCin signal with a high slew rate using a wide loop bandwidth. The noise metrics model the PLL noise for an

infinite loop bandwidth as: PLL_Total = 10*log[10^{(PLL_Flat/10)}+10^{(PLL_Flicker/10)}]; PLL_Flat = PN1 Hz + 20*log(N) + 10*log(f_PD); PLL_Flicker

= PN10 kHz - 10*log(Offset/10 kHz) + 20*log(f_OUT/1 GHz)

(6) f_OSCin= 200 MHz; f_PD= 100 MHz; f_VCO= 6 GHz

(7) f_OSCin= 200 MHz; f_PD= 100 MHz; f_VCO= 6.001 GHz; Fractional denominator = 1000.

5

LMX2572LP

ZHCSIA2 –MAY 2018

www.ti.com.cn

Electrical Characteristics (continued)

3.0 V ≤ V_CC≤ 3.5 V, –40°C ≤ T_A≤ 85°C. Typical values are at V_CC= 3.3 V, 25°C (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

–106

–129

–149

–153.5

–105.5

–129

–149.5

–152.5

–104.5

–129

–149

–153

–103

–128

–148.5

–154

–102.5

–127

–147.5

–154

–102

–126.5

–147

–153

39

MAX

UNIT

10 kHz

100 kHz

1 MHz

f_OUT= 425 MHz

(f_VCO= 3.4 GHz)

10 MHz

10 kHz

100 kHz

1 MHz

f_OUT= 487.5 MHz

(f_VCO= 3.9 GHz)

10 MHz

10 kHz

100 kHz

1 MHz

f_OUT= 550 MHz

(f_VCO= 4.4 GHz)

10 MHz

10 kHz

100 kHz

1 MHz

PN_VCO

Open loop VCO phase noise

dBc/Hz

f_OUT= 612.5 MHz

(f_VCO= 4.9 GHz)

10 MHz

10 kHz

100 kHz

1 MHz

f_OUT= 675 MHz

(f_VCO= 5.4 GHz)

10 MHz

10 kHz

100 kHz

1 MHz

f_OUT= 737.5 MHz

(f_VCO= 5.9 GHz)

10 MHz

f_VCO= 3.4 GHz

f_VCO= 3.9 GHz

f_VCO= 4.4 GHz

f_VCO= 4.9 GHz

f_VCO= 5.4 GHz

f_VCO= 5.9 GHz

44

55

K_VCO

VCO gain

MHz/V

60

69

62

No assist

130

f_OSCin= f_PD= 100 MHz; Switch

between 3.2 GHz and 6.4 GHz

VCO frequency

t_VCOcal

VCO calibration-time⁽⁸⁾

Partial assist

50

µs

°C

Full assist

5

|ΔT_CL

|

Allowable temperature drift⁽⁹⁾VCO not being re-calibrated, –40°C ≤ T_A≤ 85°C

125

RF OUTPUT

f_OUT

RF output frequency

12.5

2000

MHz

dBm

P_OUT

Single-ended output power

f_OUT= 2 GHz

5

−33.5

−43

f_OUT= 800 MHz

f_OUT= 400 MHz

f_OUT= 800 MHz

f_OUT= 400 GHz

f_OUT= 2 GHz

H2_OUT

Second harmonic

OUTx_PWR

= 15

dBc

ps

–10.5

−10

H3_OUT

Third harmonic

|t_skewCH|

Channel to channel skew

14

(8) See VCO Calibration for details.

(9) Not tested in production. Ensured by characterization. Allowable temperature drift refers to programming the device at an initial

temperature and allowing this temperature to drift WITHOUT reprogramming the device, and still have the device stay at lock. This

change could be up or down in temperature and the specification does not apply to temperatures that go outside the recommended

operating temperatures of the device.

6

LMX2572LP

www.ti.com.cn

ZHCSIA2 –MAY 2018

Electrical Characteristics (continued)

3.0 V ≤ V_CC≤ 3.5 V, –40°C ≤ T_A≤ 85°C. Typical values are at V_CC= 3.3 V, 25°C (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

PHASE SYNCHRONIZATION

Category 3

5

100

200

OSCin input frequency with

SYNC

f_OSCinSYNC

|t_skewSYNC|

MHz

ns

Categories 1 and 2

After phase synchronization;

f_OSCinSYNC = f_OUT= 100 MHz

OSCin to RFout skew

2

DIGITAL INTERFACE

V_IH

V_IL

I_IH

High-level input voltage

1.4

V_CC

0.4

25

V

µA

V

Low-level input voltage

High-level input current

Low-level input current

High-level output voltage

Low-level output voltage

–25

I_IL

25

V_OH

V_OL

Load current = –5 mA

Load current = 5 mA

V_CC– 0.5

MUXout pin

0.5

6.6 Timing Requirements

3.0 V ≤ V_CC≤ 3.5 V, –40°C ≤ T_A≤ 85°C. Typical values are at V_CC= 3.3 V, 25°C (unless otherwise noted).

MIN

NOM

MAX

UNIT

SERIAL INTERFACE WRITE TIMING

f_SCK

t_ES

SCK frequency

1 / (t_CWL+t_CWH

)

75

MHz

ns

SCK to CSB low time

SDI to SCK setup time

SDI to SCK hold time

SCK pulse width high

SCK pulse width low

CSB to SCK setup time

CSB pulse width high

5

2

5

2

t_CS

ns

t_CH

ns

t_CWH

t_CWL

t_CES

t_EWH

图 1

ns

SERIAL INTERFACE READ TIMING

f_SCK

t_ES

SCK frequency

1 / (t_CWL+t_CWH

)

50

MHz

ns

SCK to CSB low time

SDI to SCK setup time

SDI to SCK hold time

SCK pulse width high

SCK pulse width low

CSB to SCK setup time

CSB pulse width high

10

t_CS

ns

t_CH

ns

t_CWH

t_CWL

t_CES

t_EWH

图 1

ns

SYNC TIMING

t_CSPin to OSCin setup time

t_CHPin to OSCin hold time

2.5

2

ns

图 2

7

LMX2572LP

ZHCSIA2 –MAY 2018

www.ti.com.cn

6.7 Timing Diagrams

MSB

(R/W)

Address

(7-bit)

LSB

(D0)

SDI

SCK

(D15 œ D1)

t_CS

t_CH

1^st

2^nd

3^rdœ 7^th

8^th

9^thœ 23^rd

24^th

t_CE

t_CES

t_CWH

t_EWH

t_CWL

Read back register value

16-bit

MUXout

CSB

图 1. Serial Interface Timing Diagram

SYNC

OSCin

t_CS

t_CH

图 2. SYNC Timing Diagram

8

LMX2572LP

www.ti.com.cn

ZHCSIA2 –MAY 2018

6.8 Typical Characteristics

At T_A= 25°C, unless otherwise noted

-60

-80

-60

-80

425 MHz

487.5 MHz

-100

-120

-140

-160

-100

-120

-140

-160

1

2 3 45 710 20 50 100200

1000

10000 50000

1

2 3 45 710 20 50 100200

1000

10000 50000

Offset (kHz)

D033

D034

图 3. Open-Loop VCO Phase Noise at 425 MHz

图 4. Open-Loop VCO Phase Noise at 487.5 MHz

-60

-80

-60

-80

550 MHz

612.5 MHz

-100

-120

-140

-160

-100

-120

-140

-160

2 3 45 710 20 50 100200

1000

10000 50000

2 3 45 710 20 50 100200

1000

10000 50000

Offset (kHz)

D035

D036

图 5. Open-Loop VCO Phase Noise at 550 MHz

图 6. Open-Loop VCO Phase Noise at 612.5 MHz

-60

-80

-60

-80

675 MHz

737.5 MHz

-100

-120

-140

-160

-100

-120

-140

-160

2 3 45 710 20 50 100200

1000

10000 50000

2 3 45 710 20 50 100200

1000

10000 50000

Offset (kHz)

D037

D038

图 7. Open-Loop VCO Phase Noise at 675 MHz

图 8. Open-Loop VCO Phase Noise at 737.5 MHz

9

LMX2572LP

ZHCSIA2 –MAY 2018

www.ti.com.cn

Typical Characteristics (接下页)

At T_A= 25°C, unless otherwise noted

-100

-110

-120

-130

-140

-150

-160

425 MHz

487.5 MHz

-110

-120

-130

-140

-150

-160

1

2 3 5 710 20 50 100

1000

10000

100000

1

2 3 5 710 20 50 100

1000

10000

100000

Offset (kHz)

D039

D040

图 9. Wide Band Phase Noise at 425 MHz

图 10. Wide Band Phase Noise at 487.5 MHz

-100

-110

-120

-130

-140

-150

-160

-100

-110

-120

-130

-140

-150

-160

550 MHz

612.5 MHz

2 3 5 710 20 50 100

1000

10000

100000

2 3 5 710 20 50 100

1000

10000

100000

Offset (kHz)

D041

D042

图 11. Wide Band Phase Noise at 550 MHz

图 12. Wide Band Phase Noise at 612.5 MHz

-100

-110

-120

-130

-140

-150

-160

-100

-110

-120

-130

-140

-150

-160

675 MHz

737.5 MHz

2 3 5 710 20 50 100

1000

10000

100000

2 3 5 710 20 50 100

1000

10000

100000

Offset (kHz)

D043

D044

图 13. Wide Band Phase Noise at 675 MHz

图 14. Wide Band Phase Noise at 737.5 MHz

10

LMX2572LP

www.ti.com.cn

ZHCSIA2 –MAY 2018

Typical Characteristics (接下页)

At T_A= 25°C, unless otherwise noted

1800

1600

1400

1200

1000

800

VCO frequency jump from 6400 MHz to 3200 MHz

1600

1400

1200

1000

800

VCO frequency jump from 3200 MHz to 6400 MHz

600

-20

600

-20

0

20

40

60

80 100 120 140 160 180

0

20

40

60

80 100 120 140 160 180

Time (µs)

D045

D046

图 15. VCO Calibration Time

图 16. VCO Calibration Time

10

8

9

6

3

4

0

2

OUTx_PWR

-3

-6

-9

-12

5

12

18

0

f_OUT

-2

-4

-6

250 MHz

500 MHz

1000 MHz

2000 MHz

0

200 400 600 800 1000 1200 1400 1600 1800 2000

2

4

6

8

10

12

14

16

18

f_OUT(MHz)

OUTx_PWR

D047

D048

图 17. Output Power vs Frequency

图 18. Configurable Output Power

487.5032

487.5026

487.5019

487.5013

487.5006

487.5

425.085

425.068

425.051

425.034

425.017

425

487.4994

487.4987

487.4981

487.4974

487.4968

424.983

424.966

424.949

424.932

424.915

-250 -200 -150 -100 -50

0

50 100 150 200 250

-500

-300

-100

100

300

500

Time (µs)

D007

D008

图 19. 4-Level GFSK Modulation

图 20. Discrete-Level FSK Modulation

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7 Detailed Description

7.1 Overview

The LMX2572LP is a low-power, high-performance, wideband frequency synthesizer with integrated VCO and

output divider. The VCO operates from 3.2 to 6.4 GHz, and this can be combined with the output divider to

produce any frequency in the range of 12.5 MHz to 2 GHz. Within the input path, there are two dividers and a

multiplier for flexible frequency planning. The multiplier can also move the frequencies away from the integer

boundary to allow spur reduction.

The PLL is a fractional-N PLL with a programmable delta-sigma modulator up to 4^thorder. The fractional

denominator is a programmable 32-bit long that can supply fine frequency steps easily below the 1-Hz resolution.

The denominator can also be used to do exact fractions like 1/3, 7/1000, and many others.

For applications where deterministic or adjustable phase is desired, the SYNC pin can be used to get the phase

relationship between the OSCin and RFout pins deterministic. Once this is done, the phase can be adjusted in

very fine steps of the VCO period divided by the fractional denominator.

The ultra-fast VCO calibration is ideal for applications where the frequency must be swept or abruptly changed.

The frequency can be manually programmed, or the device can be set up to do ramps and chirps.

The FSK generator can support FSK generation in discrete 2-, 4-, or 8-level FSK. It can also support an arbitrary

level FSK.

The LMX2572LP device requires only a single 3.3-V power supply and uses very low current. The internal power

supplies are provided by integrated LDOs, eliminating the need for high performance external LDOs.

Digital logic interface is compatible with 1.8-V input. The user can program the device through the serial

interface. The device can be powered down through register programming or by toggling the Chip Enable (CE)

pin.

7.2 Functional Block Diagram

CPout

Vtune

OSCinP

OSCinM

Pre-R

Divider

Post-R

Divider

Charge

Pump

RFoutAP

RFoutAM

,

x2

MULT

CSB

SCK

SDI

N-Divider

÷2/4/8…/256

Serial Interface

LDOs

RFoutBP

RFoutBM

Lock Detect or

Register Readback

Phase

Sync

Ramp Generator

FSK Generator

ꢀû

Modulator

MUXout

Enable

SYNC

CE

RampClk RampDir SysRefReq

7.3 Feature Description

7.3.1 Reference Oscillator Input

The OSCin pins are used as a frequency reference input to the device. The input is high impedance and requires

AC-coupling capacitors at the pin. The OSCin pins can be driven single-ended with a CMOS clock, XO, or single-

ended differential clock. Differential clock input is also supported, which makes the device easier to interface with

high-performance system clock devices such as TI’s LMK series clock devices. As the OSCin signal is used as a

clock for the VCO calibration, a proper reference signal must be applied at the OSCin pin at the time of

programming FCAL_EN.

7.3.2 Reference Path

The reference path consists of an OSCin doubler (OSC_2X), Pre-R divider (PLL_R_PRE), Multiplier (MULT), and

a Post-R divider (PLL_R).

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Feature Description (接下页)

Phase

Frequency

Detector

Pre-R

Divider

Post-R

Divider

OSCin

Doubler

Multiplier

图 21. Reference Path

The Doubler allows one to double the input reference frequency up to 250 MHz. The Doubler adds minimal noise

and is useful for raising the phase detector frequency for better phase noise. The Doubler can also be used to

avoid spurs. The Doubler uses both the rising and falling edges of the input signal, so the input signal must have

50% duty cycle if the Doubler is enabled. Note that the Multiplier cannot be used if the Doubler is engaged.

The Pre-R divider can help reduce input frequency so that the Multiplier can be used and the maximum 200-MHz

input frequency limitation of the Post-R divider can be met.

The Multiplier multiplies the frequency up under the allowable multiplications of 3, 4, 5, 6, and 7. In combination

with the Pre-R and Post-R dividers, the Multiplier offers the flexibility to shift the phase detector frequency away

from frequencies that may create integer boundary spurs with the VCO and the output frequencies. Be aware

that unlike the Doubler, the Multiplier degrades the PLL figure of merit. This degradation would only matter,

however, for a very clean reference oscillator input and if the loop bandwidth was wide. The user should not use

the Doubler while using the Multiplier. The Multiplier is bypassed if its value is set to 1.

The Post-R divider can be used to further divide down the frequency to the phase detector frequency. When it is

used (PLL_R > 1), the input frequency to this divider is limited to 200 MHz.

Use 公式 1 to calculate the phase detector frequency, f_PD

.

f_PD= f_OSCin× OSC_2X × MULT / (PLL_R_PRE × PLL_R)

(1)

表 1 summarizes the usage boundaries of these functional blocks in the reference path.

表 1. Reference Path Boundaries

INPUT

FREQUENCY

(MHz)

OUTPUT

FREQUENCY

(MHz)

PARAMETER

VALUE

NOTES

MIN

MAX

MIN

MAX

OSCin

Doubler

N/A

5

250

When OSC_2X = 1, Multiplier cannot be used at the same

time.

0 (Bypassed), 1 (x2)

5

125

200

40

10

0.25

60

250

200

150

200

Pre-R divider

Multiplier

1 (Bypassed), 2, 3, …, 254, 255

1 (Bypassed), 3, 4, 5, 6, 7

1 (Bypass), 2, 3, …, 254, 255

Keep it equals 1 unless when necessary.

When the output frequency is greater than 100MHz, set

MULT_HI = 1.

10

5

Post-R divider

200

0.25

7.3.3 PLL Phase Detector and Charge Pump

The phase detector compares the outputs of the Post-R divider and N divider and generates a correction current

corresponding to the phase error until the two signals are aligned in phase. This charge-pump current is software

programmable to many different levels, allowing modification of the closed-loop bandwidth of the PLL.

表 2. Charge Pump Gain

CGP

0

1

2

3

4 or 8

5 or 9

6 or 10

7 or 11

12

13

14

15

UNIT

Gain

Tri-state

625

1250

1875

2500

3125

3750

4375

5000

5625

6250

6875

µA

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7.3.4 PLL N Divider and Fractional Circuitry

The N divider includes fractional compensation and can achieve any fractional denominator (PLL_DEN) from 1 to

(2³²– 1). The integer portion of N (PLL_N) is the whole part of the N divider value, and the fractional portion,

N_frac= PLL_NUM / PLL_DEN, is the remaining fraction. PLL_N, PLL_NUM and PLL_DEN are software

programmable. The higher the denominator, the finer the resolution step of the output. For example, even when

using f_PD= 200 MHz, the output can increment in steps of 200 MHz / (2³²– 1) = 0.0466 Hz. 公式 2 shows the

relationship between the phase detector and VCO frequencies. Note that in SYNC mode, there is an extra divider

that is not shown in 公式 2.

f_VCO= f_PD× [PLL_N + (PLL_NUM / PLL_DEN)]

(2)

The multi-stage noise-shaping (MASH) sigma-delta modulator that controls the fractional division is also

programmable from integer mode to fourth order. All of these settings work for integer channel where PLL_NUM

= 0. To make the fractional spurs consistent, the modulator is reset any time that the R0 register is programmed.

The N divider has minimum value restrictions based on the modulator order. Furthermore, the PFD_DLY_SEL bit

must be programmed in accordance to 表 3.

表 3. Minimum N Divider Restrictions

MASH ORDER

SECOND ORDER

VCO

FREQUENCY

(GHz)

INTEGER

FIRST ORDER

PFD_DLY_SEL

THIRD ORDER

PFD_DLY_SEL

FOURTH ORDER

N

PFD_DLY_SEL

N

PFD_DLY_SEL

N

PFD_DLY_SEL

f_VCO< 4

20

24

0

1

25

29

1

2

26

30

1

2

32

36

2

3

44

48

4

5

4 ≤ f_VCO< 4.9

4.9 ≤ f_VCO≤ 6.4

7.3.5 Voltage-Controlled Oscillator

The LMX2572LP includes a fully integrated VCO. The VCO generates a frequency which varies with the tuning

voltage from the loop filter. The entire VCO frequency range, 3.2 to 6.4 GHz, covers an octave that allows the

channel divider to take care of frequencies below the lower bound.

To reduce the VCO tuning gain, thus improving the VCO phase noise performance, the VCO frequency range is

divided into 6 different frequency bands. This creates the need for frequency calibration to determine the correct

frequency band given in a desired output frequency. The VCO is also calibrated for amplitude to optimize phase

noise. These calibration routines are activated any time that the R0 register is programmed with the FCAL_EN bit

equals one. It is important that a valid OSCin signal must present before VCO calibration begins. This device will

support a full sweep of the valid temperature range of 125°C (–40°C to 85°C) without having to re-calibrate the

VCO. This is important for continuous operation of the synthesizer under the most extreme temperature variation.

7.3.6 Channel Divider

To go below the VCO lower bound of 3.2 GHz, the channel divider can be used. The channel divider consists of

several segments, and the total division value is equal to the multiplication of them. Therefore, not all values are

valid.

RFoutA

VCO

÷2,4,8,16,

32,64,128,

256

RFoutB

图 22. Channel Divider

7.3.7 Output Buffer

The output buffers are differential push-pull type buffers, thus no external pullup to V_CCis required. The output

impedance of the buffer is very small, and as such, the buffer can be AC-coupled to drive a 50-Ω load. Output

power of the buffer can be programed to various levels. The buffer can be disabled while still keeping the PLL in

lock.

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7.3.8 Lock Detect

The MUXout pin can be configured to output a signal that gives an indication for the PLL being locked. If the

MUXout pin is configured as a lock detect output (MUXOUT_LD_SEL = 1), the MUXout pin output is a logic

HIGH voltage when the device is locked. When the device is unlocked, the MUXout pin output is a logic LOW

voltage.

There are options to select the definition of PLL being locked. If LD_TYPE = 0, lock detect asserts a HIGH output

after the VCO has finished calibration and the LD_DLY timeout counter is finished. If LD_TYPE = 1, in addition to

the VCO calibration and counter check, lock detect will assert a HIGH output if the VCO tuning voltage is also

within an acceptable limits.

7.3.9 Register Readback

The MUXout pin can also be configured to read back useful information from the device. Common uses for

readback are:

•

Read back registers to ensure that they have been programmed to the correct value. LMX2572LP allows any

of its registers to be read back.

•

Read back the lock detect status to determine if the PLL is in lock.

Read back VCO calibration information so that it can be used to improve the lock time.

7.3.10 Powerdown

The user can use the CE pin or the POWERDOWN bit to power the LMX2572LP up or down. All registers are

preserved in memory while the device is powered down.

The wake-up time for the device to come out of the powered state is adjustable. See Power-Up, Wake-Up Time

for details.

7.3.11 Phase Synchronization

The SYNC pin allows the user to synchronize the LMX2572LP such that the delay from the rising edge of th

OSCin signal to the RF output signal is deterministic. Phase synchronization is especially useful if there are

multiple LMX2572LP devices in a system and it is desirable to have all the RF outputs aligned in phase.

f_OUT

1

2

f_OSCin

Device 1

f_OUT1

f_OUT

SYNC

f_OSCin

Device 2

f_OUT2

SYNC

t₁

t₂

图 23. Phase Synchronization

Initially, the devices are locked to the input but are not synchronized. The user sends a synchronization pulse

that is re-clocked to the next rising edge of the OSCin pulse. After a given time, t₁, the devices are synchronized.

This time is dominated by the sum of the VCO calibration time, the analog settling time of the PLL loop, and the

MASH_RST_COUNT, if used in fractional mode. After synchronization, both devices will have a deterministic

delay of t₂, related to OSCin.

7.3.12 Phase Adjustment

The LMX2572LP can use the sigma-delta modulator to adjust the output signal phase with respect to the input

reference. The phase shift every time you write the value of MASH_SEED is 公式 3:

Phase shift in degree = 360° × (MASH_SEED / PLL_DEN) × (P / CHDIV)

where

•

P = 2 when VCO_PHASE_SYNC_EN = 1, else P = 1

(3)

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For example, if

•

MASH_SEED = 800

PLL_DEN = 1000

CHDIV = 32

VCO_PHASE_SYNC_EN = 0

Phase shift = 360° × (800 / 1000) × (1 / 32) = 9°. If we write 800 to MASH_SEED 40 times, then we will shift the

phase by 360°.

There are a couple of restrictions when using phase adjustment:

•

Phase adjustment does not work with MASH_ORDER equals 0 (Integer mode) or 1 (First order).

Phase adjustment is possible with integer channels (PLL_NUM = 0) as long as MASH_ORDER is greater

than 1.

•

PLL_DEN must be greater than PLL_NUM + MASH_SEED.

7.3.13 Ramping Function

The LMX2572LP supports the ability to make frequency ramping waveforms using manual mode or automatic

mode.

In manual ramping mode, the user defines a step and uses the RampClk and RampDir pins to create the ramp.

The output frequency jumps from one frequency to another frequency on each ramp.

In automatic ramping mode, the user sets up the ramp with up to two linear segments in advance and the device

automatically creates this ramp. The output waveform is a continuous frequency sweep between the start and

end frequencies. If the frequency ramping range is small (approximately 10 MHz), no VCO calibration break is

necessary in the middle of the ramp.

When using ramp, the following must be set accordingly:

•

Phase detector frequency must be between f_OSCin/ 2^CAL_CLK_DIVand 125 MHz.

OUT_FORCE = 1 to force the RF outputs not to be automatically muted during VCO calibration.

LD_DLY = 0 to avoid interfering with VCO calibration.

PLL_DEN = 2³²– 1. The actual denominator value being used in ramping mode is 2²⁴.

Time

Manual Ramping Mode

Automatic Ramping Mode

图 24. Ramping Modes

7.3.14 FSK Modulation

Direct digital FSK modulation is supported in LMX2572LP. FSK modulation is achieved by changing the output

frequency by changing the N divider value. The LMX2572LP supports three different types of FSK operation.

1. FSK SPI mode. This mode supports discrete 2-, 4- and 8-level FSK modulation. There are eight dedicated

registers used to pre-store the desired FSK frequency deviations. Program FSK_SPI_DEV_SEL to select

one of the FSK deviations at a time.

2. FSK SPI FAST mode. In this mode, instead of selecting one of the pre-stored FSK deviations, change the

FSK deviation directly by writing to FSK_SPI_FAST_DEV. As a result, this mode supports arbitrary-level

FSK, which is useful to construct pulse-shaping or analog-FM modulation.

3. FSK I2S mode. This mode is similar to the FSK SPI FAST mode, but the programming format is an I2S

format on dedicated pins instead of SPI. The benefit of using I2S is that this interface could be shared and

synchronous to other digital audio interfaces. In this mode, only the 16 bits of the DATA field are required to

program. The data is transmitted on the high or low side of the frame sync (programmable in register R114,

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FSK_I2S_FS_POL). The unused side of the frame sync needs to be at least one clock cycle. In other words,

17 (16 + 1) CLK cycles are required at a minimum for one I2S frame. Maximum I2S clock rate is 75 MHz.

Timing diagram is shown in 图 26 while the timing specification is same as SPI write timing as shown in the

Timing Requirements section.

Time

图 25. FSK Modulation

I2S DATA

(RampDir)

MSB

LSB

MSB

t_CS

t_CH

I2S CLK

(RampClk)

t_CES

t_CWH

t_CE

t_EWH

t_CWL

I2S FS

Frame (n)^th

Frame (n+1)^th

(SysRefReq)

图 26. FSK I2S Timing Diagram

7.4 Device Functional Modes

表 4 lists the device functional modes of the LMX2572LP.

表 4. Device Functional Modes

MODE

DESCRIPTION

Normal operation mode The device is used as a high frequency signal source without any addition features.

FSK mode

SYNC mode

Ramping mode

Generates discrete-level FSK or arbitrary-level pulse-shaped FSK modulation.

This mode is used to ensure deterministic phase between OSCin and RFout.

Automatic frequency sweeping without the need of continuous SPI programming.

7.5 Programming

The LMX2572LP is programmed using several 24-bit shift registers. The shift register consists of a data field, an

address field, and a R/W bit. The MSB is the R/W bit. 0 means register write while 1 means register read. The

following seven bits, ADDR[6:0], form the address field which is used to decode the internal register address.

The remaining 16 bits form the data field DATA[15:0]. Serial data is shifted MSB first into the shift register. See

图 1 for timing diagram details.

To write registers:

•

The R/W bit must be set to 0.

The data on SDI pin is clocked into the shift register upon the rising edge of the clocks on SCK pin. On the

rising edge of the 24^thclock cycle, the data is transferred from the data field into the selected register bank.

•

The CSB pin may be held high after programming, which causes the LMX2572LP to ignore clock pulses.

If the SCK and SDI lines are toggled while the VCO is in lock, as is sometimes the case when these lines are

shared between devices, the phase noise may be degraded during the time of this programming.

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Programming (接下页)

To read back registers:

•

The R/W bit must be set to 1.

The data field contents on the SDI line are ignored.

The read back data on MUXout pin is clocked out starting from the falling edge of the 8^thclock cycle.

7.5.1 Recommended Initial Power-On Programming

7.5.1.1 Programming Sequence

When the device is first powered up, it must be initialized, and the ordering of this programming is important. The

sequence is listed below. After this sequence is completed, the device should be running and locked to the

proper frequency.

1. Apply power to the device and ensure all the supply pins are at the proper levels.

2. If CE is low, pull it high.

3. Wait 500 µs for the internal LDOs to become stable.

4. Ensure that a valid reference clock is applied to the OSCin pins.

5. Program register R0 with RESET = 1. This will ensure all the registers are reset to their default values. This

bit is self-clearing.

6. Program in sequence registers R125, R124, R123, ..., R1 and then R0.

7.5.1.2 Programming Register

There are altogether 126 programmable registers. However, not every register is required to be programmed at

initial power-on.

For example, most of the registers have fixed field value which is also equal to their silicon default value. After

programming R0 with RESET = 1, these register fields have returned to their silicon default values. As such, it is

not necessary to program these registers again. Similarly, for those registers having configurable fields, if the

desired field values are equal to the silicon default values, again it is not necessary to program these registers

again after programming R0 with RESET = 1.

In 表 5, Depends means it is up to the user's decision of whether programming the register or not based upon

the application need.

表 5. Suggested Register Programming

REGISTER

PROGRAM

Yes

REGISTER

PROGRAM

No

REGISTER

PROGRAM

Yes

REGISTER

PROGRAM

No

REGISTER

84

PROGRAM

Depends

No

REGISTER

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

PROGRAM

Depends

No

0

1

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

Depends

No

Yes

No

85

2

No

Depends

No

86

3

No

87

No

4

No

88

No

5

Depends

No

89

No

6

No

Depends

Yes

90

No

7

No

91

No

8

Yes

No

92

No

9

No

93

No

Depends

10

11

12

13

14

15

16

17

18

19

Yes

No

94

No

95

No

Depends

No

96

Depends

No

97

Depends

No

98

Yes

Depends

Yes

99

Depends

No

Depends

No

Depends

100

101

102

103

Depends

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Programming (接下页)

表 5. Suggested Register Programming (接下页)

REGISTER

PROGRAM

REGISTER

PROGRAM

REGISTER

PROGRAM

REGISTER

PROGRAM

REGISTER

PROGRAM

REGISTER

125

PROGRAM

20

Depends

41

Depends

62

Depends

83

Depends

104

Depends

No

7.5.2 Recommended Sequence for Changing Frequencies

The recommended sequence for changing frequencies in different scenarios is as follows:

1. If the N divider is changing, program the relevant registers and then program R0 with FCAL_EN = 1.

2. In FSK and Ramp mode, the fractional numerator is changing; program the relevant registers only.

7.5.3 Double Buffering

Some register fields support double buffering. That is, the change to these fields would not be effective

immediately. To latch the new values into the device requires programming R0 again with FCAL_EN = 1. The

following register fields support double buffering, see 表 69 for details.

•

MASH order (MASH_ORDER)

Fractional numerator (PLL_NUM)

N divider (PLL_N)

Doubler (OSC_2X); Pre-R divider (PLL_R_PRE); Multiplier (MULT); Post-R divider (PLL_R)

For example,

1. Program PLL_R and PLL_N to new values. If double buffering for these fields is enabled, the PLL will remain

unchanged.

2. Program R0 with FCAL_EN = 1. The PLL will calibrate and lock using the new PLL_R and PLL_N values.

7.5.4 Block Programming

In a register write sequence, instead of sending 24 bits (one W/R bit, seven address bits, and 16 data bits) of

payload for each register (with Block Programming), only the first register write requires the W/R bit and the

address bits. The succeeding registers require sending only the 16-bit of data. However, the succeeding

registers must be in descending order. For example, if the first register is R20, then all 24 bits of payload must be

sent for R20. The next register must be R19, but only the 16-bit data is required. The programming sequence is

as follows:

1. Pull CSB pin LOW.

2. Write 0x14aaaa for R20.

3. Write 0xbbbb for R19, followed by 0xcccc for R18, and so on.

4. After the last register write is completed, pull CSB pin HIGH to finish Block Programming.

Since there is no CSB pulse between each register, the 16-bit of data field of each register can be sent

immediately after the previous one.

MSB

(R/W)

Address

(7-bit)

Data

(R20)

Data

(R19)

Data

(R18)

SDI

SCK

CSB

1^st

2^ndœ8^th

9^thœ24^th

25^thœ40^th

41^thœ56^th

图 27. Block Programming Timing Example

Block Programming applies to both register write and read.

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表 6 lists the access codes for the LMX2572 registers.

表 6. Access Type Codes

ACCESS TYPE CODE

Read Type

DESCRIPTION

R

Read

Write Type

W

Write

Reset or Default Value

-n

Value after reset

7.6.1 Register R0 (offset = 00h) [reset = 221Ch]

图 28. Register R0

15

14

13

1

12

0

11

10

0

9

8

7

6

5

4

1

3

2

1

0

RAMP_E VCO_PH

ADD_HO

LD

OUT_MU

TE

FCAL_HPFD_ADJ

FCAL_LPFD_ADJ

FCAL_E MUXOU

N

RESET

POWER

DOWN

N

ASE_SY

NC_EN

T_LD_S

EL

R/W-0h

R/W-2h

R/W-0h

R/W-1h

R/W-0h

R/W-1h

R/W-0h

表 7. Register R0 Field Descriptions

Bit

Field

Type Reset Description

R/W 0h

15

RAMP_EN

Enables frequency ramping. The action of programming register R0 with RAMP_EN =

1 starts the ramping. Be aware that this is in the same register as FCAL_EN, so

toggling this bit also can active the ramping if RAMP_EN = 1. RAMP_EN applies to

both automatic and manual ramping modes.

0: Normal operation

1: Starts frequency ramping

14

VCO_PHASE_SYNC_EN R/W 0h

Enables phase sync mode. In this state, part of the channel divider is put in the

feedback path to ensure deterministic phase. The action of toggling this bit from 0 to 1

also sends an asynchronous SYNC pulse.

0: Normal operation

1: Phase sync mode

13 - 12

11

R/W 2h

Program 2h to this field.

ADD_HOLD

R/W 0h

Freeze the register address in Block Programming. See Block Programming for

details.

10

9

R/W 0h

R/W 1h

Program 0h to this field.

OUT_MUTE

Mutes RF outputs (RFoutA and RFoutB) when the VCO is calibrating.

0: Disabled

1: Muted

8 - 7

FCAL_HPFD_ADJ

R/W 0h

Set this field in accordance to the phase detector frequency for optimal VCO

calibration.

0: f_PD≤ 37.5 MHz

1: 37.5 MHz < f_PD≤ 75 MHz

2: 75 MHz < f_PD≤ 100 MHz

3: f_PD> 100 MHz

6 - 5

FCAL_LPFD_ADJ

R/W 0h

Set this field in accordance to the phase detector frequency for optimal VCO

calibration.

0: f_PD≥ 10 MHz

1: 10 MHz > f_PD≥ 5 MHz

2: 5 MHz > f_PD≥ 2.5 MHz

3: f_PD< 2.5 MHz

4

3

R/W 1h

Program 1h to this field.

FCAL_EN

Enables and activates VCO frequency calibration. Writing register R0 with this bit set

to a 1 enables and triggers the VCO frequency calibration. Writing 0 to this field is

prohibited.

0: Invalid

1: Enabled

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表 7. Register R0 Field Descriptions (接下页)

Bit

Field

Type Reset Description

2

MUXOUT_LD_SEL

R/W 1h

R/W 0h

Selects the functionality of the MUXout pin.

0: Register readback

1: Lock detect

1

0

RESET

Resets all registers to silicon default values. This bit is self-clearing.

0: Normal operation

1: Reset

POWERDOWN

Powers down the device.

0: Normal operation

1: Power down

7.6.2 Register R1 (offset = 01h) [reset = 0808h]

图 29. Register R1

15

0

14

0

13

0

12

0

11

1

10

0

9

0

8

0

7

0

6

0

5

0

4

0

3

1

2

1

0

CAL_CLK_DIV

R/W-0h

R/W-101h

表 8. Register R1 Field Descriptions

Bit

Field

Type Reset Description

15 - 3

2 - 0

R/W 101h

R/W 0h

Program 101h to this field.

CAL_CLK_DIV

Divides down the state machine clock during VCO calibration. Maximum state

machine clock frequency is 200 MHz.

State machine clock frequency = f_OSCin/ (2^CAL_CLK_DIV).

0: f_OSCin≤ 200 MHz

1: 200 MHz < f_OSCin≤ 250 MHz

All other values are not used.

7.6.3 Register R2 (offset = 02h) [reset = 0500h]

图 30. Register R2

15

0

14

0

13

0

12

0

11

0

10

1

9

0

8

1

7

0

6

0

5

0

4

0

3

0

2

0

1

0

R/W-500h

表 9. Register R2 Field Descriptions

Bit

Field

Type Reset Description

R/W 500h Program 500h to this field.

After programming R0 with RESET = 1, no need to program this register.

15 - 0

7.6.4 Register R3 (offset = 03h) [reset = 0782h]

图 31. Register R3

15

0

14

0

13

0

12

0

11

0

10

1

9

1

8

1

7

1

6

0

5

0

4

0

3

0

2

0

1

0

R/W-782h

表 10. Register R3 Field Descriptions

Bit

Field

Type Reset Description

R/W 782h Program 782h to this field.

After programming R0 with RESET = 1, no need to program this register.

15 - 0

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7.6.5 Register R4 (offset = 04h) [reset = 0A43h]

图 32. Register R4

15

0

14

0

13

0

12

0

11

1

10

0

9

1

8

0

7

0

6

1

5

0

4

0

3

0

2

0

1

0

1

R/W-A43h

表 11. Register R4 Field Descriptions

Bit

Field

Type Reset Description

15 - 0

R/W A43h Program A43h to this field.

After programming R0 with RESET = 1, no need to program this register.

7.6.6 Register R5 (offset = 05h) [reset = 30C8h]

图 33. Register R5

15

0

14

0

13

1

12

11

10

0

9

0

8

0

7

1

6

1

5

0

4

0

3

1

2

0

1

0

IPBUF_T IPBUF_T

YPE

ERM

R/W-1h

R/W-0h

R/W-C8h

表 12. Register R5 Field Descriptions

Bit

15 - 13

12

Field

Type Reset Description

R/W 1h

Program 1h to this field.

IPBUF_TYPE

IPBUF_TERM

R/W 1h

Selects OSCin input type.

0: Differential input

1: Single-ended input

11

R/W 0h

Enables internal 50-Ω terminations on both OSCin and OSCin* pins. This function is

valid even if OSCin input is configured as single-ended input.

0: Normal operation

1: OSCin and OSCin* pins are internally 50-Ω terminated

10 - 0

R/W C8h

Program C8h to this field.

7.6.7 Register R6 (offset = 06h) [reset = C802h]

图 34. Register R6

15

14

13

12

11

10

0

9

0

8

0

7

0

6

0

5

0

4

0

3

0

2

0

1

0

LDO_DLY

R/W-19h

R/W-2h

表 13. Register R6 Field Descriptions

Bit

Field

Type Reset Description

15 - 11 LDO_DLY

R/W 19h

LDO start up delay. Delay duration is a function of state machine clock. See Power-

Up, Wake-Up Time for details.

10 - 0

R/W 2h

Program 2h to this field.

7.6.8 Register R7 (offset = 07h) [reset = 00B2h]

图 35. Register R7

15

0

14

13

0

12

0

11

0

10

0

9

0

8

0

7

1

6

0

5

1

4

1

3

0

2

0

1

0

OUT_FO

RCE

R/W-0h

R/W-B2h

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表 14. Register R7 Field Descriptions

Bit

15

14

Field

Type Reset Description

R/W 0h

Program 0h to this field.

OUT_FORCE

Forces the RF outputs not to be automatically muted during VCO calibration. This bit

should be enabled during frequency ramping.

0: Mute setting depends on OUT_MUTE

1: No mute during VCO calibration

13 - 0

R/W B2h

Program B2h to this field.

7.6.9 Register R8 (offset = 08h) [reset = 2000h]

图 36. Register R8

15

0

14

13

1

12

0

11

10

0

9

0

8

0

7

0

6

0

5

0

4

0

3

0

2

0

1

0

VCO_DA

CISET_F

ORCE

VCO_CA

PCTRL_

FORCE

R/W-0h

R/W-2h

R/W-0h

表 15. Register R8 Field Descriptions

Bit

15

14

Field

Type Reset Description

R/W 0h Program 0h to this field.

VCO_DACISET_FORCE R/W 0h

Forces VCO_DACISET value. Useful for fully-assisted VCO calibration and debugging

purposes.

0: Normal operation

1: Use VCO_DACISET value instead of the value obtained from VCO calibration

13 - 12

11

R/W 2h

Program 2h to this field.

VCO_CAPCTRL_FORCE R/W 0h

Forces VCO_CAPCTRL value. Useful for fully-assisted VCO calibration and

debugging purposes.

0: Normal operation

1: Use VCO_CAPCTRL value instead of the value obtained from VCO calibration

10 - 0

R/W 0h

Program 0h to this field.

7.6.10 Register R9 (offset = 09h) [reset = 0004h]

图 37. Register R9

15

0

14

13

0

12

11

0

10

0

9

0

8

0

7

0

6

0

5

0

4

0

3

0

2

1

0

MULT_H

I

OSC_2X

R/W-0h

R/W-4h

表 16. Register R9 Field Descriptions

Bit

15

14

Field

Type Reset Description

R/W 0h

Program 0h to this field.

MULT_HI

Sets this bit to 1 if the output frequency of the Multiplier is greater than 100 MHz.

0: Multiplier output ≤ 100 MHz

1: Multiplier output > 100 MHz

13

12

R/W 0h

Program 0h to this field.

OSC_2X

Enables reference path Doubler.

0: Disabled

1: Enabled

11 - 0

R/W 4h

Program 4h to this field.

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7.6.11 Register R10 (offset = 0Ah) [reset = 10F8h]

图 38. Register R10

15

0

14

0

13

0

12

1

11

10

9

8

7

6

1

5

1

4

1

3

1

2

0

1

0

MULT

R/W-1h

R/W-78h

表 17. Register R10 Field Descriptions

Bit

Field

Type Reset Description

15 - 12

R/W 1h

Program 1h to this field.

11 - 7 MULT

Reference path frequency Multiplier. Input frequency to the Multiplier: 10 to 40 MHz.

Multiplier output frequency: 60 to 150 MHz.

0: Not used

1: Bypassed

2: Not recommended. Use OSC_2X instead of MULT

3: 3X

·····

7: 7X

8 - 31: Not recommended

6 - 0

R/W 78h

Program 78h to this field.

7.6.12 Register R11 (offset = 0Bh) [reset = B018h]

图 39. Register R11

15

1

14

0

13

1

12

1

11

10

9

8

7

6

5

4

3

1

2

0

1

0

PLL_R

R/W-Bh

R/W-1h

R/W-8h

表 18. Register R11 Field Descriptions

Bit

Field

Type Reset Description

15 - 12

R/W Bh

R/W 1h

R/W 8h

Program Bh to this field.

11 - 4 PLL_R

3 - 0

Reference path Post-R divider. It is the divider after the frequency Multiplier.

Program 8h to this field.

7.6.13 Register R12 (offset = 0Ch) [reset = 5001h]

图 40. Register R12

15

0

14

1

13

0

12

1

11

10

9

8

7

6

5

4

3

2

1

0

PLL_R_PRE

R/W-1h

R/W-5h

表 19. Register R12 Field Descriptions

Bit

Field

Type Reset Description

15 - 12

R/W 5h

R/W 1h

Program 5h to this field.

Reference path Pre-R divider. It is the divider before the frequency Multiplier.

11 - 0 PLL_R_PRE

7.6.14 Register R13 (offset = 0Dh) [reset = 4000h]

图 41. Register R13

15

0

14

1

13

0

12

0

11

0

10

0

9

0

8

0

7

0

6

0

5

0

4

0

3

0

2

0

1

0

R/W-4000h

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表 20. Register R13 Field Descriptions

Bit

Field

Type Reset Description

15 - 0

R/W 4000h Program 4000h to this field.

After programming R0 with RESET = 1, no need to program this register.

7.6.15 Register R14 (offset = 0Eh) [reset = 1840h]

图 42. Register R14

15

0

14

0

13

0

12

1

11

1

10

0

9

0

8

0

7

0

6

5

4

3

2

0

1

0

CPG

R/W-30h

R/W-8h

R/W-0h

表 21. Register R14 Field Descriptions

Bit

Field

Type Reset Description

15 - 7

6 - 3

R/W 30h

R/W 8h

Program 30h to this field.

CPG

Effective charge pump gain. This is the sum of the up and down currents. Each

increment represents 625 µA.

0: Tri-state

1: 625 µA

2: 1250 µA

3: 1875 µA

·····

15: 6875 µA

2 - 0

R/W 0h

Program 0h to this field.

7.6.16 Register R15 (offset = 0Fh) [reset = 060Eh]

图 43. Register R15

15

0

14

0

13

0

12

0

11

0

10

1

9

1

8

0

7

0

6

0

5

0

4

0

3

1

2

1

0

R/W-60Eh

表 22. Register R15 Field Descriptions

Bit

Field

Type Reset Description

15 - 0

R/W 60Eh Program 60Eh to this field.

After programming R0 with RESET = 1, no need to program this register.

7.6.17 Register R16 (offset = 10h) [reset = 0080h]

图 44. Register R16

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

7

6

5

4

3

2

1

0

VCO_DACISET

R/W-80h

R/W-0h

表 23. Register R16 Field Descriptions

Bit

Field

Type Reset Description

15 - 9

8 - 0

R/W 0h

Program 0h to this field.

Programmable current setting for the VCO that is applied when

VCO_DACISET_FORCE = 1. Useful for fully-assisted VCO calibration.

VCO_DACISET

R/W 80h

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7.6.18 Register R17 (offset = 11h) [reset = 0096h]

图 45. Register R17

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

7

6

5

4

3

2

1

0

VCO_DACISET_STRT

R/W-96h

R/W-0h

表 24. Register R17 Field Descriptions

Bit

Field

Type Reset Description

15 - 9

8 - 0

R/W 0h

Program 0h to this field.

Starting calibration value for VCO_DACISET.

VCO_DACISET_STRT

R/W 96h

7.6.19 Register R18 (offset = 12h) [reset = 0064h]

图 46. Register R18

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

7

0

6

1

5

1

4

0

3

0

2

1

0

R/W-64h

表 25. Register R18 Field Descriptions

Bit

Field

Type Reset Description

R/W 64h Program 64h to this field.

After programming R0 with RESET = 1, no need to program this register.

15 - 0

7.6.20 Register R19 (offset = 13h) [reset = 27B7h]

图 47. Register R19

15

0

14

0

13

1

12

0

11

0

10

1

9

1

8

1

7

6

5

4

3

2

1

0

VCO_CAPCTRL

R/W-B7h

R/W-27h

表 26. Register R19 Field Descriptions

Bit

Field

Type Reset Description

15 - 8

7 - 0

R/W 27h

R/W B7h

Program 27h to this field.

VCO_CAPCTRL

Programmable band within VCO core that applies when VCO_CAPCTRL_FORCE = 1.

Valid values are 183 to 0, where the higher number is a lower frequency.

7.6.21 Register R20 (offset = 14h) [reset = 3048h]

图 48. Register R20

15

0

14

1

13

12

11

10

9

0

8

0

7

0

6

1

5

0

4

0

3

1

2

0

1

0

VCO_SEL

VCO_SE

L_FORC

E

R/W-0h

R/W-6h

R/W-0h

R/W-48h

表 27. Register R20 Field Descriptions

Bit

Field

Type Reset Description

15 - 14

R/W 0h

R/W 6h

Program 1h to this field.

13 - 11 VCO_SEL

User specified start VCO for calibration. This sets the VCO that is used when

VCO_SEL_STRT_EN = 1 or VCO_SEL_FORCE = 1.

1: VCO1

2: VCO2

·····

6: VCO6

All other values are not used.

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表 27. Register R20 Field Descriptions (接下页)

Bit

Field

Type Reset Description

10

VCO_SEL_FORCE

R/W 0h

Forces the VCO to use the core specified by VCO_SEL.

0: Disabled

1: Enabled

9 - 0

R/W 48h

Program 48h to this field.

7.6.22 Register R21 (offset = 15h) [reset = 0409h]

图 49. Register R21

15

0

14

0

13

0

12

0

11

0

10

1

9

0

8

0

7

0

6

0

5

0

4

0

3

1

2

0

1

0

1

R/W-409h

表 28. Register R21 Field Descriptions

Bit

Field

Type Reset Description

R/W 409h Program 409h to this field.

After programming R0 with RESET = 1, no need to program this register.

15 - 0

7.6.23 Register R22 (offset = 16h) [reset = 0001h]

图 50. Register R22

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

7

0

6

0

5

0

4

0

3

0

2

0

1

0

1

R/W-1h

表 29. Register R22 Field Descriptions

Bit

Field

Type Reset Description

R/W 1h Program 1h to this field.

After programming R0 with RESET = 1, no need to program this register.

15 - 0

7.6.24 Register R23 (offset = 17h) [reset = 007Ch]

图 51. Register R23

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

7

0

6

1

5

1

4

1

3

1

2

1

0

R/W-7Ch

表 30. Register R23 Field Descriptions

Bit

Field

Type Reset Description

R/W 7Ch Program 7Ch to this field.

After programming R0 with RESET = 1, no need to program this register.

15 - 0

7.6.25 Register R24 (offset = 18h) [reset = 071Ah]

图 52. Register R24

15

0

14

0

13

0

12

0

11

0

10

1

9

1

8

1

7

0

6

0

5

0

4

1

3

1

2

0

1

0

R/W-71Ah

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表 31. Register R24 Field Descriptions

Bit

Field

Type Reset Description

15 - 0

R/W 71Ah Program 71Ah to this field.

After programming R0 with RESET = 1, no need to program this register.

7.6.26 Register R25 (offset = 19h) [reset = 0624h]

图 53. Register R25

15

0

14

0

13

0

12

0

11

0

10

1

9

1

8

0

7

0

6

0

5

1

4

0

3

0

2

1

0

R/W-624h

表 32. Register R25 Field Descriptions

Bit

Field

Type Reset Description

R/W 624h Program 624h to this field.

After programming R0 with RESET = 1, no need to program this register.

15 - 0

7.6.27 Register R26 (offset = 1Ah) [reset = 0808h]

图 54. Register R26

15

0

14

0

13

0

12

0

11

1

10

0

9

0

8

0

7

0

6

0

5

0

4

0

3

1

2

0

1

0

R/W-808h

表 33. Register R26 Field Descriptions

Bit

Field

Type Reset Description

R/W 808h Program 808h to this field.

After programming R0 with RESET = 1, no need to program this register.

15 - 0

7.6.28 Register R27 (offset = 1Bh) [reset = 0002h]

图 55. Register R27

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

7

0

6

0

5

0

4

0

3

0

2

0

1

0

R/W-2h

表 34. Register R27 Field Descriptions

Bit

Field

Type Reset Description

R/W 2h Program 2h to this field.

After programming R0 with RESET = 1, no need to program this register.

15 - 0

7.6.29 Register R28 (offset = 1Ch) [reset = 0488h]

图 56. Register R28

15

0

14

0

13

0

12

0

11

0

10

1

9

0

8

0

7

1

6

0

5

0

4

0

3

1

2

0

1

0

R/W-488h

表 35. Register R28 Field Descriptions

Bit

Field

Type Reset Description

R/W 488h Program 488h to this field.

After programming R0 with RESET = 1, no need to program this register.

15 - 0

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7.6.30 Register R29 (offset = 1Dh) [reset = 18C6h]

图 57. Register R29

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

7

0

6

0

5

0

4

0

3

0

2

0

1

0

R/W-18C6h

表 36. Register R29 Field Descriptions

Bit

Field

Type Reset Description

15 - 0

R/W 18C6h Program 0h to this field.

7.6.31 Register R30 (offset = 1Eh) [reset = 18C6h]

图 58. Register R30

15

0

14

0

13

0

12

0

11

1

10

1

9

0

8

0

7

1

6

0

5

1

4

0

3

0

2

1

0

R/W-18C6h

表 37. Register R30 Field Descriptions

Bit

Field

Type Reset Description

15 - 0

R/W 18C6h Program CA6h to this field.

7.6.32 Register R31 (offset = 1Fh) [reset = C3E6h]

图 59. Register R31

15

1

14

1

13

0

12

0

11

0

10

0

9

1

8

1

7

1

6

1

5

1

4

0

3

0

2

1

0

R/W-C3E6h

表 38. Register R31 Field Descriptions

Bit

Field

Type Reset

R/W C3E6h Program C3E6h to this field.

After programming R0 with RESET = 1, no need to program this register.

Description

15 - 0

7.6.33 Register R32 (offset = 20h) [reset = 05BFh]

图 60. Register R32

15

0

14

0

13

0

12

0

11

0

10

1

9

0

8

1

7

1

6

0

5

1

4

1

3

1

2

1

0

1

R/W-5BFh

表 39. Register R32 Field Descriptions

Bit

Field

Type Reset Description

15 - 0

R/W 5BFh Program 5BFh to this field.

After programming R0 with RESET = 1, no need to program this register.

7.6.34 Register R33 (offset = 21h) [reset = 1E01h]

图 61. Register R33

15

0

14

0

13

0

12

1

11

1

10

1

9

1

8

0

7

0

6

0

5

0

4

0

3

0

2

0

1

0

1

R/W-1E01h

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表 40. Register R33 Field Descriptions

Bit

Field

Type Reset Description

15 - 0

R/W 1E01h Program 1E01h to this field.

After programming R0 with RESET = 1, no need to program this register.

7.6.35 Register R34 (offset = 22h) [reset = 0010h]

图 62. Register R34

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

7

0

6

0

5

0

4

1

3

0

2

1

0

PLL_N[18:16]

R/W-0h

R/W-2h

表 41. Register R34 Field Descriptions

Bit

Field

Type Reset Description

15 - 3

2 - 0

R/W 2h

R/W 0h

Program 2h to this field.

Upper 3 bits of N-divider.

PLL_N[18:16]

7.6.36 Register R35 (offset = 23h) [reset = 0004h]

图 63. Register R35

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

7

0

6

0

5

0

4

0

3

0

2

1

0

R/W-4h

表 42. Register R35 Field Descriptions

Bit

Field

Type Reset Description

R/W 4h Program 4h to this field.

After programming R0 with RESET = 1, no need to program this register.

15 - 0

7.6.37 Register R36 (offset = 24h) [reset = 0028h]

图 64. Register R36

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

PLL_N

R/W-28h

表 43. Register R36 Field Descriptions

Bit

Field

Type Reset Description

R/W 28h Lower 16 bits of N-divider.

15 - 0 PLL_N

7.6.38 Register R37 (offset = 25h) [reset = 0205h]

图 65. Register R37

15

14

0

13

12

11

10

9

8

7

0

6

0

5

0

4

0

3

0

2

1

0

1

MASH_S

EED_EN

PFD_DLY_SEL

R/W-0h

R/W-2h

R/W-5h

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表 44. Register R37 Field Descriptions

Bit

Field

Type Reset Description

15

MASH_SEED_EN

R/W 0h

Enables the MASH_SEED value to be used. This can be used for programmable

phase stepping or fractional spur optimization.

0: Disabled

1: Enabled

14

R/W 0h

R/W 2h

Program 0h to this field.

13 - 8 PFD_DLY_SEL

PFD_DLY_SEL must be adjusted in accordance to the N-divider value. See 表 3 for

details.

7 - 0

R/W 5h

Program 5h to this field.

7.6.39 Register R38 (offset = 26h) [reset = FFFFh]

图 66. Register R38

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

PLL_DEN[31:16]

R/W-FFFFh

表 45. Register R38 Field Descriptions

Bit

Field

Type Reset

Description

15 - 0 PLL_DEN[31:16]

R/W FFFFh Upper 16 bits of fractional denominator (DEN).

7.6.40 Register R39 (offset = 27h) [reset = FFFFh]

图 67. Register R39

15

14

13

12

11

10

9

8

7

6

5

PLL_DEN[15:0]

R/W-FFFFh

表 46. Register R39 Field Descriptions

Bit

Field

Type Reset

Description

15 - 0 PLL_DEN[15:0]

R/W FFFFh Lower 16 bits of fractional denominator (DEN).

7.6.41 Register R40 (offset = 28h) [reset = 0000h]

图 68. Register R40

15

14

13

12

11

10

9

8

7

6

5

MASH_SEED[31:16]

R/W-0h

表 47. Register R40 Field Descriptions

Bit

Field

Type Reset Description

15 - 0 MASH_SEED[31:16]

R/W 0h

Upper 16 bits of MASH_SEED. MASH_SEED sets the initial state of the fractional

engine. Useful for producing a phase shift and fractional spur optimization.

7.6.42 Register R41 (offset = 29h) [reset = 0000h]

图 69. Register R41

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MASH_SEED[15:0]

R/W-0h

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ZHCSIA2 –MAY 2018

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表 48. Register R41 Field Descriptions

Bit

Field

Type Reset Description

15 - 0 MASH_SEED[15:0]

R/W 0h

Lower 16 bits of MASH_SEED. MASH_SEED sets the initial state of the fractional

engine. Useful for producing a phase shift and fractional spur optimization.

7.6.43 Register R42 (offset = 2Ah) [reset = 0000h]

图 70. Register R42

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

PLL_NUM[31:16]

R/W-0h

表 49. Register R42 Field Descriptions

Bit

Field

Type Reset Description

R/W 0h Upper 16 bits of fractional numerator (NUM).

15 - 0 PLL_NUM[31:16]

7.6.44 Register R43 (offset = 2Bh) [reset = 0000h]

图 71. Register R43

15

14

13

12

11

10

9

8

7

6

5

4

3

1

PLL_NUM[15:0]

R/W-0h

表 50. Register R43 Field Descriptions

Bit

Field

Type Reset Description

R/W 0h Lower 16 bits of fractional numerator (NUM).

15 - 0 PLL_NUM[15:0]

7.6.45 Register R44 (offset = 2Ch) [reset = 08A2h]

图 72. Register R44

15

0

14

0

13

12

11

10

9

8

7

6

5

4

0

3

0

1

OUTA_PWR

OUTB_P OUTA_P MASH_R

MASH_ORDER

D

ESET_N

R/W-0h

R/W-08h

R/W-1h

R/W-0h

R/W-1h

R/W-0h

R/W-2h

表 51. Register R44 Field Descriptions

Bit

Field

Type Reset Description

15 - 14

R/W 0h

Program 0h to this field.

13 - 8 OUTA_PWR

R/W 08h

Adjusts RFoutA output power. Higher numbers give more output power. Values

greater than 18 are prohibited.

7

6

OUTB_PD

R/W 1h

R/W 0h

R/W 1h

R/W 0h

Powers down RF output B.

0: Normal operation

1: Power down

OUTA_PD

Powers down RF output A.

0: Normal operation

1: Power down

5

MASH_RESET_N

Resets MASH.

0: Reset

1: Normal operation

4 - 3

Program 0h to this field.

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表 51. Register R44 Field Descriptions (接下页)

Bit

Field

Type Reset Description

2 - 0

MASH_ORDER

R/W 2h

Sets the MASH order.

0: Integer mode

1: First order modulator

2: Second order modulator

3: Third order modulator

4: Fourth order modulator

5 - 7: Not used

7.6.46 Register R45 (offset = 2Dh) [reset = C608h]

图 73. Register R45

15

1

14

1

13

0

12

0

11

0

10

1

9

1

8

0

7

0

6

0

5

4

3

2

1

0

OUTB_PWR

R/W-08h

R/W-318h

表 52. Register R45 Field Descriptions

Bit

Field

Type Reset Description

15 - 6

5 - 0

R/W 318h

R/W 08h

Program 318h to this field.

OUTB_PWR

Adjusts RFoutB output power. Higher numbers give more output power. Values

greater than 18 are prohibited.

7.6.47 Register R46 (offset = 2Eh) [reset = 07F0h]

图 74. Register R46

15

0

14

0

13

0

12

0

11

0

10

1

9

1

8

1

7

1

6

1

5

1

4

1

3

0

2

0

1

0

R/W-7F0h

表 53. Register R46 Field Descriptions

Bit

Field

Type Reset Description

15 - 0

R/W 7F0h Program 7F0h to this field.

After programming R0 with RESET = 1, no need to program this register.

7.6.48 Register R47 (offset = 2Fh) [reset = 0300h]

图 75. Register R47

15

0

14

0

13

0

12

0

11

0

10

0

9

1

8

1

7

0

6

0

5

0

4

0

3

0

2

0

1

0

R/W-300h

表 54. Register R47 Field Descriptions

Bit

Field

Type Reset Description

R/W 300h Program 300h to this field.

After programming R0 with RESET = 1, no need to program this register.

15 - 0

7.6.49 Register R48 (offset = 30h) [reset = 03E0h]

图 76. Register R48

15

0

14

0

13

0

12

0

11

0

10

0

9

1

8

1

7

1

6

1

5

1

4

0

3

0

2

0

1

0

R/W-3E0h

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表 55. Register R48 Field Descriptions

Bit

Field

Type Reset Description

15 - 0

R/W 3E0h Program 3E0h to this field.

After programming R0 with RESET = 1, no need to program this register.

7.6.50 Register R49 (offset = 31h) [reset = 4180h]

图 77. Register R49

15

0

14

1

13

0

12

0

11

0

10

0

9

0

8

1

7

1

6

0

5

0

4

0

3

0

2

0

1

0

R/W-4180h

表 56. Register R49 Field Descriptions

Bit

Field

Type Reset Description

15 - 0

R/W 4180h Program 4180h to this field.

After programming R0 with RESET = 1, no need to program this register.

7.6.51 Register R50 (offset = 32h) [reset = 0080h]

图 78. Register R50

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

7

1

6

0

5

0

4

0

3

0

2

0

1

0

R/W-80h

表 57. Register R50 Field Descriptions

Bit

Field

Type Reset Description

R/W 80h Program 80h to this field.

After programming R0 with RESET = 1, no need to program this register.

15 - 0

7.6.52 Register R51 (offset = 33h) [reset = 0080h]

图 79. Register R51

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

7

1

6

0

5

0

4

0

3

0

2

0

1

0

R/W-80h

表 58. Register R51 Field Descriptions

Bit

Field

Type Reset Description

R/W 80h Program 80h to this field.

After programming R0 with RESET = 1, no need to program this register.

15 - 0

7.6.53 Register R52 (offset = 34h) [reset = 0420h]

图 80. Register R52

15

0

14

0

13

0

12

0

11

0

10

1

9

0

8

0

7

0

6

0

5

1

4

0

3

0

2

0

1

0

1

R/W-420h

表 59. Register R52 Field Descriptions

Bit

Field

Type Reset Description

R/W 420h Program 421h to this field.

15 - 0

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7.6.54 Register R53 (offset = 35h) [reset = 0000h]

图 81. Register R53

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

7

0

6

0

5

0

4

0

3

0

2

0

1

0

R/W-0h

表 60. Register R53 Field Descriptions

Bit

Field

Type Reset Description

R/W 0h Program 0h to this field.

After programming R0 with RESET = 1, no need to program this register.

15 - 0

7.6.55 Register R54 (offset = 36h) [reset = 0000h]

图 82. Register R54

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

7

0

6

0

5

0

4

0

3

0

2

0

1

0

R/W-0h

表 61. Register R54 Field Descriptions

Bit

Field

Type Reset Description

R/W 0h Program 0h to this field.

After programming R0 with RESET = 1, no need to program this register.

15 - 0

7.6.56 Register R55 (offset = 37h) [reset = 0000h]

图 83. Register R55

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

7

0

6

0

5

0

4

0

3

0

2

0

1

0

R/W-0h

表 62. Register R55 Field Descriptions

Bit

Field

Type Reset Description

R/W 0h Program 0h to this field.

After programming R0 with RESET = 1, no need to program this register.

15 - 0

7.6.57 Register R56 (offset = 38h) [reset = 0000h]

图 84. Register R56

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

7

0

6

0

5

0

4

0

3

0

2

0

1

0

R/W-0h

表 63. Register R56 Field Descriptions

Bit

Field

Type Reset Description

R/W 0h Program 0h to this field.

After programming R0 with RESET = 1, no need to program this register.

15 - 0

7.6.58 Register R57 (offset = 39h) [reset = 0000h]

图 85. Register R57

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

7

0

6

0

5

1

4

0

3

0

2

0

1

0

R/W-0h

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表 64. Register R57 Field Descriptions

Bit

Field

Type Reset Description

15 - 0

R/W 0h

Program 20h to this field.

7.6.59 Register R58 (offset = 3Ah) [reset = 8001h]

图 86. Register R58

15

14

13

12

11

10

9

8

0

7

0

6

0

5

0

4

0

3

0

2

0

1

0

1

INPIN_I

GNORE

INPIN_H

YST

INPIN_LVL

INPIN_FMT

R/W-1h

R/W-0h

R/W-1h

表 65. Register R58 Field Descriptions

Bit

Field

Type Reset Description

15

INPIN_IGNORE

R/W 1h

Ignore SYNC and SysRefReq pins when VCO_PHASE_SYNC = 0. This bit should be

set to 1 unless VCO_PHASE_SYNC = 1.

14

INPIN_HYST

R/W 0h

Enables high hysteresis for LVDS input to SysRefReq and SYNC pin.

0: Disabled

1: Enabled

13 - 12 INPIN_LVL

11 - 9 INPIN_FMT

R/W 0h

Sets bias level for LVDS input to SysRefReq and SYNC pin.

0: Vin / 4

1: Vin

2: Vin / 2

3: Invalid

Defines the input format of SysRefReq and SYNC pin.

0: SYNC = SysRefReq = CMOS

1: SYNC = LVDS; SysRefReq = CMOS

2: SYNC = CMOS; SysRefReq = LVDS

3: SYNC = SysRefReq = LVDS

4: SYNC = SysRefReq = CMOS

5: SYNC = LVDS (filtered); SysRefReq = CMOS

6: SYNC = CMOS; SysRefReq = LVDS (filtered)

7: SYNC = SysRefReq = LVDS (filtered)

8 - 0

R/W 1h

Program 1h to this field.

7.6.60 Register R59 (offset = 3Bh) [reset = 0001h]

图 87. Register R59

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

7

0

6

0

5

0

4

0

3

0

2

0

1

0

LD_TYP

E

R/W-0h

R/W-1h

表 66. Register R59 Field Descriptions

Bit

15 - 1

0

Field

Type Reset Description

R/W 0h

R/W 1h

Program 0h to this field.

Defines lock detect type.

LD_TYPE

0: VCOCal. Lock detect asserts a HIGH output after the VCO has finished calibration

and the LD_DLY timeout counter is finished.

1: Vtune and VCOCal. Lock detect asserts a HIGH output when VCOCal lock detect

would assert a HIGH signal and the tuning voltage to the VCO is within acceptable

limits.

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7.6.61 Register R60 (offset = 3Ch) [reset = 03E8h]

图 88. Register R60

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

LD_DLY

R/W-3E8h

表 67. Register R60 Field Descriptions

Bit

Field

Type Reset Description

15 - 0 LD_DLY

R/W 3E8h For the VCOCal lock detect, this is the delay in ¼ f_PDcycles that is added after the

calibration is finished before the VCOCal lock detect is asserted HIGH.

7.6.62 Register R61 (offset = 3Dh) [reset = 00A8h]

图 89. Register R61

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

7

1

6

0

5

1

4

0

3

1

2

0

1

0

R/W-A8h

表 68. Register R61 Field Descriptions

Bit

Field

Type Reset Description

R/W A8h Program A8h to this field.

After programming R0 with RESET = 1, no need to program this register.

15 - 0

7.6.63 Register R62 (offset = 3Eh) [reset = 00AFh]

图 90. Register R62

15

14

13

12

11

10

9

0

8

0

7

1

6

0

5

1

4

0

3

1

2

1

0

1

DBLBUF DBLBUF DBLBUF DBLBUF DBLBUF DBLBUF

_EN_5

_EN_4

_EN_3

_EN_2

_EN_1

_EN_0

R/W-0h

R/W-AFh

表 69. Register R62 Field Descriptions

Bit

Field

Type Reset Description

15

DBLBUF_EN_5

DBLBUF_EN_4

DBLBUF_EN_3

DBLBUF_EN_2

R/W 0h

Enables double buffering for the MASH order.

0: Disabled

1: Enabled

14

13

12

Enables double buffering for fractional numerator NUM.

0: Disabled

1: Enabled

Enables double buffering for the integer portion of the N-divider.

0: Disabled

1: Enabled

Enables double buffering for the Pre-R and Post-R dividers in the reference path.

Effective only if DBL_BUF_EN_3 = 1.

0: Disabled

1: Enabled

11

10

DBLBUF_EN_1

DBLBUF_EN_0

R/W 0h

R/W AFh

Enables double buffering for the Multiplier in the reference path. Effective only if

DBL_BUF_EN_3 = 1.

0: Disabled

1: Enabled

Enables double buffering for the Doubler in the reference path. Effective only if

DBL_BUF_EN_3 = 1.

0: Disabled

1: Enabled

9 - 0

Program AFh to this field.

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7.6.64 Register R63 (offset = 3Fh) [reset = 0000h]

图 91. Register R63

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

7

0

6

0

5

0

4

0

3

0

2

0

1

0

R/W-0h

表 70. Register R63 Field Descriptions

Bit

Field

Type Reset Description

R/W 0h Program 0h to this field.

After programming R0 with RESET = 1, no need to program this register.

15 - 0

7.6.65 Register R64 (offset = 40h) [reset = 1388h]

图 92. Register R64

15

0

14

0

13

0

12

1

11

0

10

0

9

1

8

1

7

1

6

0

5

0

4

0

3

1

2

0

1

0

R/W-1388h

表 71. Register R64 Field Descriptions

Bit

Field

Type Reset Description

15 - 0

R/W 1388h Program 1388h to this field.

After programming R0 with RESET = 1, no need to program this register.

7.6.66 Register R65 (offset = 41h) [reset = 0000h]

图 93. Register R65

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

7

0

6

0

5

0

4

0

3

0

2

0

1

0

R/W-0h

表 72. Register R65 Field Descriptions

Bit

Field

Type Reset Description

R/W 0h Program 0h to this field.

After programming R0 with RESET = 1, no need to program this register.

15 - 0

7.6.67 Register R66 (offset = 42h) [reset = 01F4h]

图 94. Register R66

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

1

7

1

6

1

5

1

4

1

3

0

2

1

0

R/W-1F4h

表 73. Register R66 Field Descriptions

Bit

Field

Type Reset Description

15 - 0

R/W 1F4h Program 1F4h to this field.

After programming R0 with RESET = 1, no need to program this register.

7.6.68 Register R67 (offset = 43h) [reset = 0000h]

图 95. Register R67

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

7

0

6

0

5

0

4

0

3

0

2

0

1

0

R/W-0h

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表 74. Register R67 Field Descriptions

Bit

Field

Type Reset Description

15 - 0

R/W 0h

Program 0h to this field.

After programming R0 with RESET = 1, no need to program this register.

7.6.69 Register R68 (offset = 44h) [reset = 03E8h]

图 96. Register R68

15

0

14

0

13

0

12

0

11

0

10

0

9

1

8

1

7

1

6

1

5

1

4

0

3

1

2

0

1

0

R/W-3E8h

表 75. Register R68 Field Descriptions

Bit

Field

Type Reset Description

15 - 0

R/W 3E8h Program 3E8h to this field.

After programming R0 with RESET = 1, no need to program this register.

7.6.70 Register R69 (offset = 45h) [reset = 0000h]

图 97. Register R69

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MASH_RST_COUNT[31:16]

R/W-0h

表 76. Register R69 Field Descriptions

Bit

Field

Type Reset Description

15 - 0 MASH_RST_COUNT

[31:16]

R/W 0h Upper 16 bits of MASH_RST_COUNT. This register is used to add a delay when

using phase SYNC. The delay should be set at least four times the PLL lock time. This

delay is expressed in state machine clock periods. One of these periods is equal to

2^CAL_CLK_DIV/ f_OSCin

.

7.6.71 Register R70 (offset = 46h) [reset = C350h]

图 98. Register R70

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MASH_RST_COUNT[15:0]

R/W-C350h

表 77. Register R70 Field Descriptions

Bit

Field

Type Reset Description

15 - 0 MASH_RST_COUNT

[15:0]

R/W C350h Lower 16 bits of MASH_RST_COUNT.

7.6.72 Register R71 (offset = 47h) [reset = 0080h]

图 99. Register R71

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

7

1

6

0

5

0

4

0

3

0

2

0

1

0

1

R/W-80h

表 78. Register R71 Field Descriptions

Bit

Field

Type Reset Description

R/W 80h Program 81h to this field.

15 - 0

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7.6.73 Register R72 (offset = 48h) [reset = 0001h]

图 100. Register R72

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

7

0

6

0

5

0

4

0

3

0

2

0

1

0

1

R/W-1h

表 79. Register R72 Field Descriptions

Bit

Field

Type Reset Description

R/W 1h Program 1h to this field.

After programming R0 with RESET = 1, no need to program this register.

15 - 0

7.6.74 Register R73 (offset = 49h) [reset = 003Fh]

图 101. Register R73

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

7

0

6

0

5

1

4

1

3

1

2

1

0

1

R/W-3Fh

表 80. Register R73 Field Descriptions

Bit

Field

Type Reset Description

R/W 3Fh Program 3Fh to this field.

After programming R0 with RESET = 1, no need to program this register.

15 - 0

7.6.75 Register R74 (offset = 4Ah) [reset = 0000h]

图 102. Register R74

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

7

0

6

0

5

0

4

0

3

0

2

0

1

0

R/W-0h

表 81. Register R74 Field Descriptions

Bit

Field

Type Reset Description

R/W 0h Program 0h to this field.

After programming R0 with RESET = 1, no need to program this register.

15 - 0

7.6.76 Register R75 (offset = 4Bh) [reset = 0800h]

图 103. Register R75

15

0

14

0

13

0

12

0

11

1

10

9

8

7

6

5

0

4

0

3

0

2

0

1

0

CHDIV

R/W-0h

R/W-1h

R/W-0h

表 82. Register R75 Field Descriptions

Bit

Field

Type Reset Description

15 - 11

R/W 1h

R/W 0h

Program 1h to this field.

10 - 6 CHDIV

Channel divider.

0: Divide by 2

1: Divide by 4

3: Divide by 8

5: Divide by 16

7: Divide by 32

9: Divide by 64

12: Divide by 128

14: Divide by 256

All other values are not used.

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表 82. Register R75 Field Descriptions (接下页)

Bit

Field

Type Reset Description

5 - 0

R/W 0h

Program 0h to this field.

7.6.77 Register R76 (offset = 4Ch) [reset = 000Ch]

图 104. Register R76

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

7

0

6

0

5

0

4

0

3

1

2

1

0

R/W-Ch

表 83. Register R76 Field Descriptions

Bit

Field

Type Reset Description

R/W Ch Program Ch to this field.

After programming R0 with RESET = 1, no need to program this register.

15 - 0

7.6.78 Register R77 (offset = 4Dh) [reset = 0000h]

图 105. Register R77

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

7

0

6

0

5

0

4

0

3

0

2

0

1

0

R/W-0h

表 84. Register R77 Field Descriptions

Bit

Field

Type Reset Description

R/W 0h Program 0h to this field.

After programming R0 with RESET = 1, no need to program this register.

15 - 0

7.6.79 Register R78 (offset = 4Eh) [reset = 0064h]

图 106. Register R78

15

0

14

0

13

0

12

0

11

10

0

9

8

7

6

5

4

3

2

1

0

1

RAMP_T

HRESH[

32]

QUICK_

RECAL_

EN

VCO_CAPCTRL_STRT

R/W-0h

R/W-32h

R/W-0h

表 85. Register R78 Field Descriptions

Bit

15 - 12

11

Field

Type Reset Description

R/W 0h

Program 0h to this field.

The 33^rdbit of RAMP_THRESH.

RAMP_THRESH[32]

RAMP_THRESH sets how much the ramp can change the VCO frequency before a

VCO calibration is required. If the frequency is chosen to be Δf, then RAMP_THRESH

= (Δf / f_PD) × 2²⁴

.

10

9

R/W 0h

Program 0h to this field.

QUICK_RECAL_EN

This sets the initial VCO starting calibration values. Especially useful if the frequency

change is smaller, say < 50 MHz or so.

0: Calibration starts with VCO_SEL, VCO_CAPCTRL_START,

VCO_DACISET_START

1: Calibration starts with the current value

8 - 1

0

VCO_CAPCTRL_STRT

R/W 32h

R/W 0h

This sets the starting VCO_CAPCTRL value that is used for VCO frequency

calibration. Smaller values yield a higher frequency band within a VCO core. Valid

number range is 0 to 183.

Program 1h to this field.

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7.6.80 Register R79 (offset = 4Fh) [reset = 0000h]

图 107. Register R79

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

RAMP_THRESH[31:16]

R/W-0h

表 86. Register R79 Field Descriptions

Bit

Field

Type Reset Description

R/W 0h Upper 16 bits of RAMP_THRESH. See 表 85 for description.

15 - 0 RAMP_THRESH[31:16]

7.6.81 Register R80 (offset = 50h) [reset = 0000h]

图 108. Register R80

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

RAMP_THRESH[15:0]

R/W-0h

表 87. Register R80 Field Descriptions

Bit

Field

Type Reset Description

R/W 0h Lower 16 bits of RAMP_THRESH. See 表 85 for description.

15 - 0 RAMP_THRESH[15:0]

7.6.82 Register R81 (offset = 51h) [reset = 0000h]

图 109. Register R81

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

7

0

6

0

5

0

4

0

3

0

2

0

1

0

RAMP_L

IMIT_HI

GH[32]

R/W-0h

表 88. Register R81 Field Descriptions

Bit

15 - 1

0

Field

Type Reset Description

R/W 0h

Program 0h to this field.

The 33^rdbit of RAMP_LIMIT_HIGH.

RAMP_LIMIT_HIGH[32]

RAMP_LIMIT_HIGH sets a maximum frequency that the ramp cannot exceed so that

the VCO does not get set beyond a valid frequency range.

Suppose f_HIGHis this frequency and f_VCOis the starting VCO frequency, then:

f_HIGH≥ f_VCO

;

RAMP_LIMIT_HIGH = 2²⁴× (f_HIGH– f_VCO) / f_PD

7.6.83 Register R82 (offset = 52h) [reset = 0000h]

图 110. Register R82

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

RAMP_LIMIT_HIGH[31:16]

R/W-0h

表 89. Register R82 Field Descriptions

Bit

Field

Type Reset Description

R/W 0h Upper 16 bits of RAMP_LIMIT_HIGH. See 表 88 for description.

15 - 0 RAMP_LIMIT_HIGH

[31:16]

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7.6.84 Register R83 (offset = 53h) [reset = 0000h]

图 111. Register R83

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

RAMP_LIMIT_HIGH[15:0]

R/W-0h

表 90. Register R83 Field Descriptions

Bit

Field

Type Reset Description

Lower 16 bits of RAMP_LIMIT_HIGH. See 表 88 for description.

15 - 0 RAMP_LIMIT_HIGH[15:0] R/W 0h

7.6.85 Register R84 (offset = 54h) [reset = 0000h]

图 112. Register R84

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

7

0

6

0

5

0

4

0

3

0

2

0

1

0

RAMP_L

IMIT_LO

W[32]

R/W-0h

表 91. Register R84 Field Descriptions

Bit

15 - 1

0

Field

Type Reset Description

R/W 0h

Program 0h to this field.

The 33^rdbit of RAMP_LIMIT_LOW.

RAMP_LIMIT_LOW[32]

RAMP_LIMIT_LOW sets a minimum frequency that the ramp cannot exceed so that

the VCO does not get set beyond a valid frequency range.

Suppose f_LOWis this frequency and f_VCOis the starting VCO frequency, then:

f

_LOW≤ f_VCO

;

RAMP_LIMIT_LOW = 2³³– 2²⁴× (f_VCO– f_LOW) / f_PD

7.6.86 Register R85 (offset = 55h) [reset = 0000h]

图 113. Register R85

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

RAMP_LIMIT_LOW[31:16]

R/W-0h

表 92. Register R85 Field Descriptions

Bit

Field

Type Reset Description

R/W 0h Upper 16 bits of RAMP_LIMIT_LOW. See 表 91 for description.

15 - 0 RAMP_LIMIT_LOW

[31:16]

7.6.87 Register R86 (offset = 56h) [reset = 0000h]

图 114. Register R86

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

RAMP_LIMIT_LOW[15:0]

R/W-0h

表 93. Register R86 Field Descriptions

Bit

Field

Type Reset Description

15 - 0 RAMP_LIMIT_LOW[15:0] R/W 0h

Lower 16 bits of RAMP_LIMIT_LOW. See 表 91 for description.

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7.6.88 Register R87 (offset = 57h) [reset = 0000h]

图 115. Register R87

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

7

0

6

0

5

0

4

0

3

0

2

0

1

0

R/W-0h

表 94. Register R87 Field Descriptions

Bit

Field

Type Reset Description

R/W 0h Program 0h to this field.

After programming R0 with RESET = 1, no need to program this register.

15 - 0

7.6.89 Register R88 (offset = 58h) [reset = 0000h]

图 116. Register R88

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

7

0

6

0

5

0

4

0

3

0

2

0

1

0

R/W-0h

表 95. Register R88 Field Descriptions

Bit

Field

Type Reset Description

R/W 0h Program 0h to this field.

After programming R0 with RESET = 1, no need to program this register.

15 - 0

7.6.90 Register R89 (offset = 59h) [reset = 0000h]

图 117. Register R89

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

7

0

6

0

5

0

4

0

3

0

2

0

1

0

R/W-0h

表 96. Register R89 Field Descriptions

Bit

Field

Type Reset Description

R/W 0h Program 0h to this field.

After programming R0 with RESET = 1, no need to program this register.

15 - 0

7.6.91 Register R90 (offset = 5Ah) [reset = 0000h]

图 118. Register R90

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

7

0

6

0

5

0

4

0

3

0

2

0

1

0

R/W-0h

表 97. Register R90 Field Descriptions

Bit

Field

Type Reset Description

R/W 0h Program 0h to this field.

After programming R0 with RESET = 1, no need to program this register.

15 - 0

7.6.92 Register R91 (offset = 5Bh) [reset = 0000h]

图 119. Register R91

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

7

0

6

0

5

0

4

0

3

0

2

0

1

0

R/W-0h

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表 98. Register R91 Field Descriptions

Bit

Field

Type Reset Description

15 - 0

R/W 0h

Program 0h to this field.

After programming R0 with RESET = 1, no need to program this register.

7.6.93 Register R92 (offset = 5Ch) [reset = 0000h]

图 120. Register R92

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

7

0

6

0

5

0

4

0

3

0

2

0

1

0

R/W-0h

表 99. Register R92 Field Descriptions

Bit

Field

Type Reset Description

R/W 0h Program 0h to this field.

After programming R0 with RESET = 1, no need to program this register.

15 - 0

7.6.94 Register R93 (offset = 5Dh) [reset = 0000h]

图 121. Register R93

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

7

0

6

0

5

0

4

0

3

0

2

0

1

0

R/W-0h

表 100. Register R93 Field Descriptions

Bit

Field

Type Reset Description

R/W 0h Program 0h to this field.

After programming R0 with RESET = 1, no need to program this register.

15 - 0

7.6.95 Register R94 (offset = 5Eh) [reset = 0000h]

图 122. Register R94

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

7

0

6

0

5

0

4

0

3

0

2

0

1

0

R/W-0h

表 101. Register R94 Field Descriptions

Bit

Field

Type Reset Description

R/W 0h Program 0h to this field.

After programming R0 with RESET = 1, no need to program this register.

15 - 0

7.6.96 Register R95 (offset = 5Fh) [reset = 0000h]

图 123. Register R95

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

7

0

6

0

5

0

4

0

3

0

2

0

1

0

R/W-0h

表 102. Register R95 Field Descriptions

Bit

Field

Type Reset Description

R/W 0h Program 0h to this field.

After programming R0 with RESET = 1, no need to program this register.

15 - 0

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7.6.97 Register R96 (offset = 60h) [reset = 0000h]

图 124. Register R96

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

RAMP_B

URST_E

N

RAMP_BURST_COUNT

R/W-0h

表 103. Register R96 Field Descriptions

Bit

Field

Type Reset Description

15

RAMP_BURST_EN

R/W 0h

This enables ramp burst mode. In this mode, a number of ramps equal to

RAMP_BURST_COUNT is sent out whenever RAMP_EN is set to 1. This is intended

to produce a finite pattern of ramps, instead of a continuous pattern.

0: Disabled

1: Enabled

14 - 2 RAMP_BURST_COUNT

1 - 0

R/W 0h

When RAMP_BURST_EN = 1, this sets the number of ramps that is sent out.

Program 0h to this field.

7.6.98 Register R97 (offset = 61h) [reset = 0000h]

图 125. Register R97

15

14

0

13

0

12

0

11

0

10

9

8

7

6

5

4

3

2

0

1

0

RAMP0_

RST

RAMP_TRIGB

RAMP_TRIGA

RAMP_BURST_TRI

G

R/W-0h

表 104. Register R97 Field Descriptions

Bit

Field

Type Reset Description

15

RAMP0_RST

R/W 0h

Resets RAMP0 at start of ramp to eliminate round-off errors. Applies to automatic

ramping mode only.

0: Disabled

1: Reset

14 - 11

R/W 0h

Program 0h to this field.

10 - 7 RAMP_TRIGB

Definition of ramp trigger B.

0: Disabled

1: RampClk pin rising edge

2: RampDir pin rising edge

4: Always triggered

9: RampClk pin falling edge

10: RampDir pin falling edge

All other values are not used.

6 - 3

2

RAMP_TRIGA

R/W 0h

Definition of ramp trigger A. Options are same as RAMP_TRIGB.

Program 0h to this field.

1 - 0

RAMP_BURST_TRIG

Sets what triggers the next ramp in burst mode.

0: Ramp transition

1: Trigger A

2: Trigger B

3: Not used

7.6.99 Register R98 (offset = 62h) [reset = 0000h]

图 126. Register R98

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

RAMP0_INC[29:16]

RAMP0_

DLY

R/W-0h

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表 105. Register R98 Field Descriptions

Bit

Field

Type Reset Description

15 - 2 RAMP0_INC[29:16]

R/W 0h

Upper 14 bits of RAMP0_INC.

RAMP0_INC sets the 2's compliment of the number added to the fractional numerator

on every ramp cycle.

1

R/W 0h

Program 0h to this field.

0

RAMP0_DLY

When enabled, increases RAMP0 length by basing the ramp clock on two phase

detector cycles instead of one.

0: Ramp clock = 1 f_PDcycle

1: Ramp clock = 2 f_PDcycles

7.6.100 Register R99 (offset = 63h) [reset = 0000h]

图 127. Register R99

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

RAMP0_INC[15:0]

R/W-0h

表 106. Register R99 Field Descriptions

Bit

Field

Type Reset Description

R/W 0h Lower 16 bits of RAMP0_INC. See 表 105 for description.

15 - 0 RAMP0_INC[15:0]

7.6.101 Register R100 (offset = 64h) [reset = 0000h]

图 128. Register R100

15

14

13

12

11

10

9

8

7

6

5

4

3

2

RAMP0_LEN

R/W-0h

表 107. Register R100 Field Descriptions

Bit

Field

Type Reset Description

R/W 0h Length of the ramp in phase detector cycles.

15 - 0 RAMP0_LEN

7.6.102 Register R101 (offset = 65h) [reset = 0000h]

图 129. Register R101

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

7

0

6

5

4

3

0

2

0

RAMP1_ RAMP1_ RAMP0_

DLY

RAMP0_NEXT_TRI

G

RST

R/W-0h

表 108. Register R101 Field Descriptions

Bit

15 - 7

6

Field

Type Reset Description

R/W 0h

Program 0h to this field.

RAMP1_DLY

RAMP1_RST

RAMP0_NEXT

When enabled, increases RAMP1 length by basing the ramp clock on two phase

detector cycles instead of one.

0: Ramp clock = 1 f_PDcycle

1: Ramp clock = 2 f_PDcycles

5

4

R/W 0h

Resets RAMP1 at start of ramp to eliminate round-off errors. Applies to automatic

ramping mode only.

0: Disabled

1: Reset

Defines what ramp comes after RAMP0.

0: RAMP0

1: RAMP1

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表 108. Register R101 Field Descriptions (接下页)

Bit

Field

Type Reset Description

3 - 2

1 - 0

R/W 0h

Program 0h to this field.

RAMP0_NEXT_TRIG

Defines what triggers the next ramp.

0: RAMP0_LEN timeout counter

1: Trigger A

2: Trigger B

3: Not used

7.6.103 Register R102 (offset = 66h) [reset = 0000h]

图 130. Register R102

15

0

14

0

13

12

11

10

9

8

7

6

5

4

3

2

1

0

RAMP1_INC[29:16]

R/W-0h

表 109. Register R102 Field Descriptions

Bit

Field

Type Reset Description

15 - 14

R/W 0h

Program 0h to this field.

13 - 0 RAMP1_INC[29:16]

Upper 14 bits of RAMP1_INC.

RAMP1_INC sets the 2's compliment of the number added to the fractional numerator

on every ramp cycle.

7.6.104 Register R103 (offset = 67h) [reset = 0000h]

图 131. Register R103

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

RAMP1_INC[15:0]

R/W-0h

表 110. Register R103 Field Descriptions

Bit

Field

Type Reset Description

R/W 0h Lower 16 bits of RAMP1_INC. See 表 109 for description.

15 - 0 RAMP1_INC[15:0]

7.6.105 Register R104 (offset = 68h) [reset = 0000h]

图 132. Register R104

15

14

13

12

11

10

9

8

7

6

5

4

3

2

RAMP1_LEN

R/W-0h

表 111. Register R104 Field Descriptions

Bit

Field

Type Reset Description

R/W 0h Length of the ramp in phase detector cycles.

15 - 0 RAMP1_LEN

7.6.106 Register R105 (offset = 69h) [reset = 4440h]

图 133. Register R105

15

14

13

12

11

10

9

8

7

6

5

4

3

0

2

0

RAMP_DLY_CNT

RAMP_

MANUAL

RAMP1_

G

R/W-111h

R/W-0h

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ZHCSIA2 –MAY 2018

表 112. Register R105 Field Descriptions

Bit

Field

Type Reset Description

15 - 6 RAMP_DLY_CNT

R/W 111h

For ramping mode, RAMP_DLY_CNT and RAMP_SCALE_COUNT determine the

minimum necessary time taken for VCO calibration during the ramp.

Min. VCOCal time = (1 / f_smc) / (RAMP_DLY_CNT × 2^{RAMP_SCALE_COUNT}), where f_smc

f_OSCin/ 2^CAL_CLK_DIV

=

.

5

4

RAMP_MANUAL

RAMP1_NEXT

R/W 0h

Selects the ramping mode.

0: Automatic ramping mode

1: Manual (Pin) ramping mode

Defines what ramp comes after RAMP1.

0: RAMP0

1: RAMP1

3 - 2

1 - 0

R/W 0h

Program 0h to this field.

RAMP1_NEXT_TRIG

Defines what triggers the next ramp.

0: RAMP1_LEN timeout counter

1: Trigger A

2: Trigger B

3: Not used

7.6.107 Register R106 (offset = 6Ah) [reset = 0007h]

图 134. Register R106

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

7

0

6

0

5

0

4

3

0

2

1

0

RAMP_T

RIG_CA

L

RAMP_SCALE_COUNT

R/W-0h

R/W-7h

表 113. Register R106 Field Descriptions

Bit

15 - 5

4

Field

Type Reset Description

R/W 0h

Program 0h to this field.

RAMP_TRIG_CAL

Enabling this bit causes VCO calibration to occur in automatic ramping mode at the

beginning of each ramp.

0: Disabled

1: Enabled

3

R/W 0h

R/W 7h

Program 0h to this field.

2 - 0

RAMP_SCALE_COUNT

For ramping mode, RAMP_DLY_CNT and RAMP_SCALE_COUNT determine the

minimum necessary time taken for VCO calibration during the ramp.

Min. VCOCal time = (1 / f_smc) / (RAMP_DLY_CNT × 2^{RAMP_SCALE_COUNT}), where f_smc

=

f_OSCin/ 2^CAL_CLK_DIV

.

7.6.108 Register R107 (offset = 6Bh) [reset = 0000h]

图 135. Register R107

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

7

0

6

0

5

0

4

0

3

0

2

0

1

0

R-0h

表 114. Register R107 Field Descriptions

Bit

Field

Type Reset Description

R 0h Not used. (Read back only)

15 - 0

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7.6.109 Register R108 (offset = 6Ch) [reset = 0000h]

图 136. Register R108

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

7

0

6

0

5

0

4

0

3

0

2

0

1

0

R-0h

表 115. Register R108 Field Descriptions

Bit

Field

Type Reset Description

R 0h Not used. (Read back only)

15 - 0

7.6.110 Register R109 (offset = 6Dh) [reset = 0000h]

图 137. Register R109

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

7

0

6

0

5

0

4

0

3

0

2

0

1

0

R-0h

表 116. Register R109 Field Descriptions

Bit

Field

Type Reset Description

R 0h Not used. (Read back only)

15 - 0

7.6.111 Register R110 (offset = 6Eh) [reset = 0000h]

图 138. Register R110

15

0

14

0

13

0

12

0

11

0

10

9

8

0

7

6

5

4

0

3

0

2

0

1

0

rb_LD_VTUNE

rb_VCO_SEL

R-0h

表 117. Register R110 Field Descriptions

Bit

Field

Type Reset Description

10 - 9 rb_LD_VTUNE

R

0h

Readback of Vtune lock detect.

0: Unlocked

1: Unlocked

2: Locked

3: Invalid

7 - 5

rb_VCO_SEL

R

0h

Reads back the actual VCO that the calibration has selected.

1: VCO1

2: VCO2

·····

6: VCO6

All other values are not used.

7.6.112 Register R111 (offset = 6Fh) [reset = 0000h]

图 139. Register R111

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

7

6

5

4

3

2

1

0

rb_VCO_CAPCTRL

R-0h

表 118. Register R111 Field Descriptions

Bit

Field

Type Reset Description

R 0h Reads back the actual CAPCTRL value that the VCO calibration has chosen.

7 - 0

rb_VCO_CAPCTRL

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7.6.113 Register R112 (offset = 70h) [reset = 0000h]

图 140. Register R112

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

7

6

5

4

3

2

1

0

rb_VCO_DACISET

R-0h

表 119. Register R112 Field Descriptions

Bit

Field

Type Reset Description

R 0h Reads back the actual DACISET value that the VCO calibration has chosen.

8 - 0

rb_VCO_DACISET

7.6.114 Register R113 (offset = 71h) [reset = 0000h]

图 141. Register R113

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

7

0

6

0

5

0

4

0

3

0

2

0

1

0

R-0h

表 120. Register R113 Field Descriptions

Bit

Field

Type Reset Description

R 0h Not used. (Read back only)

15 - 0

7.6.115 Register R114 (offset = 72h) [reset = 7800h]

图 142. Register R114

15

0

14

1

13

1

12

1

11

1

10

9

0

8

7

6

5

4

3

2

1

0

FSK_EN

FSK_I2S FSK_I2S

_FS_PO _CLK_P

FSK_SPI_LEVEL

FSK_SPI_DEV_SEL

FSK_MODE_SEL

L

OL

R/W-Fh

R/W-0h

表 121. Register R114 Field Descriptions

Bit

15 - 11

10

Field

Type Reset Description

R/W Fh

R/W 0h

Program Fh to this field.

FSK_EN

Enables all FSK modes.

0: Disabled

1: Enabled

9

8

R/W 0h

Program 0h to this filed.

FSK_I2S_FS_POL

Sets the polarity of the I2S Frame Sync input in FSK I2S mode.

0: Active HIGH

1: Active LOW

7

FSK_I2S_CLK_POL

FSK_SPI_LEVEL

R/W 0h

Sets the polarity of the I2S CLK input in FSK I2S mode.

0: Rising edge

1: Falling edge

6 - 5

Defines the desired FSK level in FSK SPI mode. When this bit is zero, FSK operation

in this mode is disabled even if FSK_EN = 1.

0: Disabled

1: 2FSK

2: 4FSK

3: 8FSK

4 - 2

FSK_SPI_DEV_SEL

R/W 0h

In FSK SPI mode, these bits select one of the FSK deviations as defined in registers

R116 - R123.

0: FSK_DEV0

1: FSK_DEV1

·····

7: FSK_DEV7

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表 121. Register R114 Field Descriptions (接下页)

Bit

Field

Type Reset Description

1 - 0

FSK_MODE_SEL

R/W 0h

Defines FSK mode.

0: Not used

1: FSK I2S

2: FSK SPI

3: FSK SPI FAST

7.6.116 Register R115 (offset = 73h) [reset = 0000h]

图 143. Register R115

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

7

6

5

4

3

2

0

1

0

FSK_DEV_SCALE

R/W-0h

表 122. Register R115 Field Descriptions

Bit

15 - 8

7 - 3

2 - 0

Field

Type Reset Description

R/W 0h

Program 0h to this field.

The FSK deviation will be scaled by 2^{FSK_DEV_SCALE}

FSK_DEV_SCALE

.

Program 0h to this field.

7.6.117 Register R116 (offset = 74h) [reset = 0000h]

图 144. Register R116

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

FSK_DEV0

R/W-0h

表 123. Register R116 Field Descriptions

Bit

Field

Type Reset Description

R/W 0h Defines the desired frequency deviation in FSK SPI mode.

15 - 0 FSK_DEV0

7.6.118 Register R117 (offset = 75h) [reset = 0000h]

图 145. Register R117

15

14

13

12

11

10

9

8

7

6

5

4

3

FSK_DEV1

R/W-0h

表 124. Register R117 Field Descriptions

Bit

Field

Type Reset Description

R/W 0h Defines the desired frequency deviation in FSK SPI mode.

15 - 0 FSK_DEV1

7.6.119 Register R118 (offset = 76h) [reset = 0000h]

图 146. Register R118

15

14

13

12

11

10

9

8

7

6

5

4

3

FSK_DEV2

R/W-0h

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表 125. Register R118 Field Descriptions

Bit

Field

Type Reset Description

15 - 0 FSK_DEV2

R/W 0h

Defines the desired frequency deviation in FSK SPI mode.

7.6.120 Register R119 (offset = 77h) [reset = 0000h]

图 147. Register R119

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

FSK_DEV3

R/W-0h

表 126. Register R119 Field Descriptions

Bit

Field

Type Reset Description

R/W 0h Defines the desired frequency deviation in FSK SPI mode.

15 - 0 FSK_DEV3

7.6.121 Register R120 (offset = 78h) [reset = 0000h]

图 148. Register R120

15

14

13

12

11

10

9

8

7

6

5

4

3

FSK_DEV4

R/W-0h

表 127. Register R120 Field Descriptions

Bit

Field

Type Reset Description

R/W 0h Defines the desired frequency deviation in FSK SPI mode.

15 - 0 FSK_DEV4

7.6.122 Register R121 (offset = 79h) [reset = 0000h]

图 149. Register R121

15

14

13

12

11

10

9

8

7

6

5

4

3

FSK_DEV5

R/W-0h

表 128. Register R121 Field Descriptions

Bit

Field

Type Reset Description

R/W 0h Defines the desired frequency deviation in FSK SPI mode.

15 - 0 FSK_DEV5

7.6.123 Register R122 (offset = 7Ah) [reset = 0000h]

图 150. Register R122

15

14

13

12

11

10

9

8

7

6

5

4

3

FSK_DEV6

R/W-0h

表 129. Register R122 Field Descriptions

Bit

Field

Type Reset Description

R/W 0h Defines the desired frequency deviation in FSK SPI mode.

15 - 0 FSK_DEV6

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7.6.124 Register R123 (offset = 7Bh) [reset = 0000h]

图 151. Register R123

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

FSK_DEV7

R/W-0h

表 130. Register R123 Field Descriptions

Bit

Field

Type Reset Description

R/W 0h Defines the desired frequency deviation in FSK SPI mode.

15 - 0 FSK_DEV7

7.6.125 Register R124 (offset = 7Ch) [reset = 0000h]

图 152. Register R124

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

FSK_SPI_FAST_DEV

R/W-0h

表 131. Register R124 Field Descriptions

Bit

Field

Type Reset Description

R/W 0h Defines the desired frequency deviation in FSK SPI FAST mode.

15 - 0 FSK_SPI_FAST_DEV

7.6.126 Register R125 (offset = 7Dh) [reset = 0820h]

图 153. Register R125

15

0

14

0

13

0

12

0

11

1

10

0

9

0

8

0

7

0

6

0

5

1

4

0

3

0

2

0

1

0

R/W-0820h

表 132. Register R125 Field Descriptions

Bit

Field

Type Reset Description

R/W 820h Program 820h to this field.

After programming R0 with RESET = 1, no need to program this register.

15 - 0

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LMX2572LP

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8 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

8.1.1 OSCin Configuration

OSCin supports single-ended and differential clock. Register R5 defines OSCin configuration.

表 133. OSCin Configuration

OSCin TYPE

SINGLE-ENDED CLOCK

DIFFERENTIAL CLOCK

V_T

OSCin

Configuration Diagram

OSCin

OSCin*

50Ω

IPBUF_TYPE = 0

IPBUF_TERM = 1

Register Setting

IPBUF_TYPE = 1

Single-ended and differential input clock definitions are shown in 图 154.

V_OSCin

CMOS

Sine wave

Differential

图 154. Input Clock Definition

8.1.2 OSCin Slew Rate

The slew rate of the OSCin signal can have an impact on the spurs and phase noise of the LMX2572LP if it is

too low. In general, the best performance is for a high slew rate but a lower amplitude signal, such as LVDS.

8.1.3 VCO Gain

The VCO gain varies between the six VCO cores and is the lowest at the lowest end of the band and highest at

the highest end of each band. The typical VCO gain over each VCO core is listed in 表 134.

表 134. VCO Gain

VCO CORE

VCO1

f_Min(MHz)

3200

f_Max(MHz)

3650

K_VCOMin (MHz/V)

K_VCOMax (MHz/V)

32

35

47

50

61

57

47

54

64

73

82

79

VCO2

3650

4200

VCO3

4200

4650

VCO4

4650

5200

VCO5

5200

5750

VCO6

5750

6400

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ZHCSIA2 –MAY 2018

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For an arbitrary VCO frequency, the VCO gain can be estimated as 公式 4:

K_VCO= K_VCOMin + (K_VCOMax – K_VCOMin) × (f_VCO– f_Min) / (f_Max– f_Min

)

(4)

8.1.4 VCO Calibration

The purpose of VCO calibration is to find out: (1) the correct VCO core, (2) the best band within the core, and (3)

the best VCO amplitude setting. The LMX2572LP allows the user to assist the VCO calibration. In general, there

are three kinds of assistance.

8.1.4.1 Partial Assist

Upon every frequency change, before the FCAL_EN bit is checked, the user provides a good estimate of the

initial starting point for the VCO core (VCO_SEL), band (VCO_CAPCTRL_STRT), and amplitude

(VCO_DACISET_STRT). To do the partial assist for the VCO calibration, follow this procedure:

1. Pick a VCO core that includes the desired VCO frequency. If at the boundary of two cores, choose based on

phase noise or performance.

2. Use 公式 5 to find the approximate band:

VCO_CAPCTRL_STRT = Round[C_Min– (f_VCO– f_Min) × (C_Min– C_Max) / (f_Max– f_Min)]

(5)

(6)

3. Use 公式 6 to find the approximate amplitude setting.

VCO_DACISET_STRT = Round[A_Min– (f_VCO– f_Min) × (A_Min– A_Max) / (f_Max– f_Min)]

表 135. VCO Core Parametric

VCO CORE

VCO1

f_Min(MHz)

3200

f_Max(MHz)

3650

C_Min

131

143

135

136

133

151

C_Max

19

A_Min

138

162

126

195

190

256

A_Max

137

142

114

172

163

204

VCO2

3650

4200

25

VCO3

4200

4650

34

VCO4

4650

5200

25

VCO5

5200

5750

20

VCO6

5750

6400

27

8.1.4.2 Close Frequency Assist

Upon initialization of the device, the user enables the QUICK_RECAL_EN bit. The next VCO calibration will use

the current VCO core, band, and amplitude settings as the initial starting point. This approach is useful if the

frequency change is small, say 50 MHz or so.

8.1.4.3 Full Assist

The user forces the VCO core (VCO_SEL), band (VCO_CAPCTRL), and amplitude (VCO_DACISET) and

manually sets the value. No VCO calibration will be performed. To force the set values, set VCO_SEL_FORCE,

VCO_CAPCTRL_FORCE, and VCO_DACISET_FORCE equal 1. First do a VCO calibration and then read back

the values to obtain the set values.

8.1.5 Output Buffer Control

8.1.5.1 Output Power

The OUTA_PWR and OUTB_PWR registers can be used to control the output power of the output buffers.

Values greater than 18 are prohibited.

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LMX2572LP

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10

8

9

6

3

4

0

2

OUTx_PWR

-3

-6

-9

-12

5

12

18

0

f_OUT

-2

-4

-6

250 MHz

500 MHz

1000 MHz

2000 MHz

0

200 400 600 800 1000 1200 1400 1600 1800 2000

2

4

6

8

10

12

14

16

18

f_OUT(MHz)

OUTx_PWR

D047

D048

图 155. Output Power vs Frequency

图 156. Output Power vs Power Control Bits

8.1.5.2 Power-Up Response

Use the OUTx_PD bits to power up or power down the output buffers. The RF output will vanish immediately

when the buffer is powered down. However, it takes some tiny amount of time for it to power up.

图 157. Buffer Power Up at 400-MHz Output

8.1.5.3 Unused Output Pin

Each output buffer has two differential pair pins. The buffer can be used as a single differential output or two

single-ended outputs. If only one single-ended output is necessary, the unused pin cannot be left open. The pin

should be terminated properly as shown in 图 158.

System device

RFout

图 158. Unused Output Buffer Differential Pin

8.1.6 Application for SYNC

The requirements for SYNC depend on certain setup conditions. In cases where the SYNC is not timing critical,

the setup can be done through software by toggling the VCO_PHASE_SYNC_EN bit from 0 to 1. When the

SYNC is timing critical, then setup must be done through the SYNC pin and the setup and hold times for the

OSCin pin are critical.

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ZHCSIA2 –MAY 2018

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Determine SYNC


型号：	LMX2572LPRHAT
厂家：	TEXAS INSTRUMENTS
描述：	采用 FSK 调制的 2GHz 低功耗宽带射频合成器 \| RHA \| 40 \| -40 to 85 射频
文件：	总81页 (文件大小：2003K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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