LMZ10504TZX-ADJ/NOPB [TI]
采用引线式表面贴装 TO 封装的 5.5V、4A 电源模块 | NDW | 7 | -40 to 125;
| 型号： | LMZ10504TZX-ADJ/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用引线式表面贴装 TO 封装的 5.5V、4A 电源模块 | NDW | 7 | -40 to 125 开关 电源电路 |
| 文件： | 总36页 (文件大小：1312K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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LMZ10504
ZHCS546P –DECEMBER 2009–REVISED APRIL 2019
具有 5.5V 最大输入电压的 LMZ10504 4A 电源模块
创建定制设计方案
1 特性
1
•
•
集成屏蔽电感器
2 应用
使用外部软启动、跟踪和精密使能端实现灵活启动
排序
•
•
•
从 3.3V 和 5V 电源轨到负载点的转换
空间受限型 应用
•
针对浪涌电流以及输入 UVLO 和输出短路等故障提
供保护
噪声敏感型 应用 （如收发器、医疗设备）
•
•
便于装配和制造的单个外露焊盘和标准引脚分布
与以下器件引脚到引脚兼容：
3 说明
LMZ10504 电源模块是一款完整的易用型直流/直流解
决方案，可驱动高达 4A 的负载，并具有出色的电源转
换效率、输出电压精度以及线路和负载调节功能。
LMZ10504 采用创新型封装，可提高散热性能并支持
手工或机器焊接。
–
–
LMZ10503（最大 3A/15W）
LMZ10505（最大 5A/25W）
•
•
针对 WEBENCH®和 Power Designer 提供全面支
持
电气规范
–
–
–
–
–
总输出功率最大值达 20W
LMZ10504 的输入电压轨范围为 2.95V 至 5.5V，提供
的高精度可调节输出电压低至 0.8V。PWM 开关的固
定频率为 1MHz，确保了 EMI 特性的可预测性。两个
外部补偿组件经过调节可设置最快的响应时间，并且允
许选用陶瓷输出电容或电解输出电容。外部可编程软启
动电容便于控制启动过程。LMZ10504 是一款稳定可
靠的解决方案，具有以下 功能：用于针对过流或短路
故障提供保护的无损逐周期峰值电流限制、热关断、输
入低压锁定和预偏置启动。
输出电流高达 4A
输入电压范围：2.95V 至 5.5V
输出电压范围：0.8V 至 5V
整个温度范围内的反馈电压精度达 ±1.63%
•
性能优势
–
–
–
可在高温环境下运行
效率高达 96%，能够有效减少系统产生的热量
经过低辐射发射 (EMI) 测试，符合 EN55022 B
类标准（EN 55022:2006、+A1:2007、FCC 第
15 部分 B 子部分：2007。请参阅Table 9 和布
局，获取有关测试器件的信息。）
器件信息(1)(2)
器件型号
LMZ10504
封装
封装尺寸（标称值）
TO-PMOD (7)
9.85mm × 10.16mm
–
–
通过 10V/m 辐射抗扰度电磁干扰 (EMI) 测试标
准 EN61000 4-3
(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品
附录。
针对现场可编程门阵列 (FPGA) 和特定用途集成
电路 (ASIC) 供电的快速瞬态响应
(2) 峰值回流温度等于 245°C。有关更多详细信息，请参阅
《LMZ1xxx 和 LMZ2xxx 电源模块系列设计摘要》。
•
使用 LMZ10504 并借助 WEBENCH® 电源设计器
典型应用电路
效率 (VOUT = 3.3V)
VIN
VOUT
6, 7
VOUT
FB
1
2
LMZ10504
VIN
EN
CO
5
Cin
SS
GND
4, EP
Rfbt
3
CSS
Ccomp
Rcomp
Rfbb
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNVS610
LMZ10504
ZHCS546P –DECEMBER 2009–REVISED APRIL 2019
www.ti.com.cn
目录
8.1 Application Information............................................ 14
8.2 Typical Application .................................................. 14
8.3 System Examples ................................................... 20
Power Supply Recommendations...................... 23
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 7
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description................................................. 10
7.4 Device Functional Modes........................................ 13
Application and Implementation ........................ 14
9
10 Layout................................................................... 23
10.1 Layout Guidelines ................................................. 23
10.2 Layout Examples................................................... 24
10.3 Estimate Power Dissipation and Thermal
Considerations ......................................................... 26
10.4 Power Module SMT Guidelines ............................ 27
11 器件和文档支持 ..................................................... 28
11.1 器件支持................................................................ 28
11.2 文档支持................................................................ 28
11.3 接收文档更新通知 ................................................. 28
11.4 社区资源................................................................ 29
11.5 商标....................................................................... 29
11.6 静电放电警告......................................................... 29
11.7 术语表 ................................................................... 29
12 机械、封装和可订购信息....................................... 29
7
8
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision O (June 2017) to Revision P
Page
•
仅有编辑修订；无技术性更改 ................................................................................................................................................ 1
Changes from Revision N (September 2015) to Revision O
Page
•
已更改 WEBENCH 列表项的语言；在产品说明书中进一步添加了有关 WEBENCH 的其他内容和链接................................ 1
Changes from Revision M (October 2013) to Revision N
Page
•
添加了 ESD 额定值 表、特性 说明 部分、器件功能模式、应用和实施 部分、电源建议 部分、布局 部分、器件和文档
支持 部分以及机械、封装和可订购信息 部分。...................................................................................................................... 1
Changes from Revision L (April 2013) to Revision M
Page
•
•
•
•
Deleted 10 mils....................................................................................................................................................................... 4
Changed 10 mils................................................................................................................................................................... 23
Changed 10 mils................................................................................................................................................................... 26
Added Power Module SMT Guidelines................................................................................................................................. 27
2
Copyright © 2009–2019, Texas Instruments Incorporated
LMZ10504
www.ti.com.cn
ZHCS546P –DECEMBER 2009–REVISED APRIL 2019
5 Pin Configuration and Functions
NDW Package
7-Lead TO-PMOD
Top View
VOUT
VOUT
FB
7
6
5
4
3
2
1
Exposed Pad
Connect to GND
GND
SS
EN
VIN
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
NO.
EN
2
Analog
Ground
Active-high enable input for the device.
Exposed pad is used as a thermal connection to remove heat from the device. Connect this
pad to the PCB ground plane in order to reduce thermal resistance value. EP must also
provide a direct electrical connection to the input and output capacitors ground terminals.
Connect EP to pin 4.
Exposed Pad
—
Feedback pin. This is the inverting input of the error amplifier used for sensing the output
voltage. Keep the copper area of this node small.
FB
5
4
Analog
Ground
Power ground and signal ground. Provide a direct connection to the EP. Place the bottom
feedback resistor as close as possible to GND and FB pin.
GND
Soft-start control pin. An internal 2-µA current source charges an external capacitor
connected between SS and GND pins to set the output voltage ramp rate during start-up.
The SS pin can also be used to configure the tracking feature.
SS
3
Analog
Power supply input. A low-ESR input capacitance should be located as close as possible to
the VIN pin and exposed pad (EP).
VIN
1
Power
Power
The output terminal of the internal inductor. Connect the output filter capacitor between
VOUT pin and EP.
VOUT
6, 7
Copyright © 2009–2019, Texas Instruments Incorporated
3
LMZ10504
ZHCS546P –DECEMBER 2009–REVISED APRIL 2019
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings(1)(2)(3)
MIN
MAX
UNIT
VIN, VOUT, EN, FB, SS to GND
Power dissipation
–0.3
6
V
Internally Limited
Junction temperature
150
245
150
°C
°C
°C
Peak reflow case temperature (30 s)
Storage temperature, Tstg
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) For soldering specifications, refer to the Absolute Maximum Ratings for Soldering (SNOA549).
6.2 ESD Ratings
VALUE
UNIT
V(ESD)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
V
(1) The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin. Test method is per JESD22-AI14S.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.95
–40
MAX
5.5
UNIT
V
VIN to GND
Junction temperature (TJ)
125
°C
6.4 Thermal Information
LMZ10504
THERMAL METRIC(1)
NDW (TO-PMOD)
UNIT
7 PINS
20
RθJA
Junction-to-ambient thermal resistance(2)
°C/W
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance (no air flow)
1.9
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2)
RθJA measured on a 2.25-in × 2.25-in (5.8 cm × 5.8 cm) 4-layer board, with 1-oz. copper, thirty six thermal vias, no air flow, and 1-W
power dissipation. Refer to Layout Examples or AN-2022 LMZ1050x Evaluation Board (SNVA421).
4
Copyright © 2009–2019, Texas Instruments Incorporated
LMZ10504
www.ti.com.cn
ZHCS546P –DECEMBER 2009–REVISED APRIL 2019
6.5 Electrical Characteristics
Specifications are for TJ = 25°C unless otherwise specified. Minimum and maximum limits are ensured through test, design,
or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference
purposes only. VIN = VEN = 3.3 V, unless otherwise indicated in the conditions column.
PARAMETER
TEST CONDITIONS
MIN(1)
TYP(2) MAX(1)
UNIT
SYSTEM PARAMETERS
0.8
0.82
0.8
Total feedback voltage
variation including line and VOUT = 2.5 V
load regulation
VIN = 2.95 V to 5.5 V
over the operating junction
temperature range TJ of
–40°C to 125°C
V FB
V FB
V FB
V
0.78
0.787
0.785
IOUT = 0 A to 4 A
VIN = 3.3 V, VOUT = 2.5
V
IOUT = 0 A
over the operating junction
temperature range TJ of
–40°C to 125°C
Feedback voltage variation
V
V
0.812
0.798
0.81
2.6
VIN = 3.3 V, VOUT = 2.5
V
IOUT = 4 A
over the operating junction
temperature range TJ of
–40°C to 125°C
Feedback voltage variation
over the operating junction
temperature range TJ of
–40°C to 125°C
Rising
2.95
Input UVLO threshold
(measured at VIN pin)
VIN(UVLO)
V
2.4
over the operating junction
temperature range TJ of
–40°C to 125°C
Falling
1.95
ISS
Soft-start current
Charging Current
2
µA
1.7
over the operating junction
temperature range TJ of
–40°C to 125°C
IQ
Non-switching input current VFB = 1 V
mA
3
260
500
5.5
Shutdown quiescent
current
over the operating junction
temperature range TJ of
–40°C to 125°C
ISD
VIN = 5.5 V, VEN = 0 V
µA
Output current limit
(average current)
over the operating junction
temperature range TJ of
–40°C to 125°C
IOCL
VOUT = 2.5 V
In current limit
A
4.1
6.7
fFB
Frequency foldback
250
kHz
PWM SECTION
1000
1160
fSW
Switching frequency
kHz
over the operating junction temperature range TJ of
–40°C to 125°C
750
0%
over the operating junction temperature range TJ of
–40°C to 125°C
Drange
PWM duty cycle range
100%
ENABLE CONTROL
VEN-IH EN pin rising threshold
1.23
V
V
over the operating junction temperature range TJ of
–40°C to 125°C
1.8
1.06
VEN-IF
EN pin falling threshold
over the operating junction temperature range TJ of
–40°C to 125°C
0.8
(1) Minimum and maximum limits are 100% production tested at an ambient temperature (TA) of 25°C. Limits over the operating
temperature range are ensured through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate
Average Outgoing Quality Level (AOQL).
(2) Typical numbers are at 25°C and represent the most likely parametric norm.
Copyright © 2009–2019, Texas Instruments Incorporated
5
LMZ10504
ZHCS546P –DECEMBER 2009–REVISED APRIL 2019
www.ti.com.cn
Electrical Characteristics (continued)
Specifications are for TJ = 25°C unless otherwise specified. Minimum and maximum limits are ensured through test, design,
or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference
purposes only. VIN = VEN = 3.3 V, unless otherwise indicated in the conditions column.
PARAMETER
THERMAL CONTROL
TEST CONDITIONS
MIN(1)
TYP(2) MAX(1)
UNIT
TSD
TJ for thermal shutdown
145
10
°C
°C
Hysteresis for thermal
shutdown
TSD-HYS
PERFORMANCE PARAMETERS
Refer to Table 1
VOUT = 2.5 V
Bandwidth Limit = 2 MHz
10
ΔVOUT
Output voltage ripple
mVpk-pk
Refer to Table 5 bandwidth limit = 20 MHz
5
0.04%
0.25%
0.04%
ΔVIN = 2.95 V to 5.5 V
IOUT = 0 A
ΔVFB
VFB
/
Feedback voltage line
regulation
IOUT = 0 A to 4 A
ΔVIN = 2.95 V to 5.5 V
IOUT = 0 A, VOUT = 2.5 V
ΔVOUT
VOUT
/
Output voltage line
regulation
IOUT = 0 A to 4 A
VOUT = 2.5 V
0.25%
EFFICIENCY
VOUT = 3.3 V
VOUT = 2.5 V
VOUT = 1.8 V
VOUT = 1.5 V
VOUT = 1.2 V
VOUT = 0.8 V
VOUT = 2.5 V
VOUT = 1.8 V
VOUT = 1.5 V
VOUT = 1.2 V
VOUT = 0.8V
VOUT = 3.3 V
VOUT = 2.5 V
VOUT = 1.8 V
VOUT = 1.5 V
VOUT = 1.2 V
VOUT = 0.8 V
VOUT = 2.5 V
VOUT = 1.8 V
VOUT = 1.5 V
VOUT = 1.2 V
VOUT = 0.8 V
96.1%
94.8%
93.1%
92%
Peak efficiency (1 A) VIN
5 V
=
=
η
η
η
η
90.4%
86.8%
95.7%
94.1%
93%
Peak efficiency (1 A) VIN
3.3 V
91.6%
88.3%
94.1%
92.4%
90%
Full load efficiency (4 A)
VIN = 5 V
88.3%
86.1%
80.8%
91.4%
90%
Full load efficiency (4 A)
VIN = 3.3 V
87.2%
84.9%
79.3%
6
Copyright © 2009–2019, Texas Instruments Incorporated
LMZ10504
www.ti.com.cn
ZHCS546P –DECEMBER 2009–REVISED APRIL 2019
6.6 Typical Characteristics
Unless otherwise specified, the following conditions apply: VIN = VEN = 5 V, CIN is 47-µF 10-V X5R ceramic capacitor; TA =
25°C for efficiency curves and waveforms.
VOUT = 3.3 V
VOUT = 1.8 V
VOUT = 1.2 V
VOUT = 2.5 V
VOUT = 1.5 V
VOUT = 0.8 V
Figure 1. Efficiency
Figure 3. Efficiency
Figure 5. Efficiency
Figure 2. Efficiency
Figure 4. Efficiency
Figure 6. Efficiency
Copyright © 2009–2019, Texas Instruments Incorporated
7
LMZ10504
ZHCS546P –DECEMBER 2009–REVISED APRIL 2019
www.ti.com.cn
Typical Characteristics (continued)
Unless otherwise specified, the following conditions apply: VIN = VEN = 5 V, CIN is 47-µF 10-V X5R ceramic capacitor; TA =
25°C for efficiency curves and waveforms.
VIN = 5 V, RθJA = 20°C/W
Figure 7. Current Derating
VIN = 3.3 V, RθJA = 20°C/W
Figure 8. Current Derating
VOUT = 2.5 V, IOUT = 0 A
VIN = 5 V, VOUT = 2.5 V, IOUT = 4 A Evaluation Board
Figure 10. Start-Up
Figure 9. Radiated Emissions (EN 55022, Class B)
VOUT = 2.5 V, IOUT = 0 A
VIN = 3.3 V, VOUT = 2.5 V, IOUT = 0.4-A to 3.6-A to 0.4-A step
20 mV/DIV, 20-MHz Bandwidth Limited
Refer to Table 5 for BOM, includes optional components
Figure 12. Load Transient Response
Figure 11. Prebiased Start-Up
8
Copyright © 2009–2019, Texas Instruments Incorporated
LMZ10504
www.ti.com.cn
ZHCS546P –DECEMBER 2009–REVISED APRIL 2019
Typical Characteristics (continued)
Unless otherwise specified, the following conditions apply: VIN = VEN = 5 V, CIN is 47-µF 10-V X5R ceramic capacitor; TA =
25°C for efficiency curves and waveforms.
VIN = 3.3 V, VOUT = 2.5 V, IOUT = 4 A, 20 mV/DIV
Refer to Table 5 for BOM
VIN = 5.0 V, VOUT = 2.5 V, IOUT = 0.4-A to 3.6-A to 0.4-A step
20 mV/DIV, 20-MHz Bandwidth Limited
Refer to Table 5 for BOM, includes optional components
Figure 13. Load Transient Response
Figure 14. Output Voltage Ripple
VIN = 5.0 V, VOUT = 2.5 V, IOUT = 4 A,
20 mV/DIV, Refer to Table 5 for BOM
Figure 15. Output Voltage Ripple
Copyright © 2009–2019, Texas Instruments Incorporated
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LMZ10504
ZHCS546P –DECEMBER 2009–REVISED APRIL 2019
www.ti.com.cn
7 Detailed Description
7.1 Overview
The LMZ10504 power module is a complete, easy-to-use DC-DC solution capable of driving up to a 4-A load
with exceptional power conversion efficiency, output voltage accuracy, line and load regulation. The LMZ10504 is
available in an innovative package that enhances thermal performance and allows for hand or machine
soldering. The LMZ10504 is a reliable and robust solution with the following features: lossless cycle-by-cycle
peak current limit to protect for overcurrent or short-circuit fault, thermal shutdown, input undervoltage lockout,
and prebiased start-up.
7.2 Functional Block Diagram
VIN
1
1W
2.2 mF
2
2.2 mF
EN
1.5 mH
Voltage
Mode
6, 7
VOUT
3
Control
SS
5
4, EP
GND
FB
7.3 Feature Description
7.3.1 Enable
The LMZ10504 features an enable (EN) pin and associated comparator to allow the user to easily sequence the
LMZ10504 from an external voltage rail, or to manually set the input UVLO threshold. The turnon or rising
threshold and hysteresis for this comparator are typically 1.23 V and 0.15 V, respectively. The precise reference
for the enable comparator allows the user to ensure that the LMZ10504 will be disabled when the system
demands it to be.
The EN pin should not be left floating. For always-on operation, connect EN to VIN.
7.3.2 Enable and UVLO
Using a resistor divider from VIN to EN as shown in the schematic diagram below, the input voltage at which the
part begins switching can be increased above the normal input UVLO level according to:
Rent + Renb
V
= 1.23V ì
IN(UVLO)
Renb
(1)
For example, suppose that the required input UVLO level is 3.69 V. Choosing Renb = 10 kΩ, then we calculate
Rent = 20 kΩ.
10
Copyright © 2009–2019, Texas Instruments Incorporated
LMZ10504
www.ti.com.cn
ZHCS546P –DECEMBER 2009–REVISED APRIL 2019
Feature Description (continued)
VIN
VIN
EN
LMZ10504
Rent
Cin1
Renb
GND
Figure 16. Setting Enable and UVLO
Alternatively, the EN pin can be driven from another voltage source to cater to system sequencing requirements
commonly found in FPGA and other multi-rail applications. Figure 17 shows an LMZ10504 that is sequenced to
start based on the voltage level of a master system rail (VOUT1).
VOUT1
VIN
VOUT2
VIN
EN
VOUT
Rent
LMZ10504
CO1
Cin1
Renb
GND
Figure 17. Setting Enable and UVLO Using External Power Supply
7.3.3 Soft-Start
The LMZ10504 begins to operate when both the VIN and EN, voltages exceed the rising UVLO and enable
thresholds, respectively. A controlled soft-start eliminates inrush currents during start-up and allows the user
more control and flexibility when sequencing the LMZ10504 with other power supplies.
In the event of either VIN or EN decreasing below the falling UVLO or enable threshold respectively, the voltage
on the soft-start pin is collapsed by discharging the soft-start capacitor by a 14-µA (typical) current sink to
ground.
7.3.4 Soft-Start Capacitor
Determine the soft-start capacitance with the following relationship:
tssìIss
VFB
CSS
=
where
•
•
•
VFB is the internal reference voltage (nominally 0.8 V),
ISS is the soft-start charging current (nominally 2 µA)
and CSS is the external soft-start capacitance.
(2)
(3)
Thus, the required soft-start capacitor per unit output voltage start-up time is given by:
CSS = 2.5 nF / ms
For example, a 4-ms soft-start time will yield a 10-nF capacitance. The minimum soft-start capacitance is 680 pF.
Copyright © 2009–2019, Texas Instruments Incorporated
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LMZ10504
ZHCS546P –DECEMBER 2009–REVISED APRIL 2019
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Feature Description (continued)
7.3.5 Tracking
The LMZ10504 can track the output of a master power supply during soft-start by connecting a resistor divider to
the SS pin. In this way, the output voltage slew rate of the LMZ10504 will be controlled by a master supply for
loads that require precise sequencing. When the tracking function is used, a small value soft-start capacitor
should be connected to the SS pin to alleviate output voltage overshoot when recovering from a current limit
fault.
Master Power
Supply
VOUT1
VIN
VOUT2
VIN
VOUT
Rtrkt
EN
SS
LMZ10504
CO1
Cin1
VSS
Rtrkb
GND
Figure 18. Tracking Using External Power Supply
7.3.6 Tracking - Equal Soft-Start Time
One way to use the tracking feature is to design the tracking resistor divider so that the master supply output
voltage, VOUT1, and the LMZ10504 output voltage, VOUT2, both rise together and reach their target values at the
same time. This is termed ratiometric start-up. For this case, the equation governing the values of tracking divider
resistors Rtrkb and Rtrkt is given by:
Rtrkt
Rtrkb
=
VOUT1-1.0V
(4)
The above equation includes an offset voltage, of 200 mV, to ensure that the final value of the SS pin voltage
exceeds the reference voltage of the LMZ10504. This offset will cause the LMZ10504 output voltage to reach
regulation slightly before the master supply. For a value of 33 kΩ, 1% is recommended for Rtrkt as a compromise
between high-precision and low-quiescent current through the divider while minimizing the effect of the 2-µA soft-
start current source.
For example, if the master supply voltage VOUT1 is 3.3 V and the LMZ10504 output voltage was 1.8 V, then the
value of Rtrkb needed to give the two supplies identical soft-start times would be 14.3 kΩ. Figure 19 shows an
example of tracking using the equal soft-start time.
RATIOMETRIC STARTUP
VOUT1
VOUT2
EN
TIME
Figure 19. Timing Diagram for Tracking Using Equal Soft-Start Time
12
Copyright © 2009–2019, Texas Instruments Incorporated
LMZ10504
www.ti.com.cn
ZHCS546P –DECEMBER 2009–REVISED APRIL 2019
Feature Description (continued)
7.3.7 Tracking - Equal Slew Rates
Alternatively, the tracking feature can be used to have similar output voltage ramp rates. This is referred to as
simultaneous start-up. In this case, the tracking resistors can be determined based on Equation 5:
0.8V
Rtrkb
=
ìRtrkt
VOUT2 - 0.8V
(5)
and to ensure proper overdrive of the SS pin
VOUT2 < 0.8ì VOUT1
(6)
For the example case of VOUT1 = 5 V and VOUT2 = 2.5 V, with Rtrkt set to 33 kΩ as before, Rtrkb is calculated from
the above equation to be 15.5 kΩ. Figure 20 shows an example of tracking using the equal slew rates.
SIMULTANEOUS STARTUP
VOUT1
VOUT2
EN
TIME
Figure 20. Timing Diagram for Tracking Using Equal Slew Rates
7.3.8 Current Limit
When a current greater than the output current limit (IOCL) is sensed, the ON-time is immediately terminated and
the low-side MOSFET is activated. The low-side MOSFET stays on for the entire next four switching cycles.
During these skipped pulses, the voltage on the soft-start pin is reduced by discharging the soft-start capacitor by
a current sink on the soft-start pin of nominally 14 µA. Subsequent overcurrent events will drain more and more
charge from the soft-start capacitor, effectively decreasing the reference voltage as the output droops due to the
pulse skipping. Reactivation of the soft-start circuitry ensures that when the overcurrent situation is removed, the
part will resume normal operation smoothly.
7.3.9 Overtemperature Protection
When the LMZ10504 senses a junction temperature greater than 145°C (typical), both switching MOSFETs are
turned off and the part enters a standby state. Upon sensing a junction temperature below 135°C (typical), the
part will re-initiate the soft-start sequence and begin switching once again.
7.4 Device Functional Modes
7.4.1 Prebias Start-Up Capability
At start-up, the LMZ10504 is in a prebiased state when the output voltage is greater than zero. This often occurs
in many multi-rail applications such as when powering an ASIC, FPGA, or DSP. The output can be prebiased in
these applications through parasitic conduction paths from one supply rail to another. Even though the
LMZ10504 is a synchronous converter, it will not pull the output low when a prebias condition exists. The
LMZ10504 will not sink current during start-up until the soft-start voltage exceeds the voltage on the FB pin.
Because the device does not sink current it protects the load from damage that might otherwise occur if current
is conducted through the parasitic paths of the load.
Copyright © 2009–2019, Texas Instruments Incorporated
13
LMZ10504
ZHCS546P –DECEMBER 2009–REVISED APRIL 2019
www.ti.com.cn
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LMZ10504 is a step-down DC-to-DC power module. It is typically used to convert a higher DC voltage to a
lower DC voltage with a maximum output current of 4 A. The following design procedure can be used to select
components for the LMZ10504. Alternately, the WEBENCH software may be used to generate complete designs.
When generating a design, the WEBENCH software uses iterative design procedure and accesses
comprehensive databases of components. Please go to www.ti.com for more details.
8.2 Typical Application
This section provides several application solutions with an associated bill of materials. The compensation for
each solution was optimized to work over the full input range. Many applications have a fixed input voltage rail. It
is possible to modify the compensation to obtain a faster transient response for a given input voltage operating
point.
U1
VIN
VOUT
6, 7
5
1
2
VOUT
FB
VIN
EN
CO1
LMZ10504
Cin1
SS
3
GND
4, EP
Rfbt
CSS
C
comp
Rcomp
Rfbb
Figure 21. Typical Applications Schematic
8.2.1 Design Requirements
For this example the following application parameters exist.
•
•
•
•
•
VIN = 5 V
VOUT = 2.5 V
IOUT = 4 A
ΔVOUT = 20 mVpk-pk
ΔVo_tran = ±20 mVpk-pk
Table 1. Bill of Materials, VIN = 3.3 V to 5 V, VOUT = 2.5 V, IOUT (MAX) = 4 A, Optimized for Electrolytic Input
and Output Capacitance
DESIGNATOR
DESCRIPTION
Power Module
CASE SIZE
PFM-7
MANUFACTURER
Texas Instruments
Sanyo
MANUFACTURER P/N
LMZ10504TZ-ADJ
6TPE150MIC2
QUANTITY
U1
1
1
Cin1
150 µF, 6.3 V, 18 mΩ
C2, 6.0 x 3.2 x 1.8 mm
D3L, 7.3 x 4.3 x 2.8
mm
CO1
Rfbt
330 µF, 6.3 V, 18 mΩ
100 kΩ
Sanyo
6TPE330MIL
1
1
0603
Vishay Dale
CRCW0603100KFKEA
14
Copyright © 2009–2019, Texas Instruments Incorporated
LMZ10504
www.ti.com.cn
ZHCS546P –DECEMBER 2009–REVISED APRIL 2019
Typical Application (continued)
Table 1. Bill of Materials, VIN = 3.3 V to 5 V, VOUT = 2.5 V, IOUT (MAX) = 4 A, Optimized for Electrolytic Input
and Output Capacitance (continued)
DESIGNATOR
Rfbb
DESCRIPTION
47.5 kΩ
CASE SIZE
0603
MANUFACTURER
Vishay Dale
Vishay Dale
TDK
MANUFACTURER P/N
CRCW060347K5FKEA
CRCW060315K0FKEA
C1608C0G1H331J
QUANTITY
1
1
1
1
Rcomp
15 kΩ
0603
Ccomp
330 pF, ±5%, C0G, 50 V
10 nF, ±10%, X7R, 16 V
0603
CSS
0603
Murata
GRM188R71C103KA01
Table 2. Bill of Materials, VIN = 3.3 V, VOUT = 0.8 V, IOUT (MAX) = 4 A, Optimized for Solution Size and
Transient Response(1)
DESIGNATOR
U1
DESCRIPTION
Power Module
CASE SIZE
PFM-7
1206
MANUFACTURER
Texas Instruments
TDK
MANUFACTURER P/N
LMZ10504TZ-ADJ
QUANTITY
1
2
1
1
1
1
Cin1, CO1
Rfbt
47 µF, X5R, 6.3 V
110 kΩ
C3216X5R0J476M
0402
Vishay Dale
Vishay Dale
Murata
CRCW0402100KFKED
CRCW04021K00FKED
GRM1555C1H270JZ01
GRM155R71C103KA01
Rcomp
1.0 kΩ
0402
Ccomp
27 pF, ±5%, C0G, 50 V
10 nF, ±10%, X7R, 16 V
0402
CSS
0402
Murata
(1) In the case where the output voltage is 0.8 V, TI recommends removing Rfbb and keep Rfbt, Rcomp, and Ccomp for a type III
compensation.
8.2.2 Detailed Design Procedure
LMZ10504 is fully supported by WEBENCH and offers the following: component selection, performance,
electrical, and thermal simulations as well as the Build-It board, for a reduced design time. On the other hand, all
external components can be calculated by following the design procedure below.
1. Determine the input voltage and output voltage. Also, make note of the ripple voltage and voltage transient
requirements.
2. Determine the necessary input and output capacitance.
3. Calculate the feedback resistor divider.
4. Select the optimized compensation component values.
5. Estimate the power dissipation and board thermal requirements.
6. Follow the PCB design guideline.
7. Learn about the LMZ10504 features such as enable, input UVLO, soft start, tracking, prebiased start-up,
current limit, and thermal shutdown.
8.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LMZ10504 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
•
•
•
•
Run electrical simulations to see important waveforms and circuit performance
Run thermal simulations to understand board thermal performance
Export customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
Copyright © 2009–2019, Texas Instruments Incorporated
15
LMZ10504
ZHCS546P –DECEMBER 2009–REVISED APRIL 2019
www.ti.com.cn
8.2.2.2 Input Capacitor Selection
A 22-µF or 47-µF high-quality dielectric (X5R, X7R) ceramic capacitor rated at twice the maximum input voltage
is typically sufficient. The input capacitor must be placed as close as possible to the VIN pin and GND exposed
pad to substantially eliminate the parasitic effects of any stray inductance or resistance on the PCB and supply
lines.
Neglecting capacitor equivalent series resistance (ESR), the resultant input capacitor AC ripple voltage is a
triangular waveform. The minimum input capacitance for a given peak-to-peak value (ΔVIN) of VIN is specified as
follows:
IOUTìDì(1-D)
Cin
í
fsw ì D V
IN
where
•
the PWM duty cycle, D, is given by Equation 8
(7)
(8)
VOUT
D =
V
IN
If ΔVIN is 1% of VIN, this equals to 50 mV and fSW = 1 MHz.
2.5V
5V
2.5V
5V
≈
«
’ ≈
ì 1-
’
4Aì
∆
÷ ∆
◊ «
÷
◊
Cin
í
í 20 mF
1 MHz ì 50mV
(9)
A second criteria before finalizing the Cin bypass capacitor is the RMS current capability. The necessary RMS
current rating of the input capacitor to a buck regulator can be estimated by:
ICin(RMS) = IOUTì D(1-D)
(10)
2.5V
5V
2.5V
5V
≈
’
ICin(RMS) = 4Aì
1-
= 2A
∆
«
÷
◊
(11)
With this high AC current present in the input capacitor, the RMS current rating becomes an important
parameter. The maximum input capacitor ripple voltage and RMS current occur at 50% duty cycle. Select an
input capacitor rated for at least the maximum calculated ICin(RMS)
.
Additional bulk capacitance with higher ESR may be required to damp any resonance effects of the input
capacitance and parasitic inductance.
8.2.2.3 Output Capacitor Selection
In general, 22-µF to 100-µF, high-quality dielectric (X5R, X7R) ceramic capacitor rated at twice the maximum
output voltage is sufficient given the optimal high-frequency characteristics and low ESR of ceramic dielectrics.
Although, the output capacitor can also be of electrolytic chemistry for increased capacitance density.
Two output capacitance equations are required to determine the minimum output capacitance. One equation
determines the output capacitance (CO) based on PWM ripple voltage. The second equation determines CO
based on the load transient characteristics. Select the largest capacitance value of the two.
The minimum capacitance, given the maximum output voltage ripple (ΔVOUT) requirement, is determined by the
following equation:
DiL
CO
í
8ì fswì D VOUT - (DiLìRESR
)
where
•
the peak to peak inductor current ripple (ΔiL) is equal to Equation 13:
(12)
(13)
(V - VOUT )ìD
IN
DiL =
Lì fsw
16
Copyright © 2009–2019, Texas Instruments Incorporated
LMZ10504
www.ti.com.cn
ZHCS546P –DECEMBER 2009–REVISED APRIL 2019
RESR is the total output capacitor ESR, L is the inductance value of the internal power inductor, where L = 1.5
µH, and fSW = 1 MHz. Therefore, per the design example:
(5V- 2.5V)ì 2.5 V
5 V
DiL =
= 833 mA
1.5 mH ì 1 MHz
(14)
The minimum output capacitance requirement due to the PWM ripple voltage is:
833 mA
CO
í
»
ÿ
8ì1 MHzì 20 mV- 833 mAì3 mW
⁄
(15)
(16)
CO í 6 mF
Three mΩ is a typical RESR value for ceramic capacitors.
Equation 17 provides a good first pass capacitance requirement for a load transient:
Istepì VFBìLì V
IN
CO
í
4ì VOUTì(V - VOUT )ì D Vo_tran
IN
where
•
•
•
Istep is the peak to peak load step,
VFB = 0.8 V,
and ΔVo_tran is the maximum output voltage deviation, which is ±20 mV.
(17)
Therefore the capacitance requirement for the given design parameters is:
3.2Aì0.8Vì1.5mHì5V
4ì 2.5Vì(5V- 2.5V)ì 20mV
CO
í
(18)
(19)
CO í 39 mF
In this particular design the output capacitance is determined by the load transient requirements.
Table 3 lists some examples of commercially available capacitors that can be used with the LMZ10504.
Table 3. Recommended Output Filter Capacitors
CO (µF)
22
VOLTAGE (V), RESR (mΩ)
6.3, < 5
MAKE
MANUFACTURER
PART NUMBER
C3216X5R0J226M
C3216X5R0J476M
C3225X5R0J476M
C3225X5R1A476M
C3225X5R0J107M
TPSD157M006#0050
6TPE100MPB2
CASE SIZE
1206
Ceramic, X5R
Ceramic, X5R
Ceramic, X5R
Ceramic, X5R
Ceramic, X5R
Tantalum
TDK
TDK
47
6.3, < 5
1206
47
6.3, < 5
TDK
1210
47
10.0, < 5
6.3, < 5
TDK
1210
100
100
100
150
TDK
1210
6.3, 50
AVX
D, 7.5 × 4.3 × 2.9 mm
B2, 3.5 × 2.8 × 1.9 mm
C2, 6.0 × 3.2 × 1.8 mm
6.3, 25
Organic Polymer
Organic Polymer
Sanyo
Sanyo
6.3, 18
6TPE150MIC2
D3L, 7.3 × 4.3 × 2.8
mm
330
470
6.3, 18
6.3, 23
Organic Polymer
Niobium Oxide
Sanyo
AVX
6TPE330MIL
NOME37M006#0023
E, 7.3 × 4.3 × 4.1 mm
8.2.2.3.1 Output Voltage Setting
A resistor divider network from VOUT to the FB pin determines the desired output voltage as follows:
Rfbt + Rfbb
VOUT = 0.8Vì
Rfbb
(20)
Rfbt is defined based on the voltage loop requirements and Rfbb is then selected for the desired output voltage.
Resistors are normally selected as 0.5% or 1% tolerance. Higher accuracy resistors such as 0.1% are also
available.
Copyright © 2009–2019, Texas Instruments Incorporated
17
LMZ10504
ZHCS546P –DECEMBER 2009–REVISED APRIL 2019
www.ti.com.cn
The feedback voltage (at VOUT = 2.5 V) is accurate to within –2.5% / +2.5% over temperature and over line and
load regulation. Additionally, the LMZ10504 contains error nulling circuitry to substantially eliminate the feedback
voltage variation over temperature as well as the long-term aging effects of the internal amplifiers. In addition the
zero nulling circuit dramatically reduces the 1/f noise of the bandgap amplifier and reference. The manifestation
of this circuit action is that the duty cycle will have two slightly different but distinct operating points, each evident
every other switching cycle.
8.2.2.4 Loop Compensation
The LMZ10504 preserves flexibility by integrating the control components around the internal error amplifier while
using three small external compensation components from VOUT to FB. An integrated type II (two pole, one zero)
voltage-mode compensation network is featured. To ensure stability, an external resistor and small value
capacitor can be added across the upper feedback resistor as a pole-zero pair to complete a type III (three pole,
two zero) compensation network. The compensation components recommended in Table 4 provide type III
compensation at an optimal control loop performance. The typical phase margin is 45° with a bandwidth of 80
kHz. Calculated output capacitance values not listed in Table 4 should be verified before designing into
production. The detailed application note AN-2013 LMZ1050x/LMZ1050xEXT SIMPLE SWITCHER Power
Module (SNVA417) is available to provide verification support. . In general, calculated output capacitance values
below the suggested value will have reduced phase margin and higher control loop bandwidth. Output
capacitance values above the suggested values will experience a lower bandwidth and increased phase margin.
Higher bandwidth is associated with faster system response to sudden changes such as load transients. Phase
margin changes the characteristics of the response. Lower phase margin is associated with underdamped ringing
and higher phase margin is associated with overdamped response. Losing all phase margin will cause the
system to be unstable; an optimized area of operation is 30° to 60° of phase margin, with a bandwidth of 100
kHz ±20 kHz.
VIN
VOUT
VIN
Ccomp
EN
Rfbt
LMZ10504
Rcomp
FB
GND
Rfbb
Figure 22. Loop Compensation Control Components
Table 4. LMZ10504 Compensation Component Values
ESR (mΩ)
VIN (V)
CO (µF)
Rfbt (kΩ)(1)
Ccomp (pF)(1)
Rcomp (kΩ)(1)
MIN
2
MAX
20
20
10
5
22
200
124
82.5
63.4
63.4
226
150
316
27
68
1.5
1.4
47
2
100
150
150
150
220
220
1
150
220
220
62
0.681
1
1
5
10
26
15
31
25
50
30
60
3.48
12.1
6.98
14
100
560
(1) In the special case where the output voltage is 0.8 V, TI recommends to remove Rfbb and keep Rfbt, Rcomp, and Ccomp for a type III
compensation.
18
Copyright © 2009–2019, Texas Instruments Incorporated
LMZ10504
www.ti.com.cn
ZHCS546P –DECEMBER 2009–REVISED APRIL 2019
Table 4. LMZ10504 Compensation Component Values (continued)
ESR (mΩ)
VIN (V)
CO (µF)
Rfbt (kΩ)(1)
Ccomp (pF)(1)
Rcomp (kΩ)(1)
MIN
2
MAX
20
20
10
5
22
118
76.8
49.9
40.2
43.2
143
100
200
43
9.09
3.32
2.49
1
47
2
100
180
330
330
100
180
100
100
150
150
150
220
220
1
1
3.3
10
26
15
31
25
50
30
60
4.99
7.5
4.99
8.06
8.2.3 Application Curves
VOUT = 3.3 V
VOUT = 3.3 V
Figure 23. Current Derating
Figure 24. Efficiency
Figure 25. Radiated Emissions (EN 55022, Class B)
Copyright © 2009–2019, Texas Instruments Incorporated
19
LMZ10504
ZHCS546P –DECEMBER 2009–REVISED APRIL 2019
www.ti.com.cn
8.3 System Examples
8.3.1 Application Schematic for 3.3-V to 5-V Input and 2.5-V Output With Optimized Ripple and Transient
Response
The compensation for each solution was optimized to work over the stated input range. Many applications have a
fixed input voltage rail. It is possible to modify the compensation to obtain a faster transient response for a given
input voltage operating point. This schematic is intended to serve as a helpful starting point towards an optimized
design.
U1
Optional
VOUT
VIN
6, 7
1
2
VOUT
FB
VIN
EN
CO1
CO2
CO3
LMZ10504
C
comp
+
Cin2
Cin1
Rfbt
5
SS
GND
Rcomp
3
4, EP
CSS
Optional
Rfbb
Figure 26. Schematic for 2.5-V Output Based on 3.3-V to 5-V Input
Table 5. Bill of Materials, VIN = 3.3 V to 5 V, VOUT = 2.5 V, IOUT (MAX) = 4 A,
Optimized for Low Input and Output Ripple Voltage and Fast Transient Response(1)
DESIGNATOR
U1
DESCRIPTION
Power Module
CASE SIZE
PFM-7
1210
E
MANUFACTURER
Texas Instruments
AVX
MANUFACTURER P/N
LMZ10504TZ-ADJ
1210ZD226MAT
QUANTITY
1
2
Cin1
22 µF, X5R, 10 V
220 µF, 10 V, AL-Elec
4.7 µF, X5R, 10 V
22 µF, X5R, 6.3 V
100 µF, X5R, 6.3 V
75 kΩ
Cin2
Panasonic
AVX
EEE1AA221AP
1*
1*
1*
1
CO1
0805
1206
1812
0402
0402
0402
0402
0402
0805ZD475MAT
CO2
AVX
12066D226MAT
CO3
AVX
18126D107MAT
Rfbt
Vishay Dale
Vishay Dale
Vishay Dale
Murata
CRCW040275K0FKED
CRCW040234K8FKED
CRCW04021K00FKED
GRM1555C1H101JZ01
GRM155R71C103KA01
1
Rfbb
34.8 kΩ
1
Rcomp
Ccomp
CSS
1.0 kΩ
1
100 pF, ±5%, C0G, 50 V
10 nF, ±10%, X7R, 16 V
1
Murata
1
(1) * Optional components, include for low input and output voltage ripple.
Table 6. Output Voltage Setting (Rfbt = 75 kΩ)
VOUT
2.5 V
1.8 V
1.5 V
1.2 V
0.9 V
Rfbb
34.8 kΩ
59 kΩ
84.5 kΩ
150 kΩ
590 kΩ
20
Copyright © 2009–2019, Texas Instruments Incorporated
LMZ10504
www.ti.com.cn
ZHCS546P –DECEMBER 2009–REVISED APRIL 2019
8.3.2 Application Schematic for 3.3-V to 5-V Input and 2.5-V Output
The compensation for each solution was optimized to work over the stated input range. Many applications have a
fixed input voltage rail. It is possible to modify the compensation to obtain a faster transient response for a given
input voltage operating point. This schematic is intended to serve as a helpful starting point towards an optimized
design.
U1
VOUT
VIN
6, 7
5
1
2
VOUT
FB
VIN
EN
CO1
CO2
CO3
LMZ10504
Ren1
+
Cin4
Cin3
Cin5
Cin2
Cin1
SS
3
GND
Rfbt
4, EP
CSS
C
Rcomp
comp
Rfbb
Figure 27. Schematic for 2.5-V Output Based on 3.3-V to 5-V Input
Table 7. Bill of Materials, VIN = 3.3 V to 5 V, VOUT = 2.5 V, IOUT (MAX) = 4 A
DESIGNATOR
U1
DESCRIPTION
Power Module
1 µF, X7R, 16 V
CASE SIZE
PFM-7
0805
0805
1210
1210
E
MANUFACTURER
Texas Instruments
TDK
MANUFACTURER P/N
QUANTITY
LMZ10504TZ-ADJ
C2012X7R1C105K
C2012X5R0J475K
C3225X5R1C226M
C3225X5R0J476M
EEE1AA221AP
1
1
2
2
1
1
1
1
1
1
1
1
1
Cin1
Cin2, CO1
Cin3, CO2
Cin4
4.7 µF, X5R, 6.3 V
22 µF, X5R, 16 V
47 µF, X5R, 6.3 V
220 µF, 10 V, AL-Elec
100 µF, X5R, 6.3 V
75 kΩ
TDK
TDK
TDK
Cin5
Panasonic
TDK
CO3
1812
0805
0805
0805
0603
0805
0805
C4532X5R0J107M
CRCW080575K0FKEA
CRCW080534K8FKEA
CRCW08051K10FKEA
C1608C0G1H181J
CRCW0805100KFKEA
C2012C0G1H103J
Rfbt
Vishay Dale
Vishay Dale
Vishay Dale
TDK
Rfbb
34.8 kΩ
Rcomp
Ccomp
Ren1
1.1 kΩ
180 pF, ±5%, C0G, 50 V
100 kΩ
Vishay Dale
TDK
CSS
10 nF, ±5%, C0G, 50 V
Table 8. Output Voltage Setting (Rfbt = 75 kΩ)
VOUT
3.3 V
2.5 V
1.8 V
1.5 V
1.2 V
0.9 V
Rfbb
23.7 kΩ
34.8 kΩ
59 kΩ
84.5 kΩ
150 kΩ
590 kΩ
Copyright © 2009–2019, Texas Instruments Incorporated
21
LMZ10504
ZHCS546P –DECEMBER 2009–REVISED APRIL 2019
www.ti.com.cn
8.3.3 EMI Tested Schematic for 2.5-V Output Based on 3.3-V to 5-V Input
The compensation for each solution was optimized to work over the stated input range. Many applications have a
fixed input voltage rail. It is possible to modify the compensation to obtain a faster transient response for a given
input voltage operating point. This schematic is intended to serve as a helpful starting point towards an optimized
design.
U1
VOUT
VIN
6, 7
5
1
2
VOUT
FB
VIN
EN
CO1
LMZ10504
Cin3
Cin2
Cin1
SS
3
GND
4, EP
Rfbt
CSS
Ccomp
Rcomp
Rfbb
Figure 28. EMI Tested Schematic for 2.5-V Output Based on 3.3-V to 5-V Input
Table 9. Bill of Materials, VIN = 5 V, VOUT = 2.5 V, IOUT (MAX) = 4 A,
Tested With EN55022 Class B Radiated Emissions
DESIGNATOR
U1
DESCRIPTION
Power Module
CASE SIZE
PFM-7
0805
MANUFACTURER
Texas Instruments
TDK
MANUFACTURER P/N
LMZ10504TZ-ADJ
QUANTITY
1
1
1
1
1
1
1
1
1
1
Cin1
1 µF, X7R, 16 V
4.7 µF, X5R, 6.3 V
47 µF, X5R, 6.3 V
100 µF, X5R, 6.3 V
75 kΩ
C2012X7R1C105K
C2012X5R0J475K
C3225X5R0J476M
C4532X5R0J107M
CRCW080575K0FKEA
CRCW080534K8FKEA
CRCW08051K10FKEA
C1608C0G1H181J
C2012C0G1H103J
Cin2
0805
TDK
Cin3
1210
TDK
CO1
1812
TDK
Rfbt
0805
Vishay Dale
Vishay Dale
Vishay Dale
TDK
Rfbb
34.8 kΩ
0805
Rcomp
Ccomp
CSS
1.1 kΩ
0805
180 pF, ±5%, C0G, 50 V
10 nF, ±5%, C0G, 50 V
0603
0805
TDK
Table 10. Output Voltage Setting (Rfbt = 75 kΩ)
VOUT
3.3 V
2.5 V
1.8 V
1.5 V
1.2 V
0.9 V
Rfbb
23.7 kΩ
34.8 kΩ
59 kΩ
84.5 kΩ
150 kΩ
590 kΩ
22
Copyright © 2009–2019, Texas Instruments Incorporated
LMZ10504
www.ti.com.cn
ZHCS546P –DECEMBER 2009–REVISED APRIL 2019
9 Power Supply Recommendations
The LMZ10504 device is designed to operate from an input voltage supply range between 2.95 V and 5.5 V. This
input supply should be well regulated and able to withstand maximum input current and maintain a stable
voltage. The resistance of the input supply rail should be low enough that an input current transient does not
cause a high enough drop at the LMZ10504 supply voltage that can cause a false UVLO fault triggering and
system reset. If the input supply is more than a few inches from the LMZ10504, additional bulk capacitance may
be required in addition to the ceramic bypass capacitors. The amount of bulk capacitance is not critical, but a 47-
μF or 100-μF electrolytic capacitor is a typical choice.
10 Layout
10.1 Layout Guidelines
PCB layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance of a
DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce and resistive voltage drop in
the traces. These can send erroneous signals to the DC-DC converter resulting in poor regulation or instability.
Good layout can be implemented by following a few simple design rules.
1. Minimize area of switched current loops.
From an EMI reduction standpoint, it is imperative to minimize the high di/dt current paths. The high current
that does not overlap contains high di/dt, see Figure 29. Therefore physically place input capacitor (Cin1) as
close as possible to the LMZ10504 VIN pin and GND exposed pad to avoid observable high-frequency noise
on the output pin. This will minimize the high di/dt area and reduce radiated EMI. Additionally, grounding for
both the input and output capacitor should consist of a localized top side plane that connects to the GND
exposed pad (EP).
2. Have a single point ground.
The ground connections for the feedback, soft-start, and enable components should be routed only to the
GND pin of the device. This prevents any switched or load currents from flowing in the analog ground traces.
If not properly placed, poor grounding can result in degraded load regulation or erratic output voltage ripple
behavior. Provide the single point ground connection from pin 4 to EP.
3. Minimize trace length to the FB pin.
Both feedback resistors, Rfbt and Rfbb, and the compensation components, Rcomp and Ccomp, should be
located close to the FB pin. Since the FB node is high impedance, keep the copper area as small as
possible. This is most important as relatively high-value resistors are used to set the output voltage.
4. Make input and output bus connections as wide as possible.
This reduces any voltage drops on the input or output of the converter and maximizes efficiency. To optimize
voltage accuracy at the load, ensure that a separate feedback voltage sense trace is made at the load. Doing
so will correct for voltage drops and provide optimum output accuracy.
5. Provide adequate device heat-sinking.
Use an array of heat-sinking vias to connect the exposed pad to the ground plane on the bottom PCB layer.
If the PCB has multiple copper layers, thermal vias can also be employed to make connection to inner layer
heat-spreading ground planes. For best results use a 6 × 6 via array with minimum via diameter of 8 mils
thermal vias spaced 59 mils (1.5 mm). Ensure enough copper area is used for heat-sinking to keep the
junction temperature below 125°C.
Copyright © 2009–2019, Texas Instruments Incorporated
23
LMZ10504
ZHCS546P –DECEMBER 2009–REVISED APRIL 2019
www.ti.com.cn
10.2 Layout Examples
VIN
VOUT
LMZ10504
VIN
VOUT
dI
dt
High
Cin1
CO1
GND
Loop 2
Loop 1
Figure 29. Critical Current Loops to Minimize
Top View
Thermal Vias
GND
GND
EXPOSED PAD
CIN
COUT
1
2
3
4
5
6 7
VOUT
RFBT
VIN
RENT
RENB
CFF
CSS
RFBB
GND Plane
Figure 30. PCB Layout Guide
Figure 31. Top Copper
24
Copyright © 2009–2019, Texas Instruments Incorporated
LMZ10504
www.ti.com.cn
ZHCS546P –DECEMBER 2009–REVISED APRIL 2019
Layout Examples (continued)
Figure 32. Internal Layer 1 (Ground)
Figure 33. Internal Layer 2 (Ground and Signal Traces)
Copyright © 2009–2019, Texas Instruments Incorporated
25
LMZ10504
ZHCS546P –DECEMBER 2009–REVISED APRIL 2019
www.ti.com.cn
Layout Examples (continued)
Figure 34. Bottom Copper
10.3 Estimate Power Dissipation and Thermal Considerations
Use the current derating curves in the Typical Characteristics section to obtain an estimate of power loss
(PIC_LOSS). For the design case of VIN = 5 V, VOUT = 2.5 V, IOUT = 4 A, TA(MAX) = 85°C , and TJ(MAX) = 125°C, the
device must see a thermal resistance from case-to-ambient (θCA) of less than:
TJ(MAX) - TA(MAX)
qCA
í
- qJC
P
IC_LOSS
(21)
500 o Cì cm2
Board Area_cm2 í
ì
41oC
W
(22)
Given the typical thermal resistance from junction to case (θJC) to be 1.9°C/W (typical). Continuously operating at
a TJ greater than 125°C will have a shorten life span.
To reach θCA = 41°C/W, the PCB is required to dissipate heat effectively. With no airflow and no external heat, a
good estimate of the required board area covered by 1-oz. copper on both the top and bottom metal layers is:
500 o Cìcm2
Board Area_cm2 í
ì
qCA
W
(23)
(24)
500 o Cì cm2
Board Area_cm2 í
ì
41oC
W
As a result, approximately 12 square cm of 1-oz. copper on top and bottom layers is required for the PCB
design.
The PCB copper heat sink must be connected to the exposed pad (EP). Approximately thirty six, 8 mils thermal
vias spaced 59 mils (1.5 mm) apart must connect the top copper to the bottom copper. For an extended
discussion and formulations of thermal rules of thumb, refer to AN-2020 Thermal Design By Insight, Not
Hindsight (SNVA419) and for an example of a high thermal performance PCB layout, refer to the evaluation
board application note AN-2022 LMZ1050x Evaluation Board (SNVA421).
26
Copyright © 2009–2019, Texas Instruments Incorporated
LMZ10504
www.ti.com.cn
ZHCS546P –DECEMBER 2009–REVISED APRIL 2019
10.4 Power Module SMT Guidelines
The recommendations below are for a standard module surface mount assembly.
•
•
Land Pattern – Follow the PCB land pattern with either soldermask defined or non-soldermask defined pads
Stencil Aperture
–
For the exposed die attach pad (DAP), adjust the stencil for approximately 80% coverage of the PCB land
pattern
–
For all other I/O pads use a 1:1 ratio between the aperture and the land pattern recommendation
•
•
•
•
•
Solder Paste – Use a standard SAC Alloy such as SAC 305, type 3 or higher
Stencil Thickness – 0.125 to 0.15 mm
Reflow - Refer to solder paste supplier recommendation and optimized per board size and density
Maximum number of reflows allowed is one
Refer to Design Summary LMZ1xxx and LMZ2xxx Power Modules Family (SNAA214) for reflow information.
Figure 35. Sample Reflow Profile
Table 11. Sample Reflow Profile Table
MAX TEMP
(°C)
REACHED TIME ABOVE REACHED TIME ABOVE REACHED TIME ABOVE REACHED
PROBE
MAX TEMP
235°C
235°C
245°C
245°C
260°C
260°C
1
2
3
242.5
242.5
241.0
6.58
0.49
6.39
0.00
–
7.10
–
0.00
–
–
–
7.10
0.55
6.31
0.00
0.00
7.09
0.42
6.44
0.00
0.00
版权 © 2009–2019, Texas Instruments Incorporated
27
LMZ10504
ZHCS546P –DECEMBER 2009–REVISED APRIL 2019
www.ti.com.cn
11 器件和文档支持
11.1 器件支持
11.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此类
产品或服务单独或与任何 TI 产品或服务一起的表示或认可。
11.1.2 开发支持
11.1.2.1 使用 WEBENCH® 工具创建定制设计
单击此处，使用 LMZ10504 器件并借助 WEBENCH® 电源设计器创建定制设计方案。
1. 首先输入输入电压 (VIN)、输出电压 (VOUT) 和输出电流 (IOUT) 要求。
2. 使用优化器拨盘优化该设计的关键参数，如效率、尺寸和成本。
3. 将生成的设计与德州仪器 (TI) 的其他可行的解决方案进行比较。
WEBENCH 电源设计器可提供定制原理图以及罗列实时价格和组件供货情况的物料清单。
在多数情况下，可执行以下操作：
•
•
•
•
运行电气仿真，观察重要波形以及电路性能
运行热性能仿真，了解电路板热性能
将定制原理图和布局方案以常用 CAD 格式导出
打印设计方案的 PDF 报告并与同事共享
有关 WEBENCH 工具的详细信息，请访问 www.ti.com.cn/WEBENCH。
11.2 文档支持
11.2.1 相关文档
请参阅如下相关文档：
•
•
•
•
•
•
•
•
《AN-2027 LMZ14203 SIMPLE SWITCHER 电源模块的反向应用》(SNVA425)
《焊接的绝对最大额定值》(SNOA549)
《AN-2013 LMZ1050x/LMZ1050xEXT SIMPLE SWITCHER 电源模块》(SNVA417)
《AN-2022 LMZ1050x 评估板》(SNVA421)
《AN-2024 LMZ1420x/LMZ1200x 评估板》(SNVA422)
《AN-2020 热设计：学会洞察先机，不做事后诸葛》(SNVA419)
《AN-2026 PCB 设计对 SIMPLE SWITCHER 电源模块热性能的影响》(SNVA424)
《LMZ1xxx 和 LMZ2xxx 电源模块系列设计摘要》(SNAA214)
11.3 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
28
版权 © 2009–2019, Texas Instruments Incorporated
LMZ10504
www.ti.com.cn
ZHCS546P –DECEMBER 2009–REVISED APRIL 2019
11.4 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 商标
E2E is a trademark of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.7 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2009–2019, Texas Instruments Incorporated
29
PACKAGE OPTION ADDENDUM
www.ti.com
6-Feb-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
LMZ10504TZ-ADJ/NOPB
LMZ10504TZE-ADJ/NOPB
LMZ10504TZX-ADJ/NOPB
ACTIVE
TO-PMOD
TO-PMOD
TO-PMOD
NDW
7
7
7
250
RoHS Exempt
& Green
SN
SN
SN
Level-3-245C-168 HR
Level-3-245C-168 HR
Level-3-245C-168 HR
LMZ10504
TZ-ADJ
ACTIVE
ACTIVE
NDW
NDW
45
RoHS Exempt
& Green
-40 to 125
LMZ10504
TZ-ADJ
500
RoHS Exempt
& Green
-40 to 125
LMZ10504
TZ-ADJ
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
6-Feb-2020
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMZ10504TZ-ADJ/NOPB
TO-
PMOD
NDW
NDW
7
7
250
500
330.0
24.4
10.6 14.22
5.0
16.0
24.0
Q2
LMZ10504TZX-
ADJ/NOPB
TO-
PMOD
330.0
24.4
10.6 14.22
5.0
16.0
24.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LMZ10504TZ-ADJ/NOPB
LMZ10504TZX-ADJ/NOPB
TO-PMOD
TO-PMOD
NDW
NDW
7
7
250
500
367.0
367.0
367.0
367.0
45.0
45.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
NDW TO-PMOD
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
LMZ10504TZE-ADJ/NOPB
7
45
502
17
6700
8.4
Pack Materials-Page 3
MECHANICAL DATA
NDW0007A
BOTTOM SIDE OF PACKAGE
TOP SIDE OF PACKAGE
TZA07A (Rev D)
www.ti.com
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Copyright © 2022，德州仪器 (TI) 公司
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