LMZ14201HTZX/NOPB [TI]
SIMPLE SWITCHER® 6V 至 42V、1A 高输出电压电源模块 | NDW | 7 | -40 to 125;
| 型号： | LMZ14201HTZX/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | SIMPLE SWITCHER® 6V 至 42V、1A 高输出电压电源模块 | NDW | 7 | -40 to 125 开关 电源电路 |
| 文件： | 总35页 (文件大小：1602K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LMZ14201H
ZHCS576I –JANUARY 2011 –REVISED AUGUST 2021
LMZ14201H SIMPLE SWITCHER® 6V 至42V、1A 高输出电压电源模块
1 特性
3 描述
• 集成屏蔽式电感器
• 简单的PCB 布局
• 采用外部软启动和精密使能端实现灵活启动排序
• 防止浪涌电流
• 输入UVLO 和输出短路保护
• -40°C 至125°C 的结温范围
• 便于装配和制造的单个外露焊盘和标准引脚分配
• 低输出电压纹波
LMZ14201H SIMPLE SWITCHER® 电源模块是一款易
于使用的降压直流/直流解决方案，可驱动高达 1A 的
负载，并具有出色的电源转换效率、线路和负载调节以
及输出精度。LMZ14201H 采用创新型封装，可提高热
性能并支持手工或机器焊接。
LMZ14201H 支持6V 至42V 的输入电压轨范围，可提
供低至 5V 的高精度可调节输出电压。LMZ14201H 仅
需三个外部电阻和四个外部电容器即可完善电源解决方
案。LMZ14201H 的设计可靠而稳健，并且具有以下保
护特性：热关断、输入欠压锁定、输出过压保护、短路
保护、输出限流以及预偏置输出的启动功能。单个电阻
最高可将开关频率调节至1MHz。
• 引脚对引脚兼容系列：
– LMZ14203H/2H/1H（42V 最大3A、2A、1A）
– LMZ14203/2/1（42V 最大3A、2A、1A）
– LMZ12003/2/1（20V 最大3A、2A、1A）
• 完全支持WEBENCH® power designer
• 电气规范
器件信息
封装(1)
器件型号(2)
LMZ14201H
封装尺寸（标称值）
– 输出电流高达1A
– 输入电压范围：6V 至42V
– 输出电压低至5V
TO-PMOD (7)
10.16mm × 9.85mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
– 效率高达97%
• 性能优势
(2) 峰值回流焊温度等于245°C。请参阅SNAA214 了解更多详细
信息。
– 高效率有效降低系统产生的热量
– 无需补偿
– 低封装热阻
– 低辐射EMI（经EN 55022 B 类标准测试）1
2 应用
• 中间总线转换为12V 和24V 电源轨
• 时间关键型项目
• 空间受限且散热要求较高的应用
• 负输出电压应用
100
95
90
85
80
LMZ14201H
V
IN
V
OUT
C
R
FF
ON
R
FBT
Enable
VIN = 15V
VIN = 24V
VIN = 30V
75
R
FBB
COUT
C
C
SS
VIN = 36V
IN
VIN = 42V
70
0.0
0.2
0.4
0.6
0.8
1.0
OUTPUT CURRENT (A)
简化版应用原理图
效率VOUT = 12V，TA = 25°C
1
EN 55022:2006、+A1:2007、FCC 第15 部分B 子部分：2007。
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNVS690
LMZ14201H
ZHCS576I –JANUARY 2011 –REVISED AUGUST 2021
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Table of Contents
8 Application and Implementation..................................17
8.1 Application Information............................................. 17
8.2 Typical Application.................................................... 17
9 Power Supply Recommendations................................22
10 Layout...........................................................................23
10.1 Layout Guidelines................................................... 23
10.2 Layout Example...................................................... 24
11 Device and Documentation Support..........................27
11.1 Documentation Support.......................................... 27
11.2 接收文档更新通知................................................... 27
11.3 支持资源..................................................................27
11.4 Trademarks............................................................. 27
11.5 静电放电警告...........................................................27
11.6 术语表..................................................................... 27
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 描述................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics.............................................5
6.6 Typical Characteristics................................................7
7 Detailed Description......................................................15
7.1 Overview...................................................................15
7.2 Functional Block Diagram.........................................15
7.3 Feature Description...................................................15
7.4 Device Functional Modes..........................................16
Information.................................................................... 27
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision H (October 2015) to Revision I (August 2021)
Page
• 更新了整个文档中的表格、图和交叉参考的编号格式。..................................................................................... 1
• Updated 方程式17 .......................................................................................................................................... 21
Changes from Revision G (August 2015) to Revision H (October 2015)
Page
• Added this new bullet in the Power Module SMT Guidelines section...............................................................23
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5 Pin Configuration and Functions
VOUT
FB
7
6
SS
GND
EN
RON
VIN
Exposed Pad
Connect to GND
5
4
3
2
1
图5-1. NDW Package 7-Pin TO-PMD (Top View)
表5-1. Pin Functions
PIN
TYPE
DESCRIPTION
NO.
NAME
1
VIN
Power
Supply input —Additional external input capacitance is required between this pin and the exposed
pad (EP).
2
RON
Analog
ON-time resistor —An external resistor from VIN to this pin sets the ON-time and frequency of the
application. Typical values range from 100 kΩto 700 kΩ.
3
4
5
EN
GND
SS
Analog
Ground
Analog
Enable —Input to the precision enable comparator. Rising threshold is 1.18 V.
Ground —Reference point for all stated voltages. Must be externally connected to EP.
Soft-Start —An internal 8 µA current source charges an external capacitor to produce the soft-start
function.
6
FB
Analog
Feedback —Internally connected to the regulation, overvoltage, and short-circuit comparators. The
regulation reference point is 0.8 V at this input pin. Connect the feedback resistor divider between
the output and ground to set the output voltage.
7
VOUT
EP
Power
Output Voltage —Output from the internal inductor. Connect the output capacitor between this pin
and the EP.
Ground
—
Exposed Pad —Internally connected to pin 4. Used to dissipate heat from the package during
operation. Must be electrically connected to pin 4 external to the package.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2) (3)
MIN
–0.3
–0.3
MAX
43.5
7
UNIT
V
VIN, RON to GND
EN, FB, SS to GND
Junction Temperature
V
150
245
°C
°C
Peak Reflow Case Temperature
(30 sec)
Storage Temperature
150
°C
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) For soldering specifications, refer to the following document: SNOA549
6.2 ESD Ratings
VALUE
UNIT
V(ESD)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
MAX
42
UNIT
V
VIN
6
0
EN
6.5
V
Operation Junction Temperature
–40
125
°C
6.4 Thermal Information
LMZ14201H
THERMAL METRIC(1)
NDW (TO-PMD)
7 PINS
UNIT
4 layer printed-circuit-board, 7.62 cm x
7.62 cm (3 in x 3 in) area, 1 oz copper,
no air flow
16
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
4 layer printed-circuit-board, 6.35 cm x
6.35 cm (2.5 in x 2.5 in) area, 1 oz
copper, no air flow
18.4
1.9
RθJC(top) Junction-to-case (top) thermal resistance
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics
Minimum and maximum limits are ensured through test, design or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following
conditions apply: VIN = 24 V, VOUT = 12 V, RON = 249 kΩ
PARAMETER
SYSTEM PARAMETERS
ENABLE CONTROL
TEST CONDITIONS
VEN rising, TJ = –40°C to 125°C
VSS = 0 V, TJ = –40°C to 125°C
DC average, TJ = –40°C to 125°C
MIN(1)
1.10
8
TYP(2)
MAX(1) UNIT
VEN
EN threshold trip point
1.18
90
1.25
15
V
VEN-HYS
SOFT-START
ISS
EN threshold hysteresis
mV
SS source current
10
µA
µA
ISS-DIS
SS discharge current
–200
CURRENT LIMIT
ICL
Current limit threshold
1.5
1.95
2.7
A
VIN UVLO
EN pin floating
VIN rising
VINUVLO
Input UVLO
Hysteresis
3.75
130
V
EN pin floating
VIN falling
VINUVLO-HYST
mV
ON/OFF TIMER
tON-MIN
ON timer minimum pulse width
OFF timer pulse width
150
260
ns
ns
tOFF
REGULATION AND OVERVOLTAGE COMPARATOR
VIN = 24 V, VOUT = 12 V
VSS >+ 0.8 V
TJ = –40°C to 125°C
IOUT = 10 mA to 1 A
0.782
0.786
0.780
0.787
0.803
0.803
0.803
0.822
0.818
0.823
0.819
VFB
In-regulation feedback voltage
V
VIN = 24 V, VOUT = 12 V
VSS >+ 0.8 V
TJ = 25°C
IOUT = 10 mA to 1 A
VIN = 36 V, VOUT = 24 V
VSS >+ 0.8 V
TJ = –40°C to 125°C
IOUT = 10 mA to 1 A
VFB
In-regulation feedback voltage
V
V
VIN = 36 V, VOUT = 24 V
VSS >+ 0.8 V
TJ = 25°C
0.803
0.92
IOUT = 10 mA to 1 A
Feedback overvoltage protection
threshold
VFB-OVP
IFB
IQ
Feedback input bias current
Non-Switching Input Current
Shut Down Quiescent Current
5
1
nA
mA
μA
VFB= 0.86 V
VEN= 0 V
25
ISD
THERMAL CHARACTERISTICS
TSD
Thermal shutdown (rising)
Thermal shutdown hysteresis
165
15
°C
°C
TSD-HYST
PERFORMANCE PARAMETERS
Output Voltage Ripple
VOUT = 5 V, COUT = 100 µF 6.3 V X7R
VIN = 16 V to 42 V, IOUT= 1 A
VIN = 24 V, IOUT= 0 A to 1 A
8
0.01%
1.5
mVPP
mV/A
ΔVOUT
Line Regulation
Load Regulation
ΔVOUT/ΔVIN
ΔVOUT/ΔIOUT
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Minimum and maximum limits are ensured through test, design or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following
conditions apply: VIN = 24 V, VOUT = 12 V, RON = 249 kΩ
PARAMETER
TEST CONDITIONS
MIN(1)
TYP(2)
MAX(1) UNIT
Efficiency
VIN = 24 V, VOUT = 12 V, IOUT = 0.5 A
VIN = 24 V, VOUT = 12 V, IOUT = 1 A
94%
η
η
Efficiency
92%
(1) Minimum and Maximum limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through
correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
(2) Typical numbers are at 25°C and represent the most likely parametric norm.
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6.6 Typical Characteristics
Unless otherwise specified, the following conditions apply: VIN = 24 V; Cin = 10-uF X7R Ceramic; CO = 47 uF; TA = 25°C.
100
95
90
85
80
75
70
1.5
1.2
0.9
0.6
0.3
0.0
VIN = 8V
VIN = 12V
VIN = 24V
VIN = 36V
VIN = 42V
VIN = 8V
VIN = 12V
VIN = 24V
VIN = 36V
VIN = 42V
0.0
0.2
0.4
0.6
0.8
1.0
1.0
1.0
0.0
0.2
0.4
0.6
0.8
1.0
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
图6-1. Efficiency VOUT = 5 V, TA = 25°C
图6-2. Power Dissipation VOUT = 5 V, TA = 25°C
100
1.5
VIN = 15V
VIN = 24V
VIN = 30V
VIN = 36V
VIN = 42V
95
90
85
80
1.2
0.9
0.6
0.3
0.0
VIN = 15V
VIN = 24V
VIN = 30V
VIN = 36V
VIN = 42V
75
70
0.0
0.2
0.4
0.6
0.8
0.0
0.2
0.4
0.6
0.8
1.0
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
图6-3. Efficiency VOUT = 12 V, TA = 25°C
图6-4. Power Dissipation VOUT = 12 V, TA = 25°C
100
1.5
VIN = 24V
VIN = 30V
VIN = 36V
VIN = 42V
95
90
85
80
1.2
0.9
0.6
0.3
0.0
VIN = 24V
VIN = 30V
VIN = 36V
75
VIN = 42V
70
0.0
0.2
OUTPUT CURRENT (A)
图6-5. Efficiency VOUT = 15 V, TA = 25°C
0.4
0.6
0.8
0.0
0.2
0.4
0.6
0.8
1.0
OUTPUT CURRENT (A)
图6-6. Power Dissipation VOUT = 15 V, TA = 25°C
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6.6 Typical Characteristics (continued)
Unless otherwise specified, the following conditions apply: VIN = 24 V; Cin = 10-uF X7R Ceramic; CO = 47 uF; TA = 25°C.
100
95
90
85
80
75
70
1.5
1.2
0.9
0.6
0.3
0.0
VIN = 24V
VIN = 30V
VIN = 36V
VIN = 42V
VIN = 24V
VIN = 30V
VIN = 36V
VIN = 42V
0.0
0.2
0.4
0.6
0.8
1.0
1.0
1.0
0.0
0.2
0.4
0.6
0.8
1.0
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
图6-7. Efficiency VOUT = 18 V, TA = 25°C
图6-8. Power Dissipation VOUT = 18 V, TA = 25°C
100
1.5
VIN = 28V
VIN = 30V
VIN = 36V
VIN = 42V
95
90
85
80
1.2
0.9
0.6
0.3
0.0
VIN = 28V
VIN = 30V
VIN = 36V
75
VIN = 42V
70
0.0
0.2
0.4
0.6
0.8
0.0
0.2
0.4
0.6
0.8
1.0
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
图6-9. Efficiency VOUT = 24 V, TA = 25°C
图6-10. Power Dissipation VOUT = 24 V, TA = 25°C
100
1.5
95
90
85
80
1.2
0.9
0.6
0.3
75
VIN = 34V
VIN = 36V
VIN = 42V
VIN = 34V
VIN = 36V
VIN = 42V
70
0.0
0.0
0.0
0.2
0.4
0.6
0.8
0.2
OUTPUT CURRENT (A)
图6-12. Power Dissipation VOUT = 30 V, TA = 25°C
0.4
0.6
0.8 1.0
OUTPUT CURRENT (A)
图6-11. Efficiency VOUT = 30 V, TA = 25°C
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6.6 Typical Characteristics (continued)
Unless otherwise specified, the following conditions apply: VIN = 24 V; Cin = 10-uF X7R Ceramic; CO = 47 uF; TA = 25°C.
100
95
90
85
80
75
70
1.5
1.2
0.9
0.6
0.3
0.0
VIN = 8V
VIN = 12V
VIN = 24V
VIN = 36V
VIN = 42V
VIN = 8V
VIN = 12V
VIN = 24V
VIN = 36V
VIN = 42V
0.0
0.2
0.4
0.6
0.8
1.0
1.0
1.0
0.0
0.2
0.4
0.6
0.8
1.0
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
图6-13. Efficiency VOUT = 5 V, TA = 85°C
图6-14. Power Dissipation VOUT = 5 V, TA = 85°C
100
1.5
VIN = 15V
VIN = 24V
VIN = 30V
VIN = 36V
VIN = 42V
95
90
85
80
1.2
0.9
0.6
0.3
0.0
VIN = 15V
VIN = 24V
VIN = 30V
VIN = 36V
VIN = 42V
75
70
0.0
0.2
0.4
0.6
0.8
0.0
0.2
0.4
0.6
0.8
1.0
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
图6-15. Efficiency VOUT = 12 V, TA = 85°C
图6-16. Power Dissipation VOUT = 12 V, TA = 85°C
100
1.5
VIN = 24V
VIN = 30V
VIN = 36V
VIN = 42V
95
90
85
80
1.2
0.9
0.6
0.3
0.0
VIN = 24V
VIN = 30V
VIN = 36V
75
VIN = 42V
70
0.0
0.2
OUTPUT CURRENT (A)
图6-17. Efficiency VOUT = 15 V, TA = 85°C
0.4
0.6
0.8
0.0
0.2
0.4
0.6
0.8
1.0
OUTPUT CURRENT (A)
图6-18. Power Dissipation VOUT = 15 V, TA = 85°C
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6.6 Typical Characteristics (continued)
Unless otherwise specified, the following conditions apply: VIN = 24 V; Cin = 10-uF X7R Ceramic; CO = 47 uF; TA = 25°C.
100
95
90
85
80
75
70
1.5
1.2
0.9
0.6
0.3
0.0
VIN = 24V
VIN = 30V
VIN = 36V
VIN = 42V
VIN = 24V
VIN = 30V
VIN = 36V
VIN = 42V
0.0
0.2
0.4
0.6
0.8
1.0
1.0
1.0
0.0
0.2
0.4
0.6
0.8
1.0
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
图6-19. Efficiency VOUT = 18 V, TA = 85°C
图6-20. Power Dissipation VOUT = 18 V, TA = 85°C
100
1.5
VIN = 28V
VIN = 30V
VIN = 36V
VIN = 42V
95
90
85
80
1.2
0.9
0.6
0.3
0.0
VIN = 28V
VIN = 30V
VIN = 36V
75
VIN = 42V
70
0.0
0.2
0.4
0.6
0.8
0.0
0.2
0.4
0.6
0.8
1.0
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
图6-21. Efficiency VOUT = 24 V, TA = 85°C
图6-22. Power Dissipation VOUT = 24 V, TA = 85°C
100
1.5
95
90
85
80
1.2
0.9
0.6
0.3
75
VIN = 34V
VIN = 36V
VIN = 42V
VIN = 34V
VIN = 36V
VIN = 42V
70
0.0
0.0
0.0
0.2
0.4
0.6
0.8
0.2
OUTPUT CURRENT (A)
图6-24. Power Dissipation VOUT = 30 V, TA = 85°C
0.4
0.6
0.8 1.0
OUTPUT CURRENT (A)
图6-23. Efficiency VOUT = 30 V, TA = 85°C
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6.6 Typical Characteristics (continued)
Unless otherwise specified, the following conditions apply: VIN = 24 V; Cin = 10-uF X7R Ceramic; CO = 47 uF; TA = 25°C.
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.2
1.0
0.8
0.6
0.4
0.2
0.0
VIN = 15V
VIN = 24V
VIN = 42V
VIN = 15V
VIN = 24V
VIN = 42V
-20
0
20 40 60 80 100 120 140
-20
0
20 40 60 80 100 120 140
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
图6-25. Thermal Derating VOUT = 12 V, RθJA = 16°C/W
图6-26. Thermal Derating VOUT = 12 V, RθJA = 20°C/W
1.2
1.2
1.0
0.8
0.6
0.4
1.0
0.8
0.6
0.4
VIN = 30V
VIN = 36V
VIN = 42V
0.2
0.2
VIN = 30V
VIN = 36V
VIN = 42V
0.0
0.0
-20
0
20 40 60 80 100 120 140
-20
0
20 40 60 80 100 120 140
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
图6-27. Thermal Derating VOUT = 24 V, RθJA = 16°C/W
图6-28. Thermal Derating VOUT = 24 V, RθJA = 20°C/W
1.2
1.2
1.0
0.8
0.6
0.4
1.0
0.8
0.6
0.4
0.2
0.2
VIN = 34V
VIN = 36V
VIN = 42V
VIN = 34V
VIN = 36V
VIN = 42V
0.0
0.0
-20
0
20 40 60 80 100 120 140
-20
0
20 40 60 80 100 120 140
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
图6-29. Thermal Derating VOUT = 30 V, RθJA = 16°C/W
图6-30. Thermal Derating VOUT = 30 V, RθJA = 20°C/W
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6.6 Typical Characteristics (continued)
Unless otherwise specified, the following conditions apply: VIN = 24 V; Cin = 10-uF X7R Ceramic; CO = 47 uF; TA = 25°C.
40
35
30
25
20
15
10
5
0.20
0.15
0.10
0.05
0.00
-0.05
-0.10
-0.15
-0.20
0LFM (0m/s) air
225LFM (1.14m/s) air
500LFM (2.54m/s) air
Evaluation Board Area
VIN = 15V
VIN = 24V
VIN = 30V
VIN = 36V
VIN = 42V
0
0
10
20
30
40
50
60
0.0
0.2
0.4
0.6
0.8
1.0
2
BOARD AREA (cm )
OUTPUT CURRENT (A)
图6-32. Line and Load Regulation TA = 25°C
图6-31. Package Thermal Resistance RθJA 4 Layer PCB With 1-
oz Copper
VOUT=12V
1 µs/div
100 mV/div
图6-34. Output Ripple VIN = 24 V, IOUT = 1 A, Polymer
图6-33. Output Ripple VIN = 12 V, IOUT = 1 A, Ceramic COUT, BW
Electrolytic COUT, BW = 200 MHz
= 200 MHz
200 mV/Div
VOUT=12V
IOUT
500 mA/Div
1 ms/Div
图6-36. Load Transient Response VIN = 24 V VOUT = 12 V Load
图6-35. Load Transient Response VIN = 24 V VOUT = 12 V Load
Step From 30% to 100%
Step from 10% to 100%
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6.6 Typical Characteristics (continued)
Unless otherwise specified, the following conditions apply: VIN = 24 V; Cin = 10-uF X7R Ceramic; CO = 47 uF; TA = 25°C.
3.5
3.0
2.5
2.0
1.5
1.0
1.8
1.5
1.2
0.9
0.6
0.3
0.0
VIN = 12V
VIN = 24V
VIN = 36V
VIN = 42V
Fsw = 250kHz
Fsw = 400kHz
Fsw = 600kHz
5
10 15 20 25 30 35 40 45
INPUT VOLTAGE (V)
200 300 400 500 600 700 800
SWITCHING FREQUENCY (kHz)
图6-37. Current Limit vs. Input Voltage VOUT = 5 V
图6-38. Switching Frequency vs. Power Dissipation VOUT = 5 V
3.5
1.8
VIN = 15V
VIN = 24V
VIN = 36V
VIN = 42V
1.5
3.0
2.5
2.0
1.2
0.9
0.6
0.3
0.0
Fsw = 250kHz
Fsw = 400kHz
Fsw = 600kHz
1.5
1.0
5
10 15 20 25 30 35 40 45
INPUT VOLTAGE (V)
200 300 400 500 600 700 800
SWITCHING FREQUENCY (kHz)
图6-39. Current Limit vs. Input Voltage VOUT = 12 V
图6-40. Switching Frequency vs. Power Dissipation VOUT = 12 V
3.5
1.8
1.6
1.4
1.2
1.0
0.8
3.0
2.5
2.0
0.6
VIN = 30V
VIN = 36V
VIN = 42V
0.4
Fsw = 250kHz
Fsw = 400kHz
Fsw = 600kHz
1.5
1.0
0.2
0.0
30
33
36
39
42
45
200 300 400 500 600 700 800
SWITCHING FREQUENCY (kHz)
INPUT VOLTAGE (V)
图6-41. Current Limit vs. Input Voltage VOUT = 24 V
图6-42. Switching Frequency vs. Power Dissipation VOUT = 24 V
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6.6 Typical Characteristics (continued)
Unless otherwise specified, the following conditions apply: VIN = 24 V; Cin = 10-uF X7R Ceramic; CO = 47 uF; TA = 25°C.
80
Emissions (Evaluation Board)
EN 55022 Limit (Class B)
70
60
50
40
30
20
10
0
VOUT
ENABLE
0
200
FREQUENCY (MHz)
图6-44. Radiated EMI of Evaluation Board, VOUT = 12 V
400
600
800
1000
1 ms/Div
5V/Div
图6-43. Start-Up VIN = 24 V, IOUT = 1 A
80
70
60
50
40
30
20
10
Emissions
CISPR 22 Quasi Peak
CISPR 22 Average
0
0.1
1
10
100
FREQUENCY (MHz)
图6-45. Conducted EMI, VOUT = 12 V Evaluation Board BOM and 3.3-µH, 1-µF LC Line Filter
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7 Detailed Description
7.1 Overview
7.1.1 COT Control Circuit Overview
Constant ON-Time control is based on a comparator and an ON-time one-shot, with the output voltage feedback
compared to an internal 0.8V reference. If the feedback voltage is below the reference, the high-side MOSFET is
turned on for a fixed ON-time determined by a programming resistor RON. RON is connected to VIN such that ON-
time is reduced with increasing input supply voltage. Following this ON-time, the high-side MOSFET remains off
for a minimum of 260 ns. If the voltage on the feedback pin falls below the reference level again the ON-time
cycle is repeated. Regulation is achieved in this manner.
7.2 Functional Block Diagram
Vin
R
ENT
ENB
1
VIN
3
5
EN
SS
Linear reg
R
C
IN
Cvcc
Css
0.47 mF
VOUT
R
ON
7
2
6
RON
FB
V
O
Timer
C
15 mH
FF
Co
R
FBT
Internal
Passives
Regulator IC
R
FBB
GND
4
7.3 Feature Description
7.3.1 Output Overvoltage Comparator
The voltage at FB is compared to a 0.92-V internal reference. If FB rises above 0.92 V the ON-time is
immediately terminated. This condition is known as overvoltage protection (OVP). It can occur if the input voltage
is increased very suddenly or if the output load is decreased very suddenly. Once OVP is activated, the top
MOSFET ON-times will be inhibited until the condition clears. Additionally, the synchronous MOSFET will remain
on until inductor current falls to zero.
7.3.2 Current Limit
Current limit detection is carried out during the OFF-time by monitoring the current in the synchronous MOSFET.
Referring to the 节 7.2, when the top MOSFET is turned off, the inductor current flows through the load, the
PGND pin and the internal synchronous MOSFET. If this current exceeds the ICL value, the current limit
comparator disables the start of the next ON-time period. The next switching cycle will occur only if the FB input
is less than 0.8 V and the inductor current has decreased below ICL. Inductor current is monitored during the
period of time the synchronous MOSFET is conducting. So long as inductor current exceeds ICL, further ON-time
intervals for the top MOSFET will not occur. Switching frequency is lower during current limit due to the longer
OFF-time.
Note
The DC current limit varies with duty cycle, switching frequency, and temperature.
7.3.3 Thermal Protection
The junction temperature of the LMZ14201H should not be allowed to exceed its maximum ratings. Thermal
protection is implemented by an internal Thermal Shutdown circuit which activates at 165 °C (typical) causing
the device to enter a low power standby state. In this state the main MOSFET remains off causing VO to fall, and
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additionally the CSS capacitor is discharged to ground. Thermal protection helps prevent catastrophic failures for
accidental device overheating. When the junction temperature falls back below 145 °C (typical Hyst = 20 °C) the
SS pin is released, VO rises smoothly, and normal operation resumes.
7.3.4 Zero Coil Current Detection
The current of the lower (synchronous) MOSFET is monitored by a zero coil current detection circuit which
inhibits the synchronous MOSFET when its current reaches zero until the next ON-time. This circuit enables the
DCM operating mode, which improves efficiency at light loads.
7.3.5 Prebiased Start-Up
The LMZ14201H will properly start up into a prebiased output. This startup situation is common in multiple rail
logic applications where current paths may exist between different power rails during the startup sequence. The
prebias level of the output voltage must be less than the input UVLO set point. This will prevent the output
prebias from enabling the regulator through the high-side MOSFET body diode.
7.4 Device Functional Modes
7.4.1 Discontinuous Conduction and Continuous Conduction Modes
At light-load, the regulator will operate in discontinuous conduction mode (DCM). With load currents above the
critical conduction point, it will operate in continuous conduction mode (CCM). When operating in DCM the
switching cycle begins at zero amps inductor current; increases up to a peak value, and then recedes back to
zero before the end of the OFF-time. During the period of time that inductor current is zero, all load current is
supplied by the output capacitor. The next ON-time period starts when the voltage on the FB pin falls below the
internal reference. The switching frequency is lower in DCM and varies more with load current as compared to
CCM. Conversion efficiency in DCM is maintained because conduction and switching losses are reduced with
the smaller load and lower switching frequency.
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8 Application and Implementation
Note
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
The LMZ14201H is a step-down DC-to-DC power module. It is typically used to convert a higher DC voltage to a
lower DC voltage with a maximum output current of 1 A. The following design procedure can be used to select
components for the LMZ14201H. Alternately, the WEBENCH software may be used to generate complete
designs.
When generating a design, the WEBENCH software utilizes iterative design procedure and accesses
comprehensive databases of components. Please go to www.ti.com for more details.
8.2 Typical Application
V
R
FBT
R
FBB
R
ON
C
OUT
C
V
IN
OUT
OUT-ESR
LMZ14201H
30V
24V
18V
15V
12V
5V
34 kW
931W
619 kW 33 mF
1-75 mW
33 mF 1-60 mW
33 mF 1-60 mW
47 mF 1-65 mW
47 mF 1-75 mW
34 - 42V
28 - 42V
22 - 42V
18 - 42V
15 - 42V
8 - 42V
34 kW 1.18 kW 499 kW
34 kW 1.58 kW 374 kW
34 kW 1.91 kW 287 kW
34 kW 2.43 kW 249 kW
V
IN
34 kW 6.49 kW 100 kW 100 mF 1-145 mW
V
OUT
C
FF
R
ON
0.022 mF
* R
ENT
VIN
R
FBT
C
IN
10 mF
* R
ENB
R
FBB
C
OUT
C
SS
4700 pF
* See equation 1
to calculate values
图8-1. Simplified Application Schematic
8.2.1 Design Requirements
For this example the following application parameters exist.
• VIN Range = Up to 42 V
• VOUT = 5 V to 30 V
• IOUT = 1 A
Refer to the table in 图8-1 for more information.
8.2.2 Detailed Design Procedure
8.2.2.1 Design Steps for the LMZ14201H Application
The LMZ14201H is fully supported by WEBENCH which offers the following: component selection, electrical
simulation, thermal simulation, as well as a build-it prototype board for a reduction in design time. The following
list of steps can be used to manually design the LMZ14201H application.
1. Select minimum operating VIN with enable divider resistors.
2. Program VO with divider resistor selection.
3. Program turnon time with soft-start capacitor selection.
4. Select CO.
5. Select CIN.
6. Set operating frequency with RON
.
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7. Determine module dissipation.
8. Lay out PCB for required thermal performance.
8.2.2.1.1 Enable Divider, RENT and RENB Selection
The enable input provides a precise 1.18-V reference threshold to allow direct logic drive or connection to a
voltage divider from a higher enable voltage such as VIN. The enable input also incorporates 90 mV (typical) of
hysteresis resulting in a falling threshold of 1.09 V. The maximum recommended voltage into the EN pin is 6.5 V.
For applications where the midpoint of the enable divider exceeds 6.5 V, a small Zener diode can be added to
limit this voltage.
The function of the RENT and RENB divider shown in the 节7.2 is to allow the designer to choose an input voltage
below which the circuit will be disabled. This implements the feature of programmable undervoltage lockout. This
is often used in battery-powered systems to prevent deep discharge of the system battery. It is also useful in
system designs for sequencing of output rails or to prevent early turnon of the supply as the main input voltage
rail rises at power up. Applying the enable divider to the main input rail is often done in the case of higher input
voltage systems such as 24-V AC/DC systems where a lower boundary of operation should be established. In
the case of sequencing supplies, the divider is connected to a rail that becomes active earlier in the power-up
cycle than the LMZ14201H output rail. The two resistors should be chosen based on the following ratio:
RENT / RENB = (VIN-ENABLE/ 1.18 V) –1
(1)
The EN pin is internally pulled up to VIN and can be left floating for always-on operation. However, it is good
practice to use the enable divider and turn on the regulator when VIN is close to reaching its nominal value. This
will ensure smooth start-up and will prevent overloading the input supply.
8.2.2.1.2 Output Voltage Selection
Output voltage is determined by a divider of two resistors connected between VO and ground. The midpoint of
the divider is connected to the FB input. The voltage at FB is compared to a 0.8-V internal reference. In normal
operation an ON-time cycle is initiated when the voltage on the FB pin falls below 0.8 V. The high-side MOSFET
ON-time cycle causes the output voltage to rise and the voltage at the FB to exceed 0.8 V. As long as the
voltage at FB is above 0.8 V, ON-time cycles will not occur.
The regulated output voltage determined by the external divider resistors RFBT and RFBB is:
VO = 0.8 V × (1 + RFBT / RFBB
)
(2)
(3)
Rearranging terms; the ratio of the feedback resistors for a desired output voltage is:
RFBT / RFBB = (VO / 0.8 V) - 1
These resistors should be chosen from values in the range of 1 kΩ to 50 kΩ.
A feed-forward capacitor is placed in parallel with RFBT to improve load step transient response. Its value is
usually determined experimentally by load stepping between DCM and CCM conduction modes and adjusting for
best transient response and minimum output ripple.
A table of values for RFBT , RFBB , and RON is included in the simplified applications schematic.
8.2.2.1.3 Soft-Start Capacitor, CSS, Selection
Programmable soft-start permits the regulator to slowly ramp to its steady-state operating point after being
enabled, thereby reducing current inrush from the input supply and slowing the output voltage rise-time to
prevent overshoot.
Upon turnon, after all UVLO conditions have been passed, an internal 8uA current source begins charging the
external soft-start capacitor. The soft-start time duration to reach steady-state operation is given by the formula:
tSS = VREF × CSS / Iss = 0.8 V × CSS / 8 uA
(4)
This equation can be rearranged as follows:
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CSS = tSS × 8 μA / 0.8 V
(5)
Use of a 4700-pF capacitor results in 0.5-ms soft-start duration. This is a recommended value. Note that high
values of CSS capacitance will cause more output voltage droop when a load transient goes across the DCM-
CCM boundary. Use 方程式 18 below to find the DCM-CCM boundary load current for the specific operating
condition. If a fast load transient response is desired for steps between DCM and CCM mode the soft-start
capacitor value should be less than 0.018 µF.
Note that the following conditions will reset the soft-start capacitor by discharging the SS input to ground with an
internal 200-μA current sink:
• The enable input being “pulled low”
• Thermal shutdown condition
• Overcurrent fault
• Internal VIN UVLO
8.2.2.1.4 Output Capacitor, CO, Selection
None of the required output capacitance is contained within the module. At a minimum, the output capacitor
must meet the worst-case RMS current rating of 0.5 × ILR P-P, as calculated in 方程式 19. Beyond that, additional
capacitance will reduce output ripple so long as the ESR is low enough to permit it. A minimum value of 10 μF
is generally required. Experimentation will be required if attempting to operate with a minimum value. Low-ESR
capacitors, such as ceramic and polymer electrolytic capacitors are recommended.
8.2.2.1.4.1 Capacitance
方程式6 provides a good first pass approximation of CO for load transient requirements:
CO≥ISTEP × VFB × L × VIN/ (4 × VO × (VIN —VO) × VOUT-TRAN
)
(6)
As an example, for 1A load step, VIN = 24 V, VOUT = 12 V, VOUT-TRAN = 50 mV:
CO≥1 A × 0.8 V × 15 μH × 24 V / (4 × 12 V × ( 24 V –12 V) × 50 mV)
CO≥10.05 μF
8.2.2.1.4.2 ESR
The ESR of the output capacitor affects the output voltage ripple. High ESR will result in larger VOUT peak-to-
peak ripple voltage. Furthermore, high output voltage ripple caused by excessive ESR can trigger the
overvoltage protection monitored at the FB pin. The ESR should be chosen to satisfy the maximum desired VOUT
peak-to-peak ripple voltage and to avoid overvoltage protection during normal operation. The following equations
can be used:
ESRMAX-RIPPLE ≤VOUT-RIPPLE / ILR P-P
(7)
where
• ILR P-P is calculated using 方程式19 below.
ESRMAX-OVP < (VFB-OVP - VFB) / (ILR P-P × AFB
)
(8)
where
• AFB is the gain of the feedback network from VOUT to VFB at the switching frequency.
As worst-case, assume the gain of AFB with the CFF capacitor at the switching frequency is 1.
The selected capacitor should have sufficient voltage and RMS current rating. The RMS current through the
output capacitor is:
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I(COUT(RMS)) = ILR P-P / √12
(9)
8.2.2.1.5 Input Capacitor, CIN, Selection
The LMZ14201H module contains an internal 0.47 µF input ceramic capacitor. Additional input capacitance is
required external to the module to handle the input ripple current of the application. This input capacitance
should be as close as possible to the module. Input capacitor selection is generally directed to satisfy the input
ripple current requirements rather than by capacitance value.
Worst-case input ripple current rating is dictated by 方程式10:
I(CIN(RMS)) ≊ 1 / 2 × IO × √(D / 1-D)
(10)
where
• D ≊ VO / VIN
(As a point of reference, the worst-case ripple current will occur when the module is presented with full load
current and when VIN = 2 × VO).
Recommended minimum input capacitance is 10-uF X7R ceramic with a voltage rating at least 25% higher than
the maximum applied input voltage for the application. TI also recommends to pay attention to the voltage and
temperature deratings of the capacitor selected. Also note ripple current rating of ceramic capacitors may be
missing from the capacitor data sheet and you may have to contact the capacitor manufacturer for this rating.
If the system design requires a certain maximum value of input ripple voltage ΔVIN to be maintained then 方程式
11 may be used.
CIN ≥IO × D × (1–D) / fSW-CCM × ΔVIN
(11)
If ΔVIN is 1% of VIN for a 24-V input to 12-V output application this equals 240 mV and fSW = 400 kHz.
CIN≥1 A × 12 V/24 V × (1–12 V/24 V) / (400000 × 0.240 V)
CIN≥2.6 μF
Additional bulk capacitance with higher ESR may be required to damp any resonant effects of the input
capacitance and parasitic inductance of the incoming supply lines.
8.2.2.1.6 ON-Time, RON, Resistor Selection
Many designs will begin with a desired switching frequency in mind. As seen in the Typical Characteristics
section, the best efficiency is achieved in the 300 kHz to 400 kHz switching frequency range. 方程式 12 can be
used to calculate the RON value.
fSW(CCM) ≊ VO / (1.3 × 10-10 x RON
This can be rearranged as
)
(12)
RON ≊ VO / (1.3 × 10-10 x fSW(CCM)
(13)
The selection of RON and fSW(CCM) must be confined by limitations in the ON-time and OFF-time for the COT
Control Circuit Overview section.
The ON-time of the LMZ14201H timer is determined by the resistor RON and the input voltage VIN. It is
calculated as follows:
tON = (1.3 × 10-10 × RON) / VIN
(14)
The inverse relationship of tON and VIN gives a nearly constant switching frequency as VIN is varied. RON should
be selected such that the ON-time at maximum VIN is greater than 150 ns. The ON-timer has a limiter to ensure
a minimum of 150 ns for tON. This limits the maximum operating frequency, which is governed by 方程式15:
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fSW(MAX) = VO / (VIN(MAX) × 150 nsec)
(15)
This equation can be used to select RON if a certain operating frequency is desired so long as the minimum ON-
time of 150 ns is observed. The limit for RON can be calculated as follows:
RON ≥VIN(MAX) × 150 nsec / (1.3 × 10-10
)
(16)
If RON calculated in 方程式 13 is less than the minimum value determined in 方程式 16 a lower frequency should
be selected. Alternatively, VIN(MAX) can also be limited in order to keep the frequency unchanged.
Additionally, the minimum OFF-time of 260 ns (typical) limits the maximum duty ratio. Larger RON (lower FSW
should be selected in any application requiring large duty ratio.
)
8.2.2.1.6.1 Discontinuous Conduction and Continuous Conduction Mode Selection
Operating frequency in DCM can be calculated as follows:
2
fSW(DCM) ≊ VO × (VIN-1) × 15 μH × 1.18 × 1020 × IO / ((VIN–VO) × RON
)
(17)
In CCM, current flows through the inductor through the entire switching cycle and never falls to zero during the
OFF-time. The switching frequency remains relatively constant with load current and line voltage variations. The
CCM operating frequency can be calculated using 方程式12 above.
The approximate formula for determining the DCM/CCM boundary is as follows:
IDCB ≊ VO × (VIN–VO) / ( 2 × 15 μH × fSW(CCM) × VIN)
(18)
The inductor internal to the module is 15 μH. This value was chosen as a good balance between low and high
input voltage applications. The main parameter affected by the inductor is the amplitude of the inductor ripple
current (ILR). ILR can be calculated with:
ILR P-P = VO × (VIN- VO) / (15 µH × fSW × VIN)
(19)
where
• VIN is the maximum input voltage and fSW is determined from 方程式12.
If the output current IO is determined by assuming that IO = IL, the higher and lower peak of ILR can be
determined. Be aware that the lower peak of ILR must be positive if CCM operation is required.
8.2.3 Application Curve
100
95
90
85
80
VIN = 28V
VIN = 30V
VIN = 36V
75
VIN = 42V
70
0.0
0.2
0.4
0.6
0.8
1.0
OUTPUT CURRENT (A)
图8-2. Efficiency VOUT = 24 V, TA = 25°C
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9 Power Supply Recommendations
The LMZ14201H device is designed to operate from an input voltage supply range between 4.5 V and 42 V. This
input supply should be well regulated and able to withstand maximum input current and maintain a stable
voltage. The resistance of the input supply rail should be low enough that an input current transient does not
cause a high enough drop at the LMZ14201H supply voltage that can cause a false UVLO fault triggering and
system reset. If the input supply is more than a few inches from the LMZ14201H, additional bulk capacitance
may be required in addition to the ceramic bypass capacitors. The amount of bulk capacitance is not critical, but
a 47-μF or 100-μF electrolytic capacitor is a typical choice.
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10 Layout
10.1 Layout Guidelines
PCB layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance of a
DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce and resistive voltage drop in
the traces. These can send erroneous signals to the DC-DC converter resulting in poor regulation or instability.
Good layout can be implemented by following a few simple design rules.
1. Minimize area of switched current loops.
From an EMI reduction standpoint, it is imperative to minimize the high di/dt paths during PCB layout. The
high current loops that do not overlap have high di/dt content that will cause observable high frequency noise
on the output pin if the input capacitor (Cin1) is placed at a distance away from the LMZ14203. Therefore
place CIN1 as close as possible to the LMZ14203 VIN and GND exposed pad. This will minimize the high
di/dt area and reduce radiated EMI. Additionally, grounding for both the input and output capacitor should
consist of a localized top side plane that connects to the GND exposed pad (EP).
2. Have a single point ground.
The ground connections for the feedback, soft-start, and enable components should be routed to the GND
pin of the device. This prevents any switched or load currents from flowing in the analog ground traces. If not
properly handled, poor grounding can result in degraded load regulation or erratic output voltage ripple
behavior. Provide the single point ground connection from pin 4 to EP.
3. Minimize trace length to the FB pin.
Both feedback resistors, RFBT and RFBB, and the feed forward capacitor CFF, should be close to the FB pin.
Since the FB node is high impedance, maintain the copper area as small as possible. The trace are from
RFBT, RFBB, and CFF should be routed away from the body of the LMZ14203 to minimize noise.
4. Make input and output bus connections as wide as possible.
This reduces any voltage drops on the input or output of the converter and maximizes efficiency. To optimize
voltage accuracy at the load, ensure that a separate feedback voltage sense trace is made to the load.
Doing so will correct for voltage drops and provide optimum output accuracy.
5. Provide adequate device heat-sinking.
Use an array of heat-sinking vias to connect the exposed pad to the ground plane on the bottom PCB layer.
If the PCB has a plurality of copper layers, these thermal vias can also be employed to make connection to
inner layer heat-spreading ground planes. For best results use a 6 × 6 via array with minimum via diameter
of 8 mils thermal vias spaced 59 mils (1.5 mm). Ensure enough copper area is used for heat-sinking to keep
the junction temperature below 125°C.
10.1.1 Power Module SMT Guidelines
The recommendations below are for a standard module surface mount assembly
• Land Pattern –Follow the PCB land pattern with either soldermask defined or non-soldermask defined pads
• Stencil Aperture
– For the exposed die attach pad (DAP), adjust the stencil for approximately 80% coverage of the PCB land
pattern
– For all other I/O pads use a 1:1 ratio between the aperture and the land pattern recommendation
• Solder Paste –Use a standard SAC Alloy such as SAC 305, type 3 or higher
• Stencil Thickness –0.125 mm to 0.15 mm
• Reflow - Refer to solder paste supplier recommendation and optimized per board size and density
• Refer to AN Design Summary LMZ1xxx and LMZ2xxx Power Modules Family (SNAA214) for Reflow
information
• Maximum number of reflows allowed is one
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图10-1. Sample Reflow Profile
表10-1. Sample Reflow Profile Table
MAX TEMP
(°C)
REACHED TIME ABOVE REACHED TIME ABOVE REACHED TIME ABOVE REACHED
PROBE
MAX TEMP
235°C
235°C
245°C
245°C
260°C
260°C
1
2
3
242.5
242.5
241
6.58
0.49
6.39
0
0
0
0
0
0
–
–
7.1
0.55
6.31
7.1
–
7.09
0.42
6.44
–
–
10.2 Layout Example
V
IN
V
O
LMZ14201H
VOUT
VIN
High
di/dt
C
in1
C
O1
GND
Loop 2
Loop 1
图10-2. Critical Current Loops to Minimize
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Top View
Thermal Vias
GND
GND
EPAD
CIN
COUT
1
2
3
4
5
6
7
VOUT
VIN
RON
RFBT
RENT
CFF
CSS
RENB
RFBB
GND Plane
图10-3. PCB Layout Guide
10.2.1 Power Dissipation and Board Thermal Requirements
For a design case of VIN = 24 V, VOUT = 12 V, IOUT = 1 A, TA (MAX) = 85°C , and TJUNCTION = 125°C, the device
must see a maximum junction-to-ambient thermal resistance of:
RθJA-MAX < (TJ-MAX –TA(MAX)) / PD
(20)
This RθJA-MAX will ensure that the junction temperature of the regulator does not exceed TJ-MAX in the particular
application ambient temperature.
To calculate the required RθJA-MAX we need to get an estimate for the power losses in the IC. 图 10-4 is taken
from the Typical Characteristics section and shows the power dissipation of the LMZ14201H for VOUT = 12 V at
85°C TA.
1.5
VIN = 15V
VIN = 24V
VIN = 30V
VIN = 36V
VIN = 42V
1.2
0.9
0.6
0.3
0.0
0.0
0.2
0.4
0.6
0.8
1.0
OUTPUT CURRENT (A)
图10-4. Power Dissipation VOUT = 12 V, TA = 85°C
Using the 85°C TA power dissipation data as a conservative starting point, the power dissipation PD for VIN = 24
V and VOUT = 12 V is estimated to be 0.75 W. The necessary RθJA-MAX can now be calculated.
R
θJA-MAX < (125°C - 85°C) / 0.75 W
θJA-MAX < 53.3°C/W
(21)
(22)
R
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To achieve this thermal resistance the PCB is required to dissipate the heat effectively. The area of the PCB will
have a direct effect on the overall junction-to-ambient thermal resistance. In order to estimate the necessary
copper area we can refer to 图10-5. This graph is taken from the Typical Characteristics section and shows how
the RθJA varies with the PCB area.
40
0LFM (0m/s) air
225LFM (1.14m/s) air
500LFM (2.54m/s) air
35
Evaluation Board Area
30
25
20
15
10
5
0
0
10
20
30
40
50
60
2
BOARD AREA (cm )
图10-5. Package Thermal Resistance RθJA 4-Layer PCB With 1-oz Copper
For RθJA-MAX< 53.3°C/W and only natural convection (that is. no air flow), the PCB area can be smaller than 9
cm2. This corresponds to a square board with 3 cm × 3 cm (1.18 in × 1.18 in) copper area, 4 layers, and 1 oz
copper thickness. Higher copper thickness will further improve the overall thermal performance. Note that
thermal vias should be placed under the IC package to easily transfer heat from the top layer of the PCB to the
inner layers and the bottom layer.
For more guidelines and insight on PCB copper area, thermal vias placement, and general thermal design
practices, refer to Application Note AN-2020 (SNVA419).
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
• AN-2027 Inverting Application for the LMZ14203 SIMPLE SWITCHER Power Module, SNVA425
• Evaluation Board Application Note AN-2024, SNVA422
• AN-2026 Effect of PCB Design on Thermal Performance of SIMPLE SWITCHER Power Modules, SNVA424
• AN-2020 Thermal Design By Insight, Not Hindsight, SNVA419
• AN Design Summary LMZ1xxx and LMZ2xxx Power Modules Family, SNAA214
11.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
WEBENCH® and SIMPLE SWITCHER® are registered trademarks of Texas Instruments.
所有商标均为其各自所有者的财产。
11.5 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
11.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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重要声明和免责声明
TI 提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没
有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。
这些资源可供使用TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可
将这些资源用于研发本资源所述的TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他TI 知识产权或任何第三方知
识产权。您应全额赔偿因在这些资源的使用中对TI 及其代表造成的任何索赔、损害、成本、损失和债务，TI 对此概不负责。
TI 提供的产品受TI 的销售条款(https:www.ti.com/legal/termsofsale.html) 或ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI
提供这些资源并不会扩展或以其他方式更改TI 针对TI 产品发布的适用的担保或担保免责声明。重要声明
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021，德州仪器(TI) 公司
PACKAGE OPTION ADDENDUM
www.ti.com
16-Apr-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
250
45
(1)
(2)
(3)
(4/5)
(6)
LMZ14201HTZ/NOPB
LMZ14201HTZE/NOPB
LMZ14201HTZX/NOPB
ACTIVE
TO-PMOD
TO-PMOD
TO-PMOD
NDW
7
7
7
RoHS & Green
RoHS & Green
RoHS & Green
SN
Level-3-245C-168 HR
Level-3-245C-168 HR
Level-3-245C-168 HR
-40 to 125
-40 to 125
-40 to 125
LMZ14201
HTZ
ACTIVE
ACTIVE
NDW
SN
SN
LMZ14201
HTZ
NDW
500
LMZ14201
HTZ
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
16-Apr-2021
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMZ14201HTZ/NOPB
LMZ14201HTZX/NOPB
TO-
PMOD
NDW
NDW
7
7
250
500
330.0
24.4
10.6 14.22
5.0
16.0
24.0
Q2
TO-
330.0
24.4
10.6 14.22
5.0
16.0
24.0
Q2
PMOD
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LMZ14201HTZ/NOPB
LMZ14201HTZX/NOPB
TO-PMOD
TO-PMOD
NDW
NDW
7
7
250
500
367.0
367.0
367.0
367.0
45.0
45.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
NDW TO-PMOD
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
LMZ14201HTZE/NOPB
7
45
502
17
6700
8.4
Pack Materials-Page 3
MECHANICAL DATA
NDW0007A
BOTTOM SIDE OF PACKAGE
TOP SIDE OF PACKAGE
TZA07A (Rev D)
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022，德州仪器 (TI) 公司
相关型号：
LMZ14201TZX-ADJ/NOPB
IC SWITCHING REGULATOR, PSSO7, 10.16 X 13.77 MM, 4.57 MM HEIGHT, ROHS COMPLIANT, TO-PMOD, 7 PIN, Switching Regulator or Controller
NSC
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