LMZ14201_15 [TI]

SIMPLE SWITCHER 6V to 42V, 1A Power Module in Leaded SMT-TO Package;


型号：	LMZ14201_15
厂家：	TEXAS INSTRUMENTS
描述：	SIMPLE SWITCHER 6V to 42V, 1A Power Module in Leaded SMT-TO Package
文件：	总29页 (文件大小：1870K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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LMZ14201

SNVS649I –JANUARY 2010–REVISED OCTOBER 2015

LMZ14201 SIMPLE SWITCHER 6V to 42V, 1A Power Module in Leaded SMT-TO Package

1 Features

2 Applications

•

Integrated Shielded Inductor

Simple PCB Layout

•

Point of Load Conversions From 12-V and 24-V

Input Rail

•

Time-Critical Projects

Flexible Start-Up Sequencing Using External Soft-

Start and Precision Enable

Space Constrained and High Thermal

Requirement Applications

•

Protection Against Inrush Currents and Faults

Such as Input UVLO and Output Short Circuit

•

Negative Output Voltage Applications

(See AN-2027) SNVA425

•

–40°C to 125°C Junction Temperature Range

Single Exposed Pad and Standard Pinout for Easy

Mounting and Manufacturing

3 Description

The LMZ14201 SIMPLE SWITCHER^®power module

is an easy-to-use step-down DC-DC solution that can

drive up to 1-A load with exceptional power

conversion efficiency, line and load regulation, and

output accuracy. The LMZ14201 is available in an

•

Fast Transient Response for Powering FPGAs

and ASICs

•

Low Output Voltage Ripple

Pin-to-Pin Compatible Family:

innovative

package

that

enhances

thermal

–

LMZ1420x (42 V Maximum 3 A, 2 A, 1 A)

performance and allows for hand or machine

soldering.

–

LMZ1200x (20 V Maximum 3 A, 2 A, 1 A)

•

Fully Enabled for WEBENCH^®Power Designer

Electrical Specifications

The LMZ14201 can accept an input voltage rail

between 6 V and 42 V and deliver an adjustable and

highly accurate output voltage as low as 0.8 V. The

LMZ14201 only requires three external resistors and

four external capacitors to complete the power

solution. The LMZ14201 is a reliable and robust

design with the following protection features: thermal

shutdown, input UVLO, output overvoltage protection,

short-circuit protection, output current limit, and

allows start-up into a prebiased output. A single

resistor adjusts the switching frequency up to 1 MHz.

–

6-W Maximum Total Output Power

Up to 1-A Output Current

Input Voltage Range 6 V to 42 V

Output Voltage Range 0.8 V to 6 V

Efficiency up to 90%

•

Performance Benefits

–

Operates at High Ambient Temperature With

No Thermal Derating

Device Information⁽¹⁾⁽²⁾

High Efficiency Reduces System Heat

Generation

PART NUMBER

PACKAGE

BODY SIZE (NOM)

LMZ14201

TO-PMOD (7)

10.16 mm × 9.85 mm

Low Radiated Emissions (EMI) Tested With

EN55022 Class B Standard

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Low External Component Count

(2) Peak reflow temperature equals 245°C. See SNAA214 for

more details.

Simplified Application Schematic

Efficiency 12-V Input at 25°C

100

LMZ14201

6.0

5.0

3.3

2.5

1.8

1.5

1.2

OUT

0.8

FBT

Enable

C_OUT

FBB

25°C

0.2

0.4

0.6

0.8

OUTPUT CURRENT (A)

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

LMZ14201

SNVS649I –JANUARY 2010–REVISED OCTOBER 2015

www.ti.com

Table of Contents

Features.................................................................. 1

Applications ........................................................... 1

Description ............................................................. 1

Revision History..................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 3

6.1 Absolute Maximum Ratings ...................................... 3

6.2 ESD Ratings.............................................................. 3

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 4

6.5 Electrical Characteristics........................................... 4

6.6 Typical Characteristics ............................................. 6

Detailed Description ............................................ 11

7.1 Overview ................................................................. 11

7.2 Functional Block Diagram ....................................... 11

7.3 Feature Description................................................. 11

7.4 Device Functional Modes........................................ 12

Application and Implementation ........................ 13

8.1 Application Information............................................ 13

8.2 Typical Application .................................................. 13

Power Supply Recommendations...................... 19

10 Layout................................................................... 19

10.1 Layout Guidelines ................................................. 19

10.2 Layout Example .................................................... 21

10.3 Power Dissipation and Board Thermal

Requirements........................................................... 22

11 Device and Documentation Support ................. 23

11.1 Device Support...................................................... 23

11.2 Documentation Support ........................................ 23

11.3 Community Resources.......................................... 23

11.4 Trademarks........................................................... 23

11.5 Electrostatic Discharge Caution............................ 23

11.6 Glossary................................................................ 23

12 Mechanical, Packaging, and Orderable

Information ........................................................... 23

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision H (August 2015) to Revision I

Page

•

Added this new bullet in the Power Module SMT Guidelines section .................................................................................. 19

Changes from Revision G (May 2015) to Revision H

Page

•

Changed the title of the document ......................................................................................................................................... 1

Changes from Revision F (October 2013) to Revision G

Page

•

Added Pin Configuration and Functions section, ESD Rating table, Feature Description section, Device Functional

Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device

and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1

Removed Easy-to-Use Pin Package image .......................................................................................................................... 1

Removed Evaluation Board Schematic Diagram and BOM section..................................................................................... 22

•

Changes from Revision E (March 2013) to Revision F

Page

•

Added Peak Reflow Case Temp = 245°C ............................................................................................................................. 1

Deleted 10 mils ...................................................................................................................................................................... 5

Changed 10 mils................................................................................................................................................................... 19

Added Power Module SMT Guidelines section.................................................................................................................... 19

Changed 10 mils................................................................................................................................................................... 22

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5 Pin Configuration and Functions

NDW Package

7-Pin TO-PMOD

Top View

VOUT

GND

RON

VIN

Exposed Pad

Connect to GND

Pin Functions

TYPE

DESCRIPTION

NO.

NAME

VIN

Power

Supply input — Nominal operating range is 6 V to 42 V . A small amount of internal

capacitance is contained within the package assembly. Additional external input

capacitance is required between this pin and exposed pad.

RON

Analog

On Time Resistor — An external resistor from V_INto this pin sets the ON-time of the

application. Typical values range from 25 kΩ to 124 kΩ.

Enable — Input to the precision enable comparator. Rising threshold is 1.18 V nominal;

90 mV hysteresis nominal. Maximum recommended input level is 6.5 V.

GND

Ground

Analog

Ground — Reference point for all stated voltages. Must be externally connected to EP.

Soft-Start — An internal 8-µA current source charges an external capacitor to produce

the soft-start function. This node is discharged at 200 µA during disable, overcurrent,

thermal shutdown and internal UVLO conditions.

Analog

Feedback — Internally connected to the regulation, overvoltage, and short-circuit

comparators. The regulation reference point is 0.8 V at this input pin. Connected the

feedback resistor divider between the output and ground to set the output voltage.

VOUT

Power

Output Voltage — Output from the internal inductor. Connect the output capacitor

between this pin and exposed pad.

—

Ground

Exposed Pad — Internally connected to pin 4. Used to dissipate heat from the package

during operation. Must be electrically connected to pin 4 external to the package.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)^(1)(2)(3)

MIN

–0.3

MAX

43.5

UNIT

VIN, RON to GND

EN, FB, SS to GND

Junction Temperature

Storage Temperature

150

°C

–65

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and

specifications.

(3) For soldering specifications, see product folder at www.ti.com and SNOA549.

6.2 ESD Ratings

VALUE

UNIT

V_(ESD)

Electrostatic discharge

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

±2000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

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6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

MAX

UNIT

V_IN

6.5

Operation Junction Temperature

−40

125

°C

(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Recommended Operating Ratings are conditions

under which operation of the device is intended to be functional. For ensured specifications and test conditions, see the Electrical

Characteristics.

6.4 Thermal Information

LMZ14201

THERMAL METRIC⁽¹⁾

NDW (TO-PMOD)

UNIT

7 PINS

19.3

21.5

1.9

4 layer JEDEC Printed Circuit Board, 100 vias, No air flow

2 layer JEDEC Printed Circuit Board, No air flow

Junction-to-ambient

thermal resistance

R_θJA

°C/W

R_θJC(top)

Junction-to-case (top) thermal resistance

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

6.5 Electrical Characteristics

Limits are for T_J= 25°C only unless otherwise noted. Minimum and Maximum limits are ensured through test, design or

statistical correlation. Typical values represent the most likely parametric norm at T_J= 25°C, and are provided for reference

purposes only. Unless otherwise stated the following conditions apply: V_IN= 24 V, Vout = 3.3 V

PARAMETER

SYSTEM PARAMETERS

ENABLE CONTROL⁽³⁾

TEST CONDITIONS

MIN⁽¹⁾

TYP⁽²⁾

MAX⁽¹⁾UNIT

V_EN

EN threshold trip point

V_ENrising

1.18

over the junction temperature

(T_J) range of –40°C to +125°C

1.10

1.25

V_EN-HYS

SOFT-START

I_SS

EN threshold hysteresis

V_ENfalling

V_SS= 0 V

SS source current

µA

over the junction temperature

(T_J) range of –40°C to +125°C

I_SS-DIS

SS discharge current

-200

1.95

µA

CURRENT LIMIT

I_CL

Current limit threshold

DC average

over the junction temperature

(T_J) range of –40°C to +125°C

1.4

ON/OFF TIMER

t_ON-MIN

ON timer minimum pulse

width

150

260

t_OFF

OFF timer pulse width

(1) Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlation

using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).

(2) Typical numbers are at 25°C and represent the most likely parametric norm.

(3) EN 55022:2006, +A1:2007, FCC Part 15 Subpart B: 2007. See AN-2024 and layout for information on device under test.

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Electrical Characteristics (continued)

Limits are for T_J= 25°C only unless otherwise noted. Minimum and Maximum limits are ensured through test, design or

statistical correlation. Typical values represent the most likely parametric norm at T_J= 25°C, and are provided for reference

purposes only. Unless otherwise stated the following conditions apply: V_IN= 24 V, Vout = 3.3 V

PARAMETER

TEST CONDITIONS

MIN⁽¹⁾

TYP⁽²⁾

MAX⁽¹⁾UNIT

REGULATION AND OVERVOLTAGE COMPARATOR

V_FB

In-regulation feedback

voltage

V_SS>+ 0.8 V

T_J= -40°C to

125°C

0.798

over the junction temperature

(T_J) range of –40°C to +125°C

.777

0.818

I_O= 1 A

V_SS> +0.8 V

T_J= 25°C

0.786

0.802

0.818

I_O= 10 mA

V_FB-OV

I_FB

Feedback overvoltage

protection threshold

0.92

Feedback input bias

current

μA

I_Q

Non Switching Input

Current

V_FB= 0.86 V

V_EN= 0 V

I_SD

Shut Down Quiescent

Current

THERMAL CHARACTERISTICS

T_SD

Thermal Shutdown

Rising

Falling

165

°C

T_SD-HYST

Thermal shutdown

hysteresis

PERFORMANCE PARAMETERS

ΔV_O

Output Voltage Ripple

Line Regulation

Load Regulation

Efficiency

.01%

1.5

ΔV_O/ΔV_IN

ΔV_O/I_OUT

V_IN= 12 V to 42 V, I_O= 1 A

V_IN= 24 V

mV/A

V_IN= 24 V V_O= 3.3 V I_O= 1 A

92%

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6.6 Typical Characteristics

Unless otherwise specified, the following conditions apply: V_IN= 24 V; C_IN= 10 uF X7R Ceramic; C_O= 100 uF X7R Ceramic;

T_A= 25 C for efficiency curves and waveforms.

100

0.3

0.25

0.2

3.3

2.5

3.3

2.5

1.8

1.5

1.2

1.8

1.5

0.8

1.2

0.8

0.15

0.1

25°C

0.05

25°C

0.2

0.4

0.6

0.8

0.6

OUTPUT CURRENT (A)

0.2

0.4

0.8

OUTPUT CURRENT (A)

Figure 1. Efficiency 6-V Input at 25°C

Figure 2. Dissipation 6-V Input at 25°C

100

0.45

6.0

5.0

6.0

5.0

3.3

2.5

1.8

1.5

1.2

0.375

3.3

2.5

0.3

1.8

1.5

0.8

0.225

1.2

0.8

0.15

25°C

0.075

25°C

0.6

0.2

0.4

0.8

0.2

0.4

0.6

0.8

OUTPUT CURRENT (A)

Figure 4. Dissipation 12-V Input at 25°C

Figure 3. Efficiency 12-V Input at 25°C

0.7

100

0.6

0.5

0.4

0.3

6.0

5.0

3.3

2.5

1.8

0.2

0.1

25°C

0.6

OUTPUT CURRENT (A)

0.2

0.4

0.8

0.2

0.4

0.6

0.8

OUTPUT CURRENT (A)

Figure 6. Dissipation 24-V Input at 25°C

Figure 5. Efficiency 24-V Input at 25°C

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Typical Characteristics (continued)

Unless otherwise specified, the following conditions apply: V_IN= 24 V; C_IN= 10 uF X7R Ceramic; C_O= 100 uF X7R Ceramic;

T_A= 25 C for efficiency curves and waveforms.

100

1.2

1.0

0.8

0.6

0.4

0.2

6.0

5.0

6.0

5.0

3.3

25°C

0.2

25°C

0.6

OUTPUT CURRENT (A)

0.4

0.6

0.8

0.2

0.4

0.8

OUTPUT CURRENT (A)

Figure 7. Efficiency 36-V Input at 25°C

Figure 8. Dissipation 36-V Input at 25°C

100

1.2

1.0

0.8

0.6

0.4

0.2

6.0

5.0

6.0

5.0

3.3

25°C

0.2

25°C

0.6

OUTPUT CURRENT (A)

0.4

0.6

0.8

0.2

0.4

0.8

OUTPUT CURRENT (A)

Figure 9. Efficiency 42-V Input at 25°C

Figure 10. Dissipation 42-V Input at 25°C

0.45

100

0.375

0.3

3.3

2.5

1.8

1.5

3.3

2.5

1.8

1.5

1.2

0.225

0.15

0.075

1.2

85°C

0.2

0.4

0.6

0.8

0.6

OUTPUT CURRENT (A)

0.2

0.4

0.8

OUTPUT CURRENT (A)

Figure 11. Efficiency 6-V Input at 85°C

Figure 12. Dissipation 6-V Input at 85°C

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Typical Characteristics (continued)

Unless otherwise specified, the following conditions apply: V_IN= 24 V; C_IN= 10 uF X7R Ceramic; C_O= 100 uF X7R Ceramic;

T_A= 25 C for efficiency curves and waveforms.

100

0.45

0.375

0.3

5.0

3.3

2.5

1.8

1.5

5.0

3.3

2.5

1.8

1.5

1.2

0.225

0.15

0.075

1.2

85°C

0.2

0.4

0.6

0.8

0.6

0.2

0.4

0.8

OUTPUT CURRENT (A)

Figure 13. Efficiency 8-V Input at 85°C

Figure 14. Dissipation 8-V Input at 85°C

100

0.6

6.0

0.5

0.4

0.3

0.2

0.1

6.0

5.0

3.3

2.5

3.3

2.5

1.8

1.5

1.2

1.8

1.5

1.2

85°C

0.2

0.6

OUTPUT CURRENT (A)

0.4

0.8

0.2

0.4

0.6

0.8

OUTPUT CURRENT (A)

Figure 15. Efficiency 12-V Input at 85°C

Figure 16. Dissipation 12-V Input at 85°C

100

1.2

1.0

6.0

5.0

3.3

2.5

0.8

6.0

5.0

1.8

0.6

0.4

3.3

2.5

0.2

1.8

85°C

0.2

OUTPUT CURRENT (A)

85°C

0.4

0.6

0.8

0.6

0.2

0.4

0.8

OUTPUT CURRENT (A)

Figure 17. Efficiency 24-V Input at 85°C

Figure 18. Dissipation 24-V Input at 85°C

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Typical Characteristics (continued)

Unless otherwise specified, the following conditions apply: V_IN= 24 V; C_IN= 10 uF X7R Ceramic; C_O= 100 uF X7R Ceramic;

T_A= 25 C for efficiency curves and waveforms.

100

1.2

1.0

0.8

0.6

0.4

0.2

6.0

5.0

6.0

5.0

3.3

85°C

0.2

OUTPUT CURRENT (A)

0.6

OUTPUT CURRENT (A)

0.2

0.4

0.8

0.4

0.6

0.8

Figure 20. Dissipation 36-V Input at 85°C

Figure 19. Efficiency 36-V Input at 85°C

1.2

100

6.0

5.0

1.0

0.8

6.0

5.0

3.3

0.6

3.3

0.4

0.2

85°C

0.6

OUTPUT CURRENT (A)

0.2

0.4

0.8

0.2

0.4

0.6

0.8

OUTPUT CURRENT (A)

Figure 22. Dissipation 42-V Input at 85°C

Figure 21. Efficiency 42-V Input at 85°C

3.34

3.36

3.34

3.32

3.30

12 20

3.30

3.28

3.26

3.28

3.26

3.24

85°C

25°C

0.2

0.4

0.6

0.8

1.0

0.8

OUTPUT CURRENT (A)

1.0

0.4

0.6

0.2

OUTPUT CURRENT (A)

Figure 24. Line and Load Regulation at 85°C

Figure 23. Line and Load Regulation at 25°C

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Typical Characteristics (continued)

Unless otherwise specified, the following conditions apply: V_IN= 24 V; C_IN= 10 uF X7R Ceramic; C_O= 100 uF X7R Ceramic;

T_A= 25 C for efficiency curves and waveforms.

0.5 A/Div

20 mV/Div

200 Ps/Div

Figure 25. Output Ripple

24V_IN3.3 V_O1 A, BW = 200 MHz

Figure 26. Transient Response

24V_IN3.3 V_O0.5-A to 1-A Step

1.2

2.4

2.3

2.2

2.1

2.0

1.9

1.8

0.8

0.6

0.4

0.2

SHORT CIRCUIT

12V

ONSET

ÆJA = 19°C/W

24V

25°C

VOUT = 3.3V

36V

70 80

100 110 120

AMBIENT TEMPERATURE (C)

INPUT VOLTAGE (V)

Figure 27. Thermal Derating V_OUT= 3.3 V

Figure 28. Current Limit 1.8 V_OUTat 25°C

2.4

2.5

2.3

2.4

SHORT CIRCUIT

2.3

2.2

2.1

2.2

ONSET

2.0

2.1

ONSET

1.9

2.0

25°C

1.8

85°C

1.9

INPUT VOLTAGE (V)

Figure 29. Current Limit 3.3 V_OUTat 25°C

Figure 30. Current Limit 3.3 V_OUTat 85°C

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7 Detailed Description

7.1 Overview

7.1.1 COT Control Circuit Overview

Constant On Time control is based on a comparator and an ON-time one-shot, with the output voltage feedback

compared with an internal 0.8-V reference. If the feedback voltage is below the reference, the main MOSFET is

turned on for a fixed ON-time determined by a programming resistor R_ON. R_ONis connected to V_INsuch that ON-

time is reduced with increasing input supply voltage. Following this ON-time, the main MOSFET remains off for a

minimum of 260 ns. If the voltage on the feedback pin falls below the reference level again the ON-time cycle is

repeated. Regulation is achieved in this manner.

7.2 Functional Block Diagram

Vin

VIN

Linear reg

Cvcc

Css

0.47 PF

VOUT

RON

Timer

10 PH

FBT

Internal

Passives

Regulator IC

FBB

GND

7.3 Feature Description

7.3.1 Output Overvoltage Comparator

The voltage at FB is compared to a 0.92-V internal reference. If FB rises above 0.92-V the ON-time is

immediately terminated. This condition is known as overvoltage protection (OVP). It can occur if the input voltage

is increased very suddenly or if the output load is decreased very suddenly. Once OVP is activated, the top

MOSFET ON-times will be inhibited until the condition clears. Additionally, the synchronous MOSFET will remain

on until inductor current falls to zero.

7.3.2 Current Limit

Current limit detection is carried out during the OFF-time by monitoring the current in the synchronous MOSFET.

Referring to the Functional Block Diagram, when the top MOSFET is turned off, the inductor current flows

through the load, the PGND pin and the internal synchronous MOSFET. If this current exceeds 2.0 A (typical) the

current limit comparator disables the start of the next ON-time period. The next switching cycle will occur only if

the FB input is less than 0.8V and the inductor current has decreased below 2.0 A. Inductor current is monitored

during the period of time the synchronous MOSFET is conducting. So long as inductor current exceeds 2.0 A,

further ON-time intervals for the top MOSFET will not occur. Switching frequency is lower during current limit due

to the longer OFF-time.

NOTE

Current limit is dependent on both duty cycle and temperature as illustrated in the graphs

in the Typical Characteristics section.

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Feature Description (continued)

7.3.3 Thermal Protection

The junction temperature of the LMZ14201 should not be allowed to exceed its maximum ratings. Thermal

protection is implemented by an internal Thermal Shutdown circuit which activates at 165 °C (typical) causing the

device to enter a low power standby state. In this state the main MOSFET remains off causing V_Oto fall, and

additionally the CSS capacitor is discharged to ground. Thermal protection helps prevent catastrophic failures for

accidental device overheating. When the junction temperature falls back below 145 °C (typical Hyst = 20 °C) the

SS pin is released, V_Orises smoothly, and normal operation resumes.

Applications requiring maximum output current especially those at high input voltage may require application

derating at elevated temperatures.

7.3.4 Zero Coil Current Detection

The current of the lower (synchronous) MOSFET is monitored by a zero coil current detection circuit which

inhibits the synchronous MOSFET when its current reaches zero until the next ON-time. This circuit enables the

DCM operating mode, which improves efficiency at light loads.

7.3.5 Prebiased Start-Up

The LMZ14201 will properly start up into a prebiased output. This startup situation is common in multiple rail

logic applications where current paths may exist between different power rails during the startup sequence. The

following scope capture shows proper behavior during this event.

OUTPUT

VOLTAGE

3.3V OUTPUT

1.0 V/Div

2V PRE-BIAS

0.5 A/Div

OUTPUT

CURRENT

2.0 V/Div

1 ms/Div

ENABLE

Figure 31. Prebiased Start-Up

7.4 Device Functional Modes

7.4.1 Discontinuous Conduction and Continuous Conduction Modes

At light-load, the regulator operates in discontinuous conduction mode (DCM). With load currents above the

critical conduction point, it operates in continuous conduction mode (CCM). When operating in DCM the

switching cycle begins at zero amps inductor current; increases up to a peak value, and then recedes back to

zero before the end of the OFF-time. During the period of time that inductor current is zero, all load current is

supplied by the output capacitor. The next ON-time period starts when the voltage on the FB pin falls below the

internal reference. The switching frequency is lower in DCM and varies more with load current as compared to

CCM. Conversion efficiency in DCM is maintained because conduction and switching losses are reduced with

the smaller load and lower switching frequency.

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8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The LMZ14201 is a step-down DC-to-DC power module. It is typically used to convert a higher DC voltage to a

lower DC voltage with a maximum output current of 1 A. The following design procedure can be used to select

components for the LMZ14201. Alternately, the WEBENCH software may be used to generate complete designs.

When generating a design, the WEBENCH software uses iterative design procedure and accesses

comprehensive databases of components. For more details, go to www.ti.com.

8.2 Typical Application

Enable

LMZ14201TZ-ADJ

3.3V @ 1A

6.0V to 42V

ENT

0.022 PF

FBT

3.32k

68.1k

61.9k

C 2

FBB

ENB

1 PF

100 PF

0.022 PF

1.07k

10 PF

1 PF

11.8k

OPT

Figure 32. Evaluation Board Schematic Diagram

Table 1. Schematic Bill of Materials

V_OUT

5 V

R_FBT

5.62 K

3.32 K

2.26 K

1.87 K

1 K

R_FBB

1.07 K

1.50 K

1.13 K

8.45 K

39.2

R_ON

V_INRANGE

7.7...42 V

6...42 V

6...30 V

6...25 V

6...21 V

6...19 V

6...18 V

100 K

61.9 K

47.5 K

32.4 K

28 K

3.3 V

2.5 V

1.8 V

1.5 V

1.2 V

0.8 V

4.22 K

22.6 K

24.9 K

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Table 2. Bill of Materials

REF DES

DESCRIPTION

SIMPLE SWITCHER ®

1 µF, 50V, X7R

10 µF, 50V, X7R

1 µF, 50V, X7R

100 µF, 6.3V, X7R

3.32 kΩ

CASE SIZE

PFM-7

1206

MANUFACTURER

Texas Instruments

Taiyo Yuden

Vishay Dale

TDK

MANUFACTURER P/N

LMZ14201TZ-ADJ

C_in1

UMK316B7105KL-T

UMK325BJ106MM-T

UMK316B7105KL-T

JMK325BJ107MM-T

CRCW06033K32FKEA

CRCW06031K07FKEA

CRCW060361k9FKEA

CRCW060368k1FKEA

CRCW060311k8FKEA

C1608X7R1H223K

Optional

C_in2

1210

C_O1

1206

C_O2

1210

R_FBT

R_FBB

R_ON

R_ENT

R_ENB

C_FF

0603

1.07 kΩ

0603

61.9 kΩ

0603

68.1 kΩ

0603

11.8 kΩ

0603

22 nF, ±10%, X7R, 16V

5.1V

0603

C_SS

0603

TDK

SOD-23

—

8.2.1 Design Requirements

For this example the following application parameters exist.

•

V_INRange = Up to 42 V

V_OUT= 0.8 V to 5 V

I_OUT= 1 A

Please refer to the table in Table 1 for more information.

8.2.2 Detailed Design Procedure

8.2.2.1 Design Steps for the LMZ14201 Application

The LMZ14201 is fully supported by WEBENCH and offers the following: Component selection, electrical and

thermal simulations as well as the build-it board for a reduction in design time. The following list of steps can be

used to manually design the LMZ14201 application.

1. Select minimum operating V_INwith enable divider resistors

2. Program V_Owith divider resistor selection

3. Program turnon time with soft-start capacitor selection

4. Select C_O

5. Select C_IN

6. Set operating frequency with R_ON

7. Determine module dissipation

8. Lay out PCB for required thermal performance

8.2.2.1.1 Enable Divider, R_ENTand R_ENBSelection

The enable input provides a precise 1.18-V band-gap rising threshold to allow direct logic drive or connection to

a voltage divider from a higher enable voltage such as V_IN. The enable input also incorporates 90 mV (typical) of

hysteresis resulting in a falling threshold of 1.09 V. The maximum recommended voltage into the EN pin is 6.5 V.

For applications where the midpoint of the enable divider exceeds 6.5 V, a small Zener diode can be added to

limit this voltage.

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The function of this resistive divider is to allow the designer to choose an input voltage below which the circuit

will be disabled. This implements the feature of programmable under voltage lockout. This is often used in

battery powered systems to prevent deep discharge of the system battery. It is also useful in system designs for

sequencing of output rails or to prevent early turnon of the supply as the main input voltage rail rises at power-

up. Applying the enable divider to the main input rail is often done in the case of higher input voltage systems

such as 24V AC/DC systems where a lower boundary of operation should be established. In the case of

sequencing supplies, the divider is connected to a rail that becomes active earlier in the power-up cycle than the

LMZ14201 output rail. The two resistors should be chosen based on the following ratio:

R_ENT/ R_ENB= (V_{IN UVLO}/ 1.18 V) – 1

(1)

The LMZ14201 demonstration and evaluation boards use 11.8 kΩ for R_ENBand 68.1 kΩ for R_ENTresulting in a

rising UVLO of 8 V. This divider presents 6.25 V to the EN input when the divider input is raised to 42 V.

The EN pin is internally pulled up to VIN and can be left floating for always-on operation.

8.2.2.1.2 Output Voltage Selection

Output voltage is determined by a divider of two resistors connected between V_Oand ground. The midpoint of

the divider is connected to the FB input. The voltage at FB is compared to a 0.8-V internal reference. In normal

operation an ON-time cycle is initiated when the voltage on the FB pin falls below 0.8 V. The main MOSFET ON-

time cycle causes the output voltage to rise and the voltage at the FB to exceed 0.8 V. As long as the voltage at

FB is above 0.8 V, ON-time cycles will not occur.

The regulated output voltage determined by the external divider resistors RFBT and RFBB is:

V_O= 0.8V × (1 + R_FBT/ R_FBB

)

(2)

(3)

Rearranging terms; the ratio of the feedback resistors for a desired output voltage is:

R_FBT/ R_FBB= (V_O/ 0.8V) - 1

These resistors should be chosen from values in the range of 1.0 kΩ to 10.0 kΩ.

For V_O= 0.8 V the FB pin can be connected to the output directly so long as an output preload resistor remains

that draws more than 20 µA. Converter operation requires this minimum load to create a small inductor ripple

current and maintain proper regulation when no load is present.

A feed-forward capacitor is placed in parallel with R_FBTto improve load step transient response. Its value is

usually determined experimentally by load stepping between DCM and CCM conduction modes and adjusting for

best transient response and minimum output ripple.

A table of values for R_FBT, R_FBB, C_FF, and R_ONis included in the applications schematic.

8.2.2.1.3 Soft-Start Capacitor Selection

Programmable soft-start permits the regulator to slowly ramp to its steady state operating point after being

enabled, thereby reducing current inrush from the input supply and slowing the output voltage rise-time to

prevent overshoot.

Upon turnon, after all UVLO conditions have been passed, an internal 8-µA current source begins charging the

external soft-start capacitor. The soft-start time duration to reach steady-state operation is given by the formula:

t_SS= V_REF× C_SS/ Iss = 0.8V × C_SS/ 8 µA

(4)

This equation can be rearranged as follows:

C_SS= t_SS× 8 μA / 0.8 V

(5)

Use of a 0.022-μF results in 2.2 ms soft-start interval which is recommended as a minimum value.

As the soft-start input exceeds 0.8 V the output of the power stage will be in regulation. The soft-start capacitor

continues charging until it reaches approximately 3.8V on the SS pin. Voltage levels between 0.8 V and 3.8 V

have no effect on other circuit operation. Note the following conditions will reset the soft-start capacitor by

discharging the SS input to ground with an internal 200-μA current sink.

•

The enable input being “pulled low”

Thermal shutdown condition

Overcurrent fault

Internal V_CCUVLO (Approximately 4 V input to V_IN)

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8.2.2.1.4 C_OSelection

None of the required C_Ooutput capacitance is contained within the module. At a minimum, the output capacitor

must meet the worst-case minimum ripple current rating of 0.5 × I_{LR P-P}, as calculated in Equation 20 below.

Beyond that, additional capacitance will reduce output ripple so long as the ESR is low enough to permit it. A

minimum value of 10 μF is generally required. Experimentation will be required if attempting to operate with a

minimum value. Ceramic capacitors or other low ESR types are recommended. See AN-2024 for more detail.

Equation 6 provides a good first pass approximation of C_Ofor load transient requirements:

C_O≥I_STEP*V_FB× L × V_IN/ (4 × V_O× (V_IN– V_O) × V_OUT-TRAN

)

(6)

Solving:

C_O≥ 1 A × 0.8 V × 10 μH × 24 V / (4 × 3.3 V × ( 24 V – 3.3 V) × 33 mV) ≥ 21.3 μF

(7)

The LMZ14201 demonstration and evaluation boards are populated with a 100-uF 6.3-V X5R output capacitor.

Locations for other output capacitors are provided.

8.2.2.1.5 C_INSelection

The LMZ14201 module contains an internal 0.47 µF input ceramic capacitor. Additional input capacitance is

required external to the module to handle the input ripple current of the application. This input capacitance should

be very close to the module. Input capacitor selection is generally directed to satisfy the input ripple current

requirements rather than by capacitance value. Worst-case input ripple current rating is dictated by Equation 8:

I(C_IN(RMS)) ≊ 1 / 2 × I_O× √ (D / 1-D)

where

•

D ≊ V_O/ V_IN

(8)

(As a point of reference, the worst-case ripple current will occur when the module is presented with full load

current and when V_IN= 2 × V_O).

Recommended minimum input capacitance is 10-uF X7R ceramic with a voltage rating at least 25% higher than

the maximum applied input voltage for the application. It is also recommended that attention be paid to the

voltage and temperature deratings of the capacitor selected. It should be noted that ripple current rating of

ceramic capacitors may be missing from the capacitor data sheet and you may need to contact the capacitor

manufacturer for this rating.

If the system design requires a certain minimum value of input ripple voltage ΔV_INbe maintained then Equation 9

may be used.

C_IN≥ I_O× D × (1–D) / f_SW-CCM× ΔV_IN

(9)

If ΔV_INis 1% of V_INfor a 24-V input to 3.3-V output application this equals 240 mV and f_SW= 400 kHz.

C_IN≥ 1 A × 3.3 V / 24 V × (1– 3.3 V/24 V) / (400000 × 0.240 V)

≥ 0.9 μF

Additional bulk capacitance with higher ESR may be required to damp any resonant effects of the input

capacitance and parasitic inductance of the incoming supply lines.

8.2.2.1.6 R_ONResistor Selection

Many designs will begin with a desired switching frequency in mind. For that purpose Equation 10 can be used.

_SW(CCM)≊ V_O/ (1.3 × 10^-10× R_ON

)

(10)

This can be rearranged as

_ON≊ V_O/ (1.3 × 10 ^-10× f_SW(CCM)

)

(11)

The selection of RON and f_SW(CCM)must be confined by limitations in the ON-time and OFF-time for the COT

Control Circuit Overview section.

The ON-time of the LMZ14201 timer is determined by the resistor R_ONand the input voltage V_IN. It is calculated

as follows:

t_ON= (1.3 × 10^-10× R_ON) / V_IN

(12)

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The inverse relationship of t_ONand V_INgives a nearly constant switching frequency as V_INis varied. R_ONshould

be selected such that the ON-time at maximum V_INis greater than 150 ns. The ON-timer has a limiter to ensure

a minimum of 150 ns for t_ON. This limits the maximum operating frequency, which is governed by Equation 13:

f_SW(MAX)= V_O/ (V_IN(MAX)× 150 ns)

(13)

This equation can be used to select R_ONif a certain operating frequency is desired so long as the minimum ON-

time of 150 ns is observed. The limit for R_ONcan be calculated as follows:

_ON≥ V_IN(MAX)× 150 nsec / (1.3 × 10 ^-10

)

(14)

If R_ONcalculated in Equation 11 is less than the minimum value determined in Equation 14 a lower frequency

should be selected. Alternatively, V_IN(MAX)can also be limited to keep the frequency unchanged.

NOTE

The minimum OFF-time of 260 ns limits the maximum duty ratio. Larger R_ON(lower F_SW

)

should be selected in any application requiring large duty ratio.

8.2.2.1.6.1 Discontinuous Conduction and Continuous Conduction Mode Selection

Operating frequency in DCM can be calculated as follows:

_SW(DCM)≊ V_O× (V_IN-1) × 10 μH × 1.18 × 10²⁰× I_O/(V_IN–V_O) × R_ON

(15)

In CCM, current flows through the inductor through the entire switching cycle and never falls to zero during the

OFF-time. The switching frequency remains relatively constant with load current and line voltage variations. The

CCM operating frequency can be calculated using Equation 7 above.

Figure 33 shows a comparison pair of waveforms of the showing both CCM (upper) and DCM operating modes.

The approximate formula for determining the DCM/CCM boundary is as follows:

I_DCB≊ V_O× (V_IN–V_O) / (2 × 10 μH × f_SW(CCM)× V_IN)

(16)

Figure 34 shows a typical waveform showing the boundary condition.

500 mA/Div

2.00 Ps/Div

500 mA/Div

2.00 Ps/Div

Figure 34. Transition Mode Operation

V_IN= 24 V, V_O= 3.3 V, I_O= 0.29 A

Figure 33. CCM and DCM Operating Modes

V_IN= 12 V, V_O= 3.3 V, I_O= 1 A / 0.25 A

The inductor internal to the module is 10 μH. This value was chosen as a good balance between low and high

input voltage applications. The main parameter affected by the inductor is the amplitude of the inductor ripple

current (I_LR). I_LRcan be calculated with:

I_{LR P-P}= V_O× (V_IN– V_O) / (10 µH × f_SW× V_IN)

where

•

V_INis the maximum input voltage and f_SWis determined from Equation 10.

(17)

If the output current I_Ois determined by assuming that I_O= I_L, the higher and lower peak of I_LRcan be

determined. Be aware that the lower peak of I_LRmust be positive if CCM operation is required.

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8.2.3 Application Curves

100

1.2

0.8

0.6

0.4

0.2

0.4

0.6

0.8

0.2

50 60

70 80

90 100 110 120

OUTPUT CURRENT (A)

AMBIENT TEMPERATURE (°C)

Figure 35. Efficiency V_IN= 24 V V_OUT= 5.0 V

Figure 36. Thermal Derating Curve

V_IN= 24 V, V_OUT= 5.0 V

80.0

70.0

60.0

50.0

40.0

EN 55022 CLASS B LIMIT

30.0

20.0

10.0

0.0

1000

200

400

600

FREQUENCY (MHz)

800

Figure 37. Radiated Emissions (EN 55022 Class B)

from Evaluation Board

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9 Power Supply Recommendations

The LMZ14201 device is designed to operate from an input voltage supply range between 4.5 V and 42 V. This

input supply should be well regulated and able to withstand maximum input current and maintain a stable

voltage. The resistance of the input supply rail should be low enough that an input current transient does not

cause a high enough drop at the LMZ14201 supply voltage that can cause a false UVLO fault triggering and

system reset. If the input supply is more than a few inches from the LMZ14201, additional bulk capacitance may

be required in addition to the ceramic bypass capacitors. The amount of bulk capacitance is not critical, but a 47-

μF or 100-μF electrolytic capacitor is a typical choice.

10 Layout

10.1 Layout Guidelines

PCB layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance of a

DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce and resistive voltage drop in

the traces. These can send erroneous signals to the DC-DC converter resulting in poor regulation or instability.

Good layout can be implemented by following a few simple design rules.

1. Minimize area of switched current loops.From an EMI reduction standpoint, it is imperative to minimize

the high di/dt paths during PCB layout. The high current loops that do not overlap have high di/dt content that

will cause observable high-frequency noise on the output pin if the input capacitor (Cin1) is placed at a

distance away from the LMZ14201. Therefore place C_IN1as close as possible to the LMZ14201 VIN and

GND exposed pad. This will minimize the high di/dt area and reduce radiated EMI. Additionally, grounding for

both the input and output capacitor should consist of a localized top side plane that connects to the GND

exposed pad (EP).

2. Have a single point ground.The ground connections for the feedback, soft-start, and enable components

should be routed to the GND pin of the device. This prevents any switched or load currents from flowing in

the analog ground traces. If not properly handled, poor grounding can result in degraded load regulation or

erratic output voltage ripple behavior. Provide the single point ground connection from pin 4 to EP.

3. Minimize trace length to the FB pin.Both feedback resistors, R_FBTand R_FBB, and the feed forward

capacitor C_FF, should be close to the FB pin. Because the FB node is high impedance, maintain the copper

area as small as possible. The trace are from R_FBT, R_FBB, and C_FFshould be routed away from the body of

the LMZ14201 to minimize noise.

4. Make input and output bus connections as wide as possible.This reduces any voltage drops on the input

or output of the converter and maximizes efficiency. To optimize voltage accuracy at the load, ensure that a

separate feedback voltage sense trace is made to the load. Doing so will correct for voltage drops and

provide optimum output accuracy.

5. Provide adequate device heat-sinking.Use an array of heat-sinking vias to connect the exposed pad to the

ground plane on the bottom PCB layer. If the PCB has a plurality of copper layers, these thermal vias can

also be employed to make connection to inner layer heat-spreading ground planes. For best results use a 6

× 6 via array with minimum via diameter of 8 mils thermal vias spaced 59 mils (1.5 mm). Ensure enough

copper area is used for heat-sinking to keep the junction temperature below 125°C.

10.1.1 Power Module SMT Guidelines

The recommendations below are for a standard module surface mount assembly

•

Land Pattern – Follow the PCB land pattern with either soldermask defined or non-soldermask defined pads

Stencil Aperture

–

For the exposed die attach pad (DAP), adjust the stencil for approximately 80% coverage of the PCB land

pattern

–

For all other I/O pads use a 1:1 ratio between the aperture and the land pattern recommendation

•

Solder Paste – Use a standard SAC Alloy such as SAC 305, type 3 or higher

Stencil Thickness – 0.125 to 0.15 mm

Reflow - Refer to solder paste supplier recommendation and optimized per board size and density

Refer to AN SNAA214 for Reflow information

Maximum number of reflows allowed is one

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Layout Guidelines (continued)

Figure 38. Sample Reflow Profile

Table 3. Sample Reflow Profile Table

MAX TEMP

(°C)

REACHED TIME ABOVE REACHED TIME ABOVE REACHED TIME ABOVE REACHED

PROBE

MAX TEMP

235°C

245°C

260°C

242.5

241.0

6.58

0.49

6.39

0.00

–

7.10

–

0.00

–

7.10

0.55

6.31

0.00

7.09

0.42

6.44

0.00

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10.2 Layout Example

LMZ14201

VOUT

VIN

High

di/dt

in1

GND

Loop 2

Loop 1

Figure 39. Minimize Area of Current Loops in Buck Module

Top View

Thermal Vias

GND

EPAD

C_IN

C_OUT

VOUT

VIN

R_ON

R_FBT

R_ENT

R_ENB

C_FF

C_SS

R_FBB

GND Plane

Figure 40. PCB Layout Guide

Figure 41. EVM Board Layout - Top View

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Layout Example (continued)

Figure 42. EVM Board Layout - Bottom View

10.3 Power Dissipation and Board Thermal Requirements

For the design case of V_IN= 24 V, V_O= 3.3 V, I_O= 1A, T_AMB(MAX)= 85°C , and T_JUNCTION= 125°C, the device

must see a thermal resistance from case to ambient of less than:

R_θCA< (T_J-MAX– T_AMB(MAX)) / P_IC-LOSS– R_θJC

(18)

Given the typical thermal resistance from junction to case to be 1.9 °C/W. Use the 85°C power dissipation curves

in the Typical Performance Characteristics section to estimate the P_IC-LOSSfor the application being designed. In

this application it is 0.52W.

R_θCA= (125 — 85) / 0.52 W — 1.9 = 75

(19)

To reach R_θCA= 75, the PCB is required to dissipate heat effectively. With no airflow and no external heat, a

good estimate of the required board area covered by 1 oz. copper on both the top and bottom metal layers is:

Board Area_cm²= 500°C x cm²/W / R_θJC

(20)

As a result, approximately 6 square cm of 1 oz copper on top and bottom layers is required for the PCB design.

Additional area will decrease die temperature proportionately. The PCB copper heat sink must be connected to

the exposed pad. Approximately thirty six, 8 mils thermal vias spaced 59 mils (1.5 mm) apart must connect the

top copper to the bottom copper. For an example of a high thermal performance PCB layout of approximately 31

square cm area. Refer to the Evaluation Board application note AN-2024 SNVA422. For more information on

thermal design see AN-2020 SNVA419 and AN-2026 SNVA424.

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11 Device and Documentation Support

11.1 Device Support

11.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT

CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES

OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER

ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

11.2 Documentation Support

11.2.1 Related Documentation

•

Design Summary LMZ1 and LMZ2 Power Modules, SNAA214

AN-2027 Inverting Application for the LMZ14203 SIMPLE SWITCHER Power Module, SNVA425

Evaluation Board Application Note AN-2024, SNVA422

AN-2020 Thermal Design By Insight, Not Hindsight, SNVA419

AN-2026 Effect of PCB Design on Thermal Performance of SIMPLE SWITCHER Power Modules, SNVA424

11.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

11.4 Trademarks

E2E is a trademark of Texas Instruments.

WEBENCH, SIMPLE SWITCHER are registered trademarks of Texas Instruments.

All other trademarks are the property of their respective owners.

11.5 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

11.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

-40 to 125

Device Marking

Samples

Drawing

Qty

(1)

(2)

(6)

(3)

(4/5)

LMZ14201TZ-ADJ/NOPB

LMZ14201TZE-ADJ/NOPB

LMZ14201TZX-ADJ/NOPB

ACTIVE

TO-PMOD

NDW

250

Green (RoHS

& no Sb/Br)

CU SN

Level-3-245C-168 HR

LMZ14201

TZ-ADJ

ACTIVE

NDW

Green (RoHS

& no Sb/Br)

-40 to 125

LMZ14201

TZ-ADJ

500

Green (RoHS

& no Sb/Br)

-40 to 125

LMZ14201

TZ-ADJ

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

⁽⁶⁾Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

3-Sep-2015

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

3-Sep-2015

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

LMZ14201TZ-ADJ/NOPB

TO-

PMOD

NDW

250

500

330.0

24.4

10.6 14.22

5.0

16.0

24.0

LMZ14201TZX-ADJ/NOP

TO-

PMOD

330.0

24.4

10.6 14.22

5.0

16.0

24.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

3-Sep-2015

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

LMZ14201TZ-ADJ/NOPB

LMZ14201TZX-ADJ/NOPB

TO-PMOD

NDW

250

500

367.0

45.0

Pack Materials-Page 2

MECHANICAL DATA

NDW0007A

BOTTOM SIDE OF PACKAGE

TOP SIDE OF PACKAGE

TZA07A (Rev D)

www.ti.com

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other

changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest

issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and

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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

LMZ14201_15 [TI]

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