LMZ21701 [TI]
采用 3.5mm × 3.5mm 封装的 3V 至 17V、1A 降压直流/直流电源模块;
| 型号： | LMZ21701 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用 3.5mm × 3.5mm 封装的 3V 至 17V、1A 降压直流/直流电源模块 电源电路 |
| 文件： | 总38页 (文件大小：1753K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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LMZ21701
ZHCSD26E –AUGUST 2012–REVISED AUGUST 2018
具有 17V 最大输入电压的 LMZ21701 1A 微型模块
1 特性
2 应用
1
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集成电感
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3.3V、5V 或 12V 输入电压的
负载点转换
微型 3.5mm × 3.5mm × 1.75mm 封装
35-mm² 解决方案尺寸（单侧）
结温范围为 -40°C 至 125°C
可调输出电压
•
•
空间受限型 应用
低压降稳压器 (LDO) 替代产品
3 说明
集成补偿
LMZ21701 微型模块是易于使用的降压直流/直流解决
方案，可在空间受限的应用中驱动高达 1000mA 的 负
载。仅需一个输入电容器、一个输出电容器、一个软启
动电容器和两个电阻器即可完成基本操作。
可调软启动功能
启动至预偏置负载
电源正常状态和使能引脚
节能模式无缝转换
器件信息(1)
高达 1000mA 的输出电流
输入电压范围为 3V 至 17V
输出电压范围为 0.9V 到 6V
效率高达 95 %
器件型号
LMZ21701
封装
µSIP (8)
封装尺寸（标称值）
3.50mm x 3.50mm
(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。
1.5µA 关断电流
空白
17µA 静态电流
使用 LMZ21701 并借助 WEBENCH® 电源设计器
创建定制设计
空白
空白
简化原理图
VIN = 12V 时的效率
VIN
VOUT
100
90
80
70
60
50
40
VIN
EN
VOUT
PG
LMZ21701
C
IN
C
OUT
VOS
SS
R
R
C
FBT
SS
GND
FB
FBB
30
20
10
VOUT = 1.2 V
VOUT = 1.8 V
VOUT = 2.5 V
VOUT = 3.3 V
VOUT = 5 V
0
0.0001
0.001
0.01
0.1
1
Output Current (A)
D023
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNVS853
LMZ21701
ZHCSD26E –AUGUST 2012–REVISED AUGUST 2018
www.ti.com.cn
目录
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 7
Detailed Description .............................................. 8
7.1 Overview ................................................................... 8
7.2 Functional Block Diagram ......................................... 9
7.3 Package Construction............................................... 9
7.4 Feature Description................................................. 11
7.5 Device Functional Modes........................................ 12
8
9
Application and Implementation ........................ 13
8.1 Application Information............................................ 13
8.2 Typical Application ................................................. 13
8.3 Do's and Don'ts ...................................................... 26
Power Supply Recommendations...................... 26
9.1 Voltage Range ........................................................ 26
9.2 Current Capability ................................................... 26
9.3 Input Connection .................................................... 26
10 Layout................................................................... 27
10.1 Layout Guidelines ................................................. 27
10.2 Layout Example .................................................... 28
11 器件和文档支持 ..................................................... 31
11.1 器件支持 ............................................................... 31
11.2 商标....................................................................... 31
11.3 静电放电警告......................................................... 31
11.4 术语表 ................................................................... 31
12 机械、封装和可订购信息....................................... 32
12.1 Tape and Reel Information ................................... 32
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision D (#IMPLIED) to Revision E
Page
•
•
已添加 添加了 Webench 链接和 TI 参考设计顶部导航图标；删除了Simple Switcher 品牌 ................................................... 1
Changed Handling Ratings to ESD Ratings .......................................................................................................................... 4
Changes from Revision C (October 2014) to Revision D
Page
•
•
已更改 将“产品概述”更改成了“生产数据” ................................................................................................................................ 1
Changed to Final Limits ......................................................................................................................................................... 5
Changes from Revision B (August 2014) to Revision C
Page
•
已添加 添加了“器件信息”表和“处理额定值”表、“特性 说明”、“应用和实施”、“布局”、“器件和文档支持”以及“机械、封
装和可订购信息”，将一些曲线移到了“应用曲线”中................................................................................................................. 1
Changes from Revision A (October 2013) to Revision B
Page
•
已将数据表更改为最新 TI 标准 ............................................................................................................................................... 1
Changes from Original (August 2012) to Revision A
Page
•
已更改 说明............................................................................................................................................................................. 1
2
Copyright © 2012–2018, Texas Instruments Incorporated
LMZ21701
www.ti.com.cn
ZHCSD26E –AUGUST 2012–REVISED AUGUST 2018
5 Pin Configuration and Functions
Figure 1. LMZ21701 in the SIL0008E Package
SIL Package
8-Pin µSIP
Top View
TOP
SS
FB
VIN
EN
1
2
3
4
8
7
6
5
PAD
(GND)
PAD
(GND)
PG
VOS
GND
VOUT
Pin Functions
PIN
I/O
DESCRIPTION
NAME
SS
NO.
1
Soft-start pin. An external capacitor connected to this pin sets the internal voltage reference
ramp time. It can be used for tracking and sequencing.
I
I
FB
2
Voltage feedback. Connect resistive voltage divider to this pin to set the output voltage.
Output power good (High = VOUT ready, Low = VOUT below nominal regulation); open drain
(requires pull-up resistor; goes low impedance when EN is low).
PG
3
O
Output Voltage. Connected to one terminal of the integrated inductor. Connect output filter
capacitor between VOUT and PGND.
VOUT
4
O
GND
VOS
5
6
I
I
Ground for the power MOSFETs and gate-drive circuitry.
Output voltage sense pin and connection for the control loop circuitry.
Enable input (High = enabled, Low = disabled). Internal pull down resistor keeps logic level
low if pin is left floating.
EN
7
8
I
I
VIN
PAD
Supply voltage for control circuitry and power stage.
Electrically connected to GND. Must be soldered to a ground copper plane to achieve
appropriate power dissipation and mechanical reliability.
Copyright © 2012–2018, Texas Instruments Incorporated
3
LMZ21701
ZHCSD26E –AUGUST 2012–REVISED AUGUST 2018
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN
MAX
UNIT
VIN
−0.3
20
V
VIN +0.3 V w/ 20 V
maximum
EN, SS
−0.3
−0.3
V
FB, PG, VOS
7
10
V
PG sink current
mA
°C
°C
°C
Junction temperature, TJ-MAX
Maximum lead temperature
Storage temperature, Tstg
−40
−65
125
260
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
17
UNIT
Input voltage
3
0.9
0
V
V
Output voltage
6
Recommended load current
Junction temperature, TJ
1000
125
mA
°C
−40
(1) Operating Ratings indicate conditions for which the device is intended to be functional, but do not ensure specific performance limits. For
ensured specifications, see the Electrical Characteristics section.
6.4 Thermal Information
LMZ21701
THERMAL METRIC(1)
SIL (µSIP)
8 PINS
42.6
UNIT
RθJA
Junction-to-ambient thermal resistance(2)
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
20.8
9.4
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1.5
ψJB
9.3
RθJC(bot)
1.8
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) Junction-to-ambient thermal resistance (RθJA) is based on 4-layer board thermal measurements, performed under the conditions and
guidelines set forth in the JEDEC standards JESD51-1 to JESD51-11. RJθA varies with PCB copper area, power dissipation, and airflow.
4
Copyright © 2012–2018, Texas Instruments Incorporated
LMZ21701
www.ti.com.cn
ZHCSD26E –AUGUST 2012–REVISED AUGUST 2018
6.5 Electrical Characteristics(1)
Limits apply over the recommended operating junction temperature (TJ) range of -40°C to +125°C, unless otherwise stated.
Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following
conditions apply: VIN = 12 V.
PARAMETER
SYSTEM PARAMETERS
TEST CONDITIONS
MIN(1)
TYP(2)
MAX(1)
UNIT
IQ
Operating quiescent current
EN = high, IOUT = 0 mA, TJ = -40°C to
85°C
17
17
25
28
μA
μA
device not switching
EN = high, IOUT = 0 mA, TJ = -40°C to
125°C
device not switching
ISD
Shutdown current
EN = low, TJ = -40°C to 85°C
EN = low, TJ = -40°C to 125°C
1.5
1.5
4
5
μA
μA
VINUVLO
Input under voltage lock out rising
threshold
2.8
2.9
3
V
V
VINUVLO-HYS
Input under voltage lock out
hysteresis
0.125
0.18
0.26
TSD
Thermal shutdown
Rising Threshold
160
30
°C
°C
TSD-HYST
CONTROL
VIH, ENABLE
VIL, ENABLE
ILKG
Thermal shutdown hysteresis
Enable logic HIGH voltage
Enable logic LOW voltage
Input leakage current
0.9
V
V
0.3
1
EN = VIN or GND
0.01
95%
90%
0.07
1
μA
VTH_PG
Power Good threshold voltage
Rising (% VOUT
)
92%
87%
98%
93%
0.3
Falling (% VOUT
)
VOL_PG
Power Good output low voltage
Power Good leakage current
Softstart Pin source current
IPG = -2 mA
V
ILKG_PG
VPG = 1.8 V
400
3.2
nA
μA
ISS
2.5
2.84
POWER STAGE
RDS(ON)
High-Side MOSFET ON
Resistance
VIN ≥ 6 V
VIN = 3 V
VIN ≥ 6 V
VIN = 3 V
82
120
40
mΩ
mΩ
Low-Side MOSFET ON
Resistance
50
L
Integrated power inductor value
2.2
μH
DCR
Integrated power inductor DC
resistance
92
mΩ
ICL-HS
ICL-LS
ICL-DC
High-Side MOSFET Current Limit TA = 25°C
Low-Side MOSFET Current Limit TA = 25°C
1.4
1.8
1.2
1.3
2.2
A
A
A
Output (DC) current limit
VOUT = 5 V, TA = 85°C
(1) Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlation
using Statistical Quality Control (SQC) methods. Limits are used to calculate National’s Average Outgoing Quality Level (AOQL).
(2) Typical numbers are at 25°C and represent the most likely parametric norm.
Copyright © 2012–2018, Texas Instruments Incorporated
5
LMZ21701
ZHCSD26E –AUGUST 2012–REVISED AUGUST 2018
www.ti.com.cn
Electrical Characteristics(1) (continued)
Limits apply over the recommended operating junction temperature (TJ) range of -40°C to +125°C, unless otherwise stated.
Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following
conditions apply: VIN = 12 V.
PARAMETER
TEST CONDITIONS
MIN(1)
TYP(2)
MAX(1)
UNIT
OUTPUT
VREF
Internal reference voltage
0.7869
0.803
1
0.8191
100
V
IFB
Feedback pin leakage current
VFB = 0.8 V
nA
VOUT
Light load initial voltage accuracy Power save mode, COUT = 22 µF, TA
-40°C to 85°C, 1% FB Resistors
=
-2.3%
2.8%
VOUT
VOUT
Load regulation
VOUT = 3.3 V
PWM mode operation
0.05%
0.02%
/ A
/ V
Line regulation
3 V ≤ VIN ≤ 17 V, VOUT= 3.3 V, IOUT
1000 mA
=
PWM mode operation
SYSTEM CHARACTERISTICS
Full Load Efficiency
Light Load Efficiency
VOUT = 3.3 V, IOUT = 1000 mA
VOUT = 3.3 V, IOUT = 1 mA
93%
72%
η
6
Copyright © 2012–2018, Texas Instruments Incorporated
LMZ21701
www.ti.com.cn
ZHCSD26E –AUGUST 2012–REVISED AUGUST 2018
6.6 Typical Characteristics
Unless otherwise specified the following conditions apply: VIN = 12 V, TA = 25°C
100
90
80
70
60
50
40
30
20
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
2-LAYER 70 µm (2 oz) Cu
4-LAYER 70 µm (2 oz) Cu
VIN = 3.3 V
VIN = 5 V
VIN = 9 V
VIN = 12 V
VIN = 15 V
VIN = 17 V
0
5
10
15
20
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Load Current (A)
1
Copper Area (cm2)
D012
005
VOUT = 1.2 V
TA = 85ºC
Figure 2. Package Thermal Resistance vs. Board Copper
Area
Figure 3. Power Dissipation
0.7
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
VIN = 3.3 V
VIN = 5 V
VIN = 9 V
VIN = 12 V
VIN = 15 V
VIN = 17 V
VIN = 3.3 V
VIN = 5 V
VIN = 9 V
VIN = 12 V
VIN = 15 V
VIN = 17 V
0.6
0.5
0.4
0.3
0.2
0.1
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Load Current (A)
1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Load Current (A)
1
D006
D007
VOUT = 1.8 V
TA = 85ºC
VOUT = 2.5 V
TA = 85ºC
Figure 4. Power Dissipation
Figure 5. Power Dissipation
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
VIN = 5 V
VIN = 9 V
VIN = 9 V
VIN = 12 V
VIN = 15 V
VIN = 17 V
VIN = 12 V
VIN = 15 V
VIN = 17 V
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Load Current (A)
1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Load Current (A)
1
D008
D009
VOUT = 3.3 V
TA = 85ºC
VOUT = 5.0 V
TA = 85ºC
Figure 6. Power Dissipation
Figure 7. Power Dissipation
Copyright © 2012–2018, Texas Instruments Incorporated
7
LMZ21701
ZHCSD26E –AUGUST 2012–REVISED AUGUST 2018
www.ti.com.cn
Typical Characteristics (continued)
Unless otherwise specified the following conditions apply: VIN = 12 V, TA = 25°C
6
5.5
5
4
3.8
3.6
3.4
3.2
3
IOUT = 0.25 A
IOUT = 0.5 A
IOUT = 1 A
IOUT = 0.25 A
IOUT = 0.5 A
IOUT = 1 A
4.5
4
2.8
2.6
2.4
2.2
2
3.5
3
3
3.5
4
4.5
5
5.5
6
3
3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9
Input Voltage (V)
4
Input Voltage (V)
D011
D010
VOUT = 5.0 V
TA = 85ºC
VOUT = 3.3 V
TA = 85ºC
Figure 8. Dropout
Figure 9. Dropout
80
70
60
50
40
30
20
10
0
100
Evaluation Board
EN 55022 Class B Limit
EN 55022 Class A Limit
Peak Emissions
Quasi Peak Limit
Average Limit
90
80
70
60
50
40
30
20
10
0
0
200
400
600
800
1000
0.1
1
10
100
Frequency (MHz)
Frequency (MHz)
D004
D003
VIN= 12 V
VOUT = 3.3 V
IOUT = 1 A
VIN= 12 V
Lf = 2.2 µH
VOUT = 3.3 V
Cf = 1.0 µF
IOUT = 1 A
Figure 10. Radiated EMI on EVM
Figure 11. Conducted EMI on EVM
7 Detailed Description
7.1 Overview
The LMZ21701 Nano Module is an easy-to-use step-down DC/DC solution capable of driving up to 1000 mA load
in space-constrained applications. Only an input capacitor, an output capacitor, a softstart capacitor, and two
resistors are required for basic operation. The Nano Module comes in 8-pin DFN footprint package with an
integrated inductor. The LMZ21701 architecture is based on DCS-Control™ (Direct Control with Seamless
Transition into Power Save Mode). This architecture combines the fast transient response and stability of
hysteretic type converters along with the accurate DC output regulation of voltage mode and current mode
regulators.
The LMZ21701 architecture uses pulse width modulation (PWM) mode for medium and heavy load requirements
and Power Save Mode (PSM) at light loads for high efficiency. In PWM mode the switching frequency is
controlled over the input voltage range. The value depends on the output voltage setting and is typically reduced
at low output voltages to achieve higher efficiency. In PSM the switching frequency decreases linearly with the
load current. Since the architecture of the device supports both operation modes (PWM and PSM) in a single
circuit building block, the transition between the modes of operation is seamless with minimal effect on the output
voltage.
8
Copyright © 2012–2018, Texas Instruments Incorporated
LMZ21701
www.ti.com.cn
ZHCSD26E –AUGUST 2012–REVISED AUGUST 2018
7.2 Functional Block Diagram
HIGH SIDE
SWITCH
INDUCTOR
VIN
VOUT
2.2µH
HIGH SIDE
CURRENT
LIMIT
LDO
5V LDO
BYPASS
UVLO
HIGH SIDE DRIVER
WITH INTERNAL BOOTSTRAP
LOW SIDE
DRIVER
LOW SIDE
SWITCH
EN
PG
400kΩ
CONTROL LOGIC
LOW SIDE
CURRENT
LIMIT
ZERO
CURRENT
DETECT
THERMAL
SHUTDOWN
SOFTSTART
CURRENT AND
TRACKING
SS
VOS
DIRECT CONTROL
&
COMPENSATION
tON TIMER
6.6V
CLAMP
25pF
CFF
+
-
-
FB
GND
+
COMPARATOR
VREF
+
-
ERROR
AMPLIFIER
7.3 Package Construction
In order to achieve a small solution size the LMZ21701 Nano Module comes in an innovative MicroSiP™
package. The construction consists of a synchronous buck converter IC embedded inside an FR-4 laminate
substrate, with a power inductor mounted on top of the substrate material. See Figure 12 and Figure 13 below.
The bottom (landing pads) of the package resemble a typical 8-pin DFN package. See the Mechanical drawings
at the end of the datasheet for details on the recommended landing pattern and solder paste stencil information.
Copyright © 2012–2018, Texas Instruments Incorporated
9
LMZ21701
ZHCSD26E –AUGUST 2012–REVISED AUGUST 2018
www.ti.com.cn
Package Construction (continued)
Figure 12. LMZ21701 in the SIL0008E Package
INDUCTOR
FR-4 LAMINATE
SUBSTRATE
BOTTOM
COPPER PATTERN
EMBEDDED BUCK IC
Figure 13. LMZ21701 Package Construction Cross Section
(Illustration Only, Not to Scale)
10
Copyright © 2012–2018, Texas Instruments Incorporated
LMZ21701
www.ti.com.cn
ZHCSD26E –AUGUST 2012–REVISED AUGUST 2018
7.4 Feature Description
7.4.1 Input Undervoltage Lockout
The LMZ21701 features input undervoltage lockout (UVLO) circuit. It monitors the input voltage level and
prevents the device from switching the power MOSFETs if VIN is not high enough. The typical VIN UVLO rising
threshold is 2.9 V with 180 mV of hysteresis.
7.4.2 Enable Input (EN)
The enable pin (EN) is weakly pulled down internally through a 400-kΩ resistor to keep EN logic low when the
pin is floating. The pull-down resistor is not connected when EN is set high. Once the voltage on the enable pin
(EN) is set high the Nano Module will start operation. If EN is set low ( < 0.3 V ) the LMZ21701 will enter
shutdown mode. The typical shutdown quiescent current is 1.5 μA.
7.4.3 Soft Start and Tracking Function (SS)
When EN is set high for device operation the LMZ21701 start switching after 50-μs delay, and the output voltage
starts rising. The VOUT rising slope is controlled by the external capacitor CSS connected to the softstart (SS) pin.
The Nano Module has a 2.9 μA constant current source internally connected to the SS pin to program the
softstart time TSS
:
TSS = CSS × 1.25 V / 2.9 μA
(1)
The soft-start capacitor voltage is reset to zero volts when EN is pulled low and when the thermal protection is
active.
If tracking function is desired, the SS pin can be used to track external voltage. If the applied external tracking
voltage is between 100 mV and 1.2 V, the FB voltage will follow SS according to the following relationship:
VFB = 0.64 x VSS
(2)
7.4.4 Power Good Function (PG)
The LMZ21701 features a power good function which can be used for sequencing of multiple rails. The PG pin is
an open-drain output and requires a pull-up resistor RPG to VOUT (or any other external voltage less than 7 V).
When the Nano Module is enabled and UVLO is satisfied, the power good function starts monitoring the output
voltage. The PG pin is kept at logic low if the output has not reached the proper regulation voltage. Refer to the
Electrical Characteristics table for the PG voltage thresholds. The PG pin can sink 2 mA of current which sets the
minimum limit of the RPG resistance value:
RPG-MIN= VPULL-UP / 2 mA
(3)
The PG pin goes low impedance if the device is disabled or the thermal protection is active.
7.4.5 Output Voltage Setting
The output voltage of the LMZ21701 is set by a resistive divider from VOUT to GND, connected to the feedback
(FB) pin. The output voltage can be set between 0.9 V and 6 V. The voltage at the FB pin is regulated to 0.8 V.
The recommended minimum divider current is 2 μA. This sets a maximum limit on the bottom feedback resistor
RFBB. Its value must not exceed 400 kΩ. The top feedback resistor RFBT can be calculated using the following
formula:
RFBT = RFBB x (VOUT/ 0.8 – 1)
(4)
7.4.6 Output Current Limit and Output Short Circuit Protection
The LMZ21701 has integrated protection against heavy loads and output short circuit events. Both, the high-side
FET and low-side FET have current monitoring circuitry. If the current limit threshold of the high-side FET is
reached , the high-side FET will be turned off and the low-side FET will be turned on to ramp down the inductor
current. Once the current through the low-side FET has decreased below a safe level, the high-side device will
be allowed to turn on again. The actual DC output current depends on the input voltage, output voltage, and
switching frequency. Refer to the Application Curves section for more information.
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Feature Description (continued)
7.4.7 Thermal Protection
The nano module monitors its junction temperature (Tj) and shuts itself off if the it gets too hot. The thermal
shutdown threshold for the junction is typically 160 °C. Both, high-side and low-side FETs are turned off until the
junction temperature has decreased under the hysteresis level, typically 30 °C below the shutdown temperature.
7.5 Device Functional Modes
7.5.1 PWM Mode Operation
The LMZ21701 operates in PWM mode when the output current is greater than half the inductor ripple current.
The frequency variation in PWM mode is controlled and depends on the VIN and VOUT settings. Refer to the
Application Curves section for switching frequency graphs for several typical output voltage settings. As the load
current is decreased and the valley of the inductor current ripple reaches 0 A the device enters PSM operation to
maintain high efficiency.
7.5.2 PSM Operation
Once the load current decreases and the valley of the inductor current reaches 0 A, the LMZ21701 transitions to
power save mode of operation. The device will remain in PSM as long as the inductor current is discontinuous.
The switching frequency will decrease linearly with the load current. If VIN decreases to about 15 % above VOUT
the device will not enter PSM and will maintain output regulation in PWM mode.
12
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LMZ21701 is a step down DC-to-DC converter. It is used to convert higher DC voltage to a regulated lower
DC voltage with maximum load current of 1 A. The following design procedure can be used to select components
for the LMZ21701. Alternatively, the WEBENCH® software can be used to select from a large database of
components, run electrical simulations, and optimize the design for specific performance. Please go to
webench.ti.com to access the WEBENCH® tool.
8.2 Typical Application
For a quick start, the following component values can be used as a design starting point for several typical output
voltage rails and 1 A of output load current.
VOUT
VIN
COMPONENT VALUES FOR VOUT=1.2V
VIN
EN
VOUT
PG
C
C
C
R
R
R
IN
22µF
≥ 25V
≥ 10V
≥ 10V
1%
X7R or X5R
X7R or X5R
X7R or X5R
R
PG
OUT
SS
22µF
LMZ21701
C
IN
3300pF
41.2kꢀ
82.5kꢀ
10kꢀ
C
OUT
VOS
SS
R
R
FBT
FBB
PG
C
FBT
SS
GND
FB
1%
FBB
1%
Figure 14. Typical Applications Circuit
Figure 15. External Component Values
( VOUT = 1.2 V )
COMPONENT VALUES FOR VOUT=1.8V
COMPONENT VALUES FOR VOUT=2.5V
C
C
C
R
R
R
C
C
C
R
R
R
IN
22µF
≥ 25V
≥ 10V
≥ 10V
1%
X7R or X5R
X7R or X5R
X7R or X5R
IN
22µF
≥ 25V
≥ 10V
≥ 10V
1%
X7R or X5R
X7R or X5R
X7R or X5R
OUT
SS
22µF
OUT
SS
22µF
3300pF
147kꢀ
118kꢀ
10kꢀ
3300pF
357kꢀ
169kꢀ
10kꢀ
FBT
FBB
PG
FBT
FBB
PG
1%
1%
1%
1%
Figure 16. External Component Values
( VOUT = 1.8 V )
Figure 17. External Component Values
( VOUT = 2.5 V )
COMPONENT VALUES FOR VOUT=3.3V
COMPONENT VALUES FOR VOUT=5.0V
C
C
C
R
R
R
C
C
C
R
R
R
IN
22µF
≥ 25V
≥ 10V
≥ 10V
1%
X7R or X5R
X7R or X5R
X7R or X5R
IN
22µF
≥ 25V
≥ 10V
≥ 10V
1%
X7R or X5R
X7R or X5R
X7R or X5R
OUT
SS
22µF
OUT
SS
22µF
3300pF
1.21Mꢀ
383kꢀ
10kꢀ
3300pF
232kꢀ
44.2kꢀ
10kꢀ
FBT
FBB
PG
FBT
FBB
PG
1%
1%
1%
1%
Figure 18. External Component Values
( VOUT = 3.3 V )
Figure 19. External Component Values
( VOUT = 5.0 V )
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Typical Application (continued)
8.2.1 Design Requirements
The design procedure requires a few typical design parameters. See Table 1 below.
Table 1. Design Parameters
DESIGN PARAMETER
Input Voltage (VIN
Output Voltage (VOUT
Output Current (IOUT
Softstart time (TSS
VALUE
)
Range from 3.0 V to 17 V
Range from 0.9 V to 6 V
Up to 1000 mA
)
)
)
Minimum of 0.5 ms recommended
8.2.2 Detailed Design Procedure
8.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LMZ21701 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
•
•
•
•
Run electrical simulations to see important waveforms and circuit performance
Run thermal simulations to understand board thermal performance
Export customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.2.2 Input Capacitor (CIN)
Low ESR multi-layer ceramic capacitors (MLCC) are recommended for the input capacitor of the LMZ21701.
Using a ≥ 10 µF ceramic input capacitor in ≥ 0805 (2012 metric) case size with 25-V rating typically provides
sufficient VIN bypass. Use of multiple capacitors can also be considered. Ceramic capacitors with X5R and X7R
temperature characteristics are recommended. These provide an optimal balance between small size, cost,
reliability, and performance for applications with limited space. The DC voltage bias characteristics of the
capacitors must be considered when selecting the DC voltage rating and case size of these components. The
effective capacitance of an MLCC is typically reduced by the DC voltage bias applied across its terminals.
Selecting a part with larger capacitance, larger case size, or higher voltage rating can compensate for the
capacitance loss due to the DC voltage bias effect. For example, a 10-µF, X7R, 25-V rated capacitor used under
12-V DC bias may have approximately 8-µF effective capacitance in a 1210 (3225 metric) case size and about 6
µF in a 1206 (3216 metric) case size. As another example, a 10-µF, X7R, 16-V rated capacitor in a 1210 (3225
metric) case size used at 12-V DC bias may have approximately 5.5 µF effective capacitance. Check the
capacitor specifications published by the manufacturer.
8.2.2.3 Output Capacitor (COUT
)
Similarly to the input capacitor, it is recommended to use low ESR multi-layer ceramic capacitors for COUT
.
Ceramic capacitors with X5R and X7R temperature characteristics are recommended. Use 10 µF or larger value
and consider the DC voltage bias characteristics of the capacitor when choosing the case size and voltage
rating. For stability, the output capacitor should be in the 10 µF – 200 µF effective capacitance range.
14
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8.2.2.4 Soft-start Capacitor (CSS
)
The softstart capacitor is chosen according to the desired softstart time. As described in the Softstart and
Tracking Function section the softstart time TSS = CSS x 1.25 V / 2.9 μA.
A minimum CSS value of 1000 pF is required for monotonic VOUT ramp up.
8.2.2.5 Power Good Resistor (RPG
)
If the Power Good function is used, a pull up resistor RPG is necessary from the PG pin to an external pull-up
voltage.
The minimum RPG value is restricted by the pull down current capability of the internal pull down device.
RPG-MIN= VPULL-UP / 2 mA
(5)
The maximum RPG value is based on the maximum PG leakage current and the minimum “logic high” level
system requirements:
RPG-MAX= (VPULL-UP – VLOGIC-HIGH) / ILKG_PG
(6)
8.2.2.6 Feedback Resistors (RFBB and RFBT
)
The feedback resistors RFBB and RFBT set the desired output voltage. Choose RFBB less than 400 kΩ and
calculate the value for RFBT using the following formula:
RFBT = RFBB x (VOUT/ 0.8 – 1)
(7)
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8.2.3 Application Curves
8.2.3.1 VOUT = 1.2 V
VOUT
VIN
COMPONENT VALUES FOR VOUT=1.2V
VIN
EN
VOUT
PG
C
C
C
R
R
R
IN
22µF
≥ 25V
≥ 10V
≥ 10V
1%
X7R or X5R
X7R or X5R
X7R or X5R
R
PG
OUT
SS
22µF
LMZ21701
C
IN
3300pF
41.2kꢀ
82.5kꢀ
10kꢀ
C
OUT
VOS
SS
R
R
FBT
FBB
PG
C
FBT
SS
GND
FB
1%
FBB
1%
Figure 20. Typical Applications Circuit
Figure 21. External Component Values
(VOUT = 1.2 V)
100
90
80
70
60
50
40
30
20
10
0
0.6
0.5
0.4
0.3
0.2
0.1
0.0
VIN = 3 V
VIN = 3.3 V
VIN = 4.5 V
VIN = 5 V
VIN = 9 V
VIN = 12 V
VIN = 15 V
VIN = 17 V
VIN = 3 V
VIN = 3.3 V
VIN = 4.5 V
VIN = 5 V
VIN = 9 V
VIN = 12 V
VIN = 15 V
VIN = 17 V
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
0.0001
0.001
0.01
Load Current (A)
0.1
1
Load Current (A)
C001
D013
Figure 23. Power Dissipation VOUT = 1.2 V
Figure 22. Efficiency VOUT = 1.2 V
ILOAD 500mA/Div
PGOOD 1V/Div
ILOAD 500mA/Div
VOUT 500mV/Div
VOUT 20mV/Div AC
ENABLE 500mV/Div
1ms/Div
20MHz BW
1ms/Div
20MHz BW
Figure 25. Startup VOUT = 1.2 V
Figure 24. Load Transient VOUT = 1.2 V
16
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LMZ21701
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ZHCSD26E –AUGUST 2012–REVISED AUGUST 2018
COUT1 = 22ꢀF 10V 0805 X5R
Taiyo Yuden MK212BJ226MG-T
VOUT RIPPLE
VOUT RIPPLE
WITH 500MHz SCOPE BANDWIDTH
COUT = 22ꢀF 10V 0805 X5R
COUT2 = 3x1000pF 0805 NP0
Johanson Dielectrics 500R15N102JV4T
Taiyo Yuden MK212BJ226MG-T
50mV/Div
10mV/Div
1µs/Div
20MHz BW
500MHz BW
1µs/Div
Figure 26. 20 MHz Oscilloscope Bandwidth
Output Voltage Ripple VOUT = 1.2 V
Figure 27. 500 MHz Oscilloscope Bandwidth, 3x1000 pF
additional output capacitance
Output Voltage Ripple and HF Noise VOUT = 1.2 V
2.5
2.0
1.5
1.0
0.5
0.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
VOUT=1.2V
0
2
4
6
8
10
12
14
16
18
0
2
4
6
8
10
12
14
16
18
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
C001
C001
Figure 28. Typical Switching Frequency at 1000 mA Load
VOUT = 1.2 V
Figure 29. Typical Current Limit VOUT = 1.2 V, TA = 85 °C
1.206
1.204
1.202
1.2
1.2
1.0
0.8
0.6
VIN = 3 V
VIN = 3.3 V
VIN = 4.5 V
VIN = 5 V
VIN = 12 V
VIN = 15 V
VIN = 17 V
1.198
1.196
1.194
1.192
1.19
0.4
VIN = 3.3 V
0.2
0.0
VIN = 5 V
VIN = 12 V
VIN = 17 V
60
70
80
90
100
110
120
130
0.0001
0.001
0.01
Load Current (A)
0.1
1
Ambient Temperature (°C)
C001
D014
Figure 31. Thermal Derating for θJA = 47 ºC/W, VOUT = 1.2 V
Figure 30. Line and Load Regulation VOUT = 1.2 V
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8.2.3.2 VOUT = 1.8 V
VOUT
VIN
COMPONENT VALUES FOR VOUT=1.8V
VIN
EN
VOUT
PG
C
C
C
R
R
R
IN
22µF
≥ 25V
≥ 10V
≥ 10V
1%
X7R or X5R
X7R or X5R
X7R or X5R
R
PG
OUT
SS
22µF
LMZ21701
C
IN
3300pF
147kꢀ
118kꢀ
10kꢀ
C
OUT
VOS
SS
R
R
FBT
FBB
PG
C
FBT
SS
GND
FB
1%
FBB
1%
Figure 32. Typical Applications Circuit
Figure 33. External Component Values
(VOUT = 1.8 V)
100
90
80
70
60
50
40
30
20
10
0
0.6
0.5
0.4
0.3
0.2
0.1
0.0
VIN = 3 V
VIN = 3.3 V
VIN = 4.5 V
VIN = 5 V
VIN = 9 V
VIN = 12 V
VIN = 15 V
VIN = 17 V
VIN = 3 V
VIN = 3.3 V
VIN = 4.5 V
VIN = 5 V
VIN = 9 V
VIN = 12 V
VIN = 15 V
VIN = 17 V
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
0.0001
0.001
0.01
Load Current (A)
0.1
1
Load Current (A)
C001
D015
Figure 35. Power Dissipation VOUT = 1.8 V
Figure 34. Efficiency VOUT = 1.8 V
ILOAD 500mA/Div
PGOOD 1V/Div
ILOAD 500mA/Div
VOUT 1V/Div
VOUT 20mV/Div AC
ENABLE 500mV/Div
1ms/Div
20MHz BW
1ms/Div
20MHz BW
Figure 37. Startup VOUT = 1.8 V
Figure 36. Load Transient VOUT = 1.8 V
18
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LMZ21701
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COUT1 = 22ꢀF 10V 0805 X5R
Taiyo Yuden MK212BJ226MG-T
VOUT RIPPLE
VOUT RIPPLE
COUT = 22ꢀF 10V 0805 X5R
WITH 500MHz SCOPE BANDWIDTH
COUT2 = 3x1000pF 0805 NP0
Johanson Dielectrics 500R15N102JV4T
Taiyo Yuden MK212BJ226MG-T
10mV/Div
50mV/Div
1µs/Div
20MHz BW
500MHz BW
1µs/Div
Figure 38. 20 MHz Oscilloscope Bandwidth
Output Voltage Ripple VOUT = 1.8 V
Figure 39. 500 MHz Oscilloscope Bandwidth, 3x1000 pF
additional output capacitance
Output Voltage Ripple and HF Noise VOUT = 1.8 V
2.5
2.0
1.5
1.0
0.5
0.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
VOUT=1.8V
0
2
4
6
8
10
12
14
16
18
0
2
4
6
8
10
12
14
16
18
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
C001
C001
Figure 40. Typical Switching Frequency at 1000 mA Load
VOUT = 1.8 V
Figure 41. Typical Current Limit VOUT = 1.8 V, TA = 85 °C
1.81
1.2
1.0
0.8
0.6
VIN = 3 V
VIN = 3.3 V
VIN = 4.5 V
VIN = 5 V
VIN = 12 V
VIN = 15 V
VIN = 17 V
1.808
1.806
1.804
1.802
1.8
1.798
1.796
1.794
1.792
1.79
0.4
VIN = 3.3 V
0.2
0.0
VIN = 5 V
VIN = 12 V
VIN = 17 V
60
70
80
90
100
110
120
130
0.0001
0.001
0.01
Load Current (A)
0.1
1
Ambient Temperature (°C)
C001
D016
Figure 43. Thermal Derating for θJA= 47ºC/W VOUT = 1.8 V
Figure 42. Line and Load Regulation VOUT = 1.8 V
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8.2.3.3 VOUT = 2.5 V
VOUT
VIN
COMPONENT VALUES FOR VOUT=2.5V
VIN
EN
VOUT
PG
C
C
C
R
R
R
IN
22µF
≥ 25V
≥ 10V
≥ 10V
1%
X7R or X5R
X7R or X5R
X7R or X5R
R
PG
OUT
SS
22µF
LMZ21701
C
IN
3300pF
357kꢀ
169kꢀ
10kꢀ
C
OUT
VOS
SS
R
R
FBT
FBB
PG
C
FBT
SS
GND
FB
1%
FBB
1%
Figure 44. Typical Applications Circuit
Figure 45. External Component Values
(VOUT = 2.5 V)
100
90
80
70
60
50
40
30
20
10
0
0.6
0.5
0.4
0.3
0.2
0.1
0.0
VIN = 3.3 V
VIN = 4.5 V
VIN = 5 V
VIN = 9 V
VIN = 12 V
VIN = 15 V
VIN = 17 V
VIN = 3.3 V
VIN = 4.5 V
VIN = 5 V
VIN = 9 V
VIN = 12 V
VIN = 15 V
VIN = 17 V
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
0.0001
0.001
0.01
Load Current (A)
0.1
1
Load Current (A)
C001
D017
Figure 47. Power Dissipation VOUT = 2.5 V
Figure 46. Efficiency VOUT = 2.5 V
ILOAD 500mA/Div
PGOOD 2V/Div
ILOAD 500mA/Div
VOUT 1V/Div
VOUT 20mV/Div AC
ENABLE 500mV/Div
1ms/Div
20MHz BW
1ms/Div
20MHz BW
Figure 49. Startup VOUT = 2.5 V
Figure 48. Load Transient VOUT = 2.5 V
20
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LMZ21701
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COUT1 = 22ꢀF 10V 0805 X5R
Taiyo Yuden MK212BJ226MG-T
VOUT RIPPLE
VOUT RIPPLE
COUT = 22ꢀF 10V 0805 X5R
WITH 500MHz SCOPE BANDWIDTH
COUT2 = 3x1000pF 0805 NP0
Johanson Dielectrics 500R15N102JV4T
Taiyo Yuden MK212BJ226MG-T
10mV/Div
50mV/Div
1µs/Div
20MHz BW
500MHz BW
1µs/Div
Figure 50. 20MHz Oscilloscope Bandwidth
Output Voltage Ripple VOUT = 2.5 V
Figure 51. 500 MHz Oscilloscope Bandwidth, 3x1000 pF
additional output capacitance
Output Voltage Ripple and HF Noise VOUT = 2.5 V
2.5
2.0
1.5
1.0
0.5
0.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
VOUT=2.5V
0
2
4
6
8
10
12
14
16
18
0
2
4
6
8
10
12
14
16
18
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
C001
C001
Figure 52. Typical Switching Frequency at 1000 mA Load
VOUT = 2.5 V
Figure 53. Typical Current Limit VOUT = 2.5 V, TA = 85 °C
2.5
1.2
1.0
0.8
0.6
VIN = 3 V
VIN = 3.3 V
VIN = 4.5 V
VIN = 5 V
VIN = 12 V
VIN = 15 V
VIN = 17 V
2.498
2.496
2.494
2.492
2.49
2.488
2.486
2.484
2.482
2.48
0.4
VIN = 5 V
0.2
0.0
VIN = 12 V
VIN = 15 V
VIN = 17 V
60
70
80
90
100
110
120
130
0.0001
0.001
0.01
Load Current (A)
0.1
1
Ambient Temperature (°C)
C001
D018
Figure 55. Thermal Derating for θJA = 47 ºC/W, VOUT = 2.5 V
Figure 54. Line and Load Regulation VOUT = 2.5 V
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8.2.3.4 VOUT = 3.3 V
VOUT
VIN
COMPONENT VALUES FOR VOUT=3.3V
VIN
EN
VOUT
PG
C
C
C
R
R
R
IN
22µF
≥ 25V
≥ 10V
≥ 10V
1%
X7R or X5R
X7R or X5R
X7R or X5R
R
PG
OUT
SS
22µF
LMZ21701
C
IN
3300pF
1.21Mꢀ
383kꢀ
10kꢀ
C
OUT
VOS
SS
R
R
FBT
FBB
PG
C
FBT
SS
GND
FB
1%
FBB
1%
Figure 56. Typical Applications Circuit
Figure 57. External Component Values
(VOUT = 3.3 V)
100
90
80
70
60
50
40
30
20
10
0
0.6
0.5
0.4
0.3
0.2
0.1
0.0
VIN = 4.5 V
VIN = 5 V
VIN = 9 V
VIN = 12 V
VIN = 15 V
VIN = 17 V
VIN = 4.5 V
VIN = 5 V
VIN = 9 V
VIN = 12 V
VIN = 15 V
VIN = 17 V
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
0.0001
0.001
0.01
Load Current (A)
0.1
1
Load Current (A)
C001
D019
Figure 59. Power Dissipation VOUT = 3.3 V
Figure 58. Efficiency VOUT = 3.3 V
ILOAD 500mA/Div
VOUT 1V/Div
ILOAD 500mA/Div
PGOOD 2V/Div
VOUT 20mV/Div AC
ENABLE 500mV/Div
1ms/Div
20MHz BW
1ms/Div
20MHz BW
Figure 61. Startup VOUT = 3.3 V
Figure 60. Load Transient VOUT = 3.3 V
22
Copyright © 2012–2018, Texas Instruments Incorporated
LMZ21701
www.ti.com.cn
ZHCSD26E –AUGUST 2012–REVISED AUGUST 2018
COUT1 = 22ꢀF 10V 0805 X5R
Taiyo Yuden MK212BJ226MG-T
VOUT RIPPLE
VOUT RIPPLE
COUT = 22ꢀF 10V 0805 X5R
WITH 500MHz SCOPE BANDWIDTH
COUT2 = 3x1000pF 0805 NP0
Johanson Dielectrics 500R15N102JV4T
Taiyo Yuden MK212BJ226MG-T
10mV/Div
50mV/Div
1µs/Div
20MHz BW
500MHz BW
1µs/Div
Figure 62. 20 MHz Oscilloscope Bandwidth
Output Voltage Ripple VOUT = 3.3 V
Figure 63. 500 MHz Oscilloscope Bandwidth, 3x1000 pF
additional output capacitance
Output Voltage Ripple and HF Noise VOUT = 3.3 V
2.5
2.0
1.5
1.0
0.5
0.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
VOUT=3.3V
0
2
4
6
8
10
12
14
16
18
0
2
4
6
8
10
12
14
16
18
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
C001
C001
Figure 64. Typical Switching Frequency at 1000 mA Load
VOUT = 3.3 V
Figure 65. Typical Current Limit VOUT = 3.3 V, TA = 85 °C
3.316
3.314
3.312
3.31
1.2
1.0
0.8
0.6
VIN = 4.5 V
VIN = 5 V
VIN = 9 V
VIN = 12 V
VIN = 15 V
VIN = 17 V
3.308
3.306
3.304
3.302
3.3
0.4
VIN = 5 V
0.2
0.0
VIN = 12 V
VIN = 15 V
VIN = 17 V
60
70
80
90
100
110
120
130
0.0001
0.001
0.01
Load Current (A)
0.1
1
Ambient Temperature (°C)
C001
D020
Figure 67. Thermal Derating for θJA = 47 ºC/W, VOUT = 3.3 V
Figure 66. Line and Load Regulation VOUT = 3.3 V
Copyright © 2012–2018, Texas Instruments Incorporated
23
LMZ21701
ZHCSD26E –AUGUST 2012–REVISED AUGUST 2018
www.ti.com.cn
8.2.3.5 VOUT = 5.0 V
VOUT
VIN
COMPONENT VALUES FOR VOUT=5.0V
VIN
EN
VOUT
PG
C
C
C
R
R
R
IN
22µF
≥ 25V
≥ 10V
≥ 10V
1%
X7R or X5R
X7R or X5R
X7R or X5R
R
PG
OUT
SS
22µF
LMZ21701
C
IN
3300pF
232kꢀ
44.2kꢀ
10kꢀ
C
OUT
VOS
SS
R
R
FBT
FBB
PG
C
FBT
SS
GND
FB
1%
FBB
1%
Figure 68. Typical Applications Circuit
Figure 69. External Component Values
(VOUT = 5.0 V)
100
90
80
70
60
50
40
30
20
10
0
0.6
0.5
0.4
0.3
0.2
0.1
0.0
VIN = 9 V
VIN = 12 V
VIN = 15 V
VIN = 17 V
VIN = 9 V
VIN = 12 V
VIN = 15 V
VIN = 17 V
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
0.0001
0.001
0.01
Load Current (A)
0.1
1
Load Current (A)
C001
D021
Figure 71. Power Dissipation VOUT = 5.0 V
Figure 70. Efficiency VOUT = 5.0 V
ILOAD 500mA/Div
VOUT 2V/Div
ILOAD 500mA/Div
PGOOD 5V/Div
VOUT 20mV/Div AC
ENABLE 500mV/Div
1ms/Div
20MHz BW
1ms/Div
20MHz BW
Figure 73. Startup VOUT = 5.0 V
Figure 72. Load Transient VOUT = 5.0 V
24
Copyright © 2012–2018, Texas Instruments Incorporated
LMZ21701
www.ti.com.cn
ZHCSD26E –AUGUST 2012–REVISED AUGUST 2018
COUT1 = 22ꢀF 10V 0805 X5R
Taiyo Yuden MK212BJ226MG-T
VOUT RIPPLE
VOUT RIPPLE
COUT = 22ꢀF 10V 0805 X5R
WITH 500MHz SCOPE BANDWIDTH
COUT2 = 3x1000pF 0805 NP0
Johanson Dielectrics 500R15N102JV4T
Taiyo Yuden MK212BJ226MG-T
10mV/Div
50mV/Div
1µs/Div
20MHz BW
500MHz BW
1µs/Div
Figure 74. 20MHz Oscilloscope Bandwidth
Output Voltage Ripple VOUT = 5.0 V
Figure 75. 500 MHz Oscilloscope Bandwidth, 3x1000 pF
additional output capacitance
Output Voltage Ripple and HF Noise VOUT = 5.0 V
2.5
2.0
1.5
1.0
0.5
0.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
VOUT=5.0V
0
2
4
6
8
10
12
14
16
18
0
2
4
6
8
10
12
14
16
18
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
C001
C001
Figure 76. Typical Switching Frequency at 1000 mA Load
VOUT = 5 V
Figure 77. Typical Current Limit VOUT = 5 V, TA = 85°C
5.05
1.2
1.0
0.8
0.6
VIN = 9 V
VIN = 12 V
VIN = 15 V
VIN = 17 V
5.045
5.04
5.035
5.03
5.025
5.02
5.015
5.01
5.005
5
0.4
VIN = 9 V
0.2
0.0
VIN = 12 V
VIN = 15 V
VIN = 17 V
4.995
4.99
60
70
80
90
100
110
120
130
0.0001
0.001
0.01
Load Current (A)
0.1
1
Ambient Temperature (°C)
C001
D022
Figure 79. Thermal Derating for θJA= 47 ºC/W, VOUT = 5 V
Figure 78. Line and Load Regulation VOUT = 5 V
Copyright © 2012–2018, Texas Instruments Incorporated
25
LMZ21701
ZHCSD26E –AUGUST 2012–REVISED AUGUST 2018
www.ti.com.cn
8.3 Do's and Don'ts
● DO NOT exceed the Absolute Maximum Ratings.
● DO NOT exceed the Recommended Operating Conditions.
● DO NOT exceed the ESD Ratings.
● DO follow the Detailed Design Procedure.
● DO follow the PCB Layout Guidelines and Layout Example.
● DO follow the Power Supply Recommendations.
● DO visit the TI E2E Community Support Forum to have your questions answered and designs reviewed.
9 Power Supply Recommendations
9.1 Voltage Range
The voltage of the input supply must not exceed the Absolute Maximum Ratings and the Recommended
Operating Conditions of the LMZ21701.
9.2 Current Capability
The input supply must be able to supply the required input current to the LMZ21701 converter. The required
input current depends on the application's minimum required input voltage (VIN-MIN), the required output power
(VOUT × IOUT-MAX), and the converter efficiency (η).
IIN = VOUT x IOUT-MAX / (VIN-MIN x η)
For example, for a design with 10-V minimum input voltage, 5-V output, and 1-A maximum load, considering 90%
conversion efficiency, the required input current is 0.556 A.
9.3 Input Connection
Long input connection cables can cause issues with the normal operation of any buck converter.
9.3.1 Voltage Drops
Using long input wires to connect the supply to the input of any converter adds impedance in series with the
input supply. This impedance can cause a voltage drop at the VIN pin of the converter when the output of the
converter is loaded. If the input voltage is near the minimum operating voltage, this added voltage drop can
cause the converter to drop out or reset. If long wires are used during testing, it is recommended to add some
bulk (for example, electrolytic) capacitance at the input of the converter.
9.3.2 Stability
The added inductance of long input cables together with the ceramic (and low ESR) input capacitor can result in
an under damped RLC network at the input of the Buck converter. This can cause oscillations on the input and
instability. If long wires are used, it is recommended to add some electrolytic capacitance in parallel with the
ceramic input capacitor. The electrolytic capacitor's ESR will improve the damping.
Use an electrolytic capacitor with CELECTROLYTIC≥ 4 × CCERAMIC and ESRELECTROLYTIC≈ √ (LCABLE / CCERAMIC
)
For example, two cables (one for VIN and one for GND), each 1 meter (~3 ft) long with ~1-mm diameter (18
AWG), placed 1 cm (~0.4 in) apart will form a rectangular loop resulting in about 1.2 µH of inductance. The
inductance in this example can be decreased to almost half if the input wires are twisted. Based on a 22 µF
ceramic input capacitor, the recommended parallel CELECTROLYTIC is ≥ 88 µF. Using a 100 µF capacitor will be
sufficient. The recommended ESRELECTROLYTIC≈ 0.23 Ω or larger, based on about 1.2 µH of inductance and 22
µF of ceramic input capacitance.
See application note SNVA489C for more details on input filter design.
26
Copyright © 2012–2018, Texas Instruments Incorporated
LMZ21701
www.ti.com.cn
ZHCSD26E –AUGUST 2012–REVISED AUGUST 2018
10 Layout
10.1 Layout Guidelines
The PCB layout is critical for the proper operation of any DC/DC switching converter. Although using modules
can simplify the PCB layout process, care should still be taken to minimize the inductance in the high di/dt loops
and to protect sensitive nodes. The following guidelines should be followed when designing a board layout with
the LMZ21701:
10.1.1 Minimize the High di/dt Loop Area
The input capacitor, the VIN terminal, and the GND terminal of the LMZ21701 form a high di/dt loop. Place the
input capacitor as close as possible to the VIN and GND terminals of the module IC. This minimizes the area of
the high di/dt loop and results in lower inductance in the switching current path. Lower inductance in the
switching current path translates to lower voltage spikes on the internal switch node and lower noise on the
output voltage. Make the copper traces between the input capacitor and the VIN and GND terminals wide and
short for better current handling and minimized parasitic inductance.
10.1.2 Protect the Sensitive Nodes in the Circuit
The feedback node is a sensitive circuit which can pick up noise. Make the feedback node as small as possible.
This can be achieved by placing the feedback divider as close as possible to the IC. Use thin traces to the
feedback pin in order to minimize the parasitic capacitance to other nodes. The feedback network carries very
small current and thick traces are not necessary. Another sensitive node to protect is the VOS pin. Use a thin
and short trace from the VOUT terminal of the output capacitor to the VOS pin. The VOS pin is right next to the
GND terminal. For very noisy systems, a small (0402 or 0201) 0.1 µF capacitor can be placed from VOS to GND
to filter high frequency noise on the VOS line.
10.1.3 Provide Thermal Path and Shielding
Using the available layers in the PCB can help provide additional shielding and improved thermal performance.
Large unbroken GND copper areas provide good thermal and return current paths. Flood unused PCB area with
GND copper. Use thermal vias to connect the GND copper between layers.
The required board area for proper thermal dissipation can be estimated using the power dissipation curves for
the desired output voltage and the package thermal resistance vs. board area curve. Refer to the power
dissipation graphs in the Typical Characteristics section. Using the power dissipation (PDISS) for the designed
input and output voltage and the max operating ambient temperature TA for the application, estimate the required
thermal resistance RθJA with the following expression.
RθJA - REQUIRED≤ (125ºC - TA) / PDISS
(8)
Then use Figure 80 to estimate the board copper area required to achieve the calculated thermal resistance.
100
2-LAYER 70 µm (2 oz) Cu
4-LAYER 70 µm (2 oz) Cu
90
80
70
60
50
40
30
20
0
5
10
15
20
Copper Area (cm2)
D012
Figure 80. Package Thermal Resistance vs. Board Copper Area
Copyright © 2012–2018, Texas Instruments Incorporated
27
LMZ21701
ZHCSD26E –AUGUST 2012–REVISED AUGUST 2018
www.ti.com.cn
Layout Guidelines (continued)
For example, for a design with 12-V input, 5-V output, and 1-A load the power dissipation according to Figure 7
is 0.53 W.
For 85°C ambient temperature, the RθJA-REQUIRED is ≤ (125°C – 85°C) / 0.53 W, or ≤ 75°C/W. Looking at
Figure 80 the minimum copper area required to achieve this thermal resistance with a 4-layer board and 70 µm
(2 oz) copper is approximately 3 cm².
10.2 Layout Example
The following example is for a 4-layer board. Layers 2 and 4 provide additional shielding and thermal path. If a 2-
layer board is used, apply the Layer 1 and Layer 3 copper patterns for the top and bottom layers, respectively.
28
Copyright © 2012–2018, Texas Instruments Incorporated
LMZ21701
www.ti.com.cn
ZHCSD26E –AUGUST 2012–REVISED AUGUST 2018
Layout Example (continued)
PLACE THE INPUT CAPACITOR AS CLOSE
AS POSSIBLE TO THE MODULE VIN AND
GND PINS
GND VIAS TO MINIMIZE INDUCTANCE IN
THE di/dt LOOP
VIN EN VOS GND
GND
VOUT VOUT
LAYER 1
SS FB PG
PLACE THE FEEDBACK DIVIDER AS CLOSE
AS POSSIBLE TO THE MODULE TO KEEP
THE FB NODE SMALL
LAYER 2
LAYER 3
UNBROKEN GND PLANE FOR THERMAL
PERFORMANCE AND SHIELDING
ENABLE CONNECTION
VOS CONNECTION t KEEP AWAY FROM
NOISE SOURCES
CONNECTION TO THE SOFTSTART
CAPACITOR
POWER GOOD FLAG CONNECTION
UNBROKEN GND PLANE FOR THERMAL
PERFORMANCE AND SHIELDING
LAYER 4
Figure 81. Layout example
Copyright © 2012–2018, Texas Instruments Incorporated
29
LMZ21701
ZHCSD26E –AUGUST 2012–REVISED AUGUST 2018
www.ti.com.cn
Layout Example (continued)
10.2.1 High Density Layout Example for Space Constrained Applications
10.2.1.1 35 mm² Solution Size (Single Sided)
The following layout example uses 0805 case size components for the input and output capacitors and 0402
case size components for the rest of the passives.
LAYER 1
LAYER 2
SS
FB
VIN
EN
VIN
PG
VOS
GND
GND
VOUT
GND
VOUT GND
LAYER 3
LAYER 4
VOS
VOUT
Figure 82. 35 mm² Solution Size (Single Sided)
30
版权 © 2012–2018, Texas Instruments Incorporated
LMZ21701
www.ti.com.cn
ZHCSD26E –AUGUST 2012–REVISED AUGUST 2018
11 器件和文档支持
11.1 器件支持
如需问题解答和设计检查，请访问德州仪器 (TI) E2E 社区支持论坛。
11.1.1 开发支持
11.1.1.1 使用 WEBENCH® 工具创建定制设计
请单击此处，使用 LMZ21701 器件并借助 WEBENCH® 电源设计器创建定制设计方案。
1. 首先输入输入电压 (VIN)、输出电压 (VOUT) 和输出电流 (IOUT) 要求。
2. 使用优化器拨盘优化该设计的关键参数，如效率、尺寸和成本。
3. 将生成的设计与德州仪器 (TI) 的其他可行的解决方案进行比较。
WEBENCH 电源设计器可提供定制原理图以及罗列实时价格和组件供货情况的物料清单。
在多数情况下，可执行以下操作：
•
•
•
•
运行电气仿真，观察重要波形以及电路性能
运行热性能仿真，了解电路板热性能
将定制原理图和布局方案以常用 CAD 格式导出
打印设计方案的 PDF 报告并与同事共享
有关 WEBENCH 工具的详细信息，请访问 www.ti.com.cn/WEBENCH。
11.2 商标
DCS-Control, MicroSiP are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.3 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.4 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
版权 © 2012–2018, Texas Instruments Incorporated
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LMZ21701
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www.ti.com.cn
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
12.1 Tape and Reel Information
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
Reel
Diameter
(mm)
Reel
Width W1
(mm)
Package
Type
Package
Drawing
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
Device
Pins
SPQ
LMZ21701SILR
LMZ21701SILT
uSiP
uSiP
SIL
SIL
8
8
3000
250
330.0
178.0
12.4
13.2
3.75
3.75
3.75
3.75
2.2
2.2
8.0
8.0
12.0
12.0
Q2
Q2
32
版权 © 2012–2018, Texas Instruments Incorporated
LMZ21701
www.ti.com.cn
ZHCSD26E –AUGUST 2012–REVISED AUGUST 2018
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
Device
Package Type
Package Drawing Pins
SPQ
3000
250
Length (mm) Width (mm)
Height (mm)
58.0
LMZ21701SILR
LMZ21701SILT
uSiP
uSiP
SIL
SIL
8
8
383.0
223.0
353.0
194.0
35.0
版权 © 2012–2018, Texas Instruments Incorporated
33
PACKAGE OPTION ADDENDUM
www.ti.com
17-Mar-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMZ21701SILR
LMZ21701SILT
ACTIVE
ACTIVE
uSiP
uSiP
SIL
SIL
8
8
3000 RoHS & Green
250 RoHS & Green
NIAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
1701 7485 EA
1701 7485 EA
Samples
Samples
NIAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
17-Mar-2023
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMZ21701SILR
uSiP
SIL
8
3000
330.0
12.4
3.75
3.75
2.2
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
uSiP SIL
SPQ
Length (mm) Width (mm) Height (mm)
383.0 353.0 58.0
LMZ21701SILR
8
3000
Pack Materials-Page 2
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
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