LMZ23603 [TI]
具有 36V 最大输入电压的 3A SIMPLE SWITCHER® 电源模块;
| 型号： | LMZ23603 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 36V 最大输入电压的 3A SIMPLE SWITCHER® 电源模块 电源电路 |
| 文件： | 总35页 (文件大小：1245K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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LMZ23603
SNVS711J –MARCH 2011–REVISED AUGUST 2015
®
LMZ23603 3-A SIMPLE SWITCHER Power Module With 36-V Maximum Input Voltage
1
1 Features
•
•
•
Integrated Shielded Inductor
2 Applications
Simple PCB Layout
•
Point-of-load Conversions from 12-V and 24-V
Input Rail
Frequency Synchronization Input (650 kHz to 950
kHz)
•
•
Time-Critical Projects
•
•
Flexible Startup Sequencing Using External Soft-
start, Tracking and Precision Enable
Space Constrained and High Thermal
Requirement Applications
Protection Against Inrush Currents and Faults
Such as Input UVLO and Output Short Circuit
•
Negative Output Voltage Applications (See AN-
2027, SNVA425)
•
•
Junction Temperature Range –40°C to 125°C
3 Description
Single Exposed Pad and Standard Pinout for Easy
Mounting and Manufacturing
The LMZ23603 SIMPLE SWITCHER® power module
is an easy-to-use step-down DC-DC solution capable
of driving up to 3-A load. The LMZ23603 is available
in an innovative package that enhances thermal
performance and allows for hand or machine
soldering.
•
Fast Transient Response for Powering FPGAs
and ASICs
Fully Enabled for WEBENCH® Power Designer
•
•
Pin Compatible With
LMZ22005/LMZ23605/LMZ22003
The LMZ23603 can accept an input voltage rail
between 6 V and 36 V and deliver an adjustable and
highly accurate output voltage as low as 0.8 V. The
LMZ23603 only requires two external resistors and
three external capacitors to complete the power
solution. The LMZ23603 is a reliable and robust
design with the following protection features: thermal
shutdown, programmable input undervoltage lockout,
output overvoltage protection, short circuit protection,
output current limit, and allows start-up into a
•
Performance Benefits
–
High Efficiency Reduces System Heat
Generation
–
Tested to EN55022 Class B
–
See AN-2125 (SNVA473) and layout for
information on device under test.
–
VIN = 24 V, VO = 3.3 V, IO = 3 A
NOTE: EN 55022:2006, +A1:2007, FCC Part 15 Subpart B: 2007.
prebiased
output.
The
sync
input
allows
–
Low component count, only 5 external
components
synchronization over the 650-kHz to 950-kHz
switching frequency range.
–
–
Low output voltage ripple
Device Information(1)(2)
Uses PCB as heat sink, no airflow required
PART NUMBER
PACKAGE
BODY SIZE (NOM)
•
Electrical Specifications
LMZ23603
NDW (7)
10.16 mm × 9.85 mm
–
–
–
–
–
18-W maximum total output power
Up to 3-A output current
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
(2) Peak reflow temperature equals 245°C. See SNAA214 for
more details.
Input voltage range 6 V to 36 V
Output voltage range 0.8 V to 6 V
Efficiency up to 92%
Simplified Application Schematic
Efficiency 5-V Output at 25°C Ambient
100
LMZ23603
90
80
70
V
IN
V
OUT
@ 3A
R
FBT
60
50
40
9 VIn
Enable
12 Vin
20 Vin
24 Vin
30 Vin
36 Vin
See Table
C
Co
220 PF
R
SS
FBB
C
IN
0.47 PF
See Table
22 PF
0
1
2
3
OUTPUT CURRENT (A)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMZ23603
SNVS711J –MARCH 2011–REVISED AUGUST 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 3
6.1 Absolute Maximum Ratings ...................................... 3
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 4
6.6 Typical Characteristics.............................................. 6
Detailed Description ............................................ 14
7.1 Overview ................................................................. 14
7.2 Functional Block Diagram ....................................... 14
7.3 Feature Description................................................. 14
7.4 Device Functional Modes........................................ 16
8
Application and Implementation ........................ 17
8.1 Application Information............................................ 17
8.2 Typical Application ................................................. 17
Power Supply Recommendations...................... 23
9
10 Layout................................................................... 23
10.1 Layout Guidelines ................................................. 23
10.2 Layout Examples................................................... 24
10.3 Power Dissipation and Thermal Considerations... 25
10.4 Power Module SMT Guidelines ............................ 26
11 Device and Documentation Support ................. 27
11.1 Device Support...................................................... 27
11.2 Documentation Support ........................................ 27
11.3 Community Resources.......................................... 27
11.4 Trademarks........................................................... 27
11.5 Electrostatic Discharge Caution............................ 27
11.6 Glossary................................................................ 27
7
12 Mechanical, Packaging, and Orderable
Information ........................................................... 28
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision I (October 2013) to Revision J
Page
•
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
•
Deleted Easy-to-Use PFM 7-Pin Package image .................................................................................................................. 1
Changes from Revision H (April 2013) to Revision I
Page
•
•
•
•
Deleted 12 mil......................................................................................................................................................................... 4
Changed 10 mil .................................................................................................................................................................... 23
Changed 10 mil .................................................................................................................................................................... 26
Added Power Module SMT Guidelines................................................................................................................................. 26
2
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SNVS711J –MARCH 2011–REVISED AUGUST 2015
5 Pin Configuration and Functions
NDW Package
7-Pin
Top View
VOUT
SS/TRK
FB
AGND
EN
7
6
5
4
3
2
1
PGND/EP
Connect to AGND
SYNC
VIN
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
NO.
AGND
4
Ground
Analog
Analog Ground — Reference point for all stated voltages. Must be externally connected to
EP/PGND.
EN
3
—
5
Enable — Input to the precision enable comparator. Rising threshold is 1.279 V typical. Once
the module is enabled, a 21-µA source current is internally activated to facilitate
programmable hysteresis.
EP/PGND
FB
Ground
Analog
Analog
Analog
Exposed Pad / Power Ground Electrical path for the power circuits within the module. — NOT
Internally connected to AGND / pin 4. Used to dissipate heat from the package during
operation. Must be electrically connected to pin 4 external to the package.
Feedback — Internally connected to the regulation, overvoltage, and short circuit comparators.
The regulation reference point is 0.796 V at this input pin. Connect the feedback resistor
divider between the output and AGND to set the output voltage.
SS/TRK
SYNC
6
Soft-Start/Track — To extend the 1.6-ms internal soft-start connect an external soft-start
capacitor. For tracking connect to an external resistive divider connected to a higher priority
supply rail. See Design Steps for the LMZ23603 Application section.
2
Sync Input — Apply a CMOS logic level square wave whose frequency is between 650 kHz
and 950 kHz to synchronize the PWM operating frequency to an external frequency source.
When not using synchronization connect to ground. The module free running PWM frequency
is 812 kHz (typical).
VIN
1
7
Power
Power
Supply input — Nominal operating range is 6 V to 36 V. A small amount of internal
capacitance is contained within the package assembly. Additional external input capacitance
is required between this pin and exposed pad (PGND).
VOUT
Output Voltage — Output from the internal inductor. Connect the output capacitor between this
pin and exposed pad.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)(2)(3)
MIN
–0.3
–0.3
–0.3
–0.3
MAX
40
UNIT
V
VIN to PGND
EN, SYNC to AGND
5.5
V
SS/TRK, FBto AGND
AGND to PGND
2.5
V
0.3
V
Junction Temperature
Peak Reflow Case Temperature (30 sec)
Storage temperature, Tstg
150
245
150
°C
°C
°C
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(3) For soldering specifications: see product folder at www.ti.com and SNOA549
Copyright © 2011–2015, Texas Instruments Incorporated
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SNVS711J –MARCH 2011–REVISED AUGUST 2015
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6.2 ESD Ratings
VALUE
UNIT
V(ESD)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)(2)
±2000
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) The human body model is a 100pF capacitor discharged through a 1.5 kΩ resistor into each pin. Test method is per JESD-22-114.
6.3 Recommended Operating Conditions
MIN
6
MAX
36
UNIT
V
VIN
EN, SYNC
0
5
V
Operation Junction Temperature
−40
125
°C
6.4 Thermal Information
LMZ23603
NDW
THERMAL METRIC(1)
UNIT
7 PINS
4-layer Evaluation Printed-Circuit-Board, 60 vias, No
air flow
12.0
21.5
1.9
Junction-to-ambient thermal
RθJA
°C/W
°C/W
resistance(2)
2-layer JEDEC Printed-Circuit-Board, No air flow
Junction-to-case (top) thermal
resistance
RθJC(top)
No air flow
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(2)
RθJA measured on a 3.5-in × 3.5-in 4-layer board, with 3-oz. copper on outer layers and 2-oz. copper on inner layers, sixty thermal vias,
no air flow, and 1-W power dissipation. Refer to PCB layout diagrams.
6.5 Electrical Characteristics
Limits are for TJ = 25°C unless otherwise specified. Minimum and Maximum limits are specified through test, design or
statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference
purposes only. Unless otherwise stated the following conditions apply: VIN = 12V, VOUT = 3.3V
PARAMETER
SYSTEM PARAMETERS
ENABLE CONTROL
TEST CONDITIONS
MIN(1) TYP(2)
MAX(1) UNIT
1.279
1.1
VEN
EN threshold trip point
VEN rising
V
over the junction temperature (TJ)
range of –40°C to +125°C
1.458
EN input hysteresis
current
VEN-HYS
VEN > 1.279 V
–21
µA
SOFT-START
50
ISS
tSS
SS source current
VSS = 0 V
µA
60
over the junction temperature (TJ)
range of –40°C to +125°C
40
Internal soft-start interval
1.6
ms
CURRENT LIMIT
over the junction temperature (TJ)
range of –40°C to +125°C
ICL
Current limit threshold
DC average
3.4
A
INTERNAL SWITCHING OSCILLATOR
Free-running oscillator
frequency
fosc
Sync input connected to ground.
711
650
812
914 kHz
950 kHz
fsync
Synchronization range
(1) Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation
using Statistical Quality Control (SQC) methods. Limits are used to calculate TI’s Average Outgoing Quality Level (AOQL).
(2) Typical numbers are at 25°C and represent the most likely parametric norm.
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SNVS711J –MARCH 2011–REVISED AUGUST 2015
Electrical Characteristics (continued)
Limits are for TJ = 25°C unless otherwise specified. Minimum and Maximum limits are specified through test, design or
statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference
purposes only. Unless otherwise stated the following conditions apply: VIN = 12V, VOUT = 3.3V
PARAMETER
TEST CONDITIONS
MIN(1) TYP(2)
MAX(1) UNIT
Synchronization logic zero
amplitude
over the junction temperature (TJ)
range of –40°C to +125°C
VIL-sync
VIH-sync
Vsync DC
Dmax
Relative to AGND
0.4
V
V
Synchronization logic one Relative to
amplitude
over the junction temperature (TJ)
range of –40°C to +125°C
1.5
AGND.
Synchronization duty
cycle range
15%
50%
83%
85%
Maximum Duty Factor
REGULATION AND OVERVOLTAGE COMPARATOR
VSS >+ 0.8 V
0.796
In-regulation feedback
voltage
TJ = –40°C to
125°C
IO = 3 A
VFB
V
over the junction temperature (TJ)
range of –40°C to +125°C
0.776
0.816
Feedback overvoltage
protection threshold
0.86
5
VFB-OV
IFB
V
Feedback input bias
current
nA
mA
μA
Non-switchinginput
current
2.6
70
IQ
VFB= 0.86 V
VEN= 0 V
Shutdown quiescent
current
ISD
THERMAL CHARACTERISTICS
TSD
Thermal shutdown
Rising
Falling
165
15
°C
°C
TSD-HYST
Thermal shutdown
hysteresis
PERFORMANCE PARAMETERS(3)
ΔVO
Output voltage ripple
Cout = 220 µF with 7-mΩ ESR + 100-µF X7R + 2 x
0.047-µF BW at 20 MHz
9
mVPP
mV/A
ΔVO/ΔVIN
ΔVO/IOUT
η
Line regulation
VIN = 12 V to 36 V, IO= 0.001 A
VIN = 12 V, IO= 0.001 A to 3 A
VIN = 12 V VO = 3.3 V, IO = 3 A
VIN = 24 V VO = 3.3 V, IO = 3 A
VIN = 24 V VO = 3.3 V, IO = 2 A
VIN = 12 V VO = 3.3 V, IO = 1 A
±0.02%
1
Load regulation
Full load efficiency
85%
78%
80%
86%
η
Peak efficiency
(3) Refer to BOM in Table 1.
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6.6 Typical Characteristics
Unless otherwise specified, the following conditions apply: VIN = 12 V; CIN = 2 x 10 μF + 1-μF X7R Ceramic; CO = 220-μF
Specialty Polymer + 10-µF Ceramic; TA = 25°C for waveforms. Efficiency and dissipation plots marked with * have cycle
skipping at light loads resulting is slightly higher output ripple – See Design Steps section.
100
90
80
70
60
50
40
4
3
2
1
0
36 Vin
30 Vin
24 Vin
20 Vin
12 Vin
10 Vin
10 Vin
12 Vin
20 Vin
24 Vin
30 Vin
36 Vin
0
1
2
3
0
1
2
3
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Figure 1. Efficiency 6-V Output at 25°C Ambient
Figure 2. Dissipation 6-V Output at 25°C Ambient
100
4
36 Vin
30 Vin
24 Vin
20 Vin
90
80
70
12 Vin
9 Vin
3
2
1
0
60
50
40
9 VIn
12 Vin
20 Vin
24 Vin
30 Vin
36 Vin
0
1
2
3
0
1
2
3
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Figure 3. Efficiency 5-V Output at 25°C Ambient
Figure 4. Dissipation 5-V Output at 25°C Ambient
100
4
36 Vin
30 Vin
24 Vin
20 Vin
90
80
70
12 Vin
9 Vin
3
2
1
0
60
50
40
9 Vin
12 Vin
20 Vin
24 Vin
30 Vin
36 Vin
0
1
2
3
0
1
2
3
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Figure 5. Efficiency 3.3-V Output at 25°C Ambient
Figure 6. Dissipation 3.3-V Output at 25°C Ambient
6
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SNVS711J –MARCH 2011–REVISED AUGUST 2015
Typical Characteristics (continued)
Unless otherwise specified, the following conditions apply: VIN = 12 V; CIN = 2 x 10 μF + 1-μF X7R Ceramic; CO = 220-μF
Specialty Polymer + 10-µF Ceramic; TA = 25°C for waveforms. Efficiency and dissipation plots marked with * have cycle
skipping at light loads resulting is slightly higher output ripple – See Design Steps section.
90
80
70
60
50
40
30
4
3
2
1
0
36 Vin
30 Vin
24 Vin
20 Vin
12 Vin
9 Vin
6 Vin
6 Vin
9 Vin
12 Vin
20 Vin
24 Vin
30 Vin
36 Vin
0
1
2
3
0
1
2
3
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Figure 7. Efficiency 2.5-V Output at 25°C Ambient
Figure 8. Dissipation 2.5-V Output at 25°C Ambient
90
4
36 Vin*
30 Vin
24 Vin
20 Vin
80
70
60
12 Vin
9 Vin
6 Vin
3
2
1
0
6 Vin
50
9 Vin
12 Vin
20 Vin
40
24 Vin
30 Vin
36 Vin*
30
0
1
2
3
0
1
2
3
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Figure 9. Efficiency 1.8-V Output at 25°C Ambient
Figure 10. Dissipation 1.8-V Output at 25°C Ambient
85
4
36 Vin*
30 Vin*
24 Vin
20 Vin
75
65
12 Vin
9 Vin
6 Vin
3
2
1
0
55
6 Vin
45
35
25
9 Vin
12 Vin
20 Vin
24 Vin
30 Vin*
36 Vin*
0
1
2
3
0
1
2
3
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Figure 11. Efficiency 1.5-V Output at 25°C Ambient
Figure 12. Dissipation 1.5-V Output at 25°C Ambient
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Typical Characteristics (continued)
Unless otherwise specified, the following conditions apply: VIN = 12 V; CIN = 2 x 10 μF + 1-μF X7R Ceramic; CO = 220-μF
Specialty Polymer + 10-µF Ceramic; TA = 25°C for waveforms. Efficiency and dissipation plots marked with * have cycle
skipping at light loads resulting is slightly higher output ripple – See Design Steps section.
80
70
60
50
40
30
20
4
3
2
1
0
36 Vin*
30 Vin*
24 Vin
20 Vin
12 Vin
9 Vin
6 Vin
6 Vin
9 Vin
12 Vin
20 Vin
24 Vin
30 Vin*
36 Vin*
0
1
2
3
0
1
2
3
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Figure 13. Efficiency 1.2-V Output at 25°C Ambient
Figure 14. Dissipation 1.2-V Output at 25°C Ambient
80
4
36 Vin*
30 Vin*
24 Vin*
20 Vin
70
60
50
12 Vin
9 VIn
6 Vin
3
2
1
0
6 Vin
40
9 Vin
12 Vin
20 Vin
30
24 Vin*
30 Vin*
36 Vin*
20
0
1
2
3
0
1
2
3
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Figure 15. Efficiency 1-V Output at 25°C Ambient
Figure 16. Dissipation 1-V Output at 25°C Ambient
70
4
36 Vin*
30 Vin*
24 Vin*
20 Vin*
60
50
40
12 Vin
9 Vin
6 Vin
3
2
1
0
6 Vin
30
9 Vin
12 Vin
20 Vin*
20
24 Vin*
30 Vin*
36 Vin*
10
0
1
2
3
0
1
2
3
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Figure 17. Efficiency 0.8-V Output at 25°C Ambient
Figure 18. Dissipation 0.8-V Output at 25°C Ambient
8
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SNVS711J –MARCH 2011–REVISED AUGUST 2015
Typical Characteristics (continued)
Unless otherwise specified, the following conditions apply: VIN = 12 V; CIN = 2 x 10 μF + 1-μF X7R Ceramic; CO = 220-μF
Specialty Polymer + 10-µF Ceramic; TA = 25°C for waveforms. Efficiency and dissipation plots marked with * have cycle
skipping at light loads resulting is slightly higher output ripple – See Design Steps section.
100
4
36 Vin
30 Vin
90
80
70
60
50
40
24 Vin
20 Vin
12 Vin
10 Vin
3
2
1
0
10 Vin
12 Vin
20 Vin
24 Vin
30 Vin
36 Vin
0
1
2
3
4
5
0
1
2
3
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Figure 19. Efficiency 6-V Output at 85°C
Figure 20. Dissipation 6-V Output at 85°C Ambient
100
4
36 Vin
30 Vin
24 Vin
20 Vin
90
80
70
12 Vin
9 Vin
3
2
1
0
60
50
40
9 Vin
12 Vin
20 Vin
24 Vin
30 Vin
36 Vin
0
1
2
3
0
1
2
3
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Figure 22. Dissipation 5-V Output at 85°C Ambient
Figure 21. Efficiency 5-V Output at 85°C Ambient
90
4
36 Vin
30 Vin
24 Vin
20 Vin
80
70
60
12 Vin
9 Vin
3
2
1
0
50
9 Vin
12 Vin
20 Vin
40
30
24 Vin
30 Vin
36 Vin
0
1
2
3
0
1
2
3
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Figure 23. Efficiency 3.3-V Output at 85°C Ambient
Figure 24. Dissipation 3.3-V Output at 85°C Ambient
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Typical Characteristics (continued)
Unless otherwise specified, the following conditions apply: VIN = 12 V; CIN = 2 x 10 μF + 1-μF X7R Ceramic; CO = 220-μF
Specialty Polymer + 10-µF Ceramic; TA = 25°C for waveforms. Efficiency and dissipation plots marked with * have cycle
skipping at light loads resulting is slightly higher output ripple – See Design Steps section.
90
4
36 Vin
30 Vin
24 Vin
20 Vin
12 Vin
9 Vin
80
70
60
50
40
30
3
2
1
0
6 Vin
6 Vin
9 Vin
12 Vin
20 Vin
24 Vin
30 Vin
36 Vin
0
1
2
3
0
1
2
3
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Figure 26. Dissipation 2.5-V Output at 85°C Ambient
Figure 25. Efficiency 2.5-V Output at 85°C Ambient
90
4
36 Vin*
30 Vin
24 Vin
20 Vin
12 Vin
9 Vin
6 Vin
80
70
60
3
2
1
0
6 Vin
50
9 Vin
12 Vin
20 Vin
40
24 Vin
30 Vin
36 Vin*
30
0
1
2
3
0
1
2
3
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Figure 27. Efficiency 1.8-V Output at 85°C Ambient
Figure 28. Dissipation 1.8-V Output at 85°C Ambient
80
4
36 Vin*
30 Vin*
24 Vin
20 Vin
12 Vin
9 Vin
6 Vin
70
60
50
3
2
1
0
6 Vin
40
9 Vin
12 Vin
20 Vin
30
24 Vin
30 Vin*
36 Vin*
20
0
1
2
3
0
1
2
3
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Figure 29. Efficiency 1.5-V Output at 85°C Ambient
Figure 30. Dissipation 1.5-V Output at 85°C Ambient
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Typical Characteristics (continued)
Unless otherwise specified, the following conditions apply: VIN = 12 V; CIN = 2 x 10 μF + 1-μF X7R Ceramic; CO = 220-μF
Specialty Polymer + 10-µF Ceramic; TA = 25°C for waveforms. Efficiency and dissipation plots marked with * have cycle
skipping at light loads resulting is slightly higher output ripple – See Design Steps section.
80
4
36 Vin*
30 Vin*
70
60
50
40
30
20
24 Vin
20 Vin
12 Vin
9 Vin
3
2
1
0
6 Vin
6 Vin
9 Vin
12 Vin
20 Vin
24 Vin
30 Vin*
36 Vin*
0
1
2
3
0
1
2
3
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Figure 31. Efficiency 1.2-V Output at 85°C Ambient
Figure 32. Dissipation 1.2-V Output at 85°C Ambient
75
4
36 Vin*
30 Vin*
24 Vin*
20 Vin
12 Vin
9 Vin
6 Vin
65
55
3
2
1
0
45
6 Vin
35
25
15
9 Vin
12 Vin
20 Vin
24 Vin*
30 Vin*
36 Vin*
0
1
2
3
0
1
2
3
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Figure 33. Efficiency 1-V Output at 85°C Ambient
Figure 34. Dissipation 1-V Output at 85°C Ambient
70
4
36 Vin*
30 Vin*
24 Vin*
20 Vin*
12 Vin
9 Vin
6 Vin
60
50
3
2
1
0
40
6 Vin
9 Vin
12 Vin
20 Vin*
24 Vin*
30 Vin*
36 Vin*
30
20
0
1
2
3
0
1
2
3
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Figure 35. Efficiency 0.8-V Output at 85°C Ambient
Figure 36. Dissipation 0.8-V Output at 85°C Ambient
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Typical Characteristics (continued)
Unless otherwise specified, the following conditions apply: VIN = 12 V; CIN = 2 x 10 μF + 1-μF X7R Ceramic; CO = 220-μF
Specialty Polymer + 10-µF Ceramic; TA = 25°C for waveforms. Efficiency and dissipation plots marked with * have cycle
skipping at light loads resulting is slightly higher output ripple – See Design Steps section.
4
3
2
1
0
4
3
2
1
0
ꢀJA = 12°C/W
ꢀJA = 12 °C/W
30 40 50 60 70 80 90 100 110 120 130
AMBIENT TEMPERATURE (°C)
30 40 50 60 70 80 90 100 110 120 130
AMBIENT TEMPERATURE (°C)
VIN = 12 V, VOUT = 5 V
VIN = 12 V, VOUT = 3.3 V
Figure 37. Thermal Derating
Figure 38. Thermal Derating
4
3
2
1
0
4
3
2
1
0
ꢀJA=12°C/W
ꢀJA=12°C/W
30 40 50 60 70 80 90 100 110 120 130
AMBIENT TEMPERATURE (°C)
30 40 50 60 70 80 90 100 110 120 130
ANBIENT TEMPERATURE (°C)
VIN = 24 V, VOUT = 5 V
VIN = 24 V, VOUT = 3.3 V
Figure 39. Thermal Derating
Figure 40. Thermal Derating
1.002
1.001
1.000
0.999
0.998
9 Vin
12 Vin
20 Vin
24 Vin
30 Vin
36 Vin
10 mV/Div
500 ns/Div
0
1
2
3
OUTPUT CURRENT (A)
12 VIN, 3.3 VO at 3 A, BW = 20 MHz
VOUT = 3.3 V Normalized
Figure 42. Output Ripple from Evaluation Board
Figure 41. Normalized Line and Load Regulation
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Typical Characteristics (continued)
Unless otherwise specified, the following conditions apply: VIN = 12 V; CIN = 2 x 10 μF + 1-μF X7R Ceramic; CO = 220-μF
Specialty Polymer + 10-µF Ceramic; TA = 25°C for waveforms. Efficiency and dissipation plots marked with * have cycle
skipping at light loads resulting is slightly higher output ripple – See Design Steps section.
2A/Div
10 mV/Div
500 ns/Div
100 mV/Div
500 µs/Div
12 VIN, 3.3 VO at 3 A BW = 250 MHz
12 VIN, 3.3 VO, 0.5- to 3-A Step
Figure 43. Output Ripple from Evaluation Board
Figure 44. Transient Response from Evaluation Board
9
8
7
6
5
4
3
2
1
0
Output Current
Input Current
0
4
8
12 16 20 24 28 32 36
INPUT VOLTAGE (V)
Figure 45. Short Circuit Current
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7 Detailed Description
7.1 Overview
The architecture used is an internally compensated emulated peak current mode control, based on a monolithic
synchronous SIMPLE SWITCHER core capable of supporting high load currents. The output voltage is
maintained through feedback compared with an internal 0.8-V reference. For emulated peak current-mode, the
valley current is sampled on the down-slope of the inductor current. This is used as the DC value of current to
start the next cycle.
The primary application for emulated peak current-mode is high input voltage to low output voltage operating at a
narrow duty cycle. By sampling the inductor current at the end of the switching cycle and adding an external
ramp, the minimum ON-time can be significantly reduced, without the need for blanking or filtering which is
normally required for peak current-mode control.
7.2 Functional Block Diagram
V
IN
Linear
Regulator
2M
C
IN
CINint
CBST
EN
SYNC
SS/TRK
800 kHz
PWM
V
O
3.3 uH
0.796 VREF
FB
CSS
RFBT
RFBB
C
O
Comp
EP/
PGND
AGND
Regulator IC
Internal Passives
7.3 Feature Description
7.3.1 Synchronization Input
The PWM switching frequency can be synchronized to an external frequency source. If this feature is not used,
connect this input either directly to ground, or connect to ground through a resistor of 1.5-kΩ or less. The allowed
synchronization frequency range is 650 kHz to 950 kHz. The typical input threshold is 1.4-V transition level.
Ideally the input clock must overdrive the threshold by a factor of 2, so direct drive from 3.3-V logic through a 1.5-
kΩ Thevenin source resistance is recommended. Applying a sustained logic 1 corresponds to zero Hz PWM
frequency and will cause the module to stop switching.
7.3.2 Output Overvoltage Protection
If the voltage at FB is greater than a 0.86-V internal reference, the output of the error amplifier is pulled toward
ground, causing VO to fall.
7.3.3 Current Limit
The LMZ23603 is protected by both low-side (LS) and high-side (HS) current limit circuitry. The LS current limit
detection is carried out during the OFF-time by monitoring the current through the LS synchronous MOSFET.
Referring to the Functional Block Diagram, when the top MOSFET is turned off, the inductor current flows
through the load, the PGND pin and the internal synchronous MOSFET. If this current exceeds the low-side
current limit level the current limit comparator disables the start of the next switching period. Switching cycles are
prohibited until current drops below the limit.
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Feature Description (continued)
NOTE
DC current limit is dependent on both duty cycle and temperature as illustrated in the
graphs in the Typical Characteristics section.
The HS current limit monitors the current of top side MOSFET. Once HS current limit is detected, the HS
MOSFET is shutoff immediately, until the next cycle. Exceeding HS current limit causes VO to fall. Typical
behavior of exceeding LS current limit is that fSW drops to 1/2 of the operating frequency.
7.3.4 Thermal Protection
The junction temperature of the LMZ23603 must not be allowed to exceed its maximum ratings. Thermal
protection is implemented by an internal Thermal Shutdown circuit which activates at 165°C (typical) causing the
device to enter a low power standby state. In this state the main MOSFET remains off causing VO to fall, and
additionally the CSS capacitor is discharged to ground. Thermal protection helps prevent catastrophic failures for
accidental device overheating. When the junction temperature falls back below 150°C (typical hysteresis = 15°C)
the SS pin is released, VO rises smoothly, and normal operation resumes.
Applications requiring maximum output current especially those at high input voltage may require additional
derating at elevated temperatures.
7.3.5 Prebiased Start-Up
The LMZ23603 will properly start up into a prebiased output. This start-up situation is common in multiple rail
logic applications where current paths may exist between different power rails during the start-up sequence.
Figure 46 shows proper behavior in this mode. Trace one is Enable going high. Trace two is 1.5-V prebias rising
to 3.3 V. Rise-time determined by CSS, trace three.
Figure 46. Prebiased Start-Up
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7.4 Device Functional Modes
7.4.1 Discontinuous Conduction and Continuous Conduction Modes
At light load the regulator will operate in discontinuous conduction mode (DCM). With load currents above the
critical conduction point, it will operate in continuous conduction mode (CCM). In CCM, current flows through the
inductor through the entire switching cycle and never falls to zero during the OFF-time. When operating in DCM,
inductor current is maintained to an average value equaling IOUT. Inductor current exhibits normal behavior for
the emulated current mode control method used. Output voltage ripple typically increases during this mode of
operation.
Figure 47 is a comparison pair of waveforms of the showing both CCM (upper) and DCM operating modes.
800 kHz Sync
CCM Mode
DCM Mode
VIN = 12V, VO = 3.3V, IO = 3 A / 0.3 A 2 μs/div
Figure 47. CCM and DCM Operating Modes
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LMZ23603 is a step-down DC-to-DC power module. It is typically used to convert a higher DC voltage to a
lower DC voltage with a maximum output current of 3 A. The following design procedure can be used to select
components for the LMZ23603. Alternately, the WEBENCH software may be used to generate complete designs.
When generating a design, the WEBENCH software uses iterative design procedure and accesses
comprehensive databases of components. Please go to www.ti.com for more details.
8.2 Typical Application
U1
7V to 36V
PGND/EP
V
IN
Enable
LMZ23603TZ
3.3V @ 3A
+
O
C
6 OPT
IN
150 PF
R
FBT
R
ENT
3.32k
42.2k
SYNC
R
FRA
OPT
23.7Ö
R
FBB
R
OPT
ENH
100Ö
1,5
1.07k
C
SS
0.47µF
D1 OPT
5.1V
+
C
C 5
O
IN
0.047 PF
OPT
C 2
O
C
1,6
O
R
ENB
220 PF
100 PF
OPT
0.047 PF
C
2,3
IN
12.7k
R
SN
10 PF
1.50 kÖ
Figure 48. Simplified Evaluation Board Schematic Diagram
8.2.1 Design Requirements
For this example the following application parameters exist.
•
•
•
VIN Range = Up to 36 V
VOUT = 0.8 V to 6 V
IOUT = 3 A
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Typical Application (continued)
8.2.2 Detailed Design Procedure
8.2.2.1 Design Steps
The LMZ23603 is fully supported by WEBENCH which offers: component selection, electrical and thermal
simulations. Additionally there are both evaluation and demonstration boards that may be used as a starting point
for design. The following list of steps can be used to manually design the LMZ23603 application.
All references to values refer to Figure 48.
1. Select minimum operating VIN with enable divider resistors
2. Program VO with resistor divider selection
3. Select CO
4. Select CIN
5. Determine module power dissipation
6. Layout PCB for required thermal performance
8.2.2.2 Enable Divider, RENT, RENB and RENH Selection
Internal to the module is a 2-MΩ pullup resistor connected from VIN to Enable. For applications not requiring
precision undervoltage lockout (UVLO), the Enable input may be left open circuit and the internal resistor will
always enable the module. In such case, the internal UVLO occurs around 4.3 V.
In applications with separate supervisory circuits Enable can be directly interfaced to a logic source. In the case
of sequencing supplies, the divider is connected to a rail that becomes active earlier in the power-up cycle than
the LMZ23603 output rail.
Enable provides a precise 1.279-V threshold to allow direct logic drive or connection to a voltage divider from a
higher enable voltage such as VIN. Additionally there is 21 μA (typical) of switched offset current allowing
programmable hysteresis. See Figure 49.
The function of the enable divider is to allow the designer to choose an input voltage below which the circuit will
be disabled. This implements the feature of programmable UVLO. The two resistors must be chosen based on
the following ratio:
RENT / RENB = (VIN UVLO / 1.279 V) – 1
(1)
The LMZ23603 typical application shows 12.7 kΩ for RENB and 42.2 kΩ for RENT resulting in a rising UVLO of
5.46 V. This divider presents 8.33 V to the input when the divider is raised to 36 V which would exceed the
recommended 5.5-V limit for Enable. A midpoint 5.1-V Zener clamp is applied to allow the application to cover
the full 6-V to 36-V range of operation. The Zener clamp is not required if the target application prohibits the
maximum Enable input voltage from being exceeded.
Additional enable voltage hysteresis can be added with the inclusion of RENH. It is possible to select values for
RENT and RENB such that RENH is a value of zero allowing it to be omitted from the design.
Rising threshold can be calculated as follows:
VEN(rising) = 1.279 ( 1 + (RENT|| 2 meg)/ RENB
)
(2)
(3)
Whereas the falling threshold level can be calculated using:
VEN(falling) = VEN(rising) – 21 µA ( RENT|| 2 meg || RENTB + RENH
)
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Typical Application (continued)
INT-VCC (5V)
VIN
21 PA
2.0M
RENT
42.2k
RENH
ENABLE
RUN
100:
RENB
12.7k
5.1V
1.279V
Figure 49. Enable Input Detail
8.2.2.3 Output Voltage Selection
Output voltage is determined by a divider of two resistors connected between VO and ground. The midpoint of
the divider is connected to the FB input.
The regulated output voltage determined by the external divider resistors RFBT and RFBB is:
VO = 0.796 V × (1 + RFBT / RFBB
)
(4)
(5)
Rearranging terms; the ratio of the feedback resistors for a desired output voltage is:
RFBT / RFBB = (VO / 0.796 V) – 1
These resistors must generally be chosen from values in the range of 1.0 kΩ to 10.0 kΩ.
For VO = 0.8 V the FB pin can be connected to the output directly and RFBB can be set to 8.06 kΩ to provide
minimum output load.
Table 1 lists values for RFBT , and RFBB
.
Table 1. Evaluation Board Bill of Materials
REF DES
U1
DESCRIPTION
CASE SIZE
PFM-7
1206
CASE SIZE
MANUFACTURER P/N
LMZ23603TZ
SIMPLE SWITCHER
0.047 µF, 50 V, X7R
10 µF, 50 V, X7R
CAP, AL, 150 µF, 50 V
0.047 µF, 50 V, X7R
100 µF, 6.3 V, X7R
220 μF, 6.3 V, SP-Cap
3.32 kΩ
Texas Instruments
Yageo America
Taiyo Yuden
Panasonic
Yageo America
TDK
Cin1,5
CC1206KRX7R9BB473
UMK325BJ106MM-T
EEE-FK1H151P
Cin2,3
1210
Cin6 (OPT)
CO1,6
Radial G
1206
CC1206KRX7R9BB473
C3225X5R0J107M
EEF-UE0J221LR
CO2 (OPT)
CO5
1210
(7343)
0805
Panasonic
Panasonic
Panasonic
Vishay Dale
Panasonic
Panasonic
Vishay Dale
Vishay Dale
AVX
RFBT
ERJ-6ENF3321V
RFBB
1.07 kΩ
0805
ERJ-6ENF1071V
RSN (OPT)
RENT
1.50 kΩ
0805
CRCW08051K50FKEA
ERJ-6ENF4222V
42.2 kΩ
0805
RENB
12.7 kΩ
0805
ERJ-6ENF1272V
RFRA(OPT)
RENH
23.7 Ω
0805
CRCW080523R7FKEA
CRCW0805100RFKEA
0805YC474KAT2A
MMSZ5231BS-7-F
100 Ω
0805
CSS
0.47 μF, ±10%, X7R, 16 V
5.1 V, 0.5 W
0805
D1(OPT)
SOD-123
Diodes Inc.
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8.2.2.4 Soft-Start Capacitor Selection
Programmable soft-start permits the regulator to slowly ramp to its steady state operating point after being
enabled, thereby reducing current inrush from the input supply and slowing the output voltage rise-time.
Upon turnon, after all UVLO conditions have been passed, an internal 1.6-ms circuit slowly ramps the SS/TRK
input to implement internal soft-start. If 1.6 ms is an adequate turnon time then the Css capacitor can be left
unpopulated. Longer soft-start periods are achieved by adding an external capacitor to this input.
Soft-start duration is given by the formula:
tSS = VREF × CSS / Iss = 0.796 V × CSS / 50 µA
(6)
This equation can be rearranged as follows:
CSS = tSS × 50 μA / 0.796 V
(7)
Using a 0.22-μF capacitor results in 3.5-ms typical soft-start duration; and 0.47-μF results in 7.5 ms typical. 0.47
μF is a recommended initial value.
As the soft-start input exceeds 0.796 V the output of the power stage will be in regulation and the 50-μA current
is deactivated. The following conditions will reset the soft-start capacitor by discharging the SS input to ground
with an internal current sink.
•
•
•
The Enable input being pulled low
Thermal shutdown condition
Internal VCC UVLO (Approx 4.3-V input to VIN)
8.2.2.5 Tracking Supply Divider Option
The tracking function allows the module to be connected as a slave supply to a primary voltage rail (often the
3.3-V system rail) where the slave module output voltage is lower than that of the master. Proper configuration
allows the slave rail to power up coincident with the master rail such that the voltage difference between the rails
during ramp-up is small (that is, < 0.15 V typical). The values for the tracking resistive divider must be selected
such that the presence of the internal 50-µA current source is minimized. In most cases the ratio of the tracking
divider resistors is the same as the ratio of the output voltage setting divider. Proper operation in tracking mode
dictates the soft-start time of the slave rail be shorter than the master rail; a condition that is easy satisfy
because the CSS cap is replaced by RTKB. The tracking function is only supported for the power up interval of the
master supply; once the SS/TRK rises past 0.8 V the input is no longer enabled and the 50-µA internal current
source is switched off.
3.3V Master
2.5Vout
Int VCC
50 PA
Rfbt
2.26k
Rtkt
226
SS/TRK
FB
Rtkb
107
Rfbb
1.07k
Figure 50. Tracking Option Input Detail
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8.2.2.6 CO Selection
None of the required CO output capacitance is contained within the module. A minimum value of 200 μF is
required based on the values of internal compensation in the error amplifier. Low ESR tantalum, organic
semiconductor or specialty polymer capacitor types are recommended for obtaining lowest ripple. The output
capacitor CO may consist of several capacitors in parallel placed in close proximity to the module. The output
capacitor assembly must also meet the worst case minimum ripple current rating of 0.5 × ILR P-P, as calculated in
Equation 14 below. Beyond that, additional capacitance will reduce output ripple so long as the ESR is low
enough to permit it. Loop response verification is also valuable to confirm closed loop behavior. RLRA is included
on the typical application schematic and evaluation board for this purpose. It is not required in the end design.
For applications with dynamic load steps; the following equation provides a good first pass approximation of CO
for load transient requirements. Where VO-Tran is 100 mV on a 3.3-V output design.
CO ≥ IO-Tran / ((VO-Tran– ESR × IO–Tran) × ( FSW / VO))
(8)
Solving:
CO ≥ 2.5 A / ((0.1 V – .007 × 2.5 A) × ( 800000 Hz / 3.3 V) ≥ 125 μF
(9)
NOTE
The stability requirement for 200-µF minimum output capacitance will take precedence.
One recommended output capacitor combination is a 220-µF, 7-mΩ ESR specialty polymer cap in parallel with a
100-µF, 6.3-V X5R ceramic. This combination provides excellent performance that may exceed the requirements
of certain applications. Additionally some small ceramic capacitors can be used for high frequency EMI
suppression.
8.2.2.7 CIN Selection
The LMZ23603 module contains a small amount of internal ceramic input capacitance. Additional input
capacitance is required external to the module to handle the input ripple current of the application. The input
capacitor can be several capacitors in parallel. This input capacitance must be located in very close proximity to
the module. Input capacitor selection is generally directed to satisfy the input ripple current requirements rather
than by capacitance value. Input ripple current rating is dictated by the equation:
I(CIN(RMS)) ≊ 1 /2 × IO × SQRT (D / 1–D)
where
•
D ≊ VO / VIN
(10)
As a point of reference, the worst case ripple current will occur when the module is presented with full load
current and when VIN = 2 × VO.
Recommended minimum input capacitance is 22-µF X7R (or X5R) ceramic with a voltage rating at least 25%
higher than the maximum applied input voltage for the application. It is also recommended that attention be paid
to the voltage and temperature derating of the capacitor selected.
NOTE
Ripple current rating of ceramic capacitors may be missing from the capacitor data sheet
and you may have to contact the capacitor manufacturer for this parameter.
If the system design requires a certain minimum value of peak-to-peak input ripple voltage (ΔVIN) be maintained
then the following equation may be used.
CIN ≥ IO × D × (1–D) / fSW-CCM × ΔVIN
(11)
If ΔVIN is 1% of VIN for a 12-V input to 3.3-V output application this equals 120 mV and fSW = 812 kHz.
CIN ≥ 3 A × 3.3 V / 12 V × (1– 3.3 V / 12 V) / (812000 × 0.240 V) ≥ 22.3 μF
(12)
Additional bulk capacitance with higher ESR may be required to damp any resonant effects of the input
capacitance and parasitic inductance of the incoming supply lines. The LMZ23603 typical applications schematic
and evaluation board include a 150-μF, 50-V aluminum capacitor for this function. There are many situations
where this capacitor is not necessary.
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8.2.2.8 Discontinuous Conduction and Continuous Conduction Modes Selection
The approximate formula for determining the DCM/CCM boundary is as follows:
IDCB ≊ VO × (VIN– VO) / (2 × 3.3 μH × fSW(CCM) × VIN)
(13)
The inductor internal to the module is 3.3 μH. This value was chosen as a good balance between low and high
input voltage applications. The main parameter affected by the inductor is the amplitude of the inductor ripple
current (ILR). ILR can be calculated with:
ILR P-P = VO × (VIN – VO) / (3.3 µH × fSW × VIN)
where
•
•
VIN is the maximum input voltage
fSW is typically 812 kHz
(14)
If the output current IO is determined by assuming that IO = IL, the higher and lower peak of ILR can be
determined.
8.2.3 Application Curves
100
4
3
2
1
4
3
2
1
0
90
80
70
60
50
40
30
20
10
0
ꢀJA = 12°C/W
0
0.0 0.2 0.4 0.6 .08 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
OUTPUT CURRENT (A)
30 40 50 60 70 80 90 100 110 120 130
AMBIENT TEMPERATURE (°C)
VIN = 12 V, VOUT = 5 V
VIN = 12 V, VOUT = 5 V
Figure 51. Efficiency
Figure 52. Thermal Derating
50
45
40
35
30
25
20
15
10
5
Class A Limit
Class B Limit
Horiz Peak
Horiz Quasi-Peak
0
0
200
400
600
800
1000
FREQUENCY (MHz)
Figure 53. Radiated EMI (EN 55022)
of Demo Board (See AN-2125, SNVA473)
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9 Power Supply Recommendations
The LMZ23603 device is designed to operate from an input voltage supply range between 6 V and 36 V. This
input supply must be well regulated and able to withstand maximum input current and maintain a stable voltage.
The resistance of the input supply rail must be low enough that an input current transient does not cause a high
enough drop at the LMZ23603 supply voltage that can cause a false UVLO fault triggering and system reset. If
the input supply is more than a few inches from the LMZ23603, additional bulk capacitance may be required in
addition to the ceramic bypass capacitors. The amount of bulk capacitance is not critical, but a 47-μF or 100-μF
electrolytic capacitor is a typical choice.
10 Layout
10.1 Layout Guidelines
PCB layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance of a
DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce and resistive voltage drop in
the traces. These can send erroneous signals to the DC-DC converter resulting in poor regulation or instability.
Good layout can be implemented by following a few simple design rules.
1. Minimize area of switched current loops.
From an EMI reduction standpoint, it is imperative to minimize the high di/dt paths during PCB layout as
shown in Figure 54. The high current loops that do not overlap have high di/dt content that will cause
observable high-frequency noise on the output pin if the input capacitor (Cin1) is placed at a distance away
from the LMZ23603. Therefore place CIN1 as close as possible to the LMZ23603 VIN and PGND exposed
pad. This will minimize the high di/dt area and reduce radiated EMI. Additionally, grounding for both the input
and output capacitor must consist of a localized top side plane that connects to the PGND exposed pad
(EP).
2. Have a single point ground.
The ground connections for the feedback, soft-start, and enable components must be routed to the AGND
pin of the device. This prevents any switched or load currents from flowing in the analog ground traces. If not
properly handled, poor grounding can result in degraded load regulation or erratic output voltage ripple
behavior. Additionally provide the single point ground connection from pin 4 (AGND) to EP/PGND.
3. Minimize trace length to the FB pin.
Both feedback resistors, RFBT and RFBB must be located close to the FB pin. Because the FB node is high
impedance, maintain the copper area as small as possible. The traces from RFBT, RFBB must be routed away
from the body of the LMZ23603 to minimize possible noise pickup.
4. Make input and output bus connections as wide as possible.
This reduces any voltage drops on the input or output of the converter and maximizes efficiency. To optimize
voltage accuracy at the load, ensure that a separate feedback voltage sense trace is made to the load. Doing
so will correct for voltage drops and provide optimum output accuracy.
5. Provide adequate device heat-sinking.
Use an array of heat-sinking vias to connect the exposed pad to the ground plane on the bottom PCB layer.
If the PCB has a plurality of copper layers, these thermal vias can also be employed to make connection to
inner layer heat-spreading ground planes. For best results use a 6 × 10 via array with a minimum via
diameter of 8 mils thermal vias spaced 59 mils (1.5 mm). Ensure enough copper area is used for heat-
sinking to keep the junction temperature below 125°C.
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10.2 Layout Examples
V
IN
V
O
VOUT
VIN
High
di/dt
C
in1
C
O1
GND
Loop 2
Loop 1
Figure 54. Critical Current Loops to Minimize
Top View
Thermal Vias
GND
GND
EPAD
CIN
COUT
1
2
3
4
5
6
7
VOUT
VIN
RFBT
SYNC
RENT
RENB
CFF
CSS
RFBB
GND Plane
Figure 55. PCB Layout Guide
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Layout Examples (continued)
Figure 56. Top View Evaluation Board – See AN–2085 SNVA457
Figure 57. Bottom View Demonstration Board
10.3 Power Dissipation and Thermal Considerations
When calculating module dissipation use the maximum input voltage and the average output current for the
application. Many common operating conditions are provided in the characteristic curves such that less common
applications can be derived through interpolation. In all designs, the junction temperature must be kept below the
rated maximum of 125°C.
For the design case of VIN = 24 V, VO = 3.3 V, IO = 3 A, and TAMB(MAX) = 85°C, the module must see a thermal
resistance from case to ambient of less than:
RθCA< (TJ-MAX – TA-MAX) / PIC-LOSS – RθJC
(15)
Given the typical thermal resistance from junction to case to be 1.9°C/W. Use the 85°C power dissipation curves
in the Typical Characteristics section to estimate the PIC-LOSS for the application being designed. In this
application it is 3 W.
RθCA = (125 – 85) / 3 W – 1.9 = 11.4
(16)
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Power Dissipation and Thermal Considerations (continued)
To reach RθCA = 11.4., the PCB is required to dissipate heat effectively. With no airflow and no external heat, a
good estimate of the required board area covered by 2 oz. copper on both the top and bottom metal layers is:
Board_Area_cm2 = 500°C × cm2/W / RθCA
(17)
As a result, approximately 44 square cm of 2-oz copper on top and bottom layers is required for the PCB design.
The PCB copper heat sink must be connected to the exposed pad. Approximately sixty, 8 mil thermal vias
spaced 39 mils (1.0 mm) apart connect the top copper to the bottom copper. For an example of a high thermal
performance PCB layout for SIMPLE SWITCHER power modules, refer to AN-2085 (SNVA457), AN-2125
(SNVA473), AN-2020 (SNVA419) and AN-2026 (SNVA424).
10.4 Power Module SMT Guidelines
The recommendations below are for a standard module surface mount assembly
•
•
Land Pattern — Follow the PCB land pattern with either soldermask defined or non-soldermask defined pads
Stencil Aperture
–
For the exposed die attach pad (DAP), adjust the stencil for approximately 80% coverage of the PCB land
pattern
–
For all other I/O pads use a 1:1 ratio between the aperture and the land pattern recommendation
•
•
•
•
•
Solder Paste — Use a standard SAC Alloy such as SAC 305, type 3 or higher
Stencil Thickness — 0.125 to 0.15 mm
Reflow — Refer to solder paste supplier recommendation and optimized per board size and density
Refer to Design Summary LMZ1xxx and LMZ2xxx Power Modules Family (SNAA214) for reflow information
Maximum number of reflows allowed is one
Figure 58. Sample Reflow Profile
Table 2. Sample Reflow Profile Table
MAX TEMP
(°C)
REACHED TIME ABOVE REACHED TIME ABOVE REACHED TIME ABOVE REACHED
PROBE
MAX TEMP
235°C
235°C
245°C
245°C
260°C
260°C
1
2
3
242.5
242.5
241.0
6.58
0.49
6.39
0.00
–
7.10
–
0.00
–
–
–
7.10
0.55
6.31
0.00
0.00
7.09
0.42
6.44
0.00
0.00
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.1.2 Development Support
For developmental support, see the following:
WEBENCH Tool, http://www.ti.com/webench
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation, see the following:
•
•
•
•
•
•
•
•
•
AN-2027 Inverting Application for the LMZ14203 SIMPLE SWITCHER Power Module, (SNVA425)
Absolute Maximum Ratings for Soldering, (SNOA549)
AN-2024 LMZ1420x / LMZ1200x Evaluation Board (SNVA422)
AN-2085 LMZ23605/03, LMZ22005/03 Evaluation Board (SNVA457)
AN-2054 Evaluation Board for LM10000 - PowerWise AVS System Controller (SNVA437)
Step-Down DC-DC Converter with Integrated Low Dropout Regulator and Startup Mode (SNVA473)
AN-2020 Thermal Design By Insight, Not Hindsight (SNVA419)
AN-2026 Effect of PCB Design on Thermal Performance of SIMPLE SWITCHER Power Modules (SNVA424)
Design Summary LMZ1xxx and LMZ2xxx Power Modules Family (SNAA214)
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
WEBENCH, SIMPLE SWITCHER are registered trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
6-Feb-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
LMZ23603TZ/NOPB
LMZ23603TZE/NOPB
LMZ23603TZX/NOPB
ACTIVE
TO-PMOD
TO-PMOD
TO-PMOD
NDW
7
7
7
45
RoHS & Green
RoHS & Green
RoHS & Green
SN
SN
SN
Level-3-245C-168 HR
Level-3-245C-168 HR
Level-3-245C-168 HR
-40 to 85
-40 to 85
-40 to 85
LMZ23603
ACTIVE
ACTIVE
NDW
NDW
250
500
LMZ23603
LMZ23603
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
6-Feb-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMZ23603TZE/NOPB
LMZ23603TZX/NOPB
TO-
PMOD
NDW
NDW
7
7
250
500
330.0
24.4
10.6 14.22
5.0
16.0
24.0
Q2
TO-
330.0
24.4
10.6 14.22
5.0
16.0
24.0
Q2
PMOD
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LMZ23603TZE/NOPB
LMZ23603TZX/NOPB
TO-PMOD
TO-PMOD
NDW
NDW
7
7
250
500
367.0
367.0
367.0
367.0
45.0
45.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
NDW TO-PMOD
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
LMZ23603TZ/NOPB
7
45
502
17
6700
8.4
Pack Materials-Page 3
MECHANICAL DATA
NDW0007A
BOTTOM SIDE OF PACKAGE
TOP SIDE OF PACKAGE
TZA07A (Rev D)
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