LMZ31520 [TI]
采用 15x16x5.8mm QFN 封装的 3V 至 14.5V、20A 降压电源模块;
| 型号： | LMZ31520 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用 15x16x5.8mm QFN 封装的 3V 至 14.5V、20A 降压电源模块 电源电路 |
| 文件： | 总35页 (文件大小：1737K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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LMZ31520
ZHCSBV6E –OCTOBER 2013–REVISED SEPTEMBER 2018
采用 QFN 封装且具有 3V 至 14.5V 输入的 LMZ31520 20A
电源模块
1 特性
3 说明
1
•
完全集成的电源解决方案；
尺寸小于离散设计
LMZ31520 电源模块是一款易于使用的集成式电源解
决方案，它在一个扁平的 QFN 封装内整合了一个带有
功率 MOSFET 的 20A 直流/直流转换器、一个屏蔽式
电感器和多个无源器件。此整体电源解决方案仅需三个
外部组件，并省去了环路补偿和磁性元件选择过程。
•
15mm × 16mm × 5.8mm 封装尺寸
- 与 LMZ31530 引脚兼容
•
•
•
超快速负载阶跃响应
效率高达 96%
该器件采用 15 × 16 × 5.8mm QFN 封装，可轻松焊接
到印刷电路板上，并可实现紧凑的负载点设计。可实现
95% 以上的效率，具有超快速负载阶跃响应，以及热
阻抗为 8.6°C/W 的出色功率耗散能力。LMZ31520 提
供离散负载点设计的灵活性和特性集，并且非常适合为
广泛的集成电路 (IC) 和系统供电。先进的封装技术可
提供一个与标准 QFN 贴装和测试技术兼容的稳健耐用
且可靠的电源解决方案。
宽输出电压调节
0.6V 至 3.6V，基准精度为 1%
•
•
可选分离电源轨可实现
低至 3V 的输入电压
可选开关频率范围
（300kHz 至 850kHz）
•
•
•
•
•
•
•
•
•
可选缓启动
可调过流限制
电源正常输出
简化应用
输出电压排序
过热保护
PVIN
V5V
VIN
预偏置输出启动
运行温度范围：-40°C 至 85°C
增强的散热性能：8.6°C/W
VIN
LMZ31520
CI
符合 EN55022 A 类辐射标准
- 集成屏蔽电感器
使用 LMZ31520 并借助 WEBENCH® 电源设计器
创建定制设计方案
SENSE+
VOUT
VOUT
INH
•
ILIM
FREQ_SEL
PWRGD
VADJ
CO
RSET
2 应用
AGND
PGND
SS_SEL
•
•
•
宽带和通信基础设施
DSP 和 FPGA 负载点 应用
高密度电源系统
效率
100
95
90
85
80
75
70
65
60
55
50
Vout = 1.8 V
Fsw = 500 kHz
PVIN = 3.3 V, VIN = 5 V
PVIN = VIN = 5 V
PVIN = VIN = 12 V
0
4
8
12
16
20
C001
Output Current (A)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important
disclaimers. PRODUCTION DATA.
English Data Sheet: SLVSBM9
LMZ31520
ZHCSBV6E –OCTOBER 2013–REVISED SEPTEMBER 2018
www.ti.com.cn
4 Specifications
4.1 Absolute Maximum Ratings(1)
over operating temperature range (unless otherwise noted)
VALUE
UNIT
MIN
–0.3
–0.3
MAX
20
VIN, PVIN
V
V
Input Voltage
INH, VADJ, PWRGD, PWRGD_PU, ILIM, FREQ_SEL,
SS_SEL, V5V
7
PH
–1
–2
25
27
V
Output Voltage
PH 10ns Transient
VOUT
–0.3
6
V
VDIFF (GND to exposed thermal
pad)
±200
mV
Operating Junction Temperature
Storage Temperature
Peak Reflow Case Temperature(3)
–40
–55
125(2)
150
245(4)
3(4)
°C
°C
°C
Maximum Number of Reflows Allowed(3)
Mechanical Shock
Mil-STD-883D, Method 2002.3, 1 msec, 1/2 sine, mounted
Mil-STD-883D, Method 2007.2, 20-2000Hz
250
G
Mechanical Vibration
20
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) See the temperature derating curves in the Typical Characteristics section for thermal information.
(3) For soldering specifications, refer to the Soldering Requirements for BQFN Packages application note.
(4) Devices with a date code prior to week 14 2018 (1814) have a peak reflow case temperature of 240°C with a maximum of one reflow
4.2 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
3
MAX
14.5
14.5
3.6
UNIT
V
PVIN
VIN
Input Switching Voltage
Input Bias Voltage
Output Voltage
4.5
0.6
300
V
VOUT
fSW
V
Switching Frequency
850
kHz
2
Copyright © 2013–2018, Texas Instruments Incorporated
LMZ31520
www.ti.com.cn
ZHCSBV6E –OCTOBER 2013–REVISED SEPTEMBER 2018
4.3 Thermal Information
LMZ31520
THERMAL METRIC(1)
RLG
72 PINS
8.6
UNIT
θJA
Junction-to-ambient thermal resistance(2)
Junction-to-ambient thermal resistance(3)
Junction-to-top characterization parameter(4)
Junction-to-board characterization parameter(5)
Natural Convection
100 LFM
°C/W
°C/W
°C/W
°C/W
θJA(100LFM)
ψJT
7.8
1.6
ψJB
4.2
(1) For more information about traditional and new thermal metrics, see theSemiconductor and IC Package Thermal Metrics application
report (SPRA953).
(2) The junction-to-ambient thermal resistance, θJA, applies to devices soldered directly to a 100 mm x 100 mm, 6-layer PCB with 1 oz.
copper and natural convection cooling. Additional airflow reduces θJA
(3) The junction-to-ambient thermal resistance, θJA, applies to devices soldered directly to a 100 mm x 100 mm, 6-layer PCB with 1 oz.
copper and 100 LFM forced air cooling. Additional airflow reduces θJA
.
.
(4) The junction-to-top characterization parameter, ψJT, estimates the junction temperature, TJ, of a device in a real system, using a
procedure described in JESD51-2A (sections 6 and 7). TJ = ψJT * Pdis + TT; where Pdis is the power dissipated in the device and TT is
the temperature of the top of the device.
(5) The junction-to-board characterization parameter, ψJB, estimates the junction temperature, TJ, of a device in a real system, using a
procedure described in JESD51-2A (sections 6 and 7). TJ = ψJB * Pdis + TB; where Pdis is the power dissipated in the device and TB is
the temperature of the board 1mm from the device.
4.4 Package Specifications
LMZ31520
UNIT
Weight
4.96 grams
Flammability
Meets UL 94 V-O
Per Bellcore TR-332, 50% stress, TA = 40°C, ground benign
MTBF Calculated reliability
26.5 MHrs
4.5 Electrical Characteristics
TA = -40°C to 85°C, VIN = 12 V, VOUT = 1.8 V, IOUT = 20A
CIN = 2x 22 µF ceramic & 330 µF bulk, COUT = 4x 100 µF ceramic (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
0
TYP
MAX
20
UNIT
IOUT
VIN
Output current
A
V
V
V
Input bias voltage range
Input switching voltage range
Over IOUT range
Over IOUT range
VIN Increasing
Hysteresis
4.5
3.0(1)
14.5
14.5
4.33
PVIN
4.0
4.2
UVLO
VIN Undervoltage lockout
0.25
VOUT(adj)
Output voltage adjust range
Set-point voltage tolerance
Temperature variation
Load regulation
Over IOUT range
0.6
3.6
V
(2)
IOUT = 20 A, FCCM mode
-40°C ≤ TA ≤ +85°C
±1.0%
±0.25%
+0.3%
VOUT
Over IOUT range
(2)
Total output voltage variation
Includes set-point, load, and temperature variation
PVIN ±10%
±1.8%
±0.1%
±0.5%
Line regulation
Over PVIN range
(1) The minimum PVIN voltage is 3.0V or (VOUT+ 1.1V), whichever is greater. See VIN and PVIN Input Voltage for more details.
(2) The stated limit of the set-point voltage tolerance includes the tolerance of both the internal voltage reference and the internal
adjustment resistor. The overall output voltage tolerance will be affected by the tolerance of the external RSET resistor.
Copyright © 2013–2018, Texas Instruments Incorporated
3
LMZ31520
ZHCSBV6E –OCTOBER 2013–REVISED SEPTEMBER 2018
www.ti.com.cn
Electrical Characteristics (continued)
TA = -40°C to 85°C, VIN = 12 V, VOUT = 1.8 V, IOUT = 20A
CIN = 2x 22 µF ceramic & 330 µF bulk, COUT = 4x 100 µF ceramic (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
94
92
88
86
82
96
94
91
88
85
1%
30
25
25
MAX
UNIT
VOUT = 3.3 V, fSW = 500kHz
VOUT = 1.8 V, fSW = 500kHz
VOUT = 1.2 V, fSW = 500kHz
VOUT = 0.9 V, fSW = 500kHz
VOUT = 0.6 V, fSW = 500kHz
VOUT = 3.3 V, fSW = 500kHz
VOUT = 1.8 V, fSW = 500kHz
VOUT = 1.2 V, fSW = 500kHz
VOUT = 0.9 V, fSW = 500kHz
VOUT = 0.6 V, fSW = 500kHz
PVIN = VIN = 12 V
IO = 15 A
%
η
Efficiency
PVIN = VIN = 5 V
IO = 15 A
%
Output voltage ripple
Current limit threshold
20 MHz bandwith
VOUT
A
ILIM
Recovery time
µs
2.5 A/µs load step from 25 to 75%
IOUT(max)
Transient response
Inhibit Control
VOUT over/undershoot
mV
V
Inhibit High Voltage
Inhibit Low Voltage
1.8
Open(3)
0.6
VINH
-0.3
V
VIN = 5 V
VIN = 12 V
Good
0.5
1.2
95
0.7
mA
mA
IIN(stby)
VIN standby current
INH pin to AGND
VOUT rising
1.5
Fault
115
90
PWRGD Thresholds
%
Power Good
Fault
VOUT falling
Good
110
0.2
520
300
850
145
10
PWRGD Low Voltage
Switching frequency
I(PWRGD) = 2 mA
0.3
V
fSW
FREQ_SEL pin OPEN, IOUT = 10 A
470
570
kHz
kHz
kHz
°C
66 kΩ resistor between FREQ_SEL pin and PGND
fSEL
Frequency Select(4)
FREQ_SEL pin connected to V5V (pin 61)
Thermal shutdown
Thermal shutdown hysteresis
Thermal Shutdown
°C
(5)
Ceramic
44
94
CIN
External input capacitance
External output capacitance
µF
µF
Non-ceramic
330
400
(6)
COUT
100
5000
(3) This pin has an internal pull-up to approximately 0.4 x VIN. If this pin is left open circuit, the device operates when a valid input voltage is
applied. A small, low-leakage (<300nA) MOSFET is recommended for control.
(4) See the Frequency Select section for more information on selecting the frequency.
(5) A minimum of 44 µF (2x 22 µF) of external ceramic capacitance is required across the input (PVIN/VIN and PGND connected) for
proper operation. Locate the capacitor close to the device. See Table 3 for more details. When operating with split VIN and PVIN rails,
place 4.7 µF of ceramic capacitance directly at the VIN pin to PGND.
(6) A minimum of 100 µF of ceramic capacitance is required at the output. Locate the capacitance close to the device. Adding additional
capacitance close to the load improves the response of the regulator to load transients and reduces ripple. See Table 3 for more details.
4
Copyright © 2013–2018, Texas Instruments Incorporated
LMZ31520
www.ti.com.cn
ZHCSBV6E –OCTOBER 2013–REVISED SEPTEMBER 2018
5 Device Information
RLG PACKAGE
(TOP VIEW)
49
33
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34
PGND
PGND
NC
PGND
PGND
50
51
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
65
NC
PVIN
66
PGND
67
PGND
VOUT
VOUT
VOUT
VOUT
VOUT
NC
52
53
54
55
56
57
58
59
60
61
62
63
64
NC
PH
PH
PH
VOUT
68
PVIN
69
PGND
70
PH
71
PH
VOUT
VOUT
VOUT
VOUT
V5V
PH
PH
PH
DNC
DNC
PWRGD
PWRGD_PU
PGND
72
PGND
PGND
PGND
PGND
PGND
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
1
17
Copyright © 2013–2018, Texas Instruments Incorporated
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LMZ31520
ZHCSBV6E –OCTOBER 2013–REVISED SEPTEMBER 2018
www.ti.com.cn
Pin Functions
TERMINAL
DESCRIPTION
NAME
NO.
This pin is connected internally to the power ground of the device. This pin should only be used as the zero
volt ground reference for connecting the voltage setting resistor (RSET). Do not connect AGND to PGND.
See Layout Recommendations.
AGND
9
4
8
12
20
21
35
36
Do Not Connect. Do not connect these pins to AGND, to another DNC pin, or to any other voltage. These
pins are connected to internal circuitry. Each pin must be soldered to an isolated pad.
DNC
Frequency Select pin. Leave this pin open (floating) to select 500 kHz (typ) operating frequency. Connect
this pin to V5V pin to select 850 kHz (typ) operating frequency. Connect a 66 kΩ resistor between this pin
and PGND to select 300 kHz (typ) operating frequency. See Table 2 for more info.
FREQ_SEL
7
Current limit setting pin. Connecting a resistor between this pin and PGND sets the current limit. When left
open, refer to the Electrical Characterization table for current limit value.
ILIM
INH
6
16
29
30
31
32
45
1
Inhibit pin. Use an open drain or open collector logic device to ground this pin to control the INH function.
Not Connected. These pins are internally isolated from any signal and all other pins. Each pin must be
soldered to a pad on the PCB. These pins can be left isolated, connected to one another, or connected to
any signal on the PCB.
NC
5
17
33
34
37
38
39
40
41
46
47
48
49
50
51
62
63
64
65
67
70
72
This is the return current path for the power stage of the device. Connect these pins to the load and to the
bypass capacitors associated with VIN and VOUT. Pads 65, 67, 70, and 72 should be connected to PCB
ground planes using multiple vias for good thermal performance. Not all pins are connected together
internally. All pins must be connected together externally with a copper plane or pour directly under the
device.
PGND
6
Copyright © 2013–2018, Texas Instruments Incorporated
LMZ31520
www.ti.com.cn
ZHCSBV6E –OCTOBER 2013–REVISED SEPTEMBER 2018
Pin Functions (continued)
TERMINAL
DESCRIPTION
NAME
NO.
11
22
23
24
25
26
27
28
71
42
43
44
66
69
Phase switch node. Do not place any external component on these pins or tie them to a pin of another
function. Connect these pins using a copper area beneath pad 71.
PH
PVIN
Input switching voltage pin. This pin supplies voltage to the power switches of the converter.
Power Good flag pin. This open drain output asserts low if the output voltage is more than approximately
±6% out of regulation.
PWRGD
19
18
14
Power Good pull-up pin. This pin is connected to a 100kΩ resistor which is tied to the PWRGD pin internally.
Connect this pin to V5V or to any voltage between 1.3V and 6.5V.
PWRGD_PU
SENSE+
Remote sense connection. Connect this pin to VOUT at the load for improved regulation. This pin must be
connected to VOUT at the load, or at the module pins.
Slow-start select pin. Connect a resistor between this pin and PWRGD (or PGND) to select the slow-start
time. See the SS_SEL section of the datasheet for slow-start times and corresponding resistor values.
Connect the SS_SEL pin to PGND to select Auto-skip Eco-mode or to the PWRGD pin (pin 19) to select
FCCM.
SS_SEL
3
V5V
61
13
2
5V regulator pin. This regulator supplies the internal circuitry.
VADJ
Output voltage adjust pin. Connecting a resistor between this pin and AGND sets the output voltage.
VIN
Input bias voltage pins. Supplies the control circuitry of the power converter.
15
10
52
53
54
55
56
57
58
59
60
68
Output voltage. These pins are connected to the internal output inductor. Connect these pins to the output
load and connect external bypass capacitors between these pins and PGND.
VOUT
Copyright © 2013–2018, Texas Instruments Incorporated
7
LMZ31520
ZHCSBV6E –OCTOBER 2013–REVISED SEPTEMBER 2018
www.ti.com.cn
Functional Block Diagram
LMZ31520
VIN
ILIM
OCP
INH
V5V
VIN
Shutdown
Logic
10kΩ
100kΩ
PWRGD_PU
LDO
6.65kΩ
PWRGD
PWRGD
Logic
Thermal
VIN
Shutdown UVLO
SENSE+
Ramp
Comp
PVIN
PH
VADJ
+
+
SS/
FCCM/
Skip
Power
Stage
and
VREF
SS_SEL
Control
Logic
VOUT
PGND
Frequency
Select
FREQ_SEL
AGND
8
Copyright © 2013–2018, Texas Instruments Incorporated
LMZ31520
www.ti.com.cn
ZHCSBV6E –OCTOBER 2013–REVISED SEPTEMBER 2018
6 Typical Characteristics (PVIN = VIN = 12 V)
The electrical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for
the converter. Applies to Figure 1, Figure 2, and Figure 3. The temperature derating curves represent the conditions at which
internal components are at or below the manufacturer's maximum operating temperatures. Derating limits apply to devices
soldered directly to a 100 mm × 100 mm six-layer PCB with 1 oz. copper. Applies to Figure 4 and Figure 5.
55
45
35
25
15
5
100
90
80
70
60
50
40
30
Vo = 3.3V, fsw = 500kHz
Vo = 1.8V, fsw = 500kHz
Vo = 1.2V, fsw = 500kHz
Vo = 0.9V, fsw = 500kHz
Vo = 0.6V, fsw = 500kHz
Vo = 3.3V, fsw = 500kHz
Vo = 1.8V, fsw = 500kHz
Vo = 1.2V, fsw = 500kHz
Vo = 0.9V, fsw = 500kHz
Vo = 0.6V, fsw = 500kHz
0
4
8
12
16
20
0
4
8
12
16
20
C004
Output Current (A)
C001
Output Current (A)
Figure 2. Voltage Ripple vs. Output Current
Figure 1. Efficiency vs. Output Current
6.0
5.0
4.0
3.0
2.0
1.0
0.0
90
80
70
60
50
40
30
20
Vo = 3.3V, fsw = 500kHz
Vo = 1.8V, fsw = 500kHz
Vo = 1.2V, fsw = 500kHz
Vo = 0.9V, fsw = 500kHz
Vo = 0.6V, fsw = 500kHz
Airflow = 0 LFM
Vo ≤ 1.8V, fsw = 500kHz
Vo = 3.3V, fsw = 500kHz
0
4
8
12
16
20
0
4
8
12
16
20
C004
C001
Output Current (A)
Output Current (A)
Figure 3. Power Dissipation vs. Output Current
Figure 4. Safe Operating Area (0 LFM)
90
80
70
60
50
40
30
20
Airflow = 100 LFM
All Output Voltages
0
4
8
12
16
20
C001
Output Current (A)
Figure 5. Safe Operating Area (100 LFM)
Copyright © 2013–2018, Texas Instruments Incorporated
9
LMZ31520
ZHCSBV6E –OCTOBER 2013–REVISED SEPTEMBER 2018
www.ti.com.cn
7 Typical Characteristics (PVIN = VIN = 5 V)
The electrical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for
the converter. Applies to Figure 6, Figure 7, and Figure 8. The temperature derating curves represent the conditions at which
internal components are at or below the manufacturer's maximum operating temperatures. Derating limits apply to devices
soldered directly to a 100 mm × 100 mm six-layer PCB with 1 oz. copper. Applies to Figure 9.
100
90
80
70
60
50
40
30
45
35
25
15
5
Vo = 3.3V, fsw = 500kHz
Vo = 1.8V, fsw = 500kHz
Vo = 1.2V, fsw = 500kHz
Vo = 0.9V, fsw = 500kHz
Vo = 0.6V, fsw = 500kHz
Vo = 3.3V, fsw = 500kHz
Vo = 1.8V, fsw = 500kHz
Vo = 1.2V, fsw = 500kHz
Vo = 0.9V, fsw = 500kHz
Vo = 0.6V, fsw = 500kHz
0
4
8
12
16
20
0
4
8
12
16
20
C001
C004
Output Current (A)
Output Current (A)
Figure 6. Efficiency vs. Output Current
Figure 7. Voltage Ripple vs. Output Current
5.0
4.0
3.0
2.0
1.0
0.0
90
80
70
60
50
40
30
20
Vo = 3.3V, fsw = 500kHz
Vo = 1.8V, fsw = 500kHz
Vo = 1.2V, fsw = 500kHz
Vo = 0.9V, fsw = 500kHz
Vo = 0.6V, fsw = 500kHz
Airflow = 0 LFM
All Output Voltages
0
4
8
12
16
20
0
4
8
12
16
20
C004
C001
Output Current (A)
Output Current (A)
Figure 8. Power Dissipation vs. Output Current
Figure 9. Safe Operating Area (0 LFM)
10
Copyright © 2013–2018, Texas Instruments Incorporated
LMZ31520
www.ti.com.cn
ZHCSBV6E –OCTOBER 2013–REVISED SEPTEMBER 2018
8 Application Information
8.1 Adjusting the Output Voltage
The VADJ control sets the output voltage of the LMZ31520. The output voltage adjustment range is from 0.6V to
3.6V. The adjustment method requires the addition of RSET, which sets the output voltage, and the connection of
SENSE+ to VOUT. The RSET resistor must be connected directly between the VADJ (pin 13) and AGND (pin 9).
The SENSE+ pin (pin 14) must be connected to VOUT either at the load for improved regulation or at VOUT of
the device.
The LMZ31520 relies on a precision trimmed 0.6 V reference for the feedback voltage regulation and operates by
regulating the valley of the voltage ripple appearing at the VADJ pin. The voltage ripple is a function of the input
voltage and the output voltage, therefore the RSET resistor will change based on the input voltage. Table 1 gives
the calculated external RSET resistor for a number of common bus voltages for PVIN of 12 V, 5 V, and 3.3 V. The
recommended switching frequency is 500 kHz which can be configured by leaving the FREQ_SEL pin open. To
adjust the frequency, see Table 2.
Table 1. RSET Resistor Values
RSET (Ω)
PVIN = 5 V
open
18681
8993
5923
4416
3521
2927
2505
2190
1945
1749
1589
1456
1344
1248
1164
1091
1027
970
RSET (Ω)
PVIN = 5 V
563
VOUT (V)
0.60
0.65
0.70
0.75
0.80
0.85
0.90
0.95
1.00
1.05
1.10
1.15
1.20
1.25
1.30
1.35
1.40
1.45
1.50
1.55
1.60
1.65
1.70
1.75
1.80
1.85
1.90
1.95
2.00
2.05
2.10
PVIN = 12 V
open
18787
9024
5939
4427
3529
2934
2511
2195
1950
1754
1594
1460
1348
1251
1168
1095
1031
973
PVIN = 3.3 V
open
18588
8966
5908
4406
3513
2921
2500
2185
1941
1745
1586
1453
1341
1244
1161
1088
1024
968
VOUT (V)
2.15
2.20
2.25
2.30
2.35
2.40
2.45
2.50
2.55
2.60
2.65
2.70
2.75
2.80
2.85
2.90
2.95
3.00
3.05
3.10
3.15
3.20
3.25
3.30
3.35
3.40
3.45
3.50
3.55
3.60
PVIN = 12 V
566
548
532
516
502
488
475
462
451
439
429
419
409
400
391
382
374
367
359
352
345
339
332
326
320
315
309
304
299
294
PVIN = 3.3 V
560
542
525
510
495
481
468
456
444
433
422
412
402
393
384
375
367
359
352
345
338
331
325
318
312
307
301
296
291
286
545
528
513
498
484
471
459
447
436
425
415
405
396
387
379
370
363
355
922
919
916
348
876
873
870
341
834
831
828
335
797
793
790
328
762
759
756
322
730
727
724
316
701
698
695
310
674
671
668
305
650
646
643
300
626
623
620
294
605
602
599
289
585
581
578
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11
LMZ31520
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8.2 Frequency Select
The LMZ31520 switching frequency can be selected from several values as shown in Table 2. To select a
switching frequency, a resistor (RFREQ) must be connected between the FREQ_SEL pin and either PGND or V5V
(pin 61) as shown in Table 2. For all output voltages, the recommended switching frequency is 500 kHz which
can be configured by leaving the FREQ_SEL pin open. Table 2 also shows the output voltage range for each
frequency.
Table 2. Frequency Selection
VOUT RANGE (V)
Frequency Select (kHz)
RFREQ (kΩ)
66
Connect To
PGND
PGND
-
MIN
0.6
0.6
0.6
0.8
1.0
1.2
MAX
3.6
3.6
3.6
3.6
3.6
3.6
300
400
500
650
750
850
498
open
745
V5V
188
V5V
short
V5V
8.3 Capacitor Recommendations for the LMZ31520 Power Supply
8.3.1 Capacitor Technologies
8.3.1.1 Electrolytic, Polymer-Electrolytic Capacitors
Aluminum electrolytic capacitors provide adequate decoupling over the frequency range of 2 kHz to 150 kHz.
When using electrolytic capacitors, high-quality, polymer-electrolytic capacitors are recommended. Polymer-
electrolytic type capacitors are recommended for applications where the ambient operating temperature is less
than 0°C. The Panasonic OS-CON capacitor series is suggested due to the lower ESR, higher rated surge,
power dissipation, ripple current capability, and small package size.
8.3.1.2 Ceramic Capacitors
The performance of ceramic capacitors is most effective above 150 kHz. Multilayer ceramic capacitors have a
low ESR and a resonant frequency higher than the bandwidth of the regulator. They can be used to reduce the
reflected ripple current at the input as well as improve the transient response of the output.
8.3.1.3 Tantalum, Polymer-Tantalum Capacitors
Polymer-tantalum type capacitors are recommended for applications where the ambient operating temperature is
less than 0°C. The Panasonic POSCAP series and Kemet T530 capacitor series are recommended rather than
many other tantalum types due to their lower ESR, higher rated surge, power dissipation, ripple current
capability, and small package size. Tantalum capacitors that have no stated ESR or surge current rating are not
recommended for power applications.
8.3.1.4 Input Capacitor
The LMZ31520 requires a minimum input capacitance of 44 μF of ceramic type. The voltage rating of input
capacitors must be greater than the maximum input voltage. The input RMS ripple current is a function of the
output current and the duty cycle for any application. The input capacitor must be rated for the application's RMS
ripple current. Table 3 includes a preferred list of capacitors by vendor.
8.3.1.5 Output Capacitor
The required output capacitance of the LMZ31520 can be comprised of either all ceramic capacitors, or a
combination of ceramic and bulk capacitors. The required output capacitance must include at least 100 µF of
ceramic type. When adding additional non-ceramic bulk capacitors, low-ESR devices like the ones recommended
in Table 3 are required. The required capacitance above the minimum is determined by actual transient deviation
requirements. See Table 4 for typical transient response values for several output voltage, input voltage and
capacitance combinations. Table 3 includes a preferred list of capacitors by vendor.
12
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Capacitor Recommendations for the LMZ31520 Power Supply (continued)
Table 3. Recommended Input/Output Capacitors(1)
CAPACITOR CHARACTERISTICS
VENDOR
SERIES
PART NUMBER
WORKING VOLTAGE (V)
CAPACITANCE (µF)
ESR (2) (mΩ)
Murata
X5R
X5R
GRM32ER61E226K
25
25
22
47
2
2
TDK
C3216X5R1E476M
C3216X5R1C476M
GRM32ER61C476M
C3225X5R0J107M
GRM32ER60J107M
C3225X5R0J476K
GRM32ER60J476M
EEH-ZA1E101XP
T520V107M010ASE025
6TPE100MI
TDK
X5R
16
47
2
Murata
TDK
X5R
16
47
2
X5R
6.3
6.3
6.3
6.3
25
100
100
47
2
Murata
TDK
X5R
2
X5R
2
Murata
Panasonic
Kemet
X5R
47
2
EEH-ZA
T520
100
100
100
220
220
330
330
330
30
25
25
7
10
Panasonic
Panasonic
Kemet
POSCAP
POSCAP
T530
6.3
2.5
6.3
6.3
2.0
6.3
2R5TPE220M7
T530D227M006ATE006
T530D337M006ATE010
2TPF330M6
6
Kemet
T530
10
6
Panasonic
Panasonic
POSCAP
POSCAP
6TPE330MFL
15
(1) Capacitor Supplier Verification, RoHS, Lead-free and Material Details
Consult capacitor suppliers regarding availability, material composition, RoHS and lead-free status, and manufacturing process
requirements for any capacitors identified in this table.
(2) Maximum ESR @ 100kHz, 25°C.
8.4 Transient Response
The LMZ31520 is designed to have an ultra-fast load step response with minimal output capacitance. Table 4
shows the voltage deviation and recovery time for several different transient conditions. Several transient
(1)
waveforms are shown in Application Curves
.
Table 4. Output Voltage Transient Response
CIN1 = 3 x 47 µF CERAMIC
VOLTAGE DEVIATION (mV)
RECOVERY TIME
(µs)
VOUT (V)
VIN (V)
COUT1 Ceramic
COUT2 BULK
5 A LOAD STEP,
(1 A/µs)
10 A LOAD STEP,
(1 A/µs)
5
500 µF
500 µF
500 µF
500 µF
500 µF
500 µF
500 µF
500 µF
500 µF
500 µF
500 µF
500 µF
500 µF
500 µF
500 µF
500 µF
-
8
8
15
15
15
12
20
16
20
15
20
16
20
16
20
16
25
25
35
35
40
40
40
40
40
40
40
40
40
40
40
45
50
50
0.6
12
-
-
8
5
12
5
470 µF
6
0.9
1.2
-
8
470 µF
7
-
10
8
330 µF
-
10
8
12
5
330 µF
-
10
8
330 µF
1.8
3.3
-
10
8
12
330 µF
5
-
-
12
12
12
(1) Device configured for FCCM mode of operation, (pin 3 connected to pin 19).
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(1)
8.5 Application Curves
Figure 10. PVIN = 5V, VOUT = 1.8V, 5A Load Step
Figure 11. PVIN = 5V, VOUT = 1.2V, 10A Load Step
Figure 13. PVIN = 12V, VOUT = 1.8V, 10A Load Step
Figure 12. PVIN = 12V, VOUT = 1.0V, 10A Load Step
(1) Device configured for FCCM mode of operation, (pin 3 connected to pin 19).
14
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ZHCSBV6E –OCTOBER 2013–REVISED SEPTEMBER 2018
8.6 Application Schematics
LMZ31520
SENSE+
VOUT
V
1.2 V
VIN
OUT
V
/ P
VIN
IN
4.5 V to 14.5 V
PVIN
+
+
C
C
OUT2
220 µF
OUT1
C
C
C
IN3
IN1
IN2
2x 100 µF
100 µF 22 µF 22 µF
INH
FREQ_SEL PWRGD
SS_SEL
PGND
VADJ
R
AGND
SET
1.43 k
Figure 14. Typical Schematic
PVIN = VIN = 4.5 V to 14.5 V, VOUT = 1.2 V
V
IN
4.5 V to 14.5 V
C
IN3
4.7 µF
LMZ31520
SENSE+
VOUT
V
0.9 V
OUT
P
3.3 V
VIN
PVIN
INH
+
+
C
OUT1
C
OUT2
C
C
C
IN3
IN1
IN2
3x 100 µF
330 µF
100 µF 22 µF 22 µF
FREQ_SEL PWRGD
SS_SEL
PGND
VADJ
R
AGND
SET
2.87 k
Figure 15. Typical Schematic
PVIN = 3.3 V, VIN = 4.5 V to 14.5 V, VOUT = 0.9 V
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8.7 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LMZ31520 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
•
•
•
•
Run electrical simulations to see important waveforms and circuit performance
Run thermal simulations to understand board thermal performance
Export customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.8 VIN and PVIN Input Voltage
The LMZ31520 allows for a variety of applications by using the VIN and PVIN pins together or separately. The
VIN voltage supplies the internal control circuits of the device. The PVIN voltage provides the input voltage to the
power converter system.
If tied together, the input voltage for the VIN pin and the PVIN pin can range from 4.5 V to 14.5 V. If using the
VIN pin separately from the PVIN pin, the VIN pin must be greater than 4.5 V, and the PVIN pin can range from
as low as 3.0 V to 14.5 V. When operating from a split rail, it is recommended to supply VIN from 5 V to 12 V, for
best performance.
8.9 3.3 V PVIN Operation
Applications operating from a PVIN of 3.3 V must provide at least 4.5 V for VIN. It is recommended to supply VIN
from 5 V to 12 V, for best performance. See application note, SNVA692 for help creating 5 V from 3.3 V using a
small, simple charge pump device.
8.10 Power Good (PWRGD)
The PWRGD pin is an open drain output. Once the voltage on the SENSE+ pin is between 90% and 115% of the
set voltage, the PWRGD pin pull-down is released and the pin floats. The recommended pull-up resistor value is
between 10 kΩ and 100 kΩ to a voltage source that is less than 7 V. An internal 100 kΩ pull-up resistor is
provided internal to the device between the PWRGD pin (pin 19) and PWRGD_PU pin (pin 18). The
PWRGD_PU pin can be connected to a voltage source less than 7 V or connected directly to V5V (pin 61), which
is an internal 5V regulator. The PWRGD pin is in a defined state once VIN is greater than 1.0 V. The PWRGD
pin is pulled low when the voltage on SENSE+ is lower than 90% or greater than 115% of the nominal set
voltage. Also, the PWRGD pin is pulled low if the input UVLO or thermal shutdown is asserted or the INH pin is
pulled low.
16
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8.11 Slow Start (SS_SEL)
Connecting the SS_SEL pin to PWRGD or PGND sets the slow start interval of approximately 0.7 ms. The
connection to either PWRGD or PGND determines the mode of the LMZ31520 as decribed in Auto-Skip Eco-
mode™ / Forced Continuous Conduction Mode. Adding a resistor between SS_SEL pin and PWRGD or PGND
increases the slow start time. Increasing the slow start time will reduce inrush current.Table 5 shows a resistor
connected between SS_SEL pin and PWRGD to select FCCM and Figure 17 shows a resistor between SS_SEL
pin and PGND to select Auto-skip mode. See Table 5 below for SS resistor values and timing interval.
PWRGD
SS_SEL
PWRGD
SS_SEL
R
SS
R
SS
PGND
PGND
Figure 16. Slow-Start Resistor (RSS) in FCCM
Figure 17. Slow-Start Resistor (RSS) in Auto-skip Mode
Table 5. Slow-Start Resistor Values and Slow-Start Time
RSS (kΩ)
short
0.7
61.9
1.4
161
2.8
436
SS Time (msec)
5.6
8.12 Auto-Skip Eco-mode™ / Forced Continuous Conduction Mode
Auto-skip Eco-mode or Forced Continuous Conduction Mode (FCCM) can be selected using the SS_SEL pin
(pin 3). Connect the SS_SEL pin to PGND to select Auto-skip Eco-mode or to the PWRGD pin to select FCCM.
In Auto-skip Eco-mode, the LMZ31520 automatically reduces the switching frequency at light load conditions to
maintain high efficiency. In FCCM, the controller keeps continuous conduction mode in light load condition and
the switching frequency is kept almost constant over the entire load range. Transient performance is best in
FCCM.
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8.13 Power-Up Characteristics
When configured as shown in the front page schematic, the LMZ31520 produces a regulated output voltage
following the application of a valid input voltage. During the power-up, internal soft-start circuitry slows the rate
that the output voltage rises, thereby limiting the amount of in-rush current that can be drawn from the input
source. Figure 18 shows the start-up waveforms for a LMZ31520, operating from a 5-V input (PVIN=VIN) and
with the output voltage adjusted to 1.8 V. Figure 19 shows the start-up waveforms for a LMZ31520 starting up
into a pre-biased output voltage. The waveforms were measured with a 15-A constant current load.
Figure 19. Start-up into Pre-bias
Figure 18. Start-Up Waveforms
8.14 Pre-Biased Start-Up
The LMZ31520 has been designed to prevent the low-side MOSFET from discharging a pre-biased output.
During pre-biased startup, the low-side MOSFET does not turn on until the high-side MOSFET has started
switching. The high-side MOSFET does not start switching until the slow start voltage exceeds the voltage on the
VADJ pin. Refer to Figure 19.
8.15 Remote Sense
The SENSE+ pin must be connected to VOUT at the load, or at the device pins.
Connecting the SENSE+ pin to VOUT at the load improves the load regulation performance of the device by
allowing it to compensate for any I-R voltage drop between its output pins and the load. An I-R drop is caused by
the high output current flowing through the small amount of pin and trace resistance. This should be limited to a
maximum of 300 mV.
NOTE
The remote sense feature is not designed to compensate for the forward drop of nonlinear
or frequency dependent components that may be placed in series with the converter
output. Examples include OR-ing diodes, filter inductors, ferrite beads, and fuses. When
these components are enclosed by the SENSE+ connection, they are effectively placed
inside the regulation control loop, which can adversely affect the stability of the regulator.
18
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8.16 Output On/Off Inhibit (INH)
The INH pin provides electrical on/off control of the device. Once the INH pin voltage exceeds the threshold
voltage, the device starts operation. If the INH pin voltage is pulled below the threshold voltage, the regulator
stops switching and enters low quiescent current state.
The INH pin has an internal pull-up current source, allowing the user to float the INH pin for enabling the device.
If an application requires controlling the INH pin, use an open drain/collector device, or a suitable logic gate to
interface with the pin.
Figure 20 shows the typical application of the inhibit function. The Inhibit control has its own internal pull-up to
VIN potential. An open-collector or open-drain device is recommended to control this input.
Turning Q1 on applies a low voltage to the inhibit control (INH) pin and disables the output of the supply, shown
in Figure 21. If Q1 is turned off, the supply executes a soft-start power-up sequence, as shown in Figure 22. A
regulated output voltage is produced within 2 ms. The waveforms were measured with a 5-A constant current
load.
INH
Q1
INH
Control
PGND
Figure 20. Typical Inhibit Control
Figure 21. Inhibit Turn-Off
Figure 22. Inhibit Turn-On
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8.17 Overcurrent Protection
For protection against load faults, the LMZ31520 incorporates cycle-by-cycle overcurrent limiting control. The
inductor current is monitored during the OFF state and the controller maintains the OFF state during the period in
that the inductor current is larger than the overcurrent trip level. In cycle-by-cycle mode, applying a load that
exceeds the regulator's overcurrent threshold limits the output current and reduces the output voltage as shown
in Figure 23. If the overcurrent condition remains and the output voltage drops below 70% of the set-point, the
LMZ31520 shuts down. Following shutdown, the module periodically attempts to recover by initiating a soft-start
power-up as shown in Figure 23. This is described as a hiccup mode of operation, whereby the module
continues in a cycle of successive shutdown and power up until the load fault is removed. During this period, the
average current flowing into the fault is significantly reduced which reduces power dissipation. Once the fault is
removed, the module automatically recovers and returns to normal operation as shown in Figure 24.
Figure 23. Typical Overcurrent Limiting
Figure 24. Typical Removal of Overcurrent
8.18 Current Limit (ILIM) Adjust
The current limit of this device can be adjusted lower by connecting a resistor, RILIM, between the ILIM pin (pin 6)
and PGND. To adjust the typical current limit threshold, as listed in the electrical characteristics table, refer to
Table 6.
Table 6. Current Limit Adjust Resistor
Current Limit Reduction
RILIM (kΩ)
715
10 %
20 %
30 %
383
243
8.19 Thermal Shutdown
The internal thermal shutdown circuitry forces the device to stop switching if the junction temperature exceeds
145°C typically. The device reinitiates the power up sequence when the junction temperature drops below 135°C
typically.
20
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8.20 Layout Considerations
To achieve optimal electrical and thermal performance, an optimized PCB layout is required. Figure 25 thru
Figure 30, shows a typical PCB layout. Some considerations for an optimized layout are:
•
Use large copper areas for power planes (PVIN, VOUT, and PGND) to minimize conduction loss and thermal
stress.
•
•
•
•
•
Place ceramic input and output capacitors close to the device pins to minimize high frequency noise.
Locate additional output capacitors between the ceramic capacitor and the load.
Keep AGND and PGND separate from one another. AGND should only be used as the return for RSET
Place RSET, RFREQ, and RSS as close as possible to their respective pins.
Use multiple vias to connect the power planes to internal layers.
.
Figure 26. Typical Layer 2 Layout
Figure 25. Typical Top Layer Layout
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Layout Considerations (continued)
Figure 28. Typical Layer 4 Layout
Figure 27. Typical Layer 3 Layout
Figure 29. Typical Layer 5 Layout
Figure 30. Typical Bottom Layer Layout
22
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ZHCSBV6E –OCTOBER 2013–REVISED SEPTEMBER 2018
8.21 EMI
The LMZ31520 is compliant with EN55022 Class A radiated emissions. Figure 31 and Figure 32 show typical
examples of radiated emissions plots for the LMZ31520 operating from 5V and 12V respectively. Both graphs
include the plots of the antenna in the horizontal and vertical positions.
Figure 32. Radiated Emissions 12-V Input, 3.3-V Output,
20-A Load (EN55022 Class A)
Figure 31. Radiated Emissions 5-V Input, 1.8-V Output, 20-
A Load (EN55022 Class A)
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9 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (April 2018) to Revision E
Page
•
Updated PCB Typical Bottom Layer Layout ........................................................................................................................ 21
Changes from Revision C (June 2017) to Revision D
Page
•
•
添加 LMZ31520 的 WEBENCH® 设计链接 ............................................................................................................................ 1
Increased the peak reflow temperature and maximum number of reflows to JEDEC specifications for improved
manufacturability..................................................................................................................................................................... 2
•
•
添加器件支持 部分................................................................................................................................................................ 25
添加机械、封装和可订购信息 部分....................................................................................................................................... 26
Changes from Revision B (December 2013) to Revision C
Page
•
Added peak reflow and maximum number of reflows information ........................................................................................ 2
Changes from Revision A (December 2013) to Revision B
Page
•
Added additional capacitors to the recommended capacitor table....................................................................................... 13
Changes from Original (October 2013) to Revision A
Page
•
已更改 将状态从预览改为生产................................................................................................................................................ 1
24
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10 器件和文档支持
10.1 器件支持
10.1.1 开发支持
10.1.1.1 使用 WEBENCH® 工具创建定制设计
单击此处，使用 LMZ31520 器件并借助 WEBENCH® 电源设计器创建定制设计方案。
1. 首先输入输入电压 (VIN)、输出电压 (VOUT) 和输出电流 (IOUT) 要求。
2. 使用优化器拨盘优化该设计的关键参数，如效率、尺寸和成本。
3. 将生成的设计与德州仪器 (TI) 的其他可行的解决方案进行比较。
WEBENCH 电源设计器可提供定制原理图以及罗列实时价格和组件供货情况的物料清单。
在多数情况下，可执行以下操作：
•
•
•
•
运行电气仿真，观察重要波形以及电路性能
运行热性能仿真，了解电路板热性能
将定制原理图和布局方案以常用 CAD 格式导出
打印设计方案的 PDF 报告并与同事共享
有关 WEBENCH 工具的详细信息，请访问 www.ti.com.cn/WEBENCH。
10.2 文档支持
10.2.1 相关文档
请参阅如下相关文档：
BQFN 封装的焊接要求
10.3 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
10.4 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
10.5 商标
Eco-mode, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
10.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
10.7 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
版权 © 2013–2018, Texas Instruments Incorporated
25
LMZ31520
ZHCSBV6E –OCTOBER 2013–REVISED SEPTEMBER 2018
www.ti.com.cn
11 机械封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
11.1 Tape and Reel Information
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
Reel
Diameter
(mm)
Reel
Width W1
(mm)
Package
Type
Package
Drawing
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
Device
Pins
SPQ
LMZ31520RLGT
BQFN
RLG
72
250
330.0
24.4
15.35
16.35
6.1
20.0
24.0
Q1
26
版权 © 2013–2018, Texas Instruments Incorporated
LMZ31520
www.ti.com.cn
ZHCSBV6E –OCTOBER 2013–REVISED SEPTEMBER 2018
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
Device
Package Type
BQFN
Package Drawing Pins
RLG 72
SPQ
Length (mm) Width (mm)
383.0 353.0
Height (mm)
LMZ31520RLGT
250
58.0
版权 © 2013–2018, Texas Instruments Incorporated
27
重要声明和免责声明
TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资
源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示
担保。
所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、
验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用
所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权
许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。
TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约
束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE
邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122
Copyright © 2018 德州仪器半导体技术（上海）有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
16-Jul-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMZ31520RLGT
ACTIVE
BQFN
RLG
72
250
RoHS Exempt
& Green
NIPDAU
Level-3-245C-168 HR
-40 to 85
LMZ31520
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Mar-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMZ31520RLGT
BQFN
RLG
72
250
330.0
24.4
15.35 16.35
6.1
20.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Mar-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
BQFN RLG 72
SPQ
Length (mm) Width (mm) Height (mm)
383.0 353.0 58.0
LMZ31520RLGT
250
Pack Materials-Page 2
PACKAGE OUTLINE
RLG0072A
B4QFN - 5.9 mm max height
EXTREMELY THICK QUAD FLATPACK - NO LEAD
15.15
14.85
B
A
PIN 1 ID
16.15
15.85
(13 )
ALL AROUND
(0.2) TYP
C
5.9
5.7
2.70
SEATING PLANE
0.08 C
4X
4.72 0.1
0.05
0.00
4X 1.075
4X 1.575
33
17
71
70
5.45 0.1 2.8 0.1
3X 2.3 0.1
72
67
66
3X 2.3 0.1
2.25 0.1
3X 1.89 0.1
2X 12.8
0.000 PKG
1.44 0.1
69
68
1.33 0.1
1.9 0.1
65
0.49
0.31
2X 2.8 0.1
2X 5.45 0.1
60X
1
49
0.1
C A B
32X 0.8
0.8 0.1
32X 0.8
0.6
60X
PIN 1 ID
0.4
(45 X 0.9)
2X 12.8
4226426/A 12/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pads must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RLG0072A
B4QFN - 5.9 mm max height
EXTREMELY THICK QUAD FLATPACK - NO LEAD
(0.8)
60X (0.7)
64
2X (6.988)
49
1
4X (6.15)
4X (4.75)
68
69
3X
(2.8)
2X (5.45)
65
68X (0.4)
(1.33)
4X (2.6)
4X (1.2)
(1.9)
(2.25)
(1.44)
(15.7)
66
67
0.000 PKG
3X (1.89)
64X (0.8)
6X (1.19)
6X (2.59)
3X
(2.3)
72
70
71
3X
(2.3)
(R0.05) TYP
(
0.2) TYP
4X (4.75)
(5.45)
VIA
4X (6.15)
17
4X (1.575)
2X (6.988)
33
4X (1.075)
4X (4.62)
(14.7)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 6X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
METAL UNDER
SOLDE MASK
METAL EDGE
EXPOSED
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
SOLDER MASK DEFINED
NON SOLDER MASK DEFINED
SOLDER MASK DETAILS
4226426/A 12/2020
NOTES: (continued)
4. This package is designed to be soldered to the thermal pads on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RLG0072A
B4QFN - 5.9 mm max height
EXTREMELY THICK QUAD FLATPACK - NO LEAD
12X (1.2)
(0.8)
64
60X (0.7)
2X (6.988)
49
1
68
69
6X (2.64)
4X (5.45) (2.8)
65
68X (0.4)
(1.33)
(2.3)
(R0.05) TYP
3X (2.13)
3X (1.9)
(15.7)
(1.44)
66
0.000 PKG
64X (0.8)
72
67
70
7X (1.89)
3X (2.17)
4X (2.05)
3X (5.45)
4X
(1)
17
4X (1.575)
2X (6.988)
33
4X (1.075)
(14.7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
PADS 67 & 72: 78%
PADS 68 & 71: 73%
PADS 69 & 70: 74%
SCALE: 6X
4226426/A 12/2020
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
重要声明和免责声明
TI 提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没
有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可
将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他 TI 知识产权或任何第三方知
识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款 (https:www.ti.com.cn/zh-cn/legal/termsofsale.html) 或 ti.com.cn 上其他适用条款/TI 产品随附的其他适用条款
的约束。TI 提供这些资源并不会扩展或以其他方式更改 TI 针对 TI 产品发布的适用的担保或担保免责声明。IMPORTANT NOTICE
邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122
Copyright © 2021 德州仪器半导体技术（上海）有限公司
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