LMZ36002RVQT [TI]
采用 QFN 封装的 4.5V 至 60V、2A 降压电源模块 | RVQ | 43 | -40 to 105;
| 型号： | LMZ36002RVQT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用 QFN 封装的 4.5V 至 60V、2A 降压电源模块 | RVQ | 43 | -40 to 105 开关 电源电路 |
| 文件： | 总36页 (文件大小：1804K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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LMZ36002
ZHCSE75D –SEPTEMBER 2015–REVISED JUNE 2018
LMZ36002 4.5V 至 60V 输入、2A 电源模块
1 特性
2 应用
1
•
完整的集成式电源解决方案可实现
小尺寸的薄型设计
•
•
•
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工业和电机控制
自动测试设备
•
•
•
10mm × 10mm × 4.3mm 封装
宽输出电压调节范围（2.5V 至 7.5V）
医疗和成像设备
高密度电源系统
可调节开关频率
（200kHz 至 1MHz）
3 说明
•
•
•
•
•
•
•
•
•
•
•
•
与外部时钟同步
LMZ36002 电源模块是一款易于使用的集成式电源，
它在一个扁平的 QFN 封装内整合了一个 2A 直流/直流
转换器、一个屏蔽式电感器和多个无源器件。这套整体
电源解决方案最少只需采用三个外部组件，同时仍能够
调整关键参数以满足特定的设计要求。
针对轻负载时效率的自动脉冲频率调制 (PFM) 模式
可调软启动时间
输出电压排序/跟踪
电源正常输出
可编程欠压锁定 (UVLO)
过热热关断保护
QFN 封装易于焊接到印刷电路板上，允许回流焊温度
曲线最高达 245°C，并且具有出色的功率耗散能力。
LMZ36002 极具灵活性且 功能 丰富，非常适合为各类
器件和系统供电。
过流保护（间断模式）
预偏置输出启动
工作温度范围：–40°C 至 105°C
增强的热性能；14°C/W
器件信息(1)
器件型号
LMZ36002
封装
QFN (43)
封装尺寸
符合 EN55022 B 类辐射标准
– 集成屏蔽式电感
10.0mm × 10.00mm
•
使用 LMZ36002 并借助 WEBENCH® 电源设计器
创建定制设计方案
(1) 要了解所有可用封装，请参阅数据表末尾的可订购产品附录。
效率与输出电流间的关系
简化应用
100
LMZ36002
VIN
VOUT
COUT
PVIN
VOUT
SENSE+
VBSEL
90
80
INH/UVLO
CIN
70
PVIN = 24 V
60
PVIN = 48 V
VADJ
50
VOUT = 5 V
RSET
AGND
PGND
40
30
0
0.5
1
1.5
2
C001
Output Current (A)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SNVSA92
LMZ36002
ZHCSE75D –SEPTEMBER 2015–REVISED JUNE 2018
www.ti.com.cn
目录
7.2 Functional Block Diagram ....................................... 12
7.3 Feature Description................................................. 13
7.4 Device Functional Modes........................................ 20
Application and Implementation ........................ 21
8.1 Application Information............................................ 21
Power Supply Recommendations...................... 25
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 ESD Ratings.............................................................. 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 6
6.6 Switching Characteristics.......................................... 7
6.7 Typical Characteristics.............................................. 8
6.8 Typical Characteristics.............................................. 9
6.9 Typical Characteristics............................................ 10
6.10 Typical Characteristics (Thermal Derating)........... 11
Detailed Description ............................................ 12
7.1 Overview ................................................................. 12
8
9
10 Layout................................................................... 26
10.1 Layout Guidelines ................................................. 26
10.2 Layout Example .................................................... 26
10.3 EMI........................................................................ 27
11 器件和文档支持 ..................................................... 28
11.1 器件支持................................................................ 28
11.2 接收文档更新通知 ................................................. 28
11.3 社区资源................................................................ 28
11.4 商标....................................................................... 28
11.5 静电放电警告......................................................... 28
11.6 术语表 ................................................................... 28
12 机械、封装和可订购信息....................................... 28
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision C (April 2018) to Revision D
Page
•
•
已更改 将允许回流焊温度“最高达 260°C”更改为“最高达 245°C”，从而与绝对最大值 表保持一致 ........................................ 1
已添加 TI 参考设计顶部导航图标............................................................................................................................................ 1
Changes from Revision B (June 2017) to Revision C
Page
•
•
已添加 LMZ36002 的 WEBENCH® 设计链接......................................................................................................................... 1
Increased the peak reflow temperature and maximum number of reflows to JEDEC specifications for improved
manufacturability..................................................................................................................................................................... 5
Changes from Revision A (September 2015) to Revision B
Page
•
•
已更改 一些语法错误，并修正了一些 TI 格式，以正确反映内容。 ........................................................................................ 1
Added peak reflow and maximum number of reflows information ........................................................................................ 5
Changes from Original (September 2015) to Revision A
Page
•
已更改 从“产品预览”更改为“生产数据”.................................................................................................................................... 1
2
Copyright © 2015–2018, Texas Instruments Incorporated
LMZ36002
www.ti.com.cn
ZHCSE75D –SEPTEMBER 2015–REVISED JUNE 2018
5 Pin Configuration and Functions
RVQ Package
43-Pin QFN
(Top View)
AGND
1
PGND
31
40 39 38 37 36 35 34 33 32
PGND
PGND
AGND
AGND
AGND
AGND
DNC
2
3
4
5
30
29
28 PVIN
42
PVIN
27
PVIN
41 PGND
INH/UVLO
SS/TR
6
7
26
25
24
23
22
VBSEL
CLK
VADJ
8
RT
9
VERSA-COMP
SENSE+
RTSEL
10
43 VOUT
AGND
PWRGD_PU
11
21
12
18 19 20
13 14 15 16 17
Pin Functions
PIN
(1)
TYPE
DESCRIPTION
NAME
NO.
Zero volt reference for the analog control circuitry. All of these pins are not connected together
internal to the device and must be connected to one another externally using an analog ground
plane on the PCB. Pins 11 and 12 are internally connected to the PGND of the device at a single
point. The analog ground plane of the PCB should allow only analog ground currents to flow through
these pins.
1, 2, 3, 4,
5, 11, 12
AGND
G
Synchronization input to synchronize the device to an external clock. Connect this pin to AGND if
not used.
CLK
8
I
Do Not Connect. Do not connect these pins to AGND, to another DNC pin, or to any other voltage.
These pins are connected to internal circuitry. Each pin must be soldered to an isolated pad.
DNC
6, 40
-
Inhibit and UVLO adjust pin. Use an open drain or open collector device to control the inhibit
function. A resistor divider between this pin, AGND, and PVIN adjusts the UVLO voltage. Connect
this pin to PVIN if not used.
INH/UVLO
PGND
26
I
This is the return current path for the power stage of the device. Connect these pins to the input
source, the load, and to the bypass capacitors associated with PVIN and VOUT using power ground
planes on the PCB. Pad 41 should be connected to the ground planes using multiple vias for good
thermal performance.
19, 29, 30,
31, 32, 33,
41
G
34, 35, 36,
37, 38, 39
Phase switch node. Do not place any external components on these pins or tie them to a pin of
another function.
PH
O
I
Power input voltage. These pins supply all of the power to the device. Connect these pins to the
input source and connect external bypass capacitors between these pins and PGND close to the
device.
PVIN
27, 28, 42
20
Power Good flag pin. This open drain output asserts low if the output voltage is more than
approximately ±10% out of regulation. This pin is internally connected to an uncommitted 100-kΩ
pull-up resistor that can be pulled up to a user-defined voltage applied to the PWRGD_PU pin.
PWRGD
O
(1) G = Ground, I = Input, O = Output
Copyright © 2015–2018, Texas Instruments Incorporated
3
LMZ36002
ZHCSE75D –SEPTEMBER 2015–REVISED JUNE 2018
www.ti.com.cn
Pin Functions (continued)
PIN
(1)
TYPE
DESCRIPTION
NAME
NO.
An internal 100-kΩ pull-up resistor is connected between this pin and the PWRGD pin. If use of this
internal pull-up resistor is desired, connect this pin to an appropriate voltage source that is less than
or equal to 12 V. If unused, leave this pin floating.
PWRGD_PU
21
I
I
This pin is connected to internal frequency setting circuitry which sets the default switching
frequency to 500 kHz. An external resistor can be connected from this pin to AGND to adjust the
switching frequency. Refer to application section in datasheet.
RT
9
This pin can be used to adjust the switching frequency to 1 MHz without the need for an external
resistor. Connect this pin to AGND to adjust the frequency to 1 MHz. Otherwise, leave this pin
floating.
RTSEL
SENSE+
SS/TR
10
22
25
I
I
I
Remote sense connection. This pin must be connected to VOUT at the load or at the device pins.
Connect the pin to VOUT at the load for improved regulation.
soft-start and tracking pin. Connecting an external capacitor to this pin adjusts the output voltage
soft-start ramp above its 4.1 ms default setting. A voltage applied to this pin allows for tracking and
sequencing control.
VADJ
24
7
I
I
Connecting a resistor between this pin and AGND adjusts the output voltage.
Selectable internal bias supply. For output voltages ≥ 4.5 V, connect this pin to VOUT. For output
voltages < 4.5 V, connect this pin to AGND.
VBSEL
VERSA-
COMP
Connects to internal compensation network. This pin can be left floating or connected to the VADJ
pin to select the proper compensation depending on the output voltage.
23
I
13, 14, 15,
16, 17, 18,
43
Output voltage. These pins are connected to the internal output inductor. Connect these pins to the
output load and connect external bypass capacitors between these pins and PGND close to the
device.
VOUT
O
4
Copyright © 2015–2018, Texas Instruments Incorporated
LMZ36002
www.ti.com.cn
ZHCSE75D –SEPTEMBER 2015–REVISED JUNE 2018
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–40
MAX
65
30(2)
UNIT
V
PVIN, INH/UVLO
VOUT, SENSE+, VBSEL
V
Input voltage
VADJ, VERSA-COMP, RT, RTSEL, SS/TR
3.6
V
PWRGD, PWRGD_PU
15
V
CLK
PH
5.5
V
Output voltage
65
V
Operating junction temperature(3)
125
150
245(5)
3(5)
1500
20
°C
°C
°C
Storage temperature
–65
Peak Reflow Case Temperature(4)
Maximum Number of Reflows Allowed(4)
Mechanical shock
Mil-STD-883D, Method 2002.3, 1 msec, 1/2 sine, mounted
Mil-STD-883D, Method 2007.2, 20-2000Hz
G
G
Mechanical vibration
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The maximum voltage that can be applied to these pins is 30 V or PVIN, whichever is less.
(3) See temperature derating curves in the Typical Characteristics section for thermal information.
(4) For soldering specifications, refer to the Soldering Requirements for BQFN Packages application note.
(5) Devices with a date code prior to week 14 2018 (1814) have a peak reflow case temperature of 240°C with a maximum of one reflow
6.2 ESD Ratings
VALUE
±1000
±1000
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.5
NOM
MAX
60
UNIT
V
PVIN
VOUT
ƒSW
TA
Input voltage
Output voltage
2.5
7.5
V
Switching frequency
Operating ambient temperature
200
–40
1000
105
kHz
°C
6.4 Thermal Information
LMZ36002
THERMAL METRIC(1)
RVQ (QFN)
UNIT
43 PINS
RθJA
ψJT
Junction-to-ambient thermal resistance
14
2.6
9
°C/W
°C/W
°C/W
Junction-to-top characterization parameter
Junction-to-board characterization parameter
ψJB
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
Copyright © 2015–2018, Texas Instruments Incorporated
5
LMZ36002
ZHCSE75D –SEPTEMBER 2015–REVISED JUNE 2018
www.ti.com.cn
6.5 Electrical Characteristics
Over -40°C to +105°C free-air temperature, PVIN = 24 V, VOUT = 5 V, IOUT = IOUT(max), ƒsw = 500 kHz, CIN1 = 1 × 10-µF, 100-V
1210 ceramic, CIN2 = 1 × 100-µF 100-V electrolytic bulk, and COUT = 3 × 47-µF, 16-V 1210 ceramic (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT VOLTAGE (PVIN
)
PVIN
Input voltage range
Over IOUT range
4.5(1)
60
V
V
V
PVIN increasing
PVIN decreasing
3.2
2.8
3.8
UVLO
PVIN undervoltage lockout
OUTPUT VOLTAGE
VOUT (ADJ) Output voltage adjust range
Over IOUT range
2.5
7.5
V
Set-point voltage tolerance
Temperature variation
Line regulation
TA = 25°C, IOUT = 300 mA
±0.7%
±0.9%
±0.1%
±0.3%
±2%
±1.5(2)
-40°C ≤ TA ≤ 105°C, IOUT = 0 A
TA = 25°C, Over PVIN range, IOUT = 300 mA
TA = 25°C, IOUT = 300 mA to IOUT max
Includes set-point, line, load, and temperature
20-MHz Bandwidth
VOUT
Load regulation
Total output voltage variation
Output voltage ripple
VOUT ripple
10%
mV/pp
OUTPUT CURRENT
IOUT
IOUT
IOUT
ILIM
Output current
TA = 105°C, natural convection
TA = 105°C, 200LFM
0
0
0
1.5
2
A
A
A
A
Output current
Output current
TA = 95°C, natural convection
2
Overcurrent threshold
2.5
PERFORMANCE
VOUT = 7.5 V, ƒSW = 400 kHz
VOUT = 5 V, ƒSW = 200 kHz
95%
93%
92%
90%
87%
92%
90%
88%
86%
81%
100
PVIN = 12 V
IOUT = 1 A
VOUT = 5 V, ƒSW = 500 kHz
VOUT = 3.3 V, ƒSW= 200 kHz
VOUT = 2.5 V, ƒSW = 200 kHz
VOUT = 7.5 V, ƒSW = 400 kHz
VOUT = 5 V, ƒSW= 250 kHz
η
Efficiency
PVIN = 24 V
IOUT = 1 A
VOUT = 5 V, ƒSW= 500 kHz
VOUT = 3.3 V, ƒSW = 250 kHz
VOUT = 2.5 V, ƒSW = 250 kHz
IOUT = 50%
load step
1 A/µs slew rate
Recovery time
µs
Transient response
Over/Undershoot
2%
SLOW START
tSS
Internal soft-start time
Inhibit control
SS/TR pin open
4.1
ms
INHIBIT
VINH (high)
VINH (hys)
Precision inhibit level
2.00
2.1
2.42
V
V
Inhibit turn-off hysteresis
INH/UVLO pin conected to AGND
–0.294
II (shutdown) Input shutdown supply
current
2.4
6.2(3)
µA
POWER GOOD (PWRGD)
Good
VOUT rising
95%
110%
90%
Fault
VPWRGD
PWRGD thresholds
Fault
VOUT falling
Good
105%
(1) The minimum PVIN is 4.5 V or (VOUT / 0.75), whichever is greater. For VOUT = 3.3 V, the minimum PVIN is 4.75 V when IOUT > 1.5 A.
(2) The stated limit of the set-point voltage tolerance includes the tolerance of both the internal voltage reference and the internal
adjustment resistor. The overall output voltage tolerance is affected by the tolerance of the external RSET resistor.
(3) Specified by design. Not production tested.
6
Copyright © 2015–2018, Texas Instruments Incorporated
LMZ36002
www.ti.com.cn
ZHCSE75D –SEPTEMBER 2015–REVISED JUNE 2018
Electrical Characteristics (continued)
Over -40°C to +105°C free-air temperature, PVIN = 24 V, VOUT = 5 V, IOUT = IOUT(max), ƒsw = 500 kHz, CIN1 = 1 × 10-µF, 100-V
1210 ceramic, CIN2 = 1 × 100-µF 100-V electrolytic bulk, and COUT = 3 × 47-µF, 16-V 1210 ceramic (unless otherwise noted).
PARAMETER
THERMAL SHUTDOWN
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Shutdown Temperature
160
10
°C
°C
TSHUTDOWN
Thermal shutdown
Hysteresis
INPUT/OUTPUT CAPACITANCE
ceramic
10(4)
64(5)
µF
µF
µF
µF
µF
mΩ
CIN
External input capacitance
non-ceramic
100
100
Ceramic
Note(6)
Note(6)
Note(6)
20
Non-ceramic
COUT
External output capacitance
ceramic + non-ceramic
Equivalent series resistance (ESR)
(4) The specified minimum ceramic input capacitance represents the standard capacitance value. The actual effective capacitance after
considering the effects of DC bias and temperature variation should be ≥ 4.7 µF.
(5) The amount of required output capacitance varies depending on the output voltage (see Output Capacitor Selection ). The minimum
required output capacitance must be comprised of ceramic capacitance. The amount of required ceramic capacitance represents the
standard capacitance value. Locate the capacitance close to the device. Adding additional ceramic or non-ceramic capacitance close to
the load improves the response of the regulator to load transients.
(6) The maximum allowable output capacitance varies depending on the output voltage (see Output Capacitor Selection ).
6.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
RT and RTSEL pins open
Synchronization frequency
CLK high level
MIN
410
200
2
TYP
MAX
590
1000
5.5
UNIT
kHz
kHz
V
ƒSW
Switching frequency
500
ƒCLK
VCLK-H
VCLK-L
DCLK
CLK Control
CLK low level
0.4
V
CLK duty cycle
10%
50%
90%
版权 © 2015–2018, Texas Instruments Incorporated
7
LMZ36002
ZHCSE75D –SEPTEMBER 2015–REVISED JUNE 2018
www.ti.com.cn
6.7 Typical Characteristics
TA = 25°C, unless otherwise noted.
100
90
80
70
60
50
40
100
90
80
70
60
50
40
30
VOUT = 7.5 V, fSW = 400 kHz
VOUT = 5.0 V, fSW = 200 kHz
VOUT = 3.3 V, fSW = 200 kHz
VOUT = 2.5 V, fSW = 200 kHz
VOUT = 3.3 V, fSW = 200 kHz
VOUT = 2.5 V, fSW = 200 kHz
30
0.0
0.5
1.0
Output Current (A)
1.5
2.0
0.0
0.5
1.0
Output Current (A)
1.5
2.0
D001
D004
PVIN = 5 V
PVIN = 12 V
图 1. Efficiency vs Output Current
图 2. Efficiency vs Output Current
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0.00
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0.00
VOUT = 3.3 V, fSW = 200 kHz
VOUT = 2.5 V, fSW = 200 kHz
VOUT = 7.5 V, fSW = 400 kHz
VOUT = 5.0 V, fSW = 200 kHz
VOUT = 3.3 V, fSW = 200 kHz
VOUT = 2.5 V, fSW = 200 kHz
0.0
0.5
1.0
1.5
2.0
0.0
0.5
1.0
1.5
2.0
Output Current (A)
Output Current (A)
D002
D005
PVIN = 5 V
PVIN = 12 V
图 3. Power Dissipation vs Output Current
图 4. Power Dissipation vs Output Current
30
25
20
15
10
5
30
25
20
15
10
5
VOUT = 3.3 V, fSW = 200 kHz
VOUT = 2.5 V, fSW = 200 kHz
VOUT = 7.5 V, fSW = 400 kHz
VOUT = 5.0 V, fSW = 200 kHz
VOUT = 3.3 V, fSW = 200 kHz
VOUT = 2.5 V, fSW = 200 kHz
0
0
0.0
0.5
1.0
1.5
2.0
0.0
0.5
1.0
1.5
2.0
Output Current (A)
Output Current (A)
D003
D006
PVIN = 5 V
PVIN = 12 V
图 5. Voltage Ripple vs Output Current
图 6. Voltage Ripple vs Output Current
8
版权 © 2015–2018, Texas Instruments Incorporated
LMZ36002
www.ti.com.cn
ZHCSE75D –SEPTEMBER 2015–REVISED JUNE 2018
6.8 Typical Characteristics
TA = 25°C, unless otherwise noted.
100
90
80
70
60
50
100
90
80
70
60
50
40
30
VOUT = 7.5 V, fSW = 400 kHz
fSW = 250 kHz
fSW = 500 kHz
fSW = 750 kHz
fSW = 1 MHz
VOUT = 5.0 V, fSW = 250 kHz
VOUT = 3.3 V, fSW = 250 kHz
VOUT = 2.5 V, fSW = 250 kHz
40
30
0.0
0.5
1.0
Output Current (A)
1.5
2.0
0.0
0.5
1.0
1.5
2.0
Output Current (A)
D007
D010
PVIN = 24 V
PVIN = 24 V
VOUT = 5 V
over frequency range
图 7. Efficiency vs Output Current
图 8. Efficiency vs Output Current
2.5
2.0
1.5
1.0
0.5
0.0
2.5
2.0
1.5
1.0
0.5
0.0
fSW = 1 MHz
VOUT = 7.5 V, fSW = 400 kHz
VOUT = 5.0 V, fSW = 250 kHz
VOUT = 3.3 V, fSW = 250 kHz
VOUT = 2.5 V, fSW = 250 kHz
fSW = 750 kHz
fSW = 500 kHz
fSW = 250 kHz
0.0
0.5
1.0
1.5
2.0
0.0
0.5
1.0
1.5
2.0
Output Current (A)
Output Current (A)
D008
D011
PVIN = 24 V
PVIN = 24 V
VOUT = 5 V
over frequency range
图 9. Power Dissipation vs Output Current
图 10. Power Dissipation vs Output Current
40
30
20
10
0
40
30
20
10
0
VOUT = 7.5 V, fSW = 400 kHz
VOUT = 5.0 V, fSW = 250 kHz
VOUT = 3.3 V, fSW = 250 kHz
VOUT = 2.5 V, fSW = 250 kHz
fSW = 250 kHz
fSW = 500 kHz
fSW = 750 kHz
fSW = 1 MHz
0.0
0.5
1.0
1.5
2.0
0.0
0.5
1.0
1.5
2.0
Output Current (A)
Output Current (A)
D009
D012
PVIN = 24 V
PVIN = 24 V
VOUT = 5 V
over frequency range
图 11. Voltage Ripple vs Output Current
图 12. Voltage Ripple vs Output Current
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LMZ36002
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www.ti.com.cn
6.9 Typical Characteristics
TA = 25°C, unless otherwise noted.
100
90
80
70
60
50
100
90
80
70
60
50
40
30
VOUT = 7.5 V, fSW = 400 kHz
VOUT = 7.5 V, fSW = 400 kHz
VOUT = 5.0 V, fSW = 250 kHz
VOUT = 3.3 V, fSW = 250 kHz
VOUT = 2.5 V, fSW = 250 kHz
VOUT = 5.0 V, fSW = 300 kHz
VOUT = 3.3 V, fSW = 250 kHz
VOUT = 2.5 V, fSW = 200 kHz
40
30
0.0
0.5
1.0
Output Current (A)
1.5
2.0
0.0
0.5
1.0
Output Current (A)
1.5
2.0
D013
D016
PVIN = 36V
PVIN = 48 V
图 13. Efficiency vs Output Current
图 14. Efficiency vs Output Current
3.0
2.5
2.0
1.5
1.0
0.5
0.0
3.0
2.5
2.0
1.5
1.0
0.5
0.0
VOUT = 7.5 V, fSW = 400 kHz
VOUT = 5.0 V, fSW = 250 kHz
VOUT = 3.3 V, fSW = 250 kHz
VOUT = 2.5 V, fSW = 250 kHz
VOUT = 7.5 V, fSW = 400 kHz
VOUT = 5.0 V, fSW = 300 kHz
VOUT = 3.3 V, fSW = 250 kHz
VOUT = 2.5 V, fSW = 200 kHz
0.0
0.5
1.0
1.5
2.0
0.0
0.5
1.0
1.5
2.0
Output Current (A)
Output Current (A)
D014
D017
PVIN = 36 V
PVIN = 48 V
图 15. Power Dissipation vs Output Current
图 16. Power Dissipation vs Output Current
50
40
30
20
10
0
50
40
30
20
10
0
VOUT = 7.5 V, fSW = 400 kHz
VOUT = 5.0 V, fSW = 250 kHz
VOUT = 3.3 V, fSW = 250 kHz
VOUT = 2.5 V, fSW = 250 kHz
VOUT = 7.5 V, fSW = 400 kHz
VOUT = 5.0 V, fSW = 300 kHz
VOUT = 3.3 V, fSW = 250 kHz
VOUT = 2.5 V, fSW = 200 kHz
0.0
0.5
1.0
1.5
2.0
0.0
0.5
1.0
1.5
2.0
Output Current (A)
Output Current (A)
D015
D018
PVIN = 36 V
PVIN = 48 V
图 17. Voltage Ripple vs Output Current
图 18. Voltage Ripple vs Output Current
10
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ZHCSE75D –SEPTEMBER 2015–REVISED JUNE 2018
6.10 Typical Characteristics (Thermal Derating)
The temperature derating curves represent the conditions at which internal components are at or below the manufacturer's
maximum operating temperatures. Derating limits apply to devices soldered directly to a 50 mm × 100 mm, 4-layer PCB with
2 oz. copper.
115
115
105
105
95
85
75
65
55
45
35
25
95
85
75
65
55
45
35
25
Airflow
400LFM
Airflow
100LFM
200LFM
100LFM
Nat conv
Nat conv
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
C001
C001
Output Current (A)
Output Current (A)
PVIN = 24 V
VOUT = 3.3 V
PVIN = 48 V
VOUT = 3.3 V
图 19. Safe Operating Area
图 20. Safe Operating Area
115
115
105
105
95
85
75
65
55
45
35
25
95
85
75
65
55
45
35
25
Airflow
400LFM
Airflow
200LFM
200LFM
100LFM
Nat conv
100LFM
Nat conv
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
C001
C001
Output Current (A)
Output Current (A)
PVIN = 24 V
VOUT = 5 V
PVIN = 48 V
VOUT = 5 V
图 21. Safe Operating Area
图 22. Safe Operating Area
115
115
105
105
95
85
75
65
55
45
35
25
95
85
75
65
55
45
35
25
Airflow
400LFM
Airflow
400LFM
200LFM
100LFM
Nat conv
200LFM
100LFM
Nat conv
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
C001
C001
Output Current (A)
Output Current (A)
PVIN = 24 V
VOUT = 7.5 V
PVIN = 48 V
VOUT = 7.5 V
图 23. Safe Operating Area
图 24. Safe Operating Area
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7 Detailed Description
7.1 Overview
The LMZ36002 is a full featured 60-V input, 2-A, synchronous step down converter with PWM, MOSFETs,
inductor, and control circuitry integrated into a low-profile, overmolded package. This device enables small
designs by integrating all but the input and output capacitors, while still leaving the ability to adjust key
parameters to meet specific design requirements. The LMZ36002 provides a 3× output voltage range of 2.5 V to
7.5 V. A single external resistor is used to adjust the output voltage to the desired output. The switching
frequency is also adjustable by using an external resistor or a synchronization pulse to accommodate various
input and output voltage conditions and to optimize efficiency. The device provides accurate voltage regulation
for a variety of loads by using an internal voltage reference that is 2% accurate over temperature. Input under-
voltage lockout is internally set at 3.2 V, but can be adjusted upward using a resistor divider on the INH/UVLO
pin of the device. The INH/UVLO pin can also be pulled low to put the device in standby mode to reduce input
quiescent current. The device provides a power good signal to indicate when the output is within ±5% of its
nominal voltage. Thermal shutdown and current limit features protect the device during an overload condition.
Automatic PFM mode improves light-load efficiency. A 43-pin, QFN, package that includes exposed bottom pads
provides a thermally enhanced solution for space-constrained applications.
7.2 Functional Block Diagram
LMZ36002
LDO
PWRGD_PU
PWRGD
100 kΩ
OCP
INH/UVLO
VBSEL
PVIN
Shutdown
Logic
SENSE+
PWRGD
Logic
Thermal
PVIN
Shutdown UVLO
VERSA-COMP
20 kΩ
PH
VADJ
Power
Stage
and
+
+
VOUT
10 µH
SS/TR
VREF
Comp
Control
Logic
CLK
RT
Oscillator
PGND
AGND
RTSEL
38.3 kΩ
12
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7.3 Feature Description
7.3.1 Adjusting the Output Voltage
The VADJ pin sets the output voltage of the LMZ36002. The output voltage adjustment range is from 2.5 V to
7.5 V. The switching frequency range for any output voltage must be determined from 表 4 or 表 5. The
adjustment method requires the addition of RSET, which sets the output voltage, and the connection of SENSE+
to VOUT. The RSET resistor must be connected directly between the VADJ (pin 24) and AGND. The SENSE+ pin
(pin 22) must be connected to VOUT either at the load for improved regulation or at VOUT of the device. 表 1
lists the standard external RSET resistor for a number of common bus voltages.
表 1. Standard RSET Resistor Values for Common Output Voltages
OUTPUT VOLTAGE VOUT (V)
2.5
3.3
5.0
6.0
7.5
RSET (kΩ)
13.7
8.87
5.11
4.02
3.09
For other output voltages, the value of the required resistor can either be calculated using the following formula,
or simply selected from the range of values given in 表 2.
20
RSET
=
(kW)
»
…
ÿ
V
≈
’
OUT
-1
Ÿ
∆
«
÷
◊
1.011
⁄
(1)
表 2. Standard RSET Resistor Values
VOUT (V)
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
4.0
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
5.0
RSET (kΩ)
13.7
12.7
11.8
11.3
10.7
10.2
9.76
9.31
8.87
8.45
8.06
7.87
7.50
7.32
6.98
6.81
6.49
6.34
6.19
5.90
5.76
5.62
5.49
5.36
5.23
5.11
VOUT (V)
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
6.0
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
7.0
7.1
7.2
7.3
7.4
7.5
RSET (kΩ)
4.99
4.87
4.75
4.64
4.53
4.42
4.32
4.22
4.12
4.02
3.97
3.92
3.83
3.74
3.65
3.61
3.57
3.48
3.40
3.36
3.32
3.24
3.20
3.16
3.09
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7.3.2 Switching Frequency (RT)
The switching frequency range of the LMZ36002 is 200 kHz to 1 MHz. Not all PVIN, VOUT, and IOUT conditions
can be set to all of the frequencies in this range. See Recommended Operating Range for the allowable
operating ranges. The switching frequency can easily be set one of three ways. First, leaving the RT pin (pin 9)
and RTSEL pin (pin 10) floating (OPEN) allows operation at the default switching frequency of 500 kHz. Also,
connecting the RTSEL pin to AGND while floating the RT pin, sets the switching frequency to 1 MHz. The option
is also available to set the switching frequency to any frequency in the range of 200 kHz to 1 MHz, by connecting
a resistor (RRT) between the RT pin and AGND, while floating the RTSEL pin. See 表 3 below for standard
resistor values for setting the switching frequency or use 公式 2 to calculate RRT for additional switching
frequencies.
表 3. Switching Frequency RRT Values
Switching Frequency
250 kHz
RRT (kΩ)
158
500 kHz
78.7 or (RT pin OPEN, RTSEL pin OPEN)
53.6
750 kHz
1 MHz
38.3 or (RT pin OPEN, RTSEL pin to AGND)
40200
RRT
=
- 0.6 (kW)
Fsw(kHz)
(2)
7.3.3 Recommended Operating Range
表 4 and 表 5 below show the allowable switching frequencies for a given range of output voltages. Reference 表
4 for applications where the maximum output current is 1.75 A or less. Reference 表 5 for applications that the
output current is greater than 1.75 A. Notice that applications requiring less than 1.75 A can operate over a much
wider range of switching frequencies. For the most efficient solution, always operate at the lowest allowable
frequency.
表 4. Switching Frequency vs Output Voltage
Output Current ≤ 1.75 A
SWITCHING FREQUENCY RANGE (kHz)
VOUT RANGE (V)
PVIN = 12 V
MIN
PVIN = 24 V
PVIN = 36 V
PVIN = 48 V
MIN
MAX
1000
1000
1000
1000
900
MIN
MAX
600
MIN
MAX
400
MAX
300
400
550
630
800
2.5 - 3.5 V
>3.5 - 4.5 V
>4.5 - 5.5 V
>5.5 - 6.5 V
>6.5 - 7.5 V
200
200
200
300
300
200
200
200
200
300
200
200
200
200
300
200
200
200
200
300
850
550
1000
1000
1000
750
1000
950
表 5. Switching Frequency vs Output Voltage
Output Current > 1.75 A
SWITCHING FREQUENCY RANGE (kHz)
VOUT RANGE (V)
PVIN = 12 V
PVIN = 24 V
MIN
PVIN = 36 V
MIN
PVIN = 48 V
MIN
200
200
200
300
300
MAX
450
500
500
500
400
MAX
500
600
650
700
750
MAX
400
550
700
800
800
MIN
200
200
200
250
300
MAX
300
400
550
650
800
2.5 - 3.5 V
>3.5 - 4.5 V
>4.5 - 5.5 V
>5.5 - 6.5 V
>6.5 - 7.5 V
200
200
200
250
300
200
200
200
250
300
14
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7.3.4 Synchronization (CLK)
The LMZ36002 switching frequency can also be synchronized to an external clock from 200 kHz to 1 MHz. Not
all PVIN, VOUT, and IOUT conditions can be set to all of the frequencies in this range. See Recommended
Operating Range section for the allowable operating ranges.
To implement the synchronization feature, connect a clock signal to the CLK pin with a duty cycle between 10%
and 90%. The clock signal amplitude must transition lower than 0.4 V and higher than 2.0 V. The start of the
switching cycle is synchronized to the rising edge of CLK pin. Before the external clock is present the device
operates in RT mode and the switching frequency is set by RRT resistor. Select RRT to set the frequency close to
the external synchronization frequency. When the external clock is present, the CLK mode overrides the RT
mode. If the external clock is removed or fails at logic high or low, the LMZ36002 will switch at the frequency
programmed by the RRT resistor after a time-out period. Connect the CLK pin (pin 8) to AGND if not used.
7.3.5 Output Capacitor Selection
The minimum required and maximum output capacitance of the LMZ36002 is a function of the output voltage as
shown in 表 6. Additionally, the output voltage will determine the Versa-Comp configuration (see VERSA-COMP
Pin Configurations), which is also included in 表 6. The capacitance values listed in 表 6 are the specified
capacitance values. The effects of DC bias and temperature variation must be considered when using ceramic
capacitance. For ceramic capacitors, package size, voltage rating, and dielectric material will contribute to
differences between the specified value and the actual effective value of the capacitance. COUT(min) must be
comprised of ceramic type capacitors. Additional capacitance, not exceeding COUT(max), may be ceramic type or
low-ESR polymer type. See 表 7 for a preferred list of output capacitors by vendor.
表 6. Required Output Capacitance
MINIMUM REQUIRED
Versa-Comp
Connection
(2)
VOUT (V)
MAXIMUM COUT (µF)
(1) (2)
COUT (µF)
2.5
3.3
5.0
6.0
7.5
64
64
350
350
350
200
200
Leave OPEN
Connect to VADJ
Connect to VADJ
Connect to VADJ
Connect to VADJ
64
64
100
(1) Minimum required output capacitance must be comprised of ceramic capacitance.
(2) COUT values represent specified capacitance values.
表 7. Recommended Output Capacitors(1)
CAPACITOR CHARACTERISTICS
CAPACITANCE(2)
ESR(3)
VENDOR
SERIES
PART NUMBER
WORKING
VOLTAGE (V)
(µF)
(mΩ)
TDK
X5R
X5R
C3225X5R1C106K
16
16
10
2
2
Murata
TDK
GRM32ER61C106K
C3225X5R1C226M
GRM32ER61C226K
C3225X5R1A476M
GRM32ER61C476K
C3225X5R0J107M
GRM32ER60J107M
GRM32ER61A107M
C1210C107M4PAC7800
6TPE100MI
10
X5R
16
22
2
Murata
TDK
X5R
16
22
2
X5R
10
47
2
Murata
TDK
X5R
16
47
3
X5R
6.3
6.3
10
100
100
100
100
100
220
220
2
Murata
Murata
Kemet
X5R
2
X5R
2
X5R
16
2
Panasonic
Panasonic
Panasonic
POSCAP
POSCAP
POSCAP
6.3
6.3
6.3
18
9
6TPF220M9L
6TPE220ML
12
(1) Capacitor Supplier Verification, RoHS, Lead-free and Material Details
Consult capacitor suppliers regarding availability, material composition, RoHS and lead-free status, and manufacturing process
requirements for any capacitors identified in this table.
(2) Specified capacitance values.
(3) Maximum ESR @ 100kHz, 25°C.
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7.3.6 VERSA-COMP Pin Configurations
The versa-comp feature of the LMZ36002 allows a simple method to adjust the internal compensation network to
provide the optimized phase and gain margin based on the output voltage. This easy-to-use feature requires no
external components and is implemented by the simple configuration of two adjacent pins on the module.
The versa-comp feature must be configured in one of two ways; VERSA-COMP pin left open or VERSA-COMP
pin tied to VADJ. The output voltage determines the appropriate VERSA-COMP pin configuration. 表 8 lists the
VERSA-COMP configuration. 图 25 and 图 26 show the two possible VERSA-COMP pin configurations.
VOUT
VOUT
SENSE+
SENSE+
VERSA-COMP
VERSA-COMP
VADJ
VADJ
AGND
AGND
RSET
RSET
图 25. VERSA-COMP Open
图 26. VERSA-COMP to VADJ
表 8. VERSA-COMP Pin Configurations
VOUT RANGE (V)
VERSA-COMP PIN
CONFIGURATION
MIN
2.5
MAX
< 3.0
7.5
OPEN
3.0
Connect to VADJ
7.3.7 Input Capacitor Selection
The LMZ36002 requires a ceramic capacitor with a minimum effective input capacitance of 4.7 μF. Use only
high-quality ceramic type X5R or X7R capacitors with sufficient voltage rating. An additional 100 µF of non-
ceramic capacitance is recommended for applications with transient load requirements. The voltage rating of
input capacitors must be greater than the maximum input voltage. To compensate the derating of ceramic
capactors, a voltage rating of twice the maximum input voltage is recommended. At worst case, when operating
at 50% duty cycle and maximum load, the combined ripple current rating of the input capacitors must be at least
1.0 Arms. 表 9 includes a preferred list of capacitors by vendor.
表 9. Recommended Input Capacitors(1)
CAPACITOR CHARACTERISTICS
(2)
(3)
VENDOR
SERIES
PART NUMBER
CAPACITANCE
(µF)
ESR
WORKING VOLTAGE (V)
(mΩ)
TDK
X5R
X7R
X7R
ZA
C3225X5R1H106K
50
50
63
50
63
10
10
3
Murata
GRM32ER71H106K
GRM32ER71J106K
EEHZA1H101P
2
Murata
10
2
Panasonic
Panasonic
100
56
28
30
ZA
EEHZA1J560P
(1) Capacitor Supplier Verification, RoHS, Lead-free and Material Details
Consult capacitor suppliers regarding availability, material composition, RoHS and lead-free status, and manufacturing process
requirements for any capacitors identified in this table.
(2) Specified capacitance values
(3) Maximum ESR @ 100kHz, 25°C.
16
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7.3.8 Output On/Off Inhibit (INH/UVLO)
The INH/UVLO pin provides on and off control of the device. The INH input provides a precise 2.1 V as soon as
rising threshold to allow direct logic drive or connection to a voltage divider from a higher voltage source such as
PVIN. Once the INH/UVLO pin voltage exceeds the threshold voltage, the device starts operation. The INH input
also incorporates 300 mV (typ) of hysteresis resulting in a falling threshold of 1.8 V. If the INH/UVLO pin voltage
is pulled below the threshold voltage, the regulator stops switching and enters low quiescent current state. The
INH/UVLO pin cannot be open circuit or floating. The simplest way to enable the operation of the LMZ36002 is to
connect the INH/UVLO pin to PVIN pin directly as shown in 图 27. This connection allows the LMZ36002 device
to restart when PVIN is again within the operation range.
If an application requires controlling the INH/UVLO pin, either drive it directly with a logic input or use an open
drain and collector device to interface with the pin and place a 100-kΩ resistor between this pin and PVIN pin as
shown in 图 28. When turning Q1 on applies a low voltage to the inhibit control (INH/UVLO) pin and disables the
output of the supply, shown in 图 29. If Q1 is turned off, the supply executes a soft-start power-up sequence, as
shown in 图 30.
PVIN
PVIN
PVIN
100 kΩ
INH/UVLO
AGND
INH/UVLO
AGND
Q1
INH
Control
图 27. Enabling the Device
图 28. Typical Inhibit Control
图 29. Inhibit Turn-Off
图 30. Inhibit Turn-On
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7.3.9 Under Voltage Lockout (UVLO)
The LMZ36002 device has an internal UVLO circuit which prevents the device from operating until the PVIN
voltage exceeds the UVLO threshold, (3.2 V (typ)). The device will begin switching and the output voltage will
begin to rise once PVIN exceeds the threshold, however PVIN must be greater than (VOUT/0.75) in order to for
VOUT to regulate at the set-point voltage.
Applications may require a higher UVLO threshold to prevent early turn-on, for sequencing requirements, or to
prevent input current draw at lower input voltages. An external resistor divider can be added to the INH/UVLO pin
to adjust the UVLO threshold higher. The external resistor divider can be configured as shown in 图 31. 表 10
lists standard values for RUVLO1 and RUVLO2 to adjust the UVLO voltage higher.
PVIN
PVIN
R
R
UVLO1
UVLO2
INH/UVLO
AGND
图 31. Adjustable PVIN UVLO
表 10. Standard Resistor Values for Adjusting PVIN UVLO
VIN UVLO (V)
RUVLO1 (kΩ)
RUVLO2 (kΩ)
4.5
100
46.4
10
15
20
25
30
35
40
45
100
21.0
100
14.0
100
10.5
100
8.45
100
6.98
100
6.04
100
5.23
100
4.64
7.3.10 Remote Sense
The SENSE+ pin must be connected to VOUT at the load, or at the device pins.
Connecting the SENSE+ pin to VOUT at the load improves the load regulation performance of the device by
allowing it to compensate for any I-R voltage drop between its output pins and the load. An I-R drop is caused by
the high output current flowing through the small amount of pin and trace resistance. This should be limited to a
maximum of 300 mV.
注
The remote sense feature is not designed to compensate for the forward drop of nonlinear
or frequency dependent components that may be placed in series with the converter
output. Examples include OR-ing diodes, filter inductors, ferrite beads, and fuses. When
these components are enclosed by the SENSE+ connection, they are effectively placed
inside the regulation control loop, which can adversely affect the stability of the regulator.
7.3.11 VBSEL
The VBSEL pin allows the user to select the input source of the internal bias circuitry to improve efficiency. For
output voltages ≥ 4.5 V, connect this pin to VOUT. For output voltages < 4.5 V, connect this pin to AGND.
18
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7.3.12 Soft-Start (SS/TR)
Leaving SS/TR pin open enables the internal slow start time interval of approximately 4.1 ms. Adding additional
capacitance between the SS pin and AGND increases the slow start time. Increasing the slow start time will
reduce inrush current seen by the input source and reduce the current seen by the device when charging the
output capacitors. To avoid the activation of current limit and ensure proper start-up, the SS capacitor may need
to be increased when operating near the maximum output capacitance limit.
See 表 11 below for SS capacitor values and timing interval.
表 11. Soft-Start Capacitor Values and Soft-Start Time
CSS (nF)
open
15
22
33
47
SS Time (ms)
4.1
7
10
15
20
7.3.13 Power Good (PWRGD) and Pull-up (PWRGD_PU)
The PWRGD pin is an open drain output. Once the voltage on the SENSE+ pin is between 95% and 105% of the
set voltage, the PWRGD pin pull-down is released and the pin floats. The recommended pullup resistor value is
between 10 kΩ and 100-kΩ to a voltage source that is 12 V or less. The LMZ36002 has an internal 100-kΩ
between the PWRGD pin (pin 20) and the PWRGD_PU pin (pin 21). Connect the PWRGD_PU pin to an external
voltage source to avoid using an external pullup resistor. The PWRGD pin is pulled low when the voltage on
SENSE+ is lower than 90% or greater than 110% of the nominal set voltage.
7.3.14 Overcurrent Protection
For protection against load faults, the LMZ36002 incorporates output overcurrent protection. Applying a load that
exceeds the regulator's overcurrent threshold causes the output to shut down when the output voltage falls below
the PWRGD threshold. Following shutdown, the module periodically attempts to recover by initiating a soft-start
power-up as shown in 图 32. This is described as a hiccup mode of operation, whereby the module continues in
a cycle of successive shutdown and power up until the load fault is removed. During this period, the average
current flowing into the fault is significantly reduced which reduces power dissipation. Once the fault is removed,
the module automatically recovers and returns to normal operation as shown in 图 33.
图 33. Removal of Overcurrent
图 32. Overcurrent Limiting
7.3.15 Thermal Shutdown
The internal thermal shutdown circuitry forces the device to stop switching if the junction temperature exceeds
160°C typically. The device reinitiates the power up sequence when the junction temperature drops below 150°C
typically.
版权 © 2015–2018, Texas Instruments Incorporated
19
LMZ36002
ZHCSE75D –SEPTEMBER 2015–REVISED JUNE 2018
www.ti.com.cn
7.4 Device Functional Modes
7.4.1 Active Mode
The LMZ36002 is in Active Mode when PVIN is above the UVLO threshold and the INH/UVLO pin voltage is
above the INH high threshold. The simplest way to enable the LMZ36002 is to connect the INH/UVLO terminal to
PVIN. This allows self start-up of the LMZ36002 when the input voltage is in the operation range: 4.5 V to 60 V.
7.4.2 Light Load Operation
At light load, the LMZ36002 operates in pulse skip mode to improve efficiency and decrease power dissipation by
reducing switching losses and gate drive losses. In light load operation (PFM mode), the output voltage can rise
slightly above the set-point specification. To avoid this behavior, a 300-mA load is required on the output.
7.4.3 Shutdown Mode
The INH/UVLO pin provides electrical ON and OFF control for the LMZ36002. When the INH/UVLO pin voltage is
below the INH threshold, the device is in shutdown mode. In shutdown mode the stand-by current is 2.4 μA
typically with PVIN = 24 V. The LMZ36002 also employs under voltage lock out protection. If PVIN is below the
UVLO level, the output of the regulator turns off.
20
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LMZ36002
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ZHCSE75D –SEPTEMBER 2015–REVISED JUNE 2018
8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LMZ36002 is a synchronous step down DC-DC power module. It is used to convert a higher DC voltage to a
lower DC voltage with a maximum output current of 2 A. The following design procedure can be used to select
components for the LMZ36002. Alternately, the WEBENCH® software may be used to generate complete
designs. When generating a design, the WEBENCH software utilizes an iterative design procedure and accesses
comprehensive databases of components.
8.1.1 Minimum External Component Application
The LMZ36002 requires only a few external components to convert from a wide input voltage supply range to a
wide range of output voltages. 图 34 shows a basic LMZ36002 schematic with only the minimum required
components.
SENSE+
PVIN = 24V
VOUT = 5V
PVIN
VOUT
VBSEL
LMZ36002
10 µF
50 V
100 µF
10 V
INH/UVLO
SS/TR
CLK
PWRGD_PU
PWRGD
RTSEL
RT
VERSA-COMP
VADJ
AGND
PGND
5.11 kΩ
图 34. LMZ36002 Minimum External Component Application
8.1.1.1 Design Requirements
For this design example, use the parameters listed in 表 12 and follow the design procedures below.
表 12. Design Example Parameters
DESIGN PARAMETER
Input Voltage PVIN
VALUE
24 V typical
5.0 V
Output Voltage VOUT
Output Current Rating
Operating Frequency
2 A
500 kHz
8.1.1.2 Detailed Design Procedure
8.1.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LMZ36002 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
版权 © 2015–2018, Texas Instruments Incorporated
21
LMZ36002
ZHCSE75D –SEPTEMBER 2015–REVISED JUNE 2018
www.ti.com.cn
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
•
•
•
•
Run electrical simulations to see important waveforms and circuit performance
Run thermal simulations to understand board thermal performance
Export customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.1.1.2.2 Output Voltage Set-Point
The output voltage of the LMZ36002 device is externally adjustable using a single resistor (RSET). Select the
value of RSET from 表 2 or calculate using 公式 3:
20
RSET
=
(kW)
»
…
ÿ
V
≈
’
OUT
-1
Ÿ
∆
«
÷
◊
1.011
⁄
(3)
Knowing the desired output voltage is 5 V, the RSET value can then be calculated using 公式 3 or selected from
表 2. The formula yields a value of 5.07 kΩ. Choose the closest available value of 5.11 kΩ for RSET
.
8.1.1.2.3 RT and RTSEL
The default switching frequency of the LMZ36002 is set to 500 kHz by leaving the RT pin open and the RTSEL
pin open. The switching frequency of this application is 500-kHz, therefore no additional resistor is required to set
the switching frequency. If another frequency is desired, use 表 3 to select the required resistor value.
8.1.1.2.4 VERSA-COMP
The Versa-Comp feature of the LMZ36002 configures the internal compensation based on the output voltage.
From 表 8, the required Versa-Comp configuration for a 5-V output is to connect the VERSA-COMP pin to the
VADJ pin.
8.1.1.2.5 VBSEL
The VBSEL pin allows the user to select the input source of the internal bias circuitry to improve efficiency. For
output voltages ≥ 4.5 V, connect this pin to VOUT. For output voltages < 4.5 V, connect this pin to AGND.
8.1.1.2.6 Input Capacitors
For this design, a 10-μF, X7R dielectric ceramic capacitor rated for 50 V is used for the input decoupling
capacitor. The effective capacitance at 24 V is 5.7 μF, the equivalent series resistance (ESR) is approximately
3 mΩ, and the current-rating is 5 A.
8.1.1.2.7 Output Capacitors
The minimum required output capacitance for a 5-V output is 64 μF of ceramic capacitance. For this design, a
100-μF, X5R dielectric ceramic capacitor rated for 10 V is used for the output capacitor.
22
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LMZ36002
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ZHCSE75D –SEPTEMBER 2015–REVISED JUNE 2018
8.1.1.2.8 Application Curves
图 36. Output Ripple and PH Node Waveforms
图 35. Start-up Waveforms
8.1.2 Typical Application
图 37 shows a more typical use schematic which makes use of the INH control, Versa-Comp, SS, PWRGD and
PWRGD_PU features, along with adjusting the switching frequency with an external resistor. Setting these
additional features is described below.
SENSE+
PVIN = 24V
VOUT = 5V
PVIN
VOUT
VBSEL
100 kΩ
LMZ36002
100 µF
10 V
100 µF 100 µF
100 µF 10 µF
50 V 50 V
10 V
10 V
INH/UVLO
SS/TR
PWRGD_PU
PWRGD
Q1
PWRGD
INH
Control
22 nF
VERSA-COMP
VADJ
CLK
RTSEL
RT
5.11 kΩ
AGND
PGND
53.6 kΩ
图 37. LMZ36002 Typical Schematic
8.1.2.1 Design Requirements
For this design example, use the parameters listed in 表 13 as the input parameters. For the complete design
procedures begin with the procedures for the basic application shown in the Minimum External Component
Application section as well as the procedures listed in this section.
表 13. Design Example Parameters
DESIGN PARAMETER
Input Voltage PVIN
VALUE
24 V typical
5.0 V
Output Voltage VOUT
版权 © 2015–2018, Texas Instruments Incorporated
23
LMZ36002
ZHCSE75D –SEPTEMBER 2015–REVISED JUNE 2018
www.ti.com.cn
表 13. Design Example Parameters (接下页)
DESIGN PARAMETER
Output Current Rating
Operating Frequency
Inhibit Control
VALUE
2 A
750 kHz
Yes
Power Good Signal
Slow Start Time
Yes
10 ms
300 µF
Output Capacitance
8.1.3 Detailed Design Procedure
8.1.3.1 Switching Frequency
To adjust the switching frequency place a resistor between the RT pin (pin 9) and AGND. Refer to 表 3 to select
the required value for the RRT resistor. To set the switching frequency to 750 kHz, the value for RRT is 53.6 kΩ,
selected from 表 3.
8.1.3.2 Power Good
The PWRGD pin is an open drain output. The LMZ36002 includes an internal 100-kΩ pullup resistor between the
PWRGD pin and the PWRGD_PU pin. Connecting the PWRGD_PU pin to a pullup voltage allows use of the
PWRGD signal without adding an additional component. In this example, the 5-V output is used as the pullup
voltage.
8.1.3.3 Inhibit Control
To control the turn ON and OFF of the LMZ36002, an open-drain and collector device is recommended. The
open-drain and collector device must be rated for the maximum voltage applied to the PVIN pin. A pull-up
resistor is required between the INH/UVLO pin and PVIN. Place a 100-kΩ resistor between the INH/UVLO pin
and the PVIN pin.
8.1.3.4 VERSA-COMP
The Versa-Comp feature of the LMZ36002 configures the internal compensation based on the output voltage.
From 表 8, the required Versa-Comp configuration for a 5-V output is to connect the VERSA-COMP pin to the
VADJ pin.
8.1.3.5 VBSEL
The VBSEL pin allows the user to select the input source to the internal power circuitry to improve efficiency. For
output voltages ≥ 4.5 V, connect this pin to VOUT. For output voltages < 4.5 V, connect this pin to AGND.
8.1.3.6 Soft-Start Capacitors
When the SS/TRK pin remains floating the LMZ36002 implements a typical soft-start time of 4.1 ms. In order to
increase the slow start time, an external slow start capacitor, CSS must be placed between the SS/TRK pin and
AGND. Select a value for CSS from 表 11.
For the desired soft-start time of 10 ms, a soft-start capacitor value of 22 nF is selected from 表 11.
8.1.3.7 Input Capacitors
For this design, a 10-μF ceramic capacitor plus a 100-µF aluminum electrolytic capacitor, both rated for 50 V are
used for the input decoupling capacitors.
8.1.3.8 Output Capacitors
The maximum allowable output capacitance for a 5-V output is 350 μF of capacitance. At least 64 µF of
capacitance must be ceramic type. For this design, 3× 100-μF, X5R dielectric ceramic capacitors rated for 10 V
are used for the output capacitors.
24
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LMZ36002
www.ti.com.cn
ZHCSE75D –SEPTEMBER 2015–REVISED JUNE 2018
9 Power Supply Recommendations
The LMZ36002 is designed to operate from an input voltage supply range between 4.5 V and 60 V. This input
supply should be well regulated and able to withstand maximum input current and maintain a stable voltage. The
resistance of the input supply rail should be low enough that an input current transient does not cause a high
enough drop at the LMZ36002 supply voltage that can cause a false UVLO fault triggering and system reset.
If the input supply is located more than a few inches from the LMZ36002 additional bulk capacitance may be
required in addition to the ceramic bypass capacitors. Typically, a 47 µF or 100 μF electrolytic capacitor will
suffice.
版权 © 2015–2018, Texas Instruments Incorporated
25
LMZ36002
ZHCSE75D –SEPTEMBER 2015–REVISED JUNE 2018
www.ti.com.cn
10 Layout
The performance of any switching power supply depends as much upon the layout of the PCB as the component
selection. The following guidelines will help users design a PCB with the best power conversion performance,
thermal performance, and minimized generation of unwanted EMI.
10.1 Layout Guidelines
To achieve optimal electrical and thermal performance, an optimized PCB layout is required. 图 38 through 图
41, shows a typical PCB layout. Some considerations for an optimized layout are:
•
Use large copper areas for power planes (PVIN, VOUT, and PGND) to minimize conduction loss and thermal
stress.
•
•
•
•
•
Place ceramic input and output capacitors close to the device pins to minimize high frequency noise.
Locate additional output capacitors between the ceramic capacitor and the load.
Keep AGND and PGND separate from one another. The connection is made internal to the device.
Place RSET, RRT, and CSS as close as possible to their respective pins.
Use multiple vias to connect the power planes to internal layers.
10.2 Layout Example
图 38. Typical Top-Layer Layout
图 39. Typical Layer-2 Layout
图 40. Typical Layer-3 Layout
图 41. Typical Bottom-Layer Layout
26
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LMZ36002
www.ti.com.cn
ZHCSE75D –SEPTEMBER 2015–REVISED JUNE 2018
10.3 EMI
The LMZ36002 is compliant with EN55022 Class B radiated emissions. 图 42 through 图 45 show typical
examples of radiated emissions plots for the LMZ36002 operating from 24 V and 48 V. Both graphs include the
plots of the antenna in the horizontal and vertical positions.
图 42. Radiated Emissions (EN55022 Class B)
图 43. Radiated Emissions (EN55022 Class B)
24-V Input, 5-V Output, 2-A Load, 250 kHz
48-V Input, 5-V Output, 2-A Load, 300 kHz
图 45. Radiated Emissions (EN55022 Class B)
图 44. Radiated Emissions (EN55022 Class B)
48-V Input, 7.5-V Output, 2-A Load, 750 kHz
24-V Input, 5-V Output, 2-A Load, 500 kHz
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27
LMZ36002
ZHCSE75D –SEPTEMBER 2015–REVISED JUNE 2018
www.ti.com.cn
11 器件和文档支持
11.1 器件支持
11.1.1 开发支持
11.1.1.1 使用 WEBENCH® 工具创建定制设计
单击此处，使用 LMZ36002 器件并借助 WEBENCH® 电源设计器创建定制设计方案。
1. 首先键入输入电压 (VIN)、输出电压 (VOUT) 和输出电流 (IOUT) 要求。
2. 使用优化器拨盘优化该设计的关键参数，如效率、尺寸和成本。
3. 将生成的设计与德州仪器 (TI) 的其他可行解决方案进行比较。
WEBENCH 电源设计器可提供定制原理图以及罗列实时价格和组件供货情况的物料清单。
在多数情况下，可执行以下操作：
•
•
•
•
运行电气仿真，观察重要波形以及电路性能
运行热性能仿真，了解电路板热性能
将定制原理图和布局方案以常用 CAD 格式导出
打印设计方案的 PDF 报告并与同事共享
有关 WEBENCH 工具的详细信息，请访问 www.ti.com.cn/WEBENCH。
11.1.2 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此类
产品或服务单独或与任何 TI 产品或服务一起的表示或认可。
11.2 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.4 商标
E2E is a trademark of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
11.5 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.6 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此产品说明书的浏览器版本，请参阅左侧的导航栏。
28
版权 © 2015–2018, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
4-Jun-2020
PACKAGING INFORMATION
Orderable Device
LMZ36002RVQR
LMZ36002RVQT
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 105
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
B3QFN
B3QFN
RVQ
43
43
500
RoHS Exempt
& Green
NIPDAU
Level-3-245C-168 HR
LMZ36002
LMZ36002
ACTIVE
RVQ
250
RoHS Exempt
& Green
NIPDAU
Level-3-245C-168 HR
-40 to 105
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
4-Jun-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Mar-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMZ36002RVQR
LMZ36002RVQT
B3QFN
B3QFN
RVQ
RVQ
43
43
500
250
330.0
330.0
24.4
24.4
10.35 10.35
10.35 10.35
4.6
4.6
16.0
16.0
24.0
24.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Mar-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LMZ36002RVQR
LMZ36002RVQT
B3QFN
B3QFN
RVQ
RVQ
43
43
500
250
383.0
383.0
353.0
353.0
58.0
58.0
Pack Materials-Page 2
PACKAGE OUTLINE
RVQ0043A
B3QFN - 4.4mm max height
PLASTIC QUAD FLATPACK - NO LEAD
A
10.15
9.85
B
PIN 1
INDEX AREA
10.15
9.85
(13 )
ALL AROUND
(0.2) TYP
4.4
4.2
C
(2.17)
SEATING PLANE
0.08 C
(0.32) TYP
0.45
0.35
3.4
3.2
TYP
0.1
C A B
8X (0.975)
PKG
0.05
1.1
0.9
11
21
43
(3.6)
1.15
0.95
PKG
41
5.1
4.9
42
(1.188)
0.6
0.4
1.225
1.025
36X
2.5
2.3
31
1
40
PIN 1 ID
0.8 TYP
(3.6)
4X 8
4226463/A 02/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pads must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RVQ0043A
B3QFN - 4.4mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(9.7)
4X (8)
(0.8) TYP
(3.6)
40
1
31
(2.4)
(1.05)
36X (0.7)
(1.125)
(5)
42
(1.188)
PKG
41
(9.7)
(1.23) TYP
(3.6)
(
0.2) TYP
(1)
(3.3)
43
11
21
(R0.05) TYP
(0.4) TYP
(0.6) TYP
(0.575)
8X (0.975)
PKG
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
0.05 MIN
ALL AROUND
EXPOSED
METAL
0.05 MAX.
ALL AROUND
EXPOSED
METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAIL
4226463/A 02/2021
NOTES: (continued)
4. This package designed to be soldered to a thermal pads on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RVQ0043A
B3QFN - 4.4mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(9.7)
4X (8)
(3.6)
(0.8) TYP
40
1
31
8X (1.06)
(0.99)
36X (0.7)
42
(1.04)
41
8X (1.03)
(1.188)
PKG
0.615
(9.7)
(3.6)
(1.23)
TYP
(
0.95)
43
11
21
(0.63) TYP
(1.15)
(0.4) TYP
(R0.05) TYP
8X (0.975)
PKG
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm STENCIL THICKNESS
EXPOSED PAD 41:
73% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
EXPOSED PAD 42:
87% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
EXPOSED PAD 43:
82% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:8X
4226463/A 02/2021
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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