LMZM33602 [TI]
采用紧凑型 7x9x4mm QFN 封装的 4V 至 36V、2A 降压直流/直流电源模块;
| 型号： | LMZM33602 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用紧凑型 7x9x4mm QFN 封装的 4V 至 36V、2A 降压直流/直流电源模块 电源电路 |
| 文件： | 总36页 (文件大小：2806K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LMZM33602
ZHCSHL8D –DECEMBER 2017 –REVISED AUGUST 2020
采用QFN 封装的LMZM33602 4V 至36V 输入、2A 电源模块
1 特性
3 说明
• 完全集成的电源解决方案
– 仅需四个外部元件
– 最小解决方案尺寸< 100mm2
• 9mm × 7mm × 4mm QFN 封装
LMZM33602 电源模块是一款易于使用的集成式电源解
决方案，它在一个扁平封装内整合了一个带有功率
MOSFET 的 2A 降压直流/直流转换器、一个屏蔽式电
感器和多个无源器件。此电源解决方案仅需四个外部组
件，并且省去了设计流程中的环路补偿和磁性元件选择
过程。
– 所有引脚均分布在封装外围
– 引脚与3A LMZM33603 兼容
• 输入电压范围：4V 至36V
• 输出电压范围：1 V 至18 V
• 效率高达95%
• 可调节的开关频率范围（200kHz 至1.2MHz）
• 支持与外部时钟同步
• 电源正常状态输出
该器件采用 9mm × 7mm × 4mm、18 引脚 QFN 封
装，可轻松焊接到印刷电路板上，并实现紧凑的低厚度
负载点设计。LMZM33602 具有全套功能集，包括电源
正常状态指示、可编程UVLO、预偏置启动、过流和过
热保护，因此是为各种应用供电的出色器件。
器件信息
• 符合EN55011 B 类辐射EMI 标准
• IC 工作结温范围：–40°C 至+125°C
• 工作环境温度范围：-40°C 至+105°C
• 使用LMZM33602 并借助WEBENCH® Power
Designer 创建定制设计方案
封装尺寸（标称值）
器件型号
LMZM33602
封装
QFN (18)
9.00mm × 7.00mm
2 应用
• 工厂和楼宇自动化
• 智能电网与能源
• 工业
• 医疗
• 国防
• 反相输出应用
115
105
95
85
75
65
55
45
35
25
PGOOD
VIN
VIN
VOUT
EN/SYNC
VOUT
CIN
RFBT
LMZM33602
COUT
RT
FB
PGND
RRT
RFBB
VIN = 24V
VOUT = 3.3V, fsw = 300kHz
VOUT = 5.0V, fsw = 450kHz
VOUT = 12V, fsw = 900kHz
Copyright © 2017, Texas Instruments Incorporated
简化原理图
0.0
0.5
1.0
Output Current (A)
1.5
2.0
SOA2
安全操作区域
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNVSAO4
LMZM33602
ZHCSHL8D –DECEMBER 2017 –REVISED AUGUST 2020
www.ti.com.cn
Table of Contents
7 Detailed Description......................................................10
7.1 Overview...................................................................10
7.2 Functional Block Diagram.........................................10
7.3 Feature Description...................................................11
7.4 Device Functional Modes..........................................19
8 Application and Implementation..................................20
8.1 Application Information............................................. 20
8.2 Typical Application.................................................... 20
9 Device and Documentation Support............................27
9.1 Device Support......................................................... 27
9.2 Documentation Support............................................ 27
9.3 Receiving Notification of Documentation Updates....27
9.4 Support Resources................................................... 27
9.5 Trademarks...............................................................27
9.6 Electrostatic Discharge Caution................................27
9.7 Glossary....................................................................27
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
Pin Functions.................................................................... 3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................5
6.6 Switching Characteristics............................................6
6.7 Typical Characteristics (VIN = 5 V)..............................7
6.8 Typical Characteristics (VIN = 12 V)............................8
6.9 Typical Characteristics (VIN = 24 V)............................9
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision C (March 2018) to Revision D (August 2020)
Page
• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1
• Updated Storage temperature range in Absolute Maximum Ratings ................................................................ 4
Changes from Revision B (February 2018) to Revision C (March 2018)
Page
• Added 节9.4 section........................................................................................................................................ 24
Changes from Revision A (February 2018) to Revision B (February 2018)
Page
• 首次发布量产数据数据表.................................................................................................................................... 1
Changes from Revision * (December 2017) to Revision A (January 2018)
Page
• 添加了新应用和指向SNVA800 应用报告的链接；并作了细微的编辑更新........................................................ 1
• Added sentence re: inverting buck-boost topology to 节8.1 ........................................................................... 20
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5 Pin Configuration and Functions
AGND
1
PGND
15
18
17 16
EN/SYNC
2
PGND
DNC
14
13
RT
3
4
VIN
12
DNC
PGND
5
11
SW
VOUT
6
8
9
VOUT
SW
7
10
图5-1. RLR Package 18-Pin QFN Top View
Pin Functions
PIN
TYPE
DESCRIPTION
NO.
NAME
Analog ground. Zero voltage reference for internal references and logic. Do not connect this pin to
PGND; the connection is made internal to the device. See the 节Layout of the data sheet for a
recommended layout.
1
AGND
G
EN - Enable input to regulator. High = On, Low = Off. Can be connected to VIN. Do not float. This pin
can be used to set the input undervoltage lockout with two resistors. See 节7.3.9. SYNC - The
internal oscillator can be synchronized to an external clock via AC-coupling. See 节7.3.5 for details.
2
EN/SYNC
I
An external timing resistor connected between this pin and AGND adjusts the switching frequency of
the device. If left open, the default switching frequency is 400 kHz.
3
4
RT
I
I
VIN
Input supply voltage. Connect external input capacitors between this pin and PGND.
Power ground. This is the return current path for the power stage of the device. Connect pin 5 to the
input source, the load, and to the bypass capacitors associated with VIN and VOUT using power
ground planes on the PCB. Pins 14 and 15 are not connected to PGND internal to the device
and must be connected to PGND at pad 18. Connect pad 18 to the power ground planes using
multiple vias for good thermal performance. See 节Layout of the data sheet for a recommended
layout.
5, 14, 15, 18 PGND
G
Output voltage. These pins are connected to the internal output inductor. Connect these pins to the
output load and connect external bypass capacitors between these pins and PGND.
6, 7, 8
VOUT
SW
O
O
Switch node. Connect these pins to a small copper island under the device for thermal relief. Do not
place any external component on these pins or tie them to a pin of another function.
9, 10, 11
12, 13
Do not connect. Each pin must be soldered to an isolated pad. These pins connect to internal
circuitry. Do not connect these pins to one another, AGND, PGND, or any other voltage.
DNC
—
Feedback input. Connect the center point of the feedback resistor divider to this pin. Connect the
upper resistor (RFBT) of the feedback divider to VOUT at the desired point of regulation. Connect the
lower resistor (RFBB) of the feedback divider to AGND.
16
17
FB
I
Open drain output for power-good flag. Use a 10-kΩto 100-kΩpullup resistor to logic rail or other
DC voltage no higher than 12 V.
PGOOD
O
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6 Specifications
6.1 Absolute Maximum Ratings
Over operating ambient temperature range (unless otherwise noted)(1)
MIN
–0.3
–5.5
–0.3
–0.3
–1
MAX
42
UNIT
V
VIN
EN/SYNC
Input voltage
VIN + 0.3
15
V
PGOOD
V
FB, RT
SW
4.5
V
VIN + 0.3
42
V
Output voltage
SW (< 10-ns transients)
V
–5
VOUT
VIN
V
–0.3
Sink current
PGOOD
3
mA
G
Mechanical shock
Mechanical vibration
Mil-STD-883D, Method 2002.3, 1 msec, 1/2 sine, mounted
500
Mil-STD-883D, Method 2007.2, 20 to 2000 Hz
20
G
(2)
Operating IC junction temperature, TJ
125
°C
°C
°C
–40
–40
–55
(2)
Operating ambient temperature, TA
105
Storage temperature, Tstg
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) The ambient temperature is the air temperature of the surrounding environment. The junction temperature is the temperature of the
internal power IC when the device is powered. Operating below the maximum ambient temperature, as shown in the safe operating
area (SOA) curves in the typical characteristics sections, ensures that the maximum junction temperature of any component inside the
module is never exceeded.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2500
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
±750
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
Over operating ambient temperature range (unless otherwise noted)
MIN
4(1)
MAX
UNIT
V
Input voltage, VIN
36
18
VIN
12
1
Output voltage, VOUT
1
V
EN/SYNC voltage
V
–5
–0.3
PGOOD pullup voltage, VPGOOD
PGOOD sink current, IPGOOD
Output current, IOUT
V
mA
A
0
2
Operating ambient temperature, TA
105
°C
–40
(1) For output voltages ≤5 V, the recommended minimum VIN is 4 V or (VOUT + 1.5 V), whichever is greater. For output voltages > 5 V,
the recommended minimum VIN is (1.3 × VOUT). See Voltage Dropout for information on voltage dropout.
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6.4 Thermal Information
LMZM33602
THERMAL METRIC(1)
RLR (QFN)
18 PINS
18.9
UNIT
RθJA
ψJT
Junction-to-ambient thermal resistance(2)
Junction-to-top characterization parameter(3)
Junction-to-board characterization parameter(4)
°C/W
°C/W
°C/W
2.0
6.2
ψJB
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(2) The junction-to-ambient thermal resistance, RθJA, applies to devices soldered directly to a 63 mm × 63 mm, 4-layer PCB with 2 oz.
copper and natural convection cooling. Additional airflow reduces RθJA
.
(3) The junction-to-top board characterization parameter, ψJT, estimates the junction temperature, TJ, of a device in a real system, using a
procedure described in JESD51-2A (section 6 and 7). TJ = ψJT × Pdis + TT; where Pdis is the power dissipated in the device and TT is
the temperature of the top of the device.
(4) The junction-to-board characterization parameter, ψJB, estimates the junction temperature, TJ, of a device in a real system, using a
procedure described in JESD51-2A (sections 6 and 7). TJ = ψJB × Pdis + TB; where Pdis is the power dissipated in the device and TB
is the temperature of the board 1mm from the device.
6.5 Electrical Characteristics
Over –40°C to +105°C ambient temperature, VIN = 24 V, VOUT = 5 V, IOUT = IOUT maximum, fsw = 450 kHz (unless otherwise
noted); CIN1 = 2 × 4.7-µF, 50-V, 1210 ceramic; CIN2 = 100-µF, 50-V, electrolytic; COUT = 4 × 22-µF, 25-V, 1210 ceramic.
Minimum and maximum limits are specified through production test or by design. Typical values represent the most likely
parametric norm and are provided for reference only.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT VOLTAGE (VIN)
VIN
Input voltage
Over IOUT range
4(1)
3.3
3
36
3.9
3.5
4
V
V
VIN increasing
3.6
3.3
2
UVLO
VIN undervoltage lockout
VIN decreasing
V
ISHDN
Shutdown supply current
VEN = 0 V, VIN = 12 V
µA
OUTPUT VOLTAGE (VOUT
)
VOUT(ADJ)
Output voltage adjust
Output voltage ripple
Over IOUT range
1
18
V
VOUT(Ripple)
FEEDBACK
20-MHz bandwidth
10
mV
TA = 25°C, IOUT = 0 A
0.985
0.98
1
1
1.015
1.02
V
V
Feedback voltage(2)
Load regulation
Over VIN range, –40°C ≤TJ ≤125°C, IOUT
0 A
=
VFB
Over IOUT range, TA = 25°C
0.04%
10
IFB
Feedback leakage current VFB = 1 V
nA
CURRENT
Output current
Natural convection, TA = 25°C
0
2
A
A
IOUT
Overcurrent threshold
3.6
PERFORMANCE
VOUT = 12 V, fSW = 900 kHz
94%
90%
88%
93%
91%
89%
90
VIN = 24 V,
IOUT = 1 A
VOUT = 5 V, fSW = 450 kHz
VOUT = 3.3 V, fSW = 300 kHz
VOUT = 5 V, fSW = 450 kHz
VOUT = 3.3 V, fSW = 300 kHz
VOUT = 2.5 V, fSW = 250 kHz
Over/undershoot
Efficiency
ƞ
VIN = 12 V,
IOUT = 1 A
25% to 75%
load step
1 A/µs slew rate
mV
µs
Transient response
Recovery time
55
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Over –40°C to +105°C ambient temperature, VIN = 24 V, VOUT = 5 V, IOUT = IOUT maximum, fsw = 450 kHz (unless otherwise
noted); CIN1 = 2 × 4.7-µF, 50-V, 1210 ceramic; CIN2 = 100-µF, 50-V, electrolytic; COUT = 4 × 22-µF, 25-V, 1210 ceramic.
Minimum and maximum limits are specified through production test or by design. Typical values represent the most likely
parametric norm and are provided for reference only.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SOFT START
TSS
Internal soft start time
6
ms
THERMAL
Shutdown temperature
170
15
°C
°C
TSHDN
Thermal shutdown
Hysteresis
ENABLE (EN)
VEN-H
EN rising threshold
1.4
1.55
0.4
10
1.7
V
V
VEN-HYS
EN hysteresis voltage
VIN = 4 V to 36 V, VEN = 2 V
VIN = 4 V to 36 V, VEN = 36 V
100
1
nA
µA
IEN
EN Input leakage current
POWER GOOD (PGOOD)
VOUT rising (good)
VOUT rising (fault)
92%
94%
107%
1.5%
96.5%
110%
VPGOOD
PGOOD thresholds
104%
VOUT falling hysteresis
Minimum VIN for valid
PGOOD
1.5
0.4
V
V
50-μA pullup, VEN = 0 V, TA = 25°C
PGOOD low voltage
0.5-mA pullup, VEN = 0 V
CAPACITANCE
Ceramic type
9.4(3)
min(4)
µF
µF
CIN
External input capacitance
Non-ceramic type
47(3)
External output
capacitance
COUT
max(5)
µF
(1) See Voltage Dropout for information on voltage dropout.
(2) The overall output voltage tolerance will be affected by the tolerance of the external RFBT and RFBB resistors.
(3) A minimum of 9.4 µF (2 × 4.7 µF) ceramic input capacitance is required for proper operation. An additional 47 µF of bulk capacitance is
recommended for applications with transient load requirements. See the Input Capacitors section of the datasheet for further guidance.
(4) The minimum amount of required output capacitance varies depending on the output voltage (see Output Capacitor Selection). A
minimum amount of ceramic output capacitance is required. Locate the capacitance close to the device. Adding additional ceramic or
non-ceramic capacitance close to the load improves the response of the regulator to load transients.
(5) The maximum allowable output capacitance varies depending on the output voltage (see Output Capacitor Selection).
6.6 Switching Characteristics
Over operating ambient temperature range (unless otherwise noted)
Minimum and maximum limits are specified through production test or by design. Typical values represent the most likely
parametric norm, and are provided for reference only.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
FREQUENCY (RT) and SYNCHRONIZATION (EN/SYNC)
Default switching frequency
RT pin = open
340
200
400
460
kHz
kHz
fSW
Switching frequency range
1200
Peak-to-peak amplitude of SYNC clock AC
signal (measured at SYNC pin)
VSYNC
2.8
5.5
V
TS-MIN
Minimum SYNC ON/OFF time
100
ns
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6.7 Typical Characteristics (VIN = 5 V)
The typical characteristic data has been developed from actual products tested at 25°C. This data is considered
typical for the device.
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
VOUT, fSW
3.3 V, 300 kHz
2.5 V, 250 kHz
1.0 V, 250 kHz
VOUT, fSW
3.3 V, 300 kHz
2.5 V, 250 kHz
1.0 V, 250 kHz
0.0
0.5
1.0
Output Current (A)
1.5
2.0
0.0
0.5
1.0
Output Current (A)
1.5
2.0
D001
D005
VIN = 5 V
VIN = 5 V
图6-1. Efficiency vs Output Current
图6-2. Power Dissipation vs Output Current
10.0
9.5
9.0
8.5
8.0
7.5
7.0
6.5
6.0
5.5
5.0
115
105
95
VOUT, fSW
2.5 V, 250 kHz
3.3 V, 300 kHz
1.0 V, 250 kHz
85
75
65
55
45
Airflow
Nat Conv
35
25
0.0
0.5
1.0
Output Current (A)
1.5
2.0
0.0
0.5
1.0
Output Current (A)
1.5
2.0
D009
D004
VIN = 5 V
COUT = 4 × 22 µF, 25 V, 1210 ceramic
VIN = 5 V
All VOUT
图6-3. Voltage Ripple vs Output Current
图6-4. Safe Operating Area
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6.8 Typical Characteristics (VIN = 12 V)
The typical characteristic data has been developed from actual products tested at 25°C. This data is considered
typical for the device.
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
VOUT, fSW
5.0 V, 450 kHz
3.3 V, 300 kHz
2.5 V, 250 kHz
1.0 V, 250 kHz
VOUT, fSW
5.0 V, 450 kHz
3.3 V, 300 kHz
2.5 V, 250 kHz
1.0 V, 250 kHz
0.0
0.5
1.0
Output Current (A)
1.5
2.0
0.0
0.5
1.0
Output Current (A)
1.5
2.0
D002
D006
VIN = 12 V
VIN = 12 V
图6-5. Efficiency vs Output Current
图6-6. Power Dissipation vs Output Current
16
15
14
13
12
11
10
9
115
105
95
VOUT, fSW
2.5 V, 250 kHz
3.3 V, 300 kHz
5.0 V, 450 kHz
1.0 V, 250 kHz
85
75
65
55
8
7
45
6
Airflow
Nat Conv
35
25
5
4
0.0
0.0
0.5
1.0
Output Current (A)
1.5
2.0
0.5
1.0
Output Current (A)
1.5
2.0
D004
D010
VIN = 12 V
VOUT = 5 V
fSW = 450 kHz
VIN = 12 V
COUT = 4 × 22 µF, 25 V, 1210 ceramic
图6-8. Safe Operating Area
图6-7. Voltage Ripple vs Output Current
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6.9 Typical Characteristics (VIN = 24 V)
The typical characteristic data has been developed from actual products tested at 25°C. This data is considered
typical for the device.
100
95
90
85
80
75
70
65
60
55
50
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
VOUT, fSW
12 V, 900 kHz
5.0 V, 450 kHz
3.3 V, 300 kHz
2.5 V, 250 kHz
VOUT, fSW
12 V, 900 kHz
5.0 V, 450 kHz
3.3 V, 300 kHz
2.5 V, 250 kHz
0.0
0.5
1.0
Output Current (A)
1.5
2.0
0.0
0.5
1.0
Output Current (A)
1.5
2.0
D003
D007
VIN = 24 V
VIN = 24 V
图6-9. Efficiency vs Output Current
图6-10. Power Dissipation vs Output Current
16.0
115
105
95
VOUT, fSW
2.5 V, 250 kHz
3.3 V, 300 kHz
12 V, 900 kHz
5.0 V, 450 kHz
15.0
14.0
13.0
12.0
11.0
10.0
9.0
85
75
65
55
45
8.0
Airflow
100LFM
Nat Conv
35
7.0
25
6.0
0.0
0.5
1.0
Output Current (A)
1.5
2.0
0.0
0.5
1.0
Output Current (A)
1.5
2.0
D011
D008
VIN = 24 V
COUT = 4 × 22 µF, 25 V, 1210 ceramic
VIN = 24 V
VOUT = 5 V
fSW = 450 kHz
图6-11. Voltage Ripple vs Output Current
图6-12. Safe Operating Area
115
105
95
85
75
65
55
Airflow
45
200LFM
100LFM
Nat Conv
35
25
0.0
0.5
1.0
Output Current (A)
1.5
2.0
D012
VIN = 24 V
VOUT = 12 V
fSW = 900 kHz
图6-13. Safe Operating Area
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7 Detailed Description
7.1 Overview
The LMZM33602 is a full-featured, 36-V input, 2-A, synchronous step-down converter with PWM, MOSFETs,
shielded inductor, and control circuitry integrated into a low-profile, overmolded package. The device integration
enables small designs, while providing the ability to adjust key parameters to meet specific design requirements.
The LMZM33602 provides an output voltage range of 1 V to 18 V. An external resistor divider is used to adjust
the output voltage to the desired value. The switching frequency can also be adjusted, by either an external
resistor or a sync signal, which allows the LMZM33602 to accommodate a variety of input and output voltage
conditions as well as optimize efficiency. The device provides accurate voltage regulation over a wide load range
by using a precision internal voltage reference. Input undervoltage lockout is internally set at 3.6 V (typical), but
can be adjusted upward using a resistor divider on the EN/SYNC pin of the device. The EN/SYNC pin can also
be pulled low to put the device into standby mode to reduce input quiescent current. A power-good signal is
provided to indicate when the output is within its nominal voltage range. Thermal shutdown and current limit
features protect the device during an overload condition. An 18-pin, QFN package that includes exposed bottom
pads provides a thermally enhanced solution for space-constrained applications.
7.2 Functional Block Diagram
Thermal
Shutdown
Precision
Enable
EN/SYNC
Shutdown
Logic
Sync
Detect
OCP
Oscillator
VIN
UVLO
RT
VIN
PGOOD
SW
PGOOD
Logic
Power
Stage
and
FB
6.8µH
VOUT
Control
Logic
Soft
Start
+
+
Comp
VREF
AGND
PGND
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7.3 Feature Description
7.3.1 Adjusting the Output Voltage
A resistor divider connected to the FB pin (pin 16) programs the output voltage of the LMZM33602. The output
voltage adjustment range is from 1 V to 18 V. 图 7-1 shows the feedback resistor connections for setting the
output voltage. The recommended value of RFBB is 10 kΩ. The value for RFBT can be calculated using 方程式 1.
Depending on the output voltage, a feedforward capacitor, CFF, can be required for optimum transient
performance. 表 7-1 lists the standard external RFBT and CFF values for several output voltages between 2.5 V
and 18 V. 表 7-2 lists the values for output voltages below 2.5 V. Additionally, 表 7-1 and 表 7-2 include the
recommended switching frequency (FSW), the frequency setting resistor (RRT), and the minimum and maximum
output capacitance for each of the output voltages listed.
For designs with RFBB other than 10 kΩ, adjust CFF and RFBT such that (CFF × RFBT) is unchanged and adjust
RFBT such that (RFBT / RFBB) is unchanged.
space
RFBT = 10ì V
-1 kW
OUT
(1)
VOUT
RFBT
CFF
FB
RFBB
10 kꢀ
AGND
图7-1. Setting the Output Voltage
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表7-1. Required Component Values (VOUT ≥2.5 V)
COUT(min) (µF)(1)
COUT(max) (µF)(2)
RFBT (kΩ)(3)
15.0
RRT (kΩ)
VOUT (V)
CFF (pF)
fSW (kHz)
2.5
3.3
5
220
250
162
150
88
66
54
40
36
22
22
20
16
400
300
200
160
130
110
80
23.2
150
300
133
40.2
100
450
88.7
71.5
60.4
56.2
44.2
39.2
35.7
33.2
6
49.9
68
550
7.5
9
64.9
47
650
80.6
47
700
12
13.5
15
18
110
open
open
open
open
900
124
1000
1100
1200
75
140
65
169
55
(1) For output voltages ≥2.5 V, the minimum required output capactiance must be comprised of ceramic type and account for DC bias
and temperature derating.
(2) The maximum output capactiance must include the required ceramic COUT(min). Additional capacitance, may be ceramic type, low-ESR
polymer type, or a combination of the two.
(3) RFBB = 10.0 kΩ
表7-2. Required Component Values (VOUT < 2.5 V)
RFBT (kΩ)(1)
RRT (kΩ)
VOUT (V)
CFF (pF)
FSW (kHz)
COUT
150-µF ceramic +
470-µF polymer
1 to 2.5
open
250
162
See 方程式1
(1) RFBB = 10 kΩ. For VOUT = 1 V, RFBB= open and RFBT = 0 Ω.
7.3.2 Feedforward Capacitor, CFF
The LMZM33602 is internally compensated to be stable over the operating frequency and output voltage range.
However, depending on the output voltage, an additional feedforward capacitor can be required. TI recommends
an external feedforward capacitor, CFF, be placed in parallel with the top resistor divider, RFBT for optimum
transient performance. The value for CFF can be calculated using Equation 2.
1000
CFF
=
pF
(
)
≈
∆
«
’
÷
8.32
4p
ìR
FBT
VOUT ìCOUT ◊
(2)
where
• COUT is the value after derating in µF
• RFBT is in kΩ
Refer to 表7-1 for the recommended CFF value for several output voltages.
7.3.3 Voltage Dropout
Voltage dropout is the difference between the input voltage and output voltage that is required to maintain output
voltage regulation while providing the rated output current.
To ensure the LMZM33602 maintains output voltage regulation at the recommended switching frequency, over
the operating temperature range, the following requirements apply:
For output voltages ≤5 V, the minimum VIN is 4 V or (VOUT + 1.5 V), whichever is greater.
For output voltages > 5 V, the minimum VIN is (1.3 × VOUT).
However, if fixed switching frequency operation is not required, the LMZM33602 operates in a frequency
foldback mode when the dropout voltage is less than the recommendations above. Frequency foldback reduces
the switching frequency to allow the output voltage to maintain regulation as input voltage decreases. 图 7-2
through 图7-7 show typical dropout voltage and frequency foldback curves for 3.3-V, 5-V, and 12-V outputs at TA
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= 25°C. (Note: As ambient temperature increases, dropout voltage and frequency foldback occur at higher input
voltage.)
3.4
3.3
3.2
3.1
3.0
2.9
2.8
2.7
2.6
2.5
350
325
300
275
250
225
200
175
150
125
100
75
Iout
0.5 A
1.0 A
2.0 A
Iout
0.5 A
1.0 A
2.0 A
50
3.3
3.4
3.5
3.6
3.7 3.8
Input Voltage (V)
3.9
4.0
4.1
4.2
3.3
3.4
3.5
3.6
3.7
3.8
Input Voltage (V)
3.9
4.0
4.1
4.2
4.3
4.4
4.5
D017
D018
VOUT = 3.3 V
fSW = 300 kHz
VOUT = 3.3 V
fSW = 300 kHz
图7-2. Voltage Dropout
图7-3. Frequency Foldback
5.4
5.2
5.0
4.8
4.6
4.4
4.2
4.0
3.8
3.6
3.4
3.2
3.0
500
450
400
350
300
250
200
150
100
Iout
0.5 A
1.0 A
2.0 A
Iout
0.5 A
1.0 A
2.0 A
4.0
4.2
4.4
4.6
4.8
5.0
Input Voltage (V)
5.2
5.4
5.6
5.8
6.0
6.2
6.4
4.0
4.3
4.6
4.9
5.2
5.5
Input Voltage (V)
5.8
6.1
6.4
6.7
7.0
D019
D020
VOUT = 5 V
fSW = 450 kHz
VOUT = 5 V
fSW = 450 kHz
图7-4. Voltage Dropout
图7-5. Frequency Foldback
12.4
12.2
12.0
11.8
11.6
11.4
11.2
11.0
10.8
10.6
10.4
10.2
10.0
9.8
1000
900
800
700
600
500
400
300
200
100
0
Iout
0.5 A
1.0 A
2.0 A
Iout
0.5 A
1.0 A
2.0 A
11.0 11.2 11.4 11.6 11.8 12.0 12.2 12.4 12.6 12.8 13.0 13.2 13.4
Input Voltage (V)
11.0
11.5
12.0
12.5
13.0
13.5
Input Voltage (V)
14.0
14.5
15.0
15.5
16.0
D021
D022
VOUT = 12 V
fSW = 900 kHz
VOUT = 12 V
fSW = 900 kHz
图7-6. Voltage Dropout
图7-7. Frequency Foldback
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7.3.4 Switching Frequency (RT)
The switching frequency range of the LMZM33602 is 200 kHz to 1.2 MHz. The switching frequency can easily be
set by connecting a resistor (RRT) between the RT pin and AGND. Additionally, the RT pin can be left floating
and the LMZM33602 will operate at 400 kHz default switching frequency. Use Equation 3 to calculate the RRT
value for a desired frequency or simply select from 表7-3.
The switching frequency must be selected based on the output voltage setting of the device and the operating
input voltage. See 表 7-3 for RRT resistor values and the allowable output voltage range for a given switching
frequency for three common input voltages.
≈
’
40200
RRT
=
- 0.6 kW
(
)
∆
∆
÷
÷
fSW kHz
(
)
«
◊
(3)
表7-3. Switching Frequency vs Output Voltage
VIN = 5 V (±5%)
VIN = 12 V (±5%)
VIN = 24 V (±5%)
VOUT RANGE (V)
RRT
RESISTOR
(kΩ)
SWITCHING
FREQUENCY
(kHz)
VOUT RANGE (V)
VOUT RANGE (V)
MIN
1
MAX
3.4
MIN
1
MAX
5.5
MIN
1
MAX
6.2
200
250
300
350
200
158
133
113
1
3.5
1
6.2
1
10.6
10.6
10.7
1
3.5
1
6.8
1
1
3.5
1
7.4
1
100 or
(RT pin
open)
400
1
3.5
1
7.9
1
11.4
450
500
88.7
78.7
71.5
66.5
60.4
56.2
52.3
49.9
46.4
44.2
41.2
39.2
37.4
35.7
34.0
33.2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
3.5
3.5
3.4
3.4
3.4
3.3
3.3
3.3
3.2
3.2
3.2
3.1
3.1
3.1
3
1
1
8.4
8.9
9.3
9.5
9.4
9.3
9.2
9.1
9.0
9.0
8.9
8.8
8.7
8.6
8.5
8.5
1.2
1.3
1.4
1.6
1.7
1.8
2.0
2.1
2.2
2.3
2.5
2.6
2.7
2.9
3
12.1
12.8
13.4
14.1
14.6
15.2
15.8
16.3
16.8
17.3
17.8
18
550
1
600
1
650
1
700
1
750
1
800
1
850
1.1
1.2
1.2
1.3
1.4
1.4
1.5
1.6
900
950
1000
1050
1100
1150
1200
18
18
18
3
3.1
18
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7.3.5 Synchronization (SYNC)
The LMZM33602 switching frequency can also be synchronized to an external clock from 200 kHz to 1.2 MHz.
To implement the synchronization feature, couple an AC signal to the EN/SYNC pin (pin 2) with a peak-to-peak
amplitude of at least 2.8 V, not to exceed 5.5 V. The minimum SYNC clock ON and OFF time must be longer
than 100ns. The AC signal must be coupled through a small capacitor (1 nF) as shown in 图 7-8. RENT is
required for this synchronization circuit, but RENB is not required if an external UVLO adjustment is not needed.
Before the external clock is present, or when a valid clock signal is removed, the device works in RT mode and
the switching frequency is set by RRT resistor. Select RRT so that it sets the frequency close to the external
synchronization frequency. When the external clock is present, the SYNC mode overrides the RT mode.
The synchronization frequency must be selected based on the output voltages of the devices being
synchronized. 表7-3 shows the allowable frequencies for a given range of output voltages. For the most efficient
solution, always select the lowest allowable frequency.
VIN
VIN
RENT
CSYNC
EN/SYNC
1 nF
RENB
Clock
Source
PGND
图7-8. AC Coupled SYNC Signal
7.3.6 Input Capacitors
The LMZM33602 requires a minimum input capacitance of 9.4 μF (2 × 4.7 μF) of ceramic type. High-quality,
ceramic-type X5R or X7R capacitors with sufficient voltage rating are recommended. TI recommends an
additional 100 µF of non-ceramic capacitance for applications with transient load requirements. The voltage
rating of input capacitors must be greater than the maximum input voltage.
表7-4. Recommended Input Capacitors
CAPACITOR CHARACTERISTICS
ESR(1)
(mΩ)
CAPACITANCE (2)
(µF)
VENDOR
SERIES
PART NUMBER
WORKING VOLTAGE
(V)
Murata
X7R
X5R
X7R
X7R
ZA
GRM32ER71H475KA88L
C3225X5R1H106K250AB
GRM32ER71H106KA12
C3225X7R1H106M250AB
EEHZA1H101P
50
50
50
50
50
4.7
10
2
3
TDK
Murata
TDK
10
2
10
3
Panasonic
100
28
(1) Maximum ESR @ 100 kHz, 25°C.
(2) Standard capacitance values
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7.3.7 Output Capacitors
The LMZM33602 minimum and maximum output capacitance listed in 表 7-1 and 表 7-2 represents the amount
of effective capacitance. The effects of DC bias and temperature variation must be considered when using
ceramic capacitance. For ceramic capacitors, the package size, voltage rating, and dielectric material will
contribute to differences between the standard rated value and the actual effective value of the capacitance.
When adding additional capacitance, above COUT(min), the capacitance can be ceramic type, low-ESR polymer
type, or a combination of the two. See 表7-5 for a preferred list of output capacitors by vendor.
表7-5. Recommended Output Capacitors
CAPACITOR CHARACTERISTICS
CAPACITANCE (3)
(µF)
VENDOR
SERIES
PART NUMBER(1)
WORKING
ESR(2) (mΩ)
VOLTAGE (V)
Murata
X7R
X5R
GRM32ER71E226KE15L
25
6.3
16
22
2
2
TDK
C3225X5R0J476K
GRM32ER61C476K
C3225X5R0J107M
GRM32ER60J107M
GRM32ER61A107M
C1210C107M4PAC7800
6TPE100MI
47
Murata
X5R
47
3
TDK
X5R
6.3
6.3
10
100
100
100
100
100
150
150
220
220
330
330
470
2
Murata
X5R
2
Murata
X5R
2
Kemet
X5R
16
2
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
POSCAP
POSCAP
POSCAP
POSCAP
POSCAP
POSCAP
POSCAP
POSCAP
6.3
6.3
10
18
15
15
9
6TPE150MF
10TPF150ML
6TPF220M9L
6.3
6.3
4
6TPE220ML
12
12
9
4TPF330ML
6TPF330M9L
6.3
6.3
6TPE470MAZU
35
(1) Capacitor Supplier Verification , RoHS, Lead-free and Material Details Consult capacitor suppliers regarding availability, material
composition, RoHS and lead-free status, and manufacturing process requirements for any capacitors identified in this table.
(2) Maximum ESR @ 100 kHz, 25°C.
(3) Standard capacitance values.
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7.3.8 Output On/Off Enable (EN)
The voltage on the EN/SYNC pin provides electrical ON/OFF control of the device. Once the EN pin voltage
exceeds the threshold voltage, the device starts operation. If the EN pin voltage is pulled below the threshold
voltage, the regulator stops switching and enters low quiescent current state.
The EN pin cannot be open circuit or floating. The simplest way to enable the operation of the LMZM33602 is to
connect the EN pin to VIN directly as shown in 图 7-9. This allows self-start-up of the LMZM33602 when VIN is
within the operation range.
If an application requires controlling the EN pin, an external logic signal can be used to drive EN/SYNC pin as
shown in 图 7-10. Applications using an open drain/collector device to interface with this pin require a pullup
resistor to a voltage above the enable threshold.
图7-11 and 图7-12 show typical turn-ON and turn-OFF waveforms using the enable control.
VIN
VIN
EN/SYNC
EN/SYNC
PGND
PGND
图7-10. Typical Enable Control
图7-9. Enabling the Device
图7-12. Enable Turn-OFF
图7-11. Enable Turn-ON
7.3.9 Programmable Undervoltage Lockout (UVLO)
The LMZM33602 implements internal UVLO circuitry on the VIN pin. The device is disabled when the VIN pin
voltage falls below the internal VIN UVLO threshold. The internal VIN UVLO rising threshold is 3.9 V (maximum)
with a typical hysteresis of 300 mV.
If an application requires a higher UVLO threshold, a resistor divider can be placed on the EN/SYNC pin as
shown in 图7-13. 表7-6 lists recommended resistor values for RENT and RENB to adjust the ULVO voltage.
To ensure proper start-up and reduce input current surges, the UVLO threshold must be set to at least
(VOUT + 1.5 V) for output voltages ≤ 5 V and at least (1.3 × VOUT) for output voltages > 5 V. TI recommends to
set the UVLO threshold to approximately 80% to 85% of the minimum expected input voltage.
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VIN
VIN
RENT
EN/SYNC
PGND
RENB
图7-13. Adjustable UVLO
表7-6. Resistor Values for Adjusting UVLO
VIN UVLO (V)
RENT (kΩ)
6.5
100
35.7
10
15
20
25
30
100
20.5
100
12.7
100
9.31
100
7.32
100
6.04
RENB (kΩ)
7.3.10 Power Good (PGOOD)
The LMZM33602 has a built-in power-good signal (PGOOD) which indicates whether the output voltage is within
its regulation range. The PGOOD pin is an open-drain output that requires a pullup resistor to a nominal voltage
source of 12 V or less. The maximum recommended PGOOD sink current is 1 mA. A typical pullup resistor value
is between 10 kΩand 100 kΩ.
Once the output voltage rises above 94% of the set voltage, the PGOOD pin rises to the pullup voltage level.
The PGOOD pin is pulled low when the output voltage drops lower than 92.5% or rises higher than 107% of the
nominal set voltage. See 图7-14 for typical power-good thresholds.
VFB
107%
105.5%
94%
92.5%
PGOOD
High
Low
图7-14. Power Good Flag
7.3.11 Overcurrent Protection (OCP)
The LMZM33602 is protected from overcurrent conditions. Hiccup mode is activated if a fault condition persists
to prevent overheating. In hiccup mode, the regulator is shut down and kept off for 10 ms typical before the
LMZM33602 tries to start again. If overcurrent or short-circuit fault condition still exist, hiccup repeats until the
fault condition is removed. Hiccup mode reduces power dissipation under severe overcurrent conditions, and
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prevents overheating and potential damage to the device. Once the fault is removed, the module automatically
recovers and returns to normal operation as shown in 图7-16.
图7-15. Overcurrent Limiting
7.3.12 Thermal Shutdown
图7-16. Removal of Overcurrent
The internal thermal shutdown circuitry forces the device to stop switching if the junction temperature exceeds
170°C typically. The device reinitiates the power up sequence when the junction temperature drops below 155°C
typically.
7.4 Device Functional Modes
7.4.1 Active Mode
The LMZM33602 is in active mode when VIN is above the UVLO threshold and the EN/SYNC pin voltage is
above the EN high threshold. The simplest way to enable the LMZM33602 is to connect the EN/SYNC pin to
VIN. This allows self start-up of the LMZM33602 when the input voltage is in the operation range: 4 V to 36 V. In
active mode, the LMZM33602 is in continuous conduction mode (CCM) with fixed switching frequency.
7.4.2 Shutdown Mode
The EN/SYNC pin provides electrical ON and OFF control for the LMZM33602. When the EN/SYNC pin voltage
is below the EN low threshold, the device is in shutdown mode. In shutdown mode the standby current is 2 μA
typical. The LMZM33602 also employs input UVLO protection. If VIN is below the UVLO level, the output of the
regulator is turned off.
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8 Application and Implementation
Note
以下应用部分的信息不属于TI 组件规范，TI 不担保其准确性和完整性。客户应负责确定 TI 组件是否适
用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
The LMZM33602 is a synchronous, step-down, DC-DC power module. It is used to convert a higher DC voltage
to a lower DC voltage with a maximum output current of 2 A. The LMZM33602 can be configured in an inverting
buck-boost (IBB) topology with the output voltage inverted or negative with respect to ground. For more details,
see TI Application Report Inverting Application for the LMZM33602/03. The following design procedure can be
used to select components for the LMZM33602. Alternately, the WEBENCH® software may be used to generate
complete designs. When generating a design, the WEBENCH® software utilizes an iterative design procedure
and accesses comprehensive databases of components. See www.ti.com for more details.
8.2 Typical Application
The LMZM33602 only requires a few external components to convert from a wide input voltage supply range to a
wide range of output voltages. 图 8-1 shows a basic LMZM33602 schematic with only the minimum required
components.
PGOOD
VIN
VIN
VOUT
EN/SYNC
VOUT
CIN
CFF
LMZM33602
RFBT
COUT
RT
FB
PGND
RRT
RFBB
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图8-1. LMZM33602 Typical Schematic
8.2.1 Design Requirements
For this design example, use the parameters listed in 表 8-1 as the input parameters and follow the design
procedures in 节8.2.2.
表8-1. Design Example Parameters
DESIGN PARAMETER
VALUE
24 V typical
5 V
Input voltage VIN
Output voltage VOUT
Output current rating
Operating frequency
2 A
450 kHz
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8.2.2 Detailed Design Procedure
8.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LMZM33602 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.2.2 Output Voltage Setpoint
The output voltage of the LMZM33602 device is externally adjustable using a resistor divider. The recommended
value of RFBB is 10.0 kΩ. The value for RFBT can be selected from 表7-6 or calculated using Equation 4:
RFBT = 10ì V
-1 kW
OUT
(4)
For the desired output voltage of 5.0 V, the formula yields a value of 40 kΩ. Choose the closest available value
of 40.2 kΩfor RFBT
.
8.2.2.3 Feedforward Capacitor (CFF)
TI recommends placing an external feedforward capacitor, CFF in parallel with the top resistor divider, RFBT for
optimum transient performance. The value for CFF can be calculated using Equation 2 or selected from 表 7-1.
The recommended CFF value for 5-V application is 100 pF.
8.2.2.4 Setting the Switching Frequency
The recommended switching frequency for a 5-V application is 450 kHz. To set the swtiching frequency to
450 kHz, a 88.7-kΩRRT resistor is required.
8.2.2.5 Input Capacitors
The LMZM33602 requires a minimum input capacitance of 10 µF (or 2 × 4.7 μF) ceramic type. High-quality
ceramic type X5R or X7R capacitors with sufficient voltage rating are recommended. An additional 100 µF of
non-ceramic capacitance is recommended for applications with transient load requirements. The voltage rating
of input capacitors must be greater than the maximum input voltage.
For this design, a 10-µF, 50-V, ceramic capacitor was selected.
8.2.2.6 Output Capacitor Selection
The LMZM33602 requires a minimum amount of output capacitance for proper operation. The minimum amount
of required output varies depending on the output voltage. See 表7-1 for the required output capacitance.
For this design example, four 22-µF, 25-V ceramic capacitors are used.
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8.2.2.7 Application Curves
VIN = 24 V
VOUT = 5 V
IOUT = 0.5 A to 1 A
Slew rate: 1 A/µs
VIN = 24 V
VOUT = 5 V
COUT = 4 × 22 µF
COUT = 4 × 22 µF
图8-3. Enable Turn-on
图8-2. Transient Response
Power Supply Recommendations
The LMZM33602 is designed to operate from an input voltage supply range between 4 V and 36 V. This input
supply must be well regulated and able to withstand maximum input current and maintain a stable voltage. The
resistance of the input supply rail must be low enough that an input current transient does not cause a high
enough drop at the LMZM33602 supply voltage that can cause a false UVLO fault triggering and system reset.
If the input supply is located more than a few inches from the LMZM33602 additional bulk capacitance may be
required in addition to the ceramic bypass capacitors. The typical amount of bulk capacitance is a 100-µF
electrolytic capacitor.
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Layout
The performance of any switching power supply depends as much upon the layout of the PCB as the component
selection. The following guidelines will help users design a PCB with the best power conversion performance,
optimal thermal performance, and minimized generation of unwanted EMI.
9.1 Layout Guidelines
To achieve optimal electrical and thermal performance, an optimized PCB layout is required. 图 9-1 through 图
9-4 show a typical PCB layout. Some considerations for an optimized layout are:
• Use large copper areas for power planes (VIN, VOUT, and PGND) to minimize conduction loss and thermal
stress.
• Connect PGND pins 14 and 15 directly to pin 18 using thick copper traces.
• Connect the SW pins together using a small copper island under the device for thermal relief.
• Place ceramic input and output capacitors close to the device pins to minimize high frequency noise.
• Locate additional output capacitors between the ceramic capacitor and the load.
• Keep AGND and PGND separate from one another.
• Place RFBT, RFBB, RRT, and CFF as close as possible to their respective pins.
• Use multiple vias to connect the power planes to internal layers.
9.2 Layout Examples
图9-1. Typical Top-Layer Layout
图9-2. Typical Layer-2 Layout
图9-3. Typical Layer 3 Layout
图9-4. Typical Bottom-Layer Layout
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9.3 Theta JA versus PCB Area
The amount of PCB copper effects the thermal performance of the device. 图 9-5 shows the effects of copper
area on the junction-to-ambient thermal resistance (RθJA) of the LMZM33602. The junction-to-ambient thermal
resistance is plotted for a 2-layer PCB and a 4-layer PCB with PCB area from 16 cm2 to 49 cm2.
To determine the required copper area for an application:
1. Determine the maximum power dissipation of the device in the application by referencing the power
dissipation graphs in 节6.7 to 节6.9.
2. Calculate the maximum θJA using Equation 5 and the maximum ambient temperature of the application.
(125˘C œ TA(max)
)
ꢀJA
=
(˘C/W)
PD(max)
(5)
3. Reference 图9-5 to determine the minimum required PCB area for the application conditions.
32
2-layer PCB
4-layer PCB
30
28
26
24
22
20
18
16
15
20
25
30
35
40
45
50
PCB Area (cm²)
ThJA
图9-5. θJA vs PCB Area
9.4 EMI
The LMZM33602 is compliant with EN55011 Class B radiated emissions. 图 9-6, 图 9-7, and 图 9-8 show typical
examples of radiated emissions plots for the LMZM33602. The graphs include the plots of the antenna in the
horizontal and vertical positions.
9.4.1 EMI Plots
EMI plots were measured using the standard LMZM33602EVM with no input filter.
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图9-6. Radiated Emissions 24-V Input, 5-V Output, 2-A Load (EN55011 Class B)
图9-7. Radiated Emissions 24-V Input, 12-V Output, 2-A Load (EN55011 Class B)
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图9-8. Radiated Emissions 12-V Input, 5-V Output, 2-A Load (EN55011 Class B)
9.5 Package Specifications
LMZM33602
VALUE
UNIT
Weight
0.74
grams
Flammability
Meets UL 94 V-O
MTBF Calculated Reliability
Per Bellcore TR-332, 50% stress, TA = 40°C, ground benign
98.0
MHrs
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9 Device and Documentation Support
9.1 Device Support
9.1.1 Development Support
9.1.1.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LMZM33602 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
9.2 Documentation Support
9.2.1 Related Documentation
For related documentation see the following:
TI Application Report Inverting Application for the LMZM33602/03
9.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
9.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
9.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
WEBENCH® is a registered trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
9.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
9.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
10.1 Tape and Reel Information
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
Reel
Diameter
(mm)
Reel
Width W1
(mm)
Package
Type
Package
Drawing
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
Device
Pins
SPQ
LMZM33602RLRR
B3QFN
RLR
18
500
330.0
24.4
7.35
9.35
4.35
12.0
24.0
Q1
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TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
Device
Package Type
B3QFN
Package Drawing Pins
RLR 18
SPQ
Length (mm) Width (mm)
383.0 353.0
Height (mm)
LMZM33602RLRR
500
58.0
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMZM33602RLRR
ACTIVE
B3QFN
RLR
18
500
RoHS & Green
NIPDAU
Level-3-250C-168 HR
-40 to 105
LMZM33602
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
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16-Oct-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMZM33602RLRR
B3QFN
RLR
18
500
330.0
24.4
7.35
9.35
4.35
12.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
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*All dimensions are nominal
Device
Package Type Package Drawing Pins
B3QFN RLR 18
SPQ
Length (mm) Width (mm) Height (mm)
383.0 353.0 58.0
LMZM33602RLRR
500
Pack Materials-Page 2
PACKAGE OUTLINE
RLR0018A
B3QFN - 4.1 mm max height
S
C
A
L
E
1
.
3
0
0
PLASTIC QUAD FLATPACK - NO LEAD
A
7.15
6.85
B
PIN 1 INDEX AREA
9.15
8.85
4.1 MAX
C
SEATING PLANE
0.05
0.00
0.08 C
2X 5.551
2X
(0.2) TYP
(0.255) TYP
36X 0.5
EXPOSED
THERMAL PAD
PKG
8
10
7
6
11
2X 3.48 0.05
2X 0.77 0.05
2X
PKG
7.5
5
12
15
2X 1.6
0.05
0.3
46X
0.2
0.1
C A B
0.05
1
18
0.6
PIN 1 ID
(OPTIONAL)
TYP
0.4
2X 1.33
2X 0.105
2X 1
4223378/C 05/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pads must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RLR0018A
B3QFN - 4.1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
METAL UNDER
SOLDER MASK
TYP
2X (1.6)
PKG
(0.5) TYP
4X (0.595)
12X (0.7)
6X
(0.45)
SOLDER MASK
OPENING
TYP
18
(4.35)
(4.33) TYP
4X (0.62)
15
(3.8)
1
(3.42) TYP
2X (3.48)
(
0.2) VIA
46X (0.25)
TYP
(2.51) TYP
(1.6) TYP
12
0.05 MIN
TYP
(0.69) TYP
5
PKG
0.000
(0.175) TYP
(0.825) TYP
(0.15) TYP
11
(1.6) TYP
(R0.05) TYP
6
(2.51) TYP
(3.42) TYP
7X (0.25)
(3.8)
4X (3.935)
(4.33) TYP
10
7
(4.35)
8
LAND PATTERN EXAMPLE
SOLDER MASK DEFINED
SCALE: 12X
4223378/C 05/2018
NOTES: (continued)
4. This package designed to be soldered to a thermal pads on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RLR0018A
B3QFN - 4.1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
16X (0.67)
16X (0.71)
6X (0.29)
8X (0.265)
5X (0.7)
18
(4.568)
(4.35)
(3.875)
15
1
2X (3.75)
(2.965)
(2.055)
46X (0.25)
EXPOSED METAL
TYP
12
(1.145)
5
(R0.05) TYP
0.000 PKG
(1.145)
(2.055)
11
(0.25) TYP
6
7
4X (0.585)
(2.965)
METAL UNDER
SOLDER MASK
TYP
2X (3.75)
(3.875)
4X (3.93)
10
(4.35)
SOLDER MASK EDGE
TYP
2X (4.568)
8
4X (0.61)
7X (0.7)
EXPOSED
METAL
TYP
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD 8 & 18:
68% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:12X
4223378/C 05/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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