LP2980-ADJ [TI]
具有使能功能的 50mA、16V、可调节低压降稳压器;
| 型号： | LP2980-ADJ |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有使能功能的 50mA、16V、可调节低压降稳压器 稳压器 |
| 文件： | 总37页 (文件大小：2714K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LP2980-ADJ
ZHCSSD8F –APRIL 2000 –REVISED JULY 2023
LP2980-ADJ 16V、50mA、低功耗、可调节低压降稳压器
1 特性
3 说明
• VIN 范围：
LP2980-ADJ 是一款可调输出、宽输入、低压降稳压
器，支持高达 16V 的输入电压和高达 50mA 的负载电
流。LP2980-ADJ 支持 1.2V 至 15.0V（新芯片）和
1.23V 至15.0V（旧芯片）的输出范围。
– 旧芯片：2.2V 至16V
– 新芯片：2.5V 至16V
• VOUT 范围：
– 旧芯片：1.23V 至15.0V
– 新芯片：1.2V 至15.0V
• VOUT 精度（典型值）：
此外，LP2980-ADJ（新芯片）在整个负载和温度范围
内具有 1% 的输出精度，可满足低压微控制器 (MCU)
和处理器的需求。
– 旧芯片：±1%
– 新芯片：±0.5%
• 在整个负载和温度范围内的输出精度：
在该新芯片中，高带宽 PSRR 性能在 1kHz 时大于
70dB，在 1MHz 时大于 45dB，因此有助于衰减上游
直流/直流转换器的开关频率，并尽可能地减少后置稳
压器滤波。
– 旧芯片：±3.5%
– 新芯片：±1%
内部软启动时间和电流限制保护可减小启动期间的浪涌
电流，从而尽可能降低输入电容。还包括标准保护特
性，例如过流和过热保护。
• 输出电流：高达50mA
• 静态电流，低IQ（新芯片）：
– ILOAD = 0 mA 时为55μA
– ILOAD = 50 mA 时为350μA
• 关断电流与温度间的关系：
LP2980-ADJ 采用 5 引脚、2.9mm × 1.6mm SOT-23
(DBV) 封装。
– 旧芯片：< 1μA
– 新芯片：≤0.8μA
• 输出电流限制和热保护
• 使用2.2µF 陶瓷电容器实现稳定工作（新芯片）
• 高PSRR（新芯片）：
– 1kHz 频率下为70dB，1MHz 频率下为42dB
• 工作结温：–40°C 至+125°C
封装信息
封装(1)
封装尺寸(2)
器件型号
LP2980-ADJ
DBV（SOT-23，5)
2.9mm × 2.8mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
(2) 封装尺寸（长x 宽）为标称值，并包括引脚（如适用）。
• 封装：5 引脚SOT-23 (DBV)
2 应用
• 家用断路器
• 固态硬盘(SSD)
• 电表
• 电器
• 楼宇自动化
250
VOUT
VIN
1mA
10mA
50mA
IN
OUT
ADJ
200
150
100
50
LP2980-ADJ
R1
R2
CFF
ON/
OFF
COUT
CIN
GND
GND
GND
GND
0
-75 -50 -25
0
25 50 75 100 125 150
GND
Temperature (°C)
典型应用电路
新芯片的压降电压与温度间的关系
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNVS001
LP2980-ADJ
ZHCSSD8F –APRIL 2000 –REVISED JULY 2023
www.ti.com.cn
Table of Contents
7.4 Device Functional Modes..........................................19
8 Application and Implementation..................................21
8.1 Application Information............................................. 21
8.2 Typical Application.................................................... 25
8.3 Power Supply Recommendations.............................28
8.4 Layout....................................................................... 28
9 Device and Documentation Support............................29
9.1 Device Support......................................................... 29
9.2 接收文档更新通知..................................................... 29
9.3 支持资源....................................................................29
9.4 Trademarks...............................................................29
9.5 静电放电警告............................................................ 29
9.6 术语表....................................................................... 29
10 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................6
6.6 Typical Characteristics................................................9
7 Detailed Description......................................................17
7.1 Overview...................................................................17
7.2 Functional Block Diagram.........................................17
7.3 Feature Description...................................................17
Information.................................................................... 29
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision E (April 2013) to Revision F (July 2023)
Page
• 添加了ESD 等级表、概述部分、特性说明部分、器件功能模式部分、应用和实施部分、典型应用部分、电
源建议部分、布局部分、器件和文档支持 部分，以及机械、封装和可订购信息 部分......................................1
• 在文档中添加了新芯片（M3 后缀）信息............................................................................................................1
• 更改了文档标题以及特性、应用 和说明 部分.....................................................................................................1
• 删除了应用提示 部分..........................................................................................................................................1
• Changed Pin Configuration and Functions title and section...............................................................................3
• Changed title, condition statement, and curve titles and added curves for new chip in Typical Characteristics
section................................................................................................................................................................ 9
• Changed Functional Block Diagram figure....................................................................................................... 17
• Added Device Nomenclature section................................................................................................................29
Changes from Revision D (April 2013) to Revision E (April 2013)
Page
• Changed layout of National Data Sheet to TI format........................................................................................26
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SNVS001
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5 Pin Configuration and Functions
5
VOUT
VIN
1
2
3
GND
ON/OFF
ADJ
4
图5-1. DBV Package, 5-Pin SOT-23 (Top View)
表5-1. Pin Functions
PIN
TYPE
DESCRIPTION
NAME
ADJ
NO.
4
Feedback pin to set the output voltage with help of the feedback divider. See the
Recommended Operating Conditions section for more information.
I/O
GND
2
Ground
—
Enable pin for the LDO. Driving the ON/OFF pin high enables the device. Driving this pin low
disables the device. High and low thresholds are listed in the Electrical Characteristics table.
Tie this pin to VIN if unused.
ON/OFF
VIN
3
1
5
I
I
Input supply pin. Use a capacitor with a value of 1 µF or larger from this pin to ground. See
the Input and Output Capacitor Requirements section for more information.
Output of the regulator. Use a capacitor with a value of 4.7 µF (for legacy chip) and 2.2 μF
(for new chip) or larger from this pin to ground.(1) See the Input and Output Capacitor
Requirements section for more information.
VOUT
O
(1) The nominal output capacitance must be greater than 1 μF (for the new chip) and 2.2 μF (for the legacy chip). Throughout this
document, the nominal derating on these capacitors is 50%. Make sure that the effective capacitance at the pin is greater than 1 μF
(for the new chip) and 2.2 μF (for the legacy chip).
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English Data Sheet: SNVS001
LP2980-ADJ
ZHCSSD8F –APRIL 2000 –REVISED JULY 2023
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN
–0.3
–0.3
–0.3
MAX
UNIT
Continuous input voltage range (for legacy chip)
16
18
16
VIN
Continuous input voltage range (for new chip)
Output voltage range (for legacy chip)
VOUT
VIN + 0.3 or 18 (whichever
is smaller)
Output voltage range (for new chip)
–0.3
V
VADJ
ADJ pin voltage range (for new chip)
Input –Output voltage (for legacy chip)
ON/OFF pin voltage range (for legacy chip)
ON/OFF pin voltage range (for new chip)
Maximum output
3
16
16
18
–0.3
–0.3
–0.3
–0.3
(3)
VIN –VOUT
VON/OFF
Current
Internally limited
–55
A
Operating junction, TJ
150
150
Temperature
°C
Storage, Tstg
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) All voltages with respect to GND.
(3) In legacy chip, the output PNP structure contains a diode between the VIN and VOUT terminals that is normally reverse-biased.
Reversing the polarity from VIN to VOUT will turn on this diode
6.2 ESD Ratings
VALUE
(Legacy
Chip)
VALUE
(New
Chip)
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
NA
±3000
±1000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 2-kV HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 500-V CDM allows safe manufacturing with a standard ESD control process.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SNVS001
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6.3 Recommended Operating Conditions
MIN
2.2
NOM
MAX
16
UNIT
Supply input voltage (for legacy chip)
VIN
Supply input voltage (for new chip)
2.5
16
Output voltage (for legacy chip)
1.225
1.2
15.0
15.0
VOUT
Output voltage (for new chip)
V
ADJ voltage (for legacy chip)
1.225
1.2
VADJ
ADJ voltage (for new chip)
Enable voltage (for legacy chip)
VON/OFF
0
0
0
VIN
16
50
Enable voltage (for new chip)
IOUT
Output current
mA
(3)
CIN
Input capacitor
1
4.7
2.2
7
Output capacitor (for legacy chip) (2)
Output capacitance (for new chip) (1)
Feed-forward capacitor (for legacy chip)
Feed-forward capacitor (for new chip)
Operating junction temperature
2.2
1
μF
COUT
200
125
(4)
CFF
TJ
pF
°C
10
–40
(1) For new chip, all capacitor values are assumed to derate to 50% of the nominal capacitor value. Maintain an effective output
capacitance of 1 μF minimum for stability.
(2) For legacy chip, minimum output capacitance of 2.2 μF is required with ESR range suggested in the Recommended Capacitor Types
section
(3) For legacy chip, an input capacitor of value ≥1 μF is required. It must be located not more than 0.5″from the input pin and returned
to a clean analog ground.
(4) Regarding the requirement of feed-forward capacitor (CFF), see the Feed-Forward Capacitor section.
6.4 Thermal Information
Legacy Chip
DBV (SOT23-5)
5 PINS
205.4
New Chip
DBV (SOT23-5)
5 PINS
178.6
THERMAL METRIC (2) (1)
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
78.8
77.9
46.7
47.2
Junction-to-top characterization parameter
Junction-to-board characterization parameter
8.3
15.9
46.3
46.9
ψJB
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
note.
(2) Thermal performance results are based on the JEDEC standard of 2s2p PCB configuration. These thermal metric parameters can be
further improved by 35-55% based on thermally optimized PCB layout designs. See the analysis of the Impact of board layout on LDO
thermal performance application report.
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English Data Sheet: SNVS001
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ZHCSSD8F –APRIL 2000 –REVISED JULY 2023
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6.5 Electrical Characteristics
specified at TJ = 25°C, VIN = VOUT(nom) + 1.0 V or VIN = 2.5 V (whichever is greater), IOUT = 1 mA, VON/OFF = 2 V, CIN = 1.0
µF, and COUT = 2.2 µF (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
1.213 1.225 1.237
1.194 1.2 1.206
1.206 1.225 1.243
1.1928 1.2 1.206
1.182 1.225 1.268
1.1892 1.2 1.2108
TYP
MAX UNIT
Legacy Chip
New Chip
IL = 1mA
Legacy Chip
New Chip
1 mA < IL < 50 mA, VOUT + 1 ≤VIN ≤
16V, TJ = 25°C
VREF
Reference Voltage
V
Legacy Chip
New Chip
1 mA < IL < 50 mA, VOUT + 1 ≤VIN ≤
16V, –40°C ≤TJ ≤125°C
Legacy Chip
New Chip
3.0
6.0
4.0
15.0
4.25
3
2.5V ≤VIN ≤16V, TJ = 25°C
–0.5
ΔVREF/ Reference Voltage
Line Regulation
mV
ΔVIN
Legacy Chip
New Chip
2.5V ≤VIN ≤16V, –40°C ≤TJ ≤
125°C
Legacy Chip
New Chip
1
1
IL = 0mA
3.5
5
Legacy Chip
New Chip
IL = 0mA, –40°C ≤TJ ≤125°C
IL = 1mA
5.5
10
Legacy Chip
New Chip
7
10.5
15.5
15
Legacy Chip
New Chip
IL = 1mA, –40°C ≤TJ ≤125°C
IL = 10mA
18.5
60
VIN
-
Dropout voltage
mV
VOUT
Legacy Chip
New Chip
40
95
115
90
Legacy Chip
New Chip
IL = 10mA, –40°C ≤TJ ≤125°C
IL = 50mA
148
150
145
225
184
Legacy Chip
New Chip
120
120
Legacy Chip
New Chip
IL = 50mA, –40°C ≤TJ ≤125°C
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English Data Sheet: SNVS001
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6.5 Electrical Characteristics (continued)
specified at TJ = 25°C, VIN = VOUT(nom) + 1.0 V or VIN = 2.5 V (whichever is greater), IOUT = 1 mA, VON/OFF = 2 V, CIN = 1.0
µF, and COUT = 2.2 µF (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Legacy Chip
New Chip
60
95
70
IL = 0mA
55
Legacy Chip
New Chip
125
90
IL = 0mA, –40°C ≤TJ ≤125°C
IL = 1mA
Legacy Chip
New Chip
80
70
110
82
Legacy Chip
New Chip
170
105
220
IL = 1mA, –40°C ≤TJ ≤125°C
IL = 10mA
Legacy Chip
New Chip
120
150
188
µA
IGND
Ground Pin Current
Legacy Chip
New Chip
460
220
600
420
1200
600
1
IL = 10mA, –40°C ≤TJ ≤125°C
IL = 50mA
Legacy Chip
New Chip
320
350
Legacy Chip
New Chip
IL = 50mA, –40°C ≤TJ ≤125°C
Legacy Chip
New Chip
0.01
0.2
VON/OFF < 0.18V, VIN ≤4.3V, –40°C ≤
TJ ≤125°C
0.8
VON/OFF < 0.18V, VIN = 16V, –40°C ≤TJ
≤125°C
New Chip
2.5
Legacy Chip
New Chip
150
0.35
2.2
350
nA
30
IADJ
ADJ Pin Bias Current
1 mA ≤IL ≤50 mA
VUVLO+ Rising bias supply UVLO
2.4
VIN rising, –40°C ≤TJ ≤125°C
VIN falling, –40°C ≤TJ ≤125°C
VUVLO-
Falling bias supply UVLO
UVLO hysteresis
1.9
2.07
New Chip
V
VUVLO(HY
0.130
–40°C ≤TJ ≤125°C
ST)
High = O/P ON
Low = O/P OFF
High = O/P ON
Low = O/P OFF
VON/OFF = 0
1.6
1.6
1.4
0.55
0.82
0.7
Legacy Chip
New Chip
0.18
V
VON/OFF ON/OFF input voltage
0.18
0.01
5
–1
Legacy Chip
New Chip
VON/OFF = 5V
VON/OFF = 0
15
ION/OFF
ON/OFF input Current
Peak Output Current
µA
–0.35 –0.7
VON/OFF = 5V
0.008
150
150
150
160
160
160
220
0.5
Legacy Chip
New Chip
100
130
IO(PK)
V
OUT ≥VO(NOM) –5%
mA
µV
Legacy Chip
New Chip
IO(MAX) Short Circuit Current
RL = 0 (Steady State)
Legacy Chip
BW = 300 Hz to 50 kHz, COUT = 10µF
BW = 300 Hz to 50 kHz, COUT = 2.2µF
BW = 10 Hz to 100 kHz, COUT = 2.2µF
en
Output Noise Voltage (RMS)
New Chip
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6.5 Electrical Characteristics (continued)
specified at TJ = 25°C, VIN = VOUT(nom) + 1.0 V or VIN = 2.5 V (whichever is greater), IOUT = 1 mA, VON/OFF = 2 V, CIN = 1.0
µF, and COUT = 2.2 µF (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Legacy Chip
New Chip
f = 1 kHz, COUT = 10µF
68
ΔVOUT
ΔVIN
/
Ripple Rejection
f = 1 kHz, COUT = 2.2µF
68
dB
f = 100 kHz, COUT = 2.2µF
45
Tsd(shutdo
Shutdown, temperature increasing
Reset, temperature decreasing
170
150
wn)
Thermal shutdown threshold
New Chip
°C
Tsd(reset)
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6.6 Typical Characteristics
at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 1.0 V or 2.5 V (whichever is greater), IOUT = 1 mA, ON/OFF pin tied to
VIN, CIN = 1.0 µF, and COUT = 4.7 µF (unless otherwise noted)
3.315
3.31
VI = 4.3 V
VO = 3.3 V
Iout = 1mA
CO = 4.7uF
3.305
3.3
3.295
3.29
3.285
3.28
-75
-50
-25
0
25
50
75
100 125 150
Temp C
VIN = 4.3 V, VOUT = 3.3 V
图6-1. Output Voltage vs Temperature for Legacy Chip
图6-2. Output Voltage vs Temperature for New Chip
4
3.5
3
2.5
2
1.5
1
RLOAD
3.3 k
66
0.5
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
VIN ( V )
图6-3. Output Voltage vs VIN for Legacy Chip
图6-4. Output Voltage vs VIN for New Chip
160
220
200
180
160
140
120
100
80
TEMPERATURE
IOUT = 50 mA
IOUT
1 mA
-55 C
-40 C
0 C
25 C
85 C
125 C
150 C
140
120
100
80
50 mA
60
40
20
0
2
4
6
8
10
12
14
16
2
4
6
8
10
12
14
16
VIN ( V )
VIN ( V )
图6-5. Dropout Voltage vs VIN for New Chip
图6-6. Dropout Voltage vs VIN and Temperature for New Chip
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6.6 Typical Characteristics (continued)
at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 1.0 V or 2.5 V (whichever is greater), IOUT = 1 mA, ON/OFF pin tied to
VIN, CIN = 1.0 µF, and COUT = 4.7 µF (unless otherwise noted)
250
1mA
10mA
50mA
200
150
100
50
0
-75 -50 -25
0
25 50 75 100 125 150
Temperature (°C)
图6-7. Dropout Voltage vs Temperature for Legacy Chip
图6-8. Dropout Voltage vs Temperature for New Chip
200
VO = 3.3 V
CO = 4.7 F
175
150
125
100
75
50
Temperature
25 °C
-55 °C
-40 °C
0 °C
150 °C
45
25
85 °C
125 °C
0
0
5
10
15
20
25
30
35
40
50
IOUT (mA)
图6-9. Dropout Voltage vs Load Current for Legacy Chip
图6-10. Dropout Voltage vs Load Current for New Chip
0
-2
-4
-6
-8
-10
-12
VOUT
-14
-16
2.5 V
30
3.3 V
5 V
45
0
5
10
15
20
25
35
40
50
IOUT ( mA )
图6-11. Output Regulation vs Load Current for Legacy Chip
图6-12. Output Regulation vs Load Current for New Chip
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6.6 Typical Characteristics (continued)
at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 1.0 V or 2.5 V (whichever is greater), IOUT = 1 mA, ON/OFF pin tied to
VIN, CIN = 1.0 µF, and COUT = 4.7 µF (unless otherwise noted)
1.5
Temperature
VO = 3.3 V
-55C
-40C
0C
85C
1
0.5
0
Iout= 1mA
125C
150C
CO = 4.7uF
25C
-0.5
-1
-1.5
-2
4
6
8
10
VIN (V)
12
14
16
图6-13. Output Regulation vs Load Current and Temperature
图6-14. Output Regulation vs Input Voltage for New Chip
for New Chip
图6-15. Ground-Pin Current vs Temperature for Legacy Chip
图6-16. Ground-Pin Current vs Temperature for New Chip
700
Temperature
-55 °C
-40 °C
0 °C
25 °C
85 °C
125 °C
150 °C
600
500
400
300
200
100
0
VI = 4.3 V
VO = 3.3 V
CO = 4.7 F
0
10
20
30
40
50
IOUT
图6-17. Ground Pin Current vs Load Current for Legacy Chip
图6-18. Ground Pin Current vs Load Current for New Chip
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6.6 Typical Characteristics (continued)
at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 1.0 V or 2.5 V (whichever is greater), IOUT = 1 mA, ON/OFF pin tied to
VIN, CIN = 1.0 µF, and COUT = 4.7 µF (unless otherwise noted)
1000
Temperature
-55 °C
-40 °C
0 °C
25 °C
85 °C
125 °C
150 °C
800
600
400
200
0
VO = 3.3 V
CO = 4.7uF
-200
0
2
4
6
8
10
12
14
16
VIN
图6-19. Input Current vs Input Voltage for Legacy Chip
图6-20. Input Current vs Input Voltage for New Chip
5
4
3000
2700
2400
2100
1800
1500
1200
900
VO
I SC
VIN = 6 V
VO = 3.3 V
3
2
1
0
-1
-2
-3
-4
-5
-6
600
300
0
-300
0
200
400
600
800
1000
200s/div
VIN = 6 V
图6-22. Short-Circuit Current vs Time for New Chip
图6-21. Short-Circuit Current vs Time for Legacy Chip
5
3000
2700
2400
2100
1800
1500
1200
900
VIN = 16 V
VOUT = 3.3 V
VO
I SC
4
3
2
1
0
-1
-2
-3
-4
-5
-6
600
300
0
-300
0
200
400
600
800
1000
200s/div
图6-23. Short-Circuit Current vs Time for Legacy Chip
图6-24. Short-Circuit Current vs Time for New Chip
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6.6 Typical Characteristics (continued)
at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 1.0 V or 2.5 V (whichever is greater), IOUT = 1 mA, ON/OFF pin tied to
VIN, CIN = 1.0 µF, and COUT = 4.7 µF (unless otherwise noted)
320
166
V
O
= 3.3 V
VIN = 4.3 V
164
162
160
158
156
154
152
150
148
146
300
280
260
240
Temperature
220
200
-55 C
-40 C
0 C
85 C
125 C
150 C
25 C
0
0.5
1
1.5
2
2.5
3
3.5
0
0.5
1
1.5
2
2.5
3
3.5
VOUT (V)
Output Voltage − (V)
图6-25. Short-Circuit Current vs Output Voltage for Legacy
图6-26. Short-Circuit Current vs Output Voltage for New Chip
Chip
165
VIN = 4.3 V
COUT = 4.7 F
164
163
162
161
-55
-25
5
35
65
95
125
150
TEMPERATURE (C)
图6-27. Short-Circuit Current vs Temperature for New Chip
图6-28. ADJ Pin Bias Current vs. Load Current for Legacy Chip
30
Temp (C)
-55
-40
0
25
50
85
100
125
150
25
20
15
10
5
0
-5
0
5
10
15
20
25
30
35
40
45
50
ILOAD (mA)
图6-29. ADJ Pin Bias Current vs Load Current for New Chip
图6-30. ADJ Pin Bias Current vs Temperature for Legacy Chip
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6.6 Typical Characteristics (continued)
at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 1.0 V or 2.5 V (whichever is greater), IOUT = 1 mA, ON/OFF pin tied to
VIN, CIN = 1.0 µF, and COUT = 4.7 µF (unless otherwise noted)
18
ILOAD
1 mA
50 mA
14
10
6
2
-2
-75
-50
-25
0
25
50
75
100 125 150
TEMPERATURE (C)
图6-31. ADJ Pin Bias Current vs Temperature for New Chip
图6-32. ON/OFF Threshold vs Temperature for Legacy Chip
图6-33. ON/OFF Threshold vs Temperature for New Chip
图6-34. Output Noise Density for Legacy Chip
3.5
3.5
CFF (pF)
0
10
COUT
2.2 F
10 F
IOUT = 50 mA
COUT = 2.2 uF
IOUT = 50 mA
CFF = 10 pF
100
1000
3
2.5
2
3
2.5
2
1.5
1
1.5
1
0.5
0
0.5
0
1x101
1x102
1x103
1x104
1x105
1x106
1x107
1x101
1x102
1x103
1x104
1x105
1x106
1x107
FREQUENCY ( Hz)
FREQUENCY ( Hz)
VIN = 4.3 V, VOUT = 3.3 V, IOUT = 50 mA, CFF = 10 pF
VIN = 4.3 V, VOUT = 3.3 V, IOUT = 50 mA, COUT = 2.2 μF
图6-35. Output Noise Density vs CFF for New Chip
图6-36. Output Noise Density vs COUT for New Chip
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6.6 Typical Characteristics (continued)
at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 1.0 V or 2.5 V (whichever is greater), IOUT = 1 mA, ON/OFF pin tied to
VIN, CIN = 1.0 µF, and COUT = 4.7 µF (unless otherwise noted)
3.5
IOUT
1 mA
50 mA
COUT = 2.2 F
CFF = 10 pF
3
2.5
2
1.5
1
0.5
0
1x101
1x102
1x103
1x104
1x105
1x106
1x107
FREQUENCY ( Hz )
VIN = 4.3 V, VOUT = 3.3 V, COUT = 2.2 μF, CFF = 10 pF
图6-38. Ripple Rejection for Legacy Chip
图6-37. Output Noise Density vs IOUT for New Chip
100
100
90
80
70
60
50
40
30
20
10
0
CFF (pF)
0
10
COUT
10 uF
2.2 uF
90
100
1000
80
70
60
50
40
30
20
10
0
VOUT = 3.3V
CFF = 10pF
IOUT = 50mA
102
103
104
105
106
1x102
1x103
1x104
1x105
1x106
Frequency (Hz)
FREQUENCY (Hz)
VIN = 4.3 V, VOUT = 3.3 V, IOUT = 50 mA, CFF = 10 pF
VIN = 4.3 V, VOUT = 3.3 V, IOUT = 50 mA, COUT = 2.2 μF
图6-39. Ripple Rejection vs CFF for New Chip
图6-40. Ripple Rejection vs COUT for New Chip
120
IOUT
1 mA
50 mA
110
100
90
80
70
60
50
40
30
20
10
0
VOUT = 3.3V
COUT = 2.2uF
CFF = 10 pF
1x102
1x103
1x104
1x105
1x106
FREQUENCY (Hz)
VIN = 4.3 V, VOUT = 3.3 V, COUT = 2.2 μF, CFF = 10 pF
图6-41. Ripple Rejection vs IOUT for New Chip
图6-42. 2.2-μF ESR Curves for Legacy Chip
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6.6 Typical Characteristics (continued)
at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 1.0 V or 2.5 V (whichever is greater), IOUT = 1 mA, ON/OFF pin tied to
VIN, CIN = 1.0 µF, and COUT = 4.7 µF (unless otherwise noted)
图6-43. 4.7-μF ESR Curves for Legacy Chip
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7 Detailed Description
7.1 Overview
The LP2980-ADJ is an adjustable-output, low-dropout regulator that offers exceptional, cost-effective
performance for both portable and nonportable applications. The LP2980-ADJ has an output tolerance of 1%
across line, load, and temperature variation (for the new chip) and is capable of delivering 50 mA of continuous
load current.
This device features integrated overcurrent protection, thermal shutdown, output enable, and internal output
pulldown and has a built-in soft-start mechanism for controlled inrush current. This device delivers excellent line
and load transient performance. The operating ambient temperature range of the device is –40°C to +125°C.
7.2 Functional Block Diagram
VIN
VOUT
Current
Limit
CFF
UVLO
R1
ADJ
CF
RF
R2
Internal
Controller
Bandgap
Reference
Output
Pull-down
ON/OFF
VREF = 1.2 V
GND
GND
Thermal
Shutdown
GND
7.3 Feature Description
7.3.1 Output Enable
The ON/OFF pin for the device is an active-high pin. The output voltage is enabled when the voltage of the ON/
OFF pin is greater than the high-level input voltage of the ON/OFF pin and disabled when the ON/OFF pin
voltage is less than the low-level input voltage of the ON/OFF pin. If independent control of the output voltage is
not needed, connect the ON/OFF pin to the input of the device.
For the new chip, the device has an internal pulldown circuit that activates when the device is disabled by pulling
the ON/OFF pin voltage lower than the low-level input voltage of the ON/OFF pin, to actively discharge the
output voltage.
7.3.2 Dropout Voltage
Dropout voltage (VDO) is defined as the input voltage minus the output voltage (VIN – VOUT) at the rated output
current (IRATED), where the pass transistor is fully on. IRATED is the maximum IOUT listed in the Recommended
Operating Conditions table. The pass transistor is in the ohmic or triode region of operation, and acts as a
switch. The dropout voltage indirectly specifies a minimum input voltage greater than the nominal programmed
output voltage at which the output voltage is expected to stay in regulation. If the input voltage falls to less than
the nominal output regulation, then the output voltage falls as well.
For a CMOS regulator, the dropout voltage is determined by the drain-source on-state resistance (RDS(ON)) of the
pass transistor. Therefore, if the linear regulator operates at less than the rated current, the dropout voltage for
that current scales accordingly. The following equation calculates the RDS(ON) of the device.
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V
DO
R
=
(1)
DS ON
I
RATED
7.3.3 Current Limit
The device has an internal current limit circuit that protects the regulator during transient high-load current faults
or shorting events. The current limit is a brick-wall scheme. In a high-load current fault, the brick-wall scheme
limits the output current to the current limit (ICL). ICL is listed in the Electrical Characteristics table.
The output voltage is not regulated when the device is in current limit. When a current limit event occurs, the
device begins to heat up because of the increase in power dissipation. When the device is in brick-wall current
limit, the pass transistor dissipates power [(VIN – VOUT) × ICL]. If thermal shutdown is triggered, the device turns
off. After the device cools down, the internal thermal shutdown circuit turns the device back on. If the output
current fault condition continues, the device cycles between current limit and thermal shutdown. For more
information on current limits, see the Know Your Limits application note.
图7-1 shows a diagram of the current limit.
VOUT
Brick-wall
VOUT(NOM)
0 V
0 mA
IRATED
ICL
图7-1. Current Limit
7.3.4 Undervoltage Lockout (UVLO)
For the new chip, the device has an independent undervoltage lockout (UVLO) circuit that monitors the input
voltage, allowing a controlled and consistent turn on and off of the output voltage. To prevent the device from
turning off if the input drops during turn on, the UVLO has hysteresis as specified in the Electrical Characteristics
table.
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7.3.5 Output Pulldown
The new chip has an output pulldown circuit. The output pulldown activates in the following conditions:
• When the device is disabled (VON/OFF < VON/OFF(LOW)
)
• If 1.0 V < VIN < VUVLO
Do not rely on the output pulldown circuit for discharging a large amount of output capacitance after the input
supply has collapsed because reverse current can flow from the output to the input. This reverse current flow
can cause damage to the device. See the Reverse Current section for more details.
7.3.6 Thermal Shutdown
The device contains a thermal shutdown protection circuit to disable the device when the junction temperature
(TJ) of the pass transistor rises to TSD(shutdown) (typical). Thermal shutdown hysteresis assures that the device
resets (turns on) when the temperature falls to TSD(reset) (typical).
The thermal time-constant of the semiconductor die is fairly short, thus the device can cycle on and off when
thermal shutdown is reached until power dissipation is reduced. Power dissipation during start up can be high
from large VIN – VOUT voltage drops across the device or from high inrush currents charging large output
capacitors. Under some conditions, the thermal shutdown protection disables the device before start-up
completes.
For reliable operation, limit the junction temperature to the maximum listed in the Recommended Operating
Conditions table. Operation above this maximum temperature causes the device to exceed operational
specifications. Although the internal protection circuitry of the device is designed to protect against thermal
overall conditions, this circuitry is not intended to replace proper heat sinking. Continuously running the device
into thermal shutdown or above the maximum recommended junction temperature reduces long-term reliability.
7.4 Device Functional Modes
7.4.1 Device Functional Mode Comparison
表 7-1 shows the conditions that lead to the different modes of operation. See the Electrical Characteristics table
for parameter values.
表7-1. Device Functional Mode Comparison
PARAMETER
OPERATING MODE
VIN
VON/OFF
IOUT
TJ
Normal operation
Dropout operation
VIN > VOUT(nom) + VDO and VIN > VIN(min)
VIN(min) < VIN < VOUT(nom) + VDO
VON/OFF > VON/OFF(HI)
VON/OFF > VON/OFF(HI)
IOUT < IOUT(max)
IOUT < IOUT(max)
TJ < TSD(shutdown)
TJ < TSD(shutdown)
Disabled
(any true condition
disables the device)
VON/OFF < VON/
VIN < VUVLO
Not applicable
TJ > TSD(shutdown)
OFF(LOW)
7.4.2 Normal Operation
The device regulates to the nominal output voltage when the following conditions are met:
• The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO
• The output voltage is set by using ADJ pin (see External Feedback Resistors)
• The output current is less than the current limit (IOUT < ICL)
)
• The device junction temperature is less than the thermal shutdown temperature (TJ < TSD
)
• The ON/OFF voltage has previously exceeded the ON/OFF rising threshold voltage and has not yet
decreased to less than the enable falling threshold
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7.4.3 Dropout Operation
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other
conditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage
tracks the input voltage. During this mode, the transient performance of the device becomes significantly
degraded because the pass transistor is in the ohmic or triode region, and acts as a switch. Line or load
transients in dropout can result in large output-voltage deviations.
When the device is in a steady dropout state (defined as when the device is in dropout, VIN < VOUT(NOM) + VDO
,
directly after being in a normal regulation state, but not during start up), the pass transistor is driven into the
ohmic or triode region. When the input voltage returns to a value greater than or equal to the nominal output
voltage plus the dropout voltage (VOUT(NOM) + VDO), the output voltage can overshoot for a short period of time
while the device pulls the pass transistor back into the linear region.
7.4.4 Disabled
The output of the device can be shutdown by forcing the voltage of the ON/OFF pin to less than the maximum
ON/OFF pin low-level input voltage (see the Electrical Characteristics table). When disabled, the pass transistor
is turned off, internal circuits are shutdown, and the output voltage is actively discharged to ground by an internal
discharge circuit from the output to ground.
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8 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
8.1.1 External Feedback Resistors
The output voltage is set using the ADJ pin with help of the external feedback resistors, R1 and R2 (see 图 8-2),
according to the following equation:
V
= V
×
1 + R / R
2
(2)
OUT
ADJ
1
For the legacy chip, use a resistor from the ADJ pin to ground with a value of 51.1 kΩ.
For the new chip, to ignore the ADJ pin current error term in the VOUT equation, set the feedback divider current
to 100 times the ADJ pin current listed in the Electrical Characteristics table. This setting provides the maximum
feedback divider series resistance, as shown in the following equation:
R
+ R ≤ V
/ I × 100
ADJ
(3)
1
2
OUT
8.1.2 Recommended Capacitor Types
This section describes the recommended capacitors for both the new chip and the legacy chip.
8.1.2.1 Recommended Capacitors for the New Chip
The new chip is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the
input and output. Multilayer ceramic capacitors have become the industry standard for these types of
applications and are recommended, but must be used with good judgment. Ceramic capacitors that employ
X7R-, X5R-, and C0G-rated dielectric materials provide relatively good capacitive stability across temperature,
whereas the use of Y5V-rated capacitors is discouraged because of large variations in capacitance.
Regardless of the ceramic capacitor type selected, the effective capacitance varies with operating voltage and
temperature. Generally, expect the effective capacitance to decrease by as much as 50%. The input and output
capacitors listed in the Recommended Operating Conditions table account for an effective capacitance of
approximately 50% of the nominal value.
8.1.2.2 Recommended Capacitors for the Legacy Chip
The ESR of a good-quality tantalum capacitor is almost directly centered in the middle of the stable range of the
ESR curve (approximately 0.5 Ω–1 Ω). The temperature stability of tantalum capacitors is typically very good,
with a total variation of only approximately 2:1 over the temperature range of –40°C to +125°C (ESR increases
at colder temperatures). Avoid off-brand capacitors because some poor-quality tantalum capacitors are available
with ESR values greater than 10 Ω, which usually causes oscillation problems. One caution regarding tantalum
capacitors is that if used on the input, the ESR is low enough to be destroyed by a surge current if the capacitor
is powered up from a low impedance source (such as a battery) that has no limit on inrush current. In this case,
use a ceramic input capacitor that does not have this problem.
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Ceramic capacitors are generally larger and more costly than tantalum capacitors for a given amount of
capacitance. These capacitors also have a very low ESR that is quite stable with temperature. However, the
ESR of a ceramic capacitor is typically low enough to make an LDO oscillate. A 2.2-μF ceramic demonstrated
an ESR of approximately 15 mΩ when tested. If used as an output capacitor, this ESR can cause instability (see
the ESR curves in the Typical Characteristics section). If a ceramic capacitor is used on the output of an LDO,
place a small resistor (approximately 1 Ω) in series with the capacitor. If used as an input capacitor, no resistor is
needed because there is no requirement for ESR on capacitors used on the input.
8.1.3 Input and Output Capacitor Requirements
For the legacy chip, an input capacitor (CIN) ≥1 μF is required (the amount of capacitance can be increased
without limit). Any good-quality tantalum or ceramic capacitor can be used. The capacitor must be located no
more than half an inch from the input pin and returned to a clean analog ground.
For the new chip, although an input capacitor is not required for stability, good analog design practice is to
connect a capacitor from IN to GND. This capacitor counteracts reactive input sources and improves transient
response, input ripple, and PSRR. Use an input capacitor if the source impedance is more than 0.5 Ω. A higher
value capacitor can be necessary if large, fast rise-time load or line transients are anticipated or if the device is
located several inches from the input power source.
Dynamic performance of the device is improved with the use of an output capacitor. Use an output capacitor
within the range specified in the Recommended Operating Conditions table for stability.
8.1.4 Feed-Forward Capacitor (CFF)
A feed-forward capacitor (CFF) can be connected from the VOUT pin to the ADJ pin. CFF improves transient,
noise, and PSRR performance, but is not required for regulator stability. Recommended CFF values are listed in
the Recommended Operating Conditions table. A higher capacitance CFF can be used; however, the start-up
time increases. For a detailed description of CFF tradeoffs, see the Pros and Cons of Using a Feedforward
Capacitor with a Low-Dropout Regulator application note.
CFF and R1 form a zero in the loop gain at frequency fZ, whereas CFF, R1, and R2 form a pole in the loop gain at
frequency fP. CFF zero and pole frequencies can be calculated from the following equations:
fZ = 1 / (2 × π× CFF × R1)
(4)
(5)
fP = 1 / (2 × π× CFF × (R1 || R2))
For the legacy chip, a feed-forward capacitor (CFF) of 7 pF is required, because this capacitor provides the lead
compensation necessary for loop stability. Use a temperature-stable ceramic capacitor (NPO or COG type).
For the new chip, a CFF ≥ 10 pF is required for stability only if the feedback divider current is less than 5 μA.
The following equation calculates the feedback divider current.
IFB_Divider = VOUT / (R1 + R2)
(6)
To avoid start-up time increases from CFF, limit the product CFF × R1 < 50 µs.
For an output voltage of 1.2 V with the ADJ pin tied to the VOUT pin, no CFF is used.
8.1.5 Reverse Current
Excessive reverse current can damage this device. Reverse current flows through the intrinsic body diode of the
pass transistor instead of the normal conducting channel. At high magnitudes, this current flow degrades the
long-term reliability of the device.
Conditions where reverse current can occur are outlined in this section, all of which can exceed the absolute
maximum rating of VOUT ≤VIN + 0.3 V.
• If the device has a large COUT and the input supply collapses with little or no load current
• The output is biased when the input supply is not established
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• The output is biased above the input supply
If reverse current flow is expected in the application, use external protection to protect the device. Reverse
current is not limited in the device, so external limiting is required if extended reverse voltage operation is
anticipated.
图8-1 shows one approach for protecting the device.
Schottky Diode
Internal Body Diode
IN
OUT
CIN
COUT
GND
GND
GND
GND
图8-1. Example Circuit for Reverse Current Protection Using a Schottky Diode
8.1.6 Power Dissipation (PD)
Circuit reliability requires consideration of the device power dissipation, location of the circuit on the printed
circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator must have few
or no other heat-generating devices that cause added thermal stress.
To first-order approximation, power dissipation in the regulator depends on the input-to-output voltage difference
and load conditions. The following equation calculates power dissipation (PD).
PD = (VIN –VOUT) × IOUT
(7)
备注
Power dissipation can be minimized, and therefore greater efficiency can be achieved, by correct
selection of the system voltage rails. For the lowest power dissipation use the minimum input voltage
required for correct output regulation.
For devices with a thermal pad, the primary heat conduction path for the device package is through the thermal
pad to the PCB. Solder the thermal pad to a copper pad area under the device. This pad area must contain an
array of plated vias that conduct heat to additional copper planes for increased heat dissipation.
The maximum power dissipation determines the maximum allowable ambient temperature (TA) for the device.
According to the following equation, power dissipation and junction temperature are most often related by the
junction-to-ambient thermal resistance (RθJA) of the combined PCB and device package and the temperature of
the ambient air (TA).
TJ = TA + (RθJA × PD)
(8)
Thermal resistance (RθJA) is highly dependent on the heat-spreading capability built into the particular PCB
design, and therefore varies according to the total copper area, copper weight, and location of the planes. The
junction-to-ambient thermal resistance listed in the Thermal Information table is determined by the JEDEC
standard PCB and copper-spreading area, and is used as a relative measure of package thermal performance.
As mentioned in the An empirical analysis of the impact of board layout on LDO thermal performance application
note, RθJA can be improved by 35% to 55% compared to the Thermal Information table value with the PCB
board layout optimization.
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8.1.7 Estimating Junction Temperature
The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures
of the linear regulator when in-circuit on a typical PCB board application. These metrics are not thermal
resistance parameters and instead offer a practical and relative way to estimate junction temperature. These psi
metrics are determined to be significantly independent of the copper area available for heat-spreading. The
Thermal Information table lists the primary thermal metrics, which are the junction-to-top characterization
parameter (ψJT) and junction-to-board characterization parameter (ψJB). These parameters provide two
methods for calculating the junction temperature (TJ), as described in the following equations. Use the junction-
to-top characterization parameter (ψJT) with the temperature at the center-top of device package (TT) to
calculate the junction temperature. Use the junction-to-board characterization parameter (ψJB) with the PCB
surface temperature 1 mm from the device package (TB) to calculate the junction temperature.
TJ = TT + ψJT × PD
(9)
where:
• PD is the dissipated power
• TT is the temperature at the center-top of the device package
TJ = TB + ψJB × PD
(10)
where:
• TB is the PCB surface temperature measured 1 mm from the device package and centered on the package
edge
For detailed information on the thermal metrics and how to use them, see the Semiconductor and IC Package
Thermal Metrics application note.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SNVS001
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8.2 Typical Application
图8-2 shows the standard usage of the LP2980-ADJ as a low-dropout regulator.
VOUT
VIN
IN
OUT
LP2980-ADJ
R1
R2
CFF
ON/
COUT
CIN
ADJ
OFF
GND
GND
GND
GND
GND
图8-2. LP2980-ADJ Typical Application
8.2.1 Design Requirements
For this design, use the minimum COUT value for stability (which can be increased without limit for improved
stability and transient response). The ON/OFF pin must be actively terminated. Connect this pin to VIN if the
shutdown feature is not used. Set the output voltage using a feedback divider between the VOUT pin and the ADJ
pin. Use an optional CFF capacitor for improved transient, noise, and PSRR performance.
For the new chip, 表8-1 summarizes the design requirements for 图8-2.
表8-1. Design Parameters
PARAMETER
Input voltage
DESIGN REQUIREMENT
12 V
2.5 V
Output voltage
Output current
50 mA
R1 (feedback resistance)
R2 (feedback resistance)
108.33 kΩ
100.00 kΩ
8.2.2 Detailed Design Procedure
8.2.2.1 Setting VOUT For the LP2980-ADJ LDO
As illustrated in 图 8-2, the LP2980-ADJ uses the feedback divider to set the output voltage. The output voltage
operating range is 1.2 V to 15 V, and is calculated using:
V
= V
×
1 + R /R
2
(11)
OUT
ADJ
1
where:
• VREF = 1.2 V (typical)
Choose resistors R1 and R2 as suggested in the External Feedback Resistors section.
图8-2 depicts this configuration.
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8.2.2.2 ON/OFF Input Operation
The LP2980-ADJ is shut off by driving the ON/OFF input low, and turned on by pulling the ON/OFF input high. If
this feature is not used, the ON/OFF input must be tied to VIN to keep the regulator output on at all times (the
ON/OFF input must not be left floating).
To ensure proper operation, the signal source used to drive the ON/OFF input must be able to swing above and
below the specified turn-on/turn-off voltage thresholds that specify an ON or OFF state (see the Electrical
Characteristics table).
For the legacy chip, the turn-on (and turn-off) voltage signals applied to the ON/OFF input must have a slew rate
which is greater than 40 mV/μs.
For the new chip, there is no restriction on the slew rate of the voltage signals applied to the ON/OFF input. Both
fast and slow ramping voltage signals can be used to drive the ON/OFF pin.
备注
For the legacy chip only, the ON/OFF function does not operate correctly if a slow-moving signal is
used to drive the ON/OFF input.
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English Data Sheet: SNVS001
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8.2.3 Application Curves
at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 1.0 V or 2.5 V (whichever is greater), IOUT = 1 mA, ON/
OFF pin tied to VIN, CIN = 1.0 µF, and COUT = 4.7 µF (unless otherwise noted)
3.82
3.76
3.7
300
250
200
150
100
50
VOUT
ILOAD
ILOAD = 50 mA
VOUT = 3.3 V
3.64
3.58
3.52
3.46
3.4
0
-50
3.34
3.28
3.22
3.16
3.1
-100
-150
-200
-250
-300
0
20
40
60
80
100
120
140150
TIME ( s )
dI/dt = 1 A/μF
图8-3. Load Transient Response for Legacy Chip
图8-4. Load Transient Response for New Chip
3.41
3.39
3.37
3.35
3.33
3.31
3.29
3.27
6.5
VOUT
VIN
VOUT = 3.3 V
IOUT = 50 mA
VIN = 1 V
6
5.5
5
4.5
4
3.5
3
0
40
80
120
160
200
240
280
TIME ( s )
VOUT = 3.3 V, ΔVIN = 1 V, IOUT = 50 mA, dV/dt = 1 V/μs
图8-5. Line Transient Response for Legacy Chip
图8-6. Line Transient Response for New Chip
25
VIN
10 pF
1 nF
10 nF
20
15
10
5
0
-5
0
2
4
6
8
10
12
14
16
TIME (ms)
VOUT = 3.3 V, dV/dt = 1 V/μs
图8-7. Start-Up vs CFF for New Chip
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8.3 Power Supply Recommendations
A power supply can be used at the input voltage within the ranges given in the Recommended Operating
Conditions table. Use bypass capacitors as described in the Layout Guidelines section.
8.4 Layout
8.4.1 Layout Guidelines
• Bypass the input pin to ground with a bypass capacitor.
• The optimum placement of the bypass capacitor is closest to the VIN of the device and GND of the system.
Care must be taken to minimize the loop area formed by the bypass capacitor connection, the VIN pin, and
the GND pin of the system.
• For operation at full-rated load, use wide trace lengths to eliminate IR drop and heat dissipation.
8.4.2 Layout Example
CIN
5
COUT
OUT
5
5
IN
GND
EN
1
2
5
4
R1
R2
CFF
FB
5
5
3
GND PLANE
图8-8. Layout Diagram
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English Data Sheet: SNVS001
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9 Device and Documentation Support
9.1 Device Support
9.1.1 Device Nomenclature
表9-1. Available Options(1)
PRODUCT
VOUT
A is for higher accuracy and non-A is for standard grade. c is the accuracy specification.
xxx is the package designator. z is the package quantity. X is for large quantity reel and
non-X is for small quantity reel.
LP2980cxxxz-ADJ/NOPB
Legacy chip
A is for higher accuracy and non-A is for standard grade. xxx is the package designator.
z is the package quantity. X is for large quantity reel and non-X is for small quantity reel.
M3 is a suffix designator for newer chip redesigns, fabricated on the latest TI process
technology.
LP2980Axxxz-ADJ/M3
New chip
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
9.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
9.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
9.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
9.5 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
9.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
19-Jun-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LP2980IM5-ADJ
NRND
SOT-23
DBV
5
1000
Non-RoHS
& Green
Call TI
Level-1-260C-UNLIM
-40 to 125
L06B
LP2980IM5-ADJ/NOPB
LP2980IM5X-ADJ
ACTIVE
NRND
SOT-23
SOT-23
DBV
DBV
5
5
1000 RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
L06B
L06B
Samples
Samples
3000
Non-RoHS
& Green
Call TI
LP2980IM5X-ADJ/NOPB
ACTIVE
SOT-23
DBV
5
3000 RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
L06B
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
19-Jun-2023
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LP2980IM5-ADJ
SOT-23
DBV
DBV
DBV
DBV
5
5
5
5
1000
1000
3000
3000
178.0
178.0
178.0
178.0
8.4
8.4
8.4
8.4
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
1.4
1.4
1.4
1.4
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
Q3
Q3
Q3
Q3
LP2980IM5-ADJ/NOPB SOT-23
LP2980IM5X-ADJ SOT-23
LP2980IM5X-ADJ/NOPB SOT-23
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LP2980IM5-ADJ
LP2980IM5-ADJ/NOPB
LP2980IM5X-ADJ
SOT-23
SOT-23
SOT-23
SOT-23
DBV
DBV
DBV
DBV
5
5
5
5
1000
1000
3000
3000
208.0
208.0
208.0
208.0
191.0
191.0
191.0
191.0
35.0
35.0
35.0
35.0
LP2980IM5X-ADJ/NOPB
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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Copyright © 2023，德州仪器 (TI) 公司
相关型号：
LP2980AIBPX-3.3/NOPB
3.3V FIXED POSITIVE LDO REGULATOR, 0.225V DROPOUT, PBGA5, MICRO, BUMP, SMD-5
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