LP2985A-25DBVT [TI]
150MA LOW NOISE LOW DROPOUT REGULATOR WITH SHUTDOWN; 150MA低噪声低压差，具有关断稳压器
| 型号： | LP2985A-25DBVT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 150MA LOW NOISE LOW DROPOUT REGULATOR WITH SHUTDOWN |
| 文件： | 总23页 (文件大小：527K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SLVS522C − JULY 2004 − REVISED OCTOBER 2004
D
D
D
Available in the Texas Instruments
NanoStar and NanoFree Wafer Chip
Scale Packages
D
D
D
D
Stable With Low-ESR Capacitors, Including
Ceramic
Over-Current and Thermal Protection
High Peak-Current Capability
Output Tolerance of:
− 1% (A Grade)
− 1.5% (Standard Grade)
For V
Data Sheet
Options 3 2.3 V, See LP2985LV
OUT
Ultra-Low Dropout, Typically
− 280 mV at Full Load of 150 mA
− 7 mV at 1 mA
D
Portable Applications
− Cellular Phones
− Palmtop and Laptop Computers
− Personal Digital Assistants (PDAs)
− Digital Cameras and Camcorders
− CD Players
D
D
D
D
Wide V Range . . . 16 V Max
IN
Low I . . . 850 µA at Full Load at 150 mA
Q
Shutdown Current . . . 0.01 µA Typ
− MP3 Players
Low Noise . . . 30 µV
Capacitor
With 10-nF Bypass
RMS
DBV (SOT-23) PACKAGE
(TOP VIEW)
YEQ, YEU, YZQ, OR YZU (WCSP) PACKAGE
(TOP VIEW)
C3
1
2
3
5
4
V
GND
ON/OFF
V
OUT
IN
C1
V
V
OUT
IN
BYPASS
B2
BYPASS
GND
A1
ON/OFF
A3
description/ordering information
The LP2985 family of fixed-output, low-dropout regulators offers exceptional, cost-effective performance for
both portable and nonportable applications. Available in voltages of 2.5 V, 2.6 V, 2.7 V, 2.8 V, 2.85 V, 3 V,
3.1 V, 3.2 V, 3.3 V, and 5 V, the family has an output tolerance of 1% for the A version (1.5% for the non-A version)
and is capable of delivering 150-mA continuous load current. Standard regulator features, such as over-current
and over-temperature protection, are included.
The LP2985 has a host of features that makes the regulator an ideal candidate for a variety of portable
applications:
• Low dropout: A PNP pass element allows a typical dropout of 280 mV at 150-mA load current and 7 mV
at 1-mA load.
• Low quiescent current: The use of a vertical PNP process allows for quiescent currents that are
considerably lower than those associated with traditional lateral PNP regulators.
• Shutdown: A shutdown feature is available, allowing the regulator to consume only 0.01 µA when the
ON/OFF pin is pulled low.
• Low-ESR-capacitor friendly: The regulator is stable with low-ESR capacitors, allowing the use of small,
inexpensive, ceramic capacitors in cost-sensitive applications.
• Low noise: A BYPASS pin allows for low-noise operation, with a typical output noise of 30 µV (RMS),
with the use of a 10-nF bypass capacitor.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar and NanoFree are trademarks of Texas Instruments.
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Copyright 2004, Texas Instruments Incorporated
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ꢟ ꢣ ꢠ ꢟꢙ ꢚꢭ ꢜꢛ ꢞ ꢦꢦ ꢤꢞ ꢝ ꢞ ꢉ ꢣ ꢟ ꢣ ꢝ ꢠ ꢨ
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄꢅ
ꢆꢅ ꢇꢈꢉ ꢊ ꢀ ꢋꢌꢈꢍ ꢋ ꢎꢏ ꢐ ꢑ ꢀꢋ ꢌꢈꢒꢓ ꢋꢁ ꢋ ꢔꢕ ꢓ ꢐꢖ ꢔꢀ ꢊꢕꢋ ꢓ
ꢌꢎ ꢕ ꢗ ꢏꢗ ꢔ ꢕ ꢒꢋ ꢌꢍ
SLVS522C − JULY 2004 − REVISED OCTOBER 2004
description/ordering information (continued)
• Small packaging: For the most space-constraint needs, the regulator is available in SOT-23 package,
as well as NanoStar wafer chip scale packaging, offering an even smaller size with improved thermal
and electrical characteristics. NanoStar package technology is a major breakthrough in IC packaging
concepts, using the die as the package.
ORDERING INFORMATION
PART
GRADE
V
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
OUT
†
PACKAGE
T
J
‡
(NOM)
Reel of 3000
LP2985A-25DBVR
LP2985A-25DBVT
LP2985A-26DBVR
LP2985A-26DBVT
LP2985A-27DBVR
LP2985A-27DBVT
LP2985A-28DBVR
LP2985A-28DBVT
LP2985A-285DBVR
LP2985A-285DBVT
LP2985A-30DBVR
LP2985A-30DBVT
LP2985A-31DBVR
LP2985A-31DBVT
LP2985A-32DBVR
LP2985A-32DBVT
LP2985A-33DBVR
LP2985A-33DBVT
LP2985A-50DBVR
LP2985A-50DBVT
PREVIEW
2.5 V
Reel of 250
Reel of 3000
Reel of 250
Reel of 3000
Reel of 250
Reel of 3000
Reel of 250
Reel of 3000
Reel of 250
Reel of 3000
Reel of 250
Reel of 3000
Reel of 250
Reel of 3000
Reel of 250
Reel of 3000
Reel of 250
Reel of 3000
Reel of 250
PREVIEW
PREVIEW
2.6 V
2.7 V
2.8 V
2.85 V
3 V
LPJ_
PREVIEW
PREVIEW
A grade:
1% tolerance
−40°C to 125°C
SOT23-5 (DBV)
PREVIEW
PREVIEW
LPK_
3.1 V
3.2 V
3.3 V
5 V
PREVIEW
†
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
DBV: The actual top-side marking has one additional character that designates the assembly/test site.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅ
ꢆ ꢅ ꢇ ꢈꢉꢊ ꢀ ꢋꢌꢈꢍꢋ ꢎꢏ ꢐꢑ ꢀ ꢋ ꢌꢈꢒꢓꢋ ꢁꢋ ꢔꢕ ꢓꢐ ꢖ ꢔꢀ ꢊꢕꢋ ꢓ
ꢌ ꢎꢕ ꢗ ꢏꢗ ꢔꢕ ꢒꢋ ꢌ ꢍ
SLVS522C − JULY 2004 − REVISED OCTOBER 2004
ORDERING INFORMATION (continued)
PART
GRADE
V
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
OUT
†
PACKAGE
T
J
‡
(NOM)
2.5 V
2.6 V
2.7 V
2.8 V
2.85 V
3 V
LP2985A-25YEQR
LP2985A-26YEQR
LP2985A-27YEQR
LP2985A-28YEQR
LP2985A-285YEQR
LP2985A-30YEQR
LP2985A-31YEQR
LP2985A-32YEQR
LP2985A-33YEQR
LP2985A-50YEQR
LP2985A-25YZQR
LP2985A-26YZQR
LP2985A-27YZQR
LP2985A-28YZQR
LP2985A-285YZQR
LP2985A-30YZQR
LP2985A-31YZQR
LP2985A-32YZQR
LP2985A-33YZQR
LP2985A-50YZQR
LP2985A-25YEUR
LP2985A-26YEUR
LP2985A-27YEUR
LP2985A-28YEUR
LP2985A-285YEUR
LP2985A-30YEUR
LP2985A-31YEUR
LP2985A-32YEUR
LP2985A-33YEUR
LP2985A-50YEUR
LP2985A-25YZUR
LP2985A-26YZUR
LP2985A-27YZUR
LP2985A-28YZUR
LP2985A-285YZUR
LP2985A-30YZUR
LP2985A-31YZUR
LP2985A-32YZUR
LP2985A-33YZUR
LP2985A-50YZUR
NanoStar − WCSP
0.17-mm Bump (YEQ)
Reel of 3000
3.1 V
3.2 V
3.3 V
5 V
2.5 V
2.6 V
2.7 V
2.8 V
2.85 V
3 V
NanoFree − WCSP
0.17-mm Bump
(YZQ, Pb-free)
Reel of 3000
Reel of 3000
Reel of 3000
3.1 V
3.2 V
3.3 V
5 V
A grade:
1% tolerance
−40°C to 125°C
2.5 V
2.6 V
2.7 V
2.8 V
2.85 V
3 V
NanoFree − WCSP
0.30-mm Bump (YEU)
3.1 V
3.2 V
3.3 V
5 V
2.5 V
2.6 V
2.7 V
2.8 V
2.85 V
3 V
NanoFree − WCSP
0.30-mm Bump
(YZU, Pb-free)
3.1 V
3.2 V
3.3 V
5 V
†
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
YEQ/YZQ, YEU/YZU: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one
following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄꢅ
ꢆꢅ ꢇꢈꢉ ꢊ ꢀ ꢋꢌꢈꢍ ꢋ ꢎꢏ ꢐ ꢑ ꢀꢋ ꢌꢈꢒꢓ ꢋꢁ ꢋ ꢔꢕ ꢓ ꢐꢖ ꢔꢀ ꢊꢕꢋ ꢓ
ꢌꢎ ꢕ ꢗ ꢏꢗ ꢔ ꢕ ꢒꢋ ꢌꢍ
SLVS522C − JULY 2004 − REVISED OCTOBER 2004
ORDERING INFORMATION (continued)
V
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
OUT
†
PACKAGE
T
J
PART GRADE
‡
(NOM)
Reel of 3000
LP2985-25DBVR
LP2985-25DBVT
LP2985-26DBVR
LP2985-26DBVT
LP2985-27DBVR
LP2985-27DBVT
LP2985-28DBVR
LP2985-28DBVT
LP2985-285DBVR
LP2985-285DBVT
LP2985-30DBVR
LP2985-30DBVT
LP2985-31DBVR
LP2985-31DBVT
LP2985-32DBVR
LP2985-32DBVT
LP2985-33DBVR
LP2985-33DBVT
LP2985-50DBVR
LP2985-50DBVT
PREVIEW
2.5 V
Reel of 250
Reel of 3000
Reel of 250
Reel of 3000
Reel of 250
Reel of 3000
Reel of 250
Reel of 3000
Reel of 250
Reel of 3000
Reel of 250
Reel of 3000
Reel of 250
Reel of 3000
Reel of 250
Reel of 3000
Reel of 250
Reel of 3000
Reel of 250
PREVIEW
PREVIEW
2.6 V
2.7 V
2.8 V
2.85 V
3 V
LPG_
PREVIEW
PREVIEW
Standard grade:
1.5% tolerance
−40°C to 125°C
SOT-23 (DBV)
PREVIEW
PREVIEW
LPF_
3.1 V
3.2 V
3.3 V
5 V
PREVIEW
†
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
DBV: The actual top-side marking has one additional character that designates the assembly/test site.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅ
ꢆ ꢅ ꢇ ꢈꢉꢊ ꢀ ꢋꢌꢈꢍꢋ ꢎꢏ ꢐꢑ ꢀ ꢋ ꢌꢈꢒꢓꢋ ꢁꢋ ꢔꢕ ꢓꢐ ꢖ ꢔꢀ ꢊꢕꢋ ꢓ
ꢌ ꢎꢕ ꢗ ꢏꢗ ꢔꢕ ꢒꢋ ꢌ ꢍ
SLVS522C − JULY 2004 − REVISED OCTOBER 2004
ORDERING INFORMATION (continued)
V
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
OUT
†
PACKAGE
T
PART GRADE
J
‡
(NOM)
2.5 V
2.6 V
2.7 V
2.8 V
2.85 V
3 V
LP2985-25YEQR
LP2985-26YEQR
LP2985-27YEQR
LP2985-28YEQR
LP2985-285YEQR
LP2985-30YEQR
LP2985-31YEQR
LP2985-32YEQR
LP2985-33YEQR
LP2985-50YEQR
LP2985-25YZQR
LP2985-26YZQR
LP2985-27YZQR
LP2985-28YZQR
LP2985-285YZQR
LP2985-30YZQR
LP2985-31YZQR
LP2985-32YZQR
LP2985-33YZQR
LP2985-50YZQR
LP2985-25YEUR
LP2985-26YEUR
LP2985-27YEUR
LP2985-28YEUR
LP2985-285YEUR
LP2985-30YEUR
LP2985-31YEUR
LP2985-32YEUR
LP2985-33YEUR
LP2985-50YEUR
LP2985-25YZUR
LP2985-26YZUR
LP2985-27YZUR
LP2985-28YZUR
LP2985-285YZUR
LP2985-30YZUR
LP2985-31YZUR
LP2985-32YZUR
LP2985-33YZUR
LP2985-50YZUR
NanoStar − WCSP
0.17-mm Bump (YEQ)
Reel of 3000
3.1 V
3.2 V
3.3 V
5 V
2.5 V
2.6 V
2.7 V
2.8 V
2.85 V
3 V
NanoFree − WCSP
0.17-mm Bump
(YZQ, Pb-free)
Reel of 3000
Reel of 3000
Reel of 3000
3.1 V
3.2 V
3.3 V
5 V
Standard grade:
1.5% tolerance
−40°C to 125°C
2.5 V
2.6 V
2.7 V
2.8 V
2.85 V
3 V
NanoStar − WCSP
0.30-mm Bump (YEU)
3.1 V
3.2 V
3.3 V
5 V
2.5 V
2.6 V
2.7 V
2.8 V
2.85 V
3 V
NanoFree − WCSP
0.30-mm Bump
(YZU, Pb-free)
3.1 V
3.2 V
3.3 V
5 V
†
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
YEQ/YZQ, YEU/YZU: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one
following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄꢅ
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ꢇ
ꢈ
ꢉ
ꢊ
ꢀ
ꢌꢎ ꢕ ꢗ ꢏꢗ ꢔ ꢕ ꢒꢋ ꢌꢍ
ꢋ
ꢌ
ꢈ
ꢍ
ꢋ
ꢎ
ꢏ
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ꢑ
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ꢋ
ꢌ
ꢈ
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ꢓ
ꢋꢁ
ꢋ
ꢔ
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ꢓ
ꢐ
ꢖ
ꢔ
ꢀ
ꢊꢕꢋ
ꢓ
SLVS522C − JULY 2004 − REVISED OCTOBER 2004
functional block diagram
V
IN
ON/OFF
1.23 V
V
REF
−
+
BYPASS
V
OUT
Over-Current/
Over-Temperature
Protection
basic application circuit
LP2985A-xxDBVR
V
OUT
V
IN
1
5
†
2.2 µF
†
1 µF
GND
2
3
‡
ON/OFF
4
BYPASS
§
10 nF
†
‡
§
Minimum C
OUT
value for stability (can be increased without limit for improved stability and transient response)
ON/OFF must be actively terminated. Connect to V if shutdown feature is not used.
IN
Optional BYPASS capacitor for low-noise operation
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅ
ꢆ ꢅ ꢇ ꢈꢉꢊ ꢀ ꢋꢌꢈꢍꢋ ꢎꢏ ꢐꢑ ꢀ ꢋ ꢌꢈꢒꢓꢋ ꢁꢋ ꢔꢕ ꢓꢐ ꢖ ꢔꢀ ꢊꢕꢋ ꢓ
ꢌ ꢎꢕ ꢗ ꢏꢗ ꢔꢕ ꢒꢋ ꢌ ꢍ
SLVS522C − JULY 2004 − REVISED OCTOBER 2004
†
absolute maximum ratings over the virtual junction temperature range (unless otherwise noted)
Continuous input voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 16 V
IN
ON/OFF input voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 16 V
ON/OFF
Output voltage range (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 9 V
Input/output voltage differential range, V -V
(see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 16 V
IN OUT
Output current, I (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internally limited (short-circuit protected)
O
Package thermal impedance, θ (see Notes 3 and 4): DBV package . . . . . . . . . . . . . . . . . . . . . . . . 206°C/W
JA
YEQ/YZQ package . . . . . . . . . . . . . . . . . . TBD°C/W
YEU/YZU package . . . . . . . . . . . . . . . . . . . TBD°C/W
Operating virtual junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. If load is returned to a negative power supply in a dual-supply system, the output must be diode clamped to GND.
2. The PNP pass transistor has a parasitic diode connected between the input and output. This diode normally is reverse biased
(V > V
for more details).
), but will be forward biased if the output voltage exceeds the input voltage by a diode drop (see Application Information
IN OUT
3. Maximum power dissipation is a function of T (max), ꢀ , and T . The maximum allowable power dissipation at any allowable
J
JA
A
ambient temperature is P = (T (max) − T )/ꢀ . Operating at the absolute maximum T of 150°C can affect reliability.
D
J
A
JA
J
4. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions
MIN
MAX
UNIT
V
‡
V
V
Supply input voltage
ON/OFF input voltage
Output current
16
IN
0
V
V
ON/OFF
OUT
IN
I
150
125
mA
°C
Virtual junction temperature
T
J
−40
‡
Recommended minimum V is the greater of:
IN
a) 2.5 V or
b) V
OUT(max)
+ rated dropout voltage (max) for operating I .
L
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄꢅ
ꢆꢅ ꢇꢈꢉ ꢊ ꢀ ꢋꢌꢈꢍ ꢋ ꢎꢏ ꢐ ꢑ ꢀꢋ ꢌꢈꢒꢓ ꢋꢁ ꢋ ꢔꢕ ꢓ ꢐꢖ ꢔꢀ ꢊꢕꢋ ꢓ
ꢌꢎ ꢕ ꢗ ꢏꢗ ꢔ ꢕ ꢒꢋ ꢌꢍ
SLVS522C − JULY 2004 − REVISED OCTOBER 2004
electrical characteristics at specified virtual junction temperature range,
V
= V
(nominal)+ 1V, V
= 2 V, C = 1 mF, I = 1 mA, C
= 4.7 mF (unless otherwise noted)
IN
OUT
ON/OFF
IN
L
OUT
LP2985A-XX
MIN TYP
LP2985-XX
MIN TYP
PARAMETER
TEST CONDITIONS
UNIT
T
J
MAX
1
MAX
1.5
2.5
3.5
3.0
4.0
I
= 1 mA
25°C
25°C
−1
−1.5
−2.5
−2.5
−3.5
−1.5
−2.5
−3.5
−3.0
−4.0
L
1.5
2.5
2.5
3.5
1 mA ≤ I ≤ 50 mA
Output voltage
tolerance
L
−40°C to 125°C
25°C
nV
OUT
%V
NOM
1 mA ≤ I ≤ 150 mA
L
−40°C to 125°C
25°C
0.007 0.014
0.032
0.007 0.014
0.032
V
[V
=
IN
Line regulation
%/V
+ 1 V] to 16 V
−40°C to 125°C
25°C
OUT(NOM)
1
3
5
1
3
5
I
L
I
L
I
L
I
L
I
L
I
L
I
L
I
L
I
L
I
L
= 0
−40°C to 125°C
25°C
7
10
7
10
= 1 mA
= 10 mA
= 50 mA
= 150 mA
= 0
−40°C to 125°C
25°C
15
15
40
60
40
60
Dropout voltage
(see Note 5)
V
-V
mV
IN OUT
−40°C to 125°C
25°C
90
90
120
280
65
150
225
350
575
95
120
280
65
150
225
350
575
95
−40°C to 125°C
25°C
−40°C to 125°C
25°C
−40°C to 125°C
25°C
125
110
170
220
400
600
1000
1500
2500
0.8
2
125
110
170
220
400
600
1000
1500
2500
0.8
2
75
75
= 1 mA
= 10 mA
= 50 mA
= 150 mA
−40°C to 125°C
25°C
120
350
850
120
350
850
−40°C to 125°C
25°C
I
Ground pin current
µA
GND
−40°C to 125°C
25°C
−40°C to 125°C
25°C
V
V
V
< 0.3 V (OFF)
< 0.15 V (OFF)
= HIGH !!
0.01
0.05
0.01
0.05
ON/OFF
ON/OFF
ON/OFF
−40°C to 105°C
−40°C to 125°C
25°C
5
5
1.4
0.55
0.01
5
1.4
0.55
0.01
5
ON/OFF input
voltage
(see Note 6)
O/P ON
−40°C to 125°C
25°C
1.6
1.6
V
V
ON/OFF
V
= LOW !!
ON/OFF
O/P OFF
−40°C to 125°C
25°C
0.15
−2
0.15
−2
V
= 0
ON/OFF
ON/OFF
−40°C to 125°C
25°C
ON/OFF input
current
I
µA
ON/OFF
V
= 5 V
−40°C to 125°C
15
15
NOTES: 5. Dropout voltage is defined as the input-to-output differential at which the output voltage drops 100 mV below the value
measured with a 1-V differential.
6. The ON/OFF input must be properly driven for reliable operation (see Application Information).
8
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ꢌ ꢎꢕ ꢗ ꢏꢗ ꢔꢕ ꢒꢋ ꢌ ꢍ
SLVS522C − JULY 2004 − REVISED OCTOBER 2004
electrical characteristics at specified virtual junction temperature range,
V
= V
(nominal)+ 1V, V
= 2 V, C = 1 mF, I = 1 mA, C
= 4.7 mF (unless otherwise noted)
IN
OUT
ON/OFF
IN
L
OUT
(continued)
LP2985A-XX
LP2985-XX
TYP MAX
PARAMETER
TEST CONDITIONS
UNIT
T
J
MIN
TYP
MAX
MIN
BW = 300 Hz to 50 kHz,
Output noise
(RMS)
V
C
C
= 10 µF,
25°C
25°C
30
30
45
µV
n
OUT
BYPASS
= 10 nF
f = 1kHz,
Ripple
rejection
nV
/nV
OUT IN
C
C
= 10 µF,
BYPASS
45
dB
OUT
= 10 nF
Peak output
current
I
I
V
R
≥ V
− 5%
25°C
25°C
350
400
350
400
mA
mA
OUT(PK)
OUT
O(NOM)
Short-circuit
current
= 0 (steady state)
L
OUT(SC)
(see Note 7)
NOTE 7: See Typical Characteristics Curve, Short-Circuit Current vs V
OUT
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ꢌꢎ ꢕ ꢗ ꢏꢗ ꢔ ꢕ ꢒꢋ ꢌꢍ
SLVS522C − JULY 2004 − REVISED OCTOBER 2004
APPLICATION INFORMATION
capacitors
input capacitor (C )
in
A minimum value of 1 ꢁ F (over the entire operating temperature range) is required at the input of the LP2985.
In addition, this input capacitor should be located within 1 cm of the input pin and connected to a clean analog
ground. There are no Equivalent Series Resistance (ESR) requirements for this capacitor, and the capacitance
can be increased without limit.
output capacitor (C
)
out
As an advantage over other regulators, the LP2985 permits the use of low-ESR capacitors at the output,
including ceramic capacitors that can have an ESR as low as 5 mΩ. Tantalum and film capacitors also can be
used if size and cost are not issues. The output capacitor also should be located within 1 cm of the output pin
and be returned to a clean analog ground.
As with other PNP LDOs, stability conditions require the output capacitor to have a minimum capacitance and
an ESR that falls within a certain range.
Minimum C : 2.2 µF (can be increased without limit to improve transient response stability margin)
out
ESR range: see Figure 1
Load Current − mA
Figure 1. 2.2-V/3.3-µF ESR Curves
It is critical that both the minimum capacitance and ESR requirement be met over the entire operating
temperature range. Depending on the type of capacitors used, both these parameters can vary significantly with
temperature (see capacitor characteristics section).
noise bypass capacitor (C
)
bypass
The LP2985 allows for low-noise performance with the use of a bypass capacitor that is connected to the internal
bandgap reference via the BYPASS pin. This high-impedance bandgap circuitry is biased in the microampere
range and, thus, cannot be loaded significantly, otherwise, its output − and, correspondingly, the output of the
regulator − will change. Thus, for best output accuracy, dc leakage current through C
as much as possible and never should exceed 100 nA.
should be minimized
bypass
A 10-nF capacitor is recommended for C
; ceramic and film capacitors are well suited for this purpose.
bypass
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ꢌ ꢎꢕ ꢗ ꢏꢗ ꢔꢕ ꢒꢋ ꢌ ꢍ
SLVS522C − JULY 2004 − REVISED OCTOBER 2004
APPLICATION INFORMATION
capacitor characteristics
ceramics
Ceramic capacitors are ideal choices for use on the output of the LP2985 for several reasons. For capacitances
in the range of 2.2 µF to 4.7 µF, ceramic capacitors have the lowest cost and the lowest ESR, making them
choice candidates for filtering high-frequency noise. For instance, a typical 2.2-µF ceramic capacitor has an
ESR in the range of 10 mΩ to 20 mΩ and, thus, satisfies minimum ESR requirements of the regulator.
Ceramic capacitors have one glaring disadvantage that must be taken into account − a poor temperature
coefficient, where the capacitance can vary significantly with temperature. For instance, a large-value ceramic
capacitor (≥2.2 µF) can lose more than half of its capacitance as the temperature rises from 25°C to 85°C. Thus,
a 2.2-µF capacitor at 25°C will drop well below the minimum C
required for stability, as ambient temperature
out
rises. For this reason, select an output capacitor that maintains the minimum 2.2 µF required for stability over
the entire operating temperature range. Note that there are some ceramic capacitors that can maintain a 15%
capacitance tolerance over temperature.
tantalum
Tantalum capacitors can be used at the output of the LP2985, but there are significant disadvantages that could
prohibit their use:
• In the 1-µF to 4.7-µF range, tantalum capacitors are more expensive than ceramics of the equivalent
capacitance and voltage ratings.
• Tantalum capacitors have higher ESRs than their equivalent-sized ceramic counterparts. Thus, to meet
the ESR requirements, a higher-capacitance tantalum may be required, at the expense of larger size
and higher cost.
• The ESR of a tantalum capacitor increases as temperature drops, as much as double from 25°C to
−40°C. Thus, ESR margins must be maintained over the temperature range in order to prevent
regulator instability.
ON/OFF operation
The LP2985 allows for a shutdown mode via the ON/OFF pin. Driving the pin LOW (≤0.3 V) turns the device
OFF; conversely, a HIGH (≥1.6 V) turns the device ON. If the shutdown feature is not used, ON/OFF should be
connected to the input to ensure that the regulator is on at all times. For proper operation, do not leave ON/OFF
unconnected, and apply a signal with a slew rate of ≥40 mV/µs.
11
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ꢌꢎ ꢕ ꢗ ꢏꢗ ꢔ ꢕ ꢒꢋ ꢌꢍ
SLVS522C − JULY 2004 − REVISED OCTOBER 2004
APPLICATION INFORMATION
reverse input-output voltage
There is an inherent diode present across the PNP pass element of the LP2985.
V
IN
V
OUT
With the anode connected to the output, this diode is reverse biased during normal operation, since the input
voltage is higher than the output. However, if the output is pulled higher than the input for any reason, this diode
is forward biased and can cause a parasitic silicon-controlled rectifier (SCR) to latch, resulting in high current
flowing from the output to the input. Thus, to prevent possible damage to the regulator in any application where
the output may be pulled above the input, an external Schottky diode should be connected between the output
and input. With the anode on output, this Schottky limits the reverse voltage across the output and input pins
to ꢀ0.3 V, preventing the regulator’s internal diode from forward biasing.
Schottky
V
IN
V
OUT
LP2985
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ꢌ ꢎꢕ ꢗ ꢏꢗ ꢔꢕ ꢒꢋ ꢌ ꢍ
SLVS522C − JULY 2004 − REVISED OCTOBER 2004
TYPICAL PERFORMANCE CHARACTERISTICS
= 4.7 ꢀF, V = V +1 V, T = 255 C, ON/OFF Pin Is Tied to V
C
= 1 ꢀ F, C
OUT
IN
IN
OUT(NOM)
A
IN
(unless otherwise specified)
OUTPUT VOLTAGE
DROPOUT VOLTAGE
vs
vs
TEMPERATURE
TEMPERATURE
0.45
0.4
3.345
150 mA
V
= 3.3 V
V = 4.3 V
O
I
C = 10 nF
byp
V
= 3.3 V
O
i
o
C = 1 µF
C
I
3.335
3.325
3.315
3.305
3.295
= 4.7 µF
= 1 mA
0.35
0.3
O
0.25
0.2
50 mA
10 mA
0.15
0.1
0.05
0
1 mA
100 125 150
−50
−25
0
25
50
75
−50 −25
0
25
50
75
100
125 150
Temperature − °C
Temperature − °C
Figure 3
Figure 2
SHORT-CIRCUIT CURRENT
SHORT-CIRCUIT CURRENT
vs
TIME
vs
TIME
0.5
0.5
0.45
0.4
V = 6 V
I
V = 16 V
I
O
V
= 3.3 V
0.45
0.4
O
i
V
= 3.3 V
C = 1 µF
C
C = 1 µF
i
= 0.01 µF
byp
C
= 0.01 µF
byp
0.35
0.3
0.35
0.3
0.25
0.2
0.25
0.2
0.15
0.1
0.15
0.1
0.05
0
0.05
0
−500
−100
0
500
1000
1500
2000
100
300
500
700
Time − ms
Time − ms
Figure 4
Figure 5
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ꢌꢎ ꢕ ꢗ ꢏꢗ ꢔ ꢕ ꢒꢋ ꢌꢍ
SLVS522C − JULY 2004 − REVISED OCTOBER 2004
TYPICAL PERFORMANCE CHARACTERISTICS
= 4.7 ꢀF, V = V +1 V, T = 255 C, ON/OFF Pin Is Tied to V
IN
C
= 1 ꢀ F, C
OUT
IN
IN
OUT(NOM)
A
(unless otherwise specified)
SHORT-CIRCUIT CURRENT
vs
GROUND-PIN CURRENT
vs
OUTPUT VOLTAGE
LOAD CURRENT
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
320
300
V
C
= 3.3 V
O
V
= 3.3 V
O
= 10 nF
byp
280
260
240
220
200
0
0.5
1
1.5
2
2.5
3
3.5
20
40
60
80
100
120
140
160
0
Output Voltage − V
Load Current − mA
Figure 6
Figure 7
RIPPLE REJECTION
vs
RIPPLE REJECTION
vs
FREQUENCY
FREQUENCY
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
V = 3.7 V
V = 5 V
I
I
V
C
C
= 3.3 V
= 10 µF
= 0 nF
V
C
C
= 3.3 V
= 10 µF
O
o
byp
O
o
= 0 nF
byp
50 mA
1 mA
1 mA
50 mA
150 mA
150 mA
10
100
1K
10K
1M
10
100
1K
10K
1M
100K
100K
Frequency − Hz
Frequency − Hz
Figure 9
Figure 8
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ꢌ ꢎꢕ ꢗ ꢏꢗ ꢔꢕ ꢒꢋ ꢌ ꢍ
SLVS522C − JULY 2004 − REVISED OCTOBER 2004
TYPICAL PERFORMANCE CHARACTERISTICS
C
= 1 ꢀ F, C
= 4.7 ꢀF, V = V
+1 V, T = 255 C, ON/OFF Pin Is Tied to V
IN
OUT
IN
OUT(NOM) A IN
(unless otherwise specified)
RIPPLE REJECTION
vs
RIPPLE REJECTION
vs
FREQUENCY
FREQUENCY
100
90
80
70
60
50
40
30
20
10
0
100
V = 5 V
I
V = 5 V
I
V
C
C
= 3.3 V
= 4.7 µF
O
o
90
V
= 3.3 V
O
o
byp
C
C
= 4.7 µF
= 10 nF
= 10 nF
80
70
60
50
40
30
20
10
0
byp
1 mA
10 mA
1 mA
50 mA
100 mA
150 mA
10
100
1K
10K
1M
100K
10
100
1K
10K
100K
1M
Frequency − Hz
Frequency − Hz
Figure 10
Figure 11
OUTPUT IMPEDANCE
vs
OUTPUT IMPEDANCE
vs
FREQUENCY
FREQUENCY
10
10
C = 1 µF
i
C = 1 µF
i
C
V
= 4.7 µF
= 3.3 V
o
C
V
= 10 µF
= 3.3 V
o
O
O
1
1 mA
1
1 mA
10 mA
100 mA
10 mA
100 mA
0.1
0.01
0.1
0.01
0.001
0.001
10
100
1K
10K
100K
1M
10
100
1K
10K
100K
1M
Frequency − Hz
Frequency − Hz
Figure 13
Figure 12
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ꢌꢎ ꢕ ꢗ ꢏꢗ ꢔ ꢕ ꢒꢋ ꢌꢍ
SLVS522C − JULY 2004 − REVISED OCTOBER 2004
TYPICAL PERFORMANCE CHARACTERISTICS
= 4.7 ꢀF, V = V +1 V, T = 255 C, ON/OFF Pin Is Tied to V
IN
C
= 1 ꢀ F, C
OUT
IN
IN
OUT(NOM)
A
(unless otherwise specified)
OUTPUT NOISE DENSITY
OUTPUT NOISE DENSITY
vs
vs
FREQUENCY
FREQUENCY
10
10
I
= 1 mA
LOAD
I
= 150 mA
LOAD
1
1
C
= 100 nF
C
= 100 nF
byp
byp
C
= 1 nF
byp
C
= 1 nF
byp
0.1
0.01
0.1
C
= 10 nF
C
= 10 nF
byp
byp
0.01
0.1
1
10
Frequency − kHz
100
0.1
1
10
100
Frequency − kHz
Figure 14
Figure 15
GROUND-PIN CURRENT
vs
INPUT CURRENT
vs
TEMPERATURE
INPUT VOLTAGE
1400
1.8
V
C
= 3.3 V
V
C
= 3.3 V
O
O
= 10 nF
= 10 nF
byp
1.6
1.4
1.2
1
byp
1200
1000
800
600
400
200
0
R
= 3.3 kΩ
150 mA
L
0.8
0.6
1 mA
0 mA
R
= Open
L
50 mA
10 mA
0.4
0.2
0
0
1
2
3
4
5
6
−50
−25
0
25
50
75
100 125
150
Input Voltage − V
Temperature − °C
Figure 17
Figure 16
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ꢌ ꢎꢕ ꢗ ꢏꢗ ꢔꢕ ꢒꢋ ꢌ ꢍ
SLVS522C − JULY 2004 − REVISED OCTOBER 2004
TYPICAL PERFORMANCE CHARACTERISTICS
= 4.7 ꢀF, V = V +1 V, T = 255 C, ON/OFF Pin Is Tied to V
IN
C
= 1 ꢀ F, C
OUT
IN
IN
OUT(NOM)
A
(unless otherwise specified)
LOAD TRANSIENT RESPONSE
LOAD TRANSIENT RESPONSE
200
3.4
3.38
3.36
3.34
3.32
3.3
200
150
100
50
3.4
150
100
50
3.38
3.36
3.34
3.32
3.3
I
L
I
L
V
C
= 3.3 V
= 10 nF
O
V
C
= 3.3 V
= 10 nF
0
O
0
byp
∆I = 100 mA
byp
∆I = 150 mA
L
L
−50
−50
V
O
V
O
−100
−150
−200
−250
−100
−150
−200
−250
3.28
3.26
3.24
3.22
3.28
3.26
3.24
3.22
20 µs/div"
20 µs/div"
Figure 19
Figure 18
LOAD TRANSIENT RESPONSE
LINE TRANSIENT RESPONSE
3.4
3.38
3.36
3.34
3.32
3.3
200
3.41
5.5
150
100
50
3.39
3.37
3.35
3.33
3.31
3.29
3.27
5
V
I
4.5
I
L
V
= 3.3 V
= 0 nF
byp
= 150 mA
O
V
C
= 3.3 V
= 0 nF
C
I
O
4
0
byp
∆I = 150 mA
O
L
−50
3.5
V
O
−100
−150
−200
−250
3.28
3.26
V
O
3
2.5
3.24
3.22
2
20 µs/div"
20 µs/div"
Figure 20
Figure 21
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄꢅ
ꢆꢅ ꢇꢈꢉ ꢊ ꢀ ꢋꢌꢈꢍ ꢋ ꢎꢏ ꢐ ꢑ ꢀꢋ ꢌꢈꢒꢓ ꢋꢁ ꢋ ꢔꢕ ꢓ ꢐꢖ ꢔꢀ ꢊꢕꢋ ꢓ
ꢌꢎ ꢕ ꢗ ꢏꢗ ꢔ ꢕ ꢒꢋ ꢌꢍ
SLVS522C − JULY 2004 − REVISED OCTOBER 2004
TYPICAL PERFORMANCE CHARACTERISTICS
= 4.7 ꢀF, V = V +1 V, T = 255 C, ON/OFF Pin Is Tied to V
IN
C
= 1 ꢀ F, C
OUT
IN
IN
OUT(NOM)
A
(unless otherwise specified)
LINE TRANSIENT RESPONSE
LINE TRANSIENT RESPONSE
3.41
3.41
3.39
5.5
5
5.5
5
3.39
3.37
V
I
4.5
V
4.5
I
3.37
3.35
V
C
= 3.3 V
= 10 nF
byp
= 150 mA
V
C
= 3.3 V
= 0 nF
byp
O
O
4
4
3.35
3.33
3.31
3.29
3.27
I
O
I
O
= 1 mA
3.5
3.5
3
3.33
3
3.31
3.29
3.27
2.5
2.5
V
O
V
O
2
2
20 µs/div"
20 µs/div"
Figure 22
Figure 23
LINE TRANSIENT RESPONSE
TURN-ON TIME
4
3
2
1
0
10
5.5
3.41
3.39
3.37
V
O
5
8
6
4
2
0
V
IN
4.5
4
3.35
3.33
3.31
V
= 3.3 V
= 10 nF
byp
= 1 mA
O
C
I
3.5
O
V
C
= 3.3 V
= 0
byp
= 150 mA
O
−1
I
O
3
−2
−3
−4
V
O
V
ON/OFF
2.5
2
3.29
3.27
100 µs/div"
100 µs/div"
Figure 25
Figure 24
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅ
ꢆ ꢅ ꢇ ꢈꢉꢊ ꢀ ꢋꢌꢈꢍꢋ ꢎꢏ ꢐꢑ ꢀ ꢋ ꢌꢈꢒꢓꢋ ꢁꢋ ꢔꢕ ꢓꢐ ꢖ ꢔꢀ ꢊꢕꢋ ꢓ
ꢌ ꢎꢕ ꢗ ꢏꢗ ꢔꢕ ꢒꢋ ꢌ ꢍ
SLVS522C − JULY 2004 − REVISED OCTOBER 2004
TYPICAL PERFORMANCE CHARACTERISTICS
C
= 1 ꢀ F, C
= 4.7 ꢀF, V = V
+1 V, T = 255 C, ON/OFF Pin Is Tied to V
IN
OUT
IN
OUT(NOM) A IN
(unless otherwise specified)
TURN-ON TIME
TURN-ON TIME
10
4
3
10
8
4
V
O
V
O
3
8
2
2
1
1
6
4
2
0
6
0
0
V
C
= 3.3 V
O
V
C
= 3.3 V
4
O
−1
−1
−2
−3
−4
= 100 pF
byp
= 1 nF
byp
I
= 150 mA
LOAD
I
= 150 mA
LOAD
V
−2
ON/OFF
V
ON/OFF
2
−3
−4
0
2 ms/div"
200 µs/div"
Figure 27
Figure 26
TURN-ON TIME
4
3
2
10
8
Input
1
0
6
4
2
0
V
C
= 3.3 V
O
−1
= 10 nF
byp
I
= 150 mA
LOAD
Output
−2
−3
−4
20 ms/div"
Figure 28
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄꢅ
ꢆꢅ ꢇꢈꢉ ꢊ ꢀ ꢋꢌꢈꢍ ꢋ ꢎꢏ ꢐ ꢑ ꢀꢋ ꢌꢈꢒꢓ ꢋꢁ ꢋ ꢔꢕ ꢓ ꢐꢖ ꢔꢀ ꢊꢕꢋ ꢓ
ꢌꢎ ꢕ ꢗ ꢏꢗ ꢔ ꢕ ꢒꢋ ꢌꢍ
SLVS522C − JULY 2004 − REVISED OCTOBER 2004
WAFER CHIP SCALE INFORMATION
LP2985x-xxYEQ NanoStar (0.17-mm Bump)
LP2985x-xxYZQ NanoFree (0.17-mm Pb-Free Bump)
987
1,037
1,287
1,337
Pin A1 Index Area
0,19
0,15
0,625 Max
0,15
0,10
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. NanoStar package configuration
D. This package is tin-lead (SnPb); consult the factory for availability of lead-free material.
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅ
ꢆ ꢅ ꢇ ꢈꢉꢊ ꢀ ꢋꢌꢈꢍꢋ ꢎꢏ ꢐꢑ ꢀ ꢋ ꢌꢈꢒꢓꢋ ꢁꢋ ꢔꢕ ꢓꢐ ꢖ ꢔꢀ ꢊꢕꢋ ꢓ
ꢌ ꢎꢕ ꢗ ꢏꢗ ꢔꢕ ꢒꢋ ꢌ ꢍ
SLVS522C − JULY 2004 − REVISED OCTOBER 2004
WAFER CHIP SCALE INFORMATION
LP2985x-xxYEU NanoStar (0.30-mm Bump)
LP2985x-xxYZU NanoFree (0.30-mm Pb-Free Bump)
987
1,037
1,287
1,337
Pin A1 Index Area
0,35
0,25
0,75 Max
0,30
0,20
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. NanoStar package configuration
D. This package is tin-lead (SnPb); consult the factory for availability of lead-free material.
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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