LP2989LV [TI]

Micropower and Low-Noise, 500-mA Ultra Low-Dropout Regulator for Use With Ceramic Output Capacitors;


型号：	LP2989LV
厂家：	TEXAS INSTRUMENTS
描述：	Micropower and Low-Noise, 500-mA Ultra Low-Dropout Regulator for Use With Ceramic Output Capacitors
文件：	总26页 (文件大小：1052K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Sample &

Buy

Support &

Community

Product

Folder

Tools &

Software

Technical

Documents

LP2989LV

SNVS086K –MAY 2000–REVISED JULY 2015

LP2989LV Micropower and Low-Noise, 500-mA Ultra Low-Dropout Regulator for Use With

Ceramic Output Capacitors

1 Features

3 Description

The LP2989LV is a fixed-output 500-mA precision

LDO regulator designed for use with ceramic output

capacitors.

•

2.1-V to 16-V Input Voltage Range

Ultra-Low Dropout Voltage

500-mA Continuous Output Current

Output noise can be reduced to 18 μV (typical) by

connecting an external 10-nF capacitor to the bypass

pin.

Very Low Output Noise With External Capacitor

< 0.8-µA Quiescent Current When Shut Down

Low Ground Pin Current at All Loads

Using an optimized Vertically Integrated PNP (VIP)

0.75% Output Voltage Accuracy (A Grade)

High Peak Current Capability (800-mA typical)

Overtemperature and Overcurrent Protection

−40°C to +125°C Junction Temperature Range

process,

the

LP2989LV

delivers

superior

performance:

Ground Pin Current: Typically 3 mA at 500-mA load,

and 110 µA at 100-µA load.

Sleep Mode: The LP2989LV draws less than 0.8-µA

quiescent current when SHUTDOWN pin is pulled

low.

2 Applications

•

Notebooks and Desktop PCs

PDAs and Palmtop Computers

Wireless Communication Pins

SMPS Post-Regulators

ERROR Flag: The built-in ERROR flag goes low

when the output drops approximately 5% below

nominal.

Precision Output: Output voltage accuracy is 0.75%

(A grade) and 1.25% (standard grade) at room

temperature.

For output voltages greater than or equal to 2 V, see

the LP2989 (SNVS083) data sheet.

Device Information⁽¹⁾

PART NUMBER

PACKAGE

WSON (8)

SOIC (8)

BODY SIZE (NOM)

4.00 mm x 4.00 mm

4.90 mm x 3.91 mm

LP2989LV

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Typical Application

*Capacitance values shown are minimum required to assure stability, but may be increased without limit. Larger

output capacitor provides improved dynamic response. See the Output Capacitor section.

**Shutdown must be actively terminated (see the Shutdown Input Operation section). Tie to IN (pin 4) if not use.

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

LP2989LV

SNVS086K –MAY 2000–REVISED JULY 2015

www.ti.com

Table of Contents

7.4 Device Functional Modes........................................ 10

Application and Implementation ........................ 11

8.1 Application Information............................................ 11

8.2 Typical Application ................................................. 11

Power Supply Recommendations...................... 15

Features.................................................................. 1

Applications ........................................................... 1

Description ............................................................. 1

Revision History..................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 4

6.5 Electrical Characteristics........................................... 5

6.6 Typical Characteristics.............................................. 7

Detailed Description .............................................. 9

7.1 Overview ................................................................... 9

7.2 Functional Block Diagram ......................................... 9

7.3 Feature Description................................................... 9

10 Layout................................................................... 16

10.1 Layout Guidelines ................................................. 16

10.2 Layout Example .................................................... 16

11 Device and Documentation Support ................. 18

11.1 Documentation Support ....................................... 18

11.2 Community Resources.......................................... 18

11.3 Trademarks........................................................... 18

11.4 Electrostatic Discharge Caution............................ 18

11.5 Glossary................................................................ 18

12 Mechanical, Packaging, and Orderable

Information ........................................................... 19

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision J (April 2013) to Revision K

Page

•

Changed "Wide Supply Voltage Range (16V Max)" to "2.1-V to 16-V Input Voltage Range" in Features ........................... 1

Added Handling Rating table, Feature Description section, Device Functional Modes, Application and

Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation

Support section, and Mechanical, Packaging, and Orderable Information section; add updated Thermal Information

values; delete lead temperature from Ab Max (in POA); update pin names to TI nomenclature; removed reference to

VSSOP package option (no longer available for this part number) ...................................................................................... 1

•

Changed caption for Figure 11 .............................................................................................................................................. 8

Changes from Revision I (April 2013) to Revision J

Page

•

Changed Changed layout of National data sheet to TI format ............................................................................................ 15

Submit Documentation Feedback

Product Folder Links: LP2989LV

LP2989LV

www.ti.com

SNVS086K –MAY 2000–REVISED JULY 2015

5 Pin Configuration and Functions

D Package

8-Pin SOIC

Top View

NGN Package

8-Lead WSON

Top View

Pin Functions

I/O

DESCRIPTION

NAME

NUMBER

BYPASS

ERROR

GROUND

INPUT

—

Bypass capacitor input

Error signal output

GND

Regulator power input

DO NOT CONNECT. Device pin 2 is reserved for post packaging test and calibration

of the LP2989LV V_OUTaccuracy. Device pin 2 must be left floating. Do not connect to

any potential. Do not connect to ground. Any attempt to do pin continuity testing on

device pin 2 is discouraged. Continuity test results are variable depending on the

actions of the factory calibration. Aggressive pin continuity testing (high voltage, or

high current) on device pin 2 may activate the trim circuitry forcing V_OUTto move out

of tolerance.

N/C

—

OUTPUT

SENSE

Regulated output voltage

Feedback voltage sense input

Shutdown input

SHUTDOWN

The exposed thermal pad on the bottom of the WSON package must be connected to

a copper thermal pad on the PCB under the package. The use of thermal vias to

remove heat from the package into the PCB is recommended. Connect the thermal

pad to ground potential or leave floating. Do not connect the thermal pad to any

potential other than the same ground potential seen at device pin 3. For additional

information on using TI's Non Pull Back WSON package, see Application Note AN-

1187 Leadless Leadframe Package (LLP) (SNOA401).

Thermal Pad

—

Submit Documentation Feedback

Product Folder Links: LP2989LV

LP2989LV

SNVS086K –MAY 2000–REVISED JULY 2015

www.ti.com

6 Specifications

6.1 Absolute Maximum Ratings

If Military/Aerospace specified devices are required contact the Texas Instruments Sales Office/Distributors for availability and

specifications.⁽¹⁾

MIN

MAX

UNIT

Operating junction temperature

Power dissipation⁽²⁾

–40

125

°C

Internally limited

Input supply voltage, survival

SENSE pin

Output voltage, survival⁽³⁾

–0.3

I_OUT, Survival

Short-circuit protected

Input-output voltage, survival⁽⁴⁾

Storage temperature range, T_stg

–0.3

–65

150

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The maximum allowable power dissipation is a function of the maximum junction temperature, T_J(MAX), the junction-to-ambient thermal

resistance, R_θJA, and the ambient temperature, T_A. The maximum allowable power dissipation at any ambient temperature is calculated

using: P_(MAX)= (T_J(MAX)– T_A) / R_θJA. The value R_θJAfor the WSON (NGN) package is specifically dependent on PCB trace area, trace

material, and the number of layers and thermal vias. For improved thermal resistance and power dissipation for the WSON package,

refer to Application Note AN-1187 Leadless Leadframe Package (LLP) (SNOA401). Exceeding the maximum allowable power

dissipation causes excessive die temperature, and the regulator goes into thermal shutdown.

(3) If used in a dual-supply system where the regulator load is returned to a negative supply, the LP2989LV output must be diode-clamped

to ground.

(4) The output PNP structure contains a diode between the IN and OUT pins that is normally reverse-biased. Forcing the output above the

input turns on this diode and may induce a latch-up mode which can damage the part.

6.2 ESD Ratings

VALUE

UNIT

V_(ESD)

Electrostatic discharge

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

±2000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

MAX

125

UNIT

Operating junction temperature

Operating input supply voltage

–40

2.1

°C

6.4 Thermal Information

LP2989LV

THERMAL METRIC⁽¹⁾

NGN (WSON)

D (SOIC)

UNIT

8 PINS

34.8

28.4

12.0

0.2

8 PINS

114.5

61.1

55.6

9.7

R_θJA

Junction-to-ambient thermal resistance, High-K

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

ψ_JB

12.2

1.3

54.9

n/a

R_θJC(bot)

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

Submit Documentation Feedback

Product Folder Links: LP2989LV

LP2989LV

www.ti.com

SNVS086K –MAY 2000–REVISED JULY 2015

6.5 Electrical Characteristics

Unless otherwise specified: T_J= 25°C, V_IN= V_OUT(NOM)+ 1 V, I_OUT= 1 mA, C_OUT= 4.7 µF, C_IN= 2.2 µF, V_SD= 2 V.

LP2989LVAI-X.X⁽¹⁾

LP2989LVI-X.X⁽¹⁾

PARAMETER

TEST CONDITIONS

UNIT

MIN

TYP

MAX

MIN

TYP

MAX

−0.75

0.75

−1.25

1.25

1 mA < I_OUT< 500 mA,

V_OUT(NOM)+ 1 V ≤ V_IN≤ 16

−1.5

−4

1.5

2.5

−2.5

−5

2.5

3.5

1 mA < I_OUT< 500 mA,

V_OUT(NOM)+ 1 V ≤ V_IN≤ 16

V, –40°C ≤ T_J≤ 125°C

V_OUT

Output voltage tolerance

%V_NOM

1 mA < I_OUT< 500 mA,

V_OUT(NOM)+ 1 V ≤ V_IN≤ 16

V, −25°C ≤ T_J≤ 125°C

−3.5

−4.5

V_OUT(NOM)+ 1 V ≤ V_IN≤ 16

0.005

0.014

0.032

0.005

0.014

0.032

Output voltage line

regulation

ΔV_OUT/ΔV_IN

%/V

V_OUT(NOM)+ 1 V ≤ V_IN≤ 16

V, –40°C ≤ T_J≤ 125°C

0.005

0.4

0.005

0.4

ΔV_OUT/ΔI_OUTLoad regulation

1 mA < I_OUT< 500 mA

%V_NOM

V_OUT= 1.8 V

I_OUT= 100 µA

1.96

Minimum input voltage

required to maintain

output regulation

V_IN

(minimum)

V_OUT= 1.8 V

I_OUT= 250 µA

1.98

V_OUT= 1.8 V

I_OUT= 500 µA

2.11

110

2.11

110

I_OUT= 100 µA

175

200

175

200

µA

I_OUT= 100 µA, –40°C ≤ T_J≤

125°C

I_OUT= 200 mA

I_OUT= 200 mA, –40°C ≤ T_J

≤ 125°C

3.5

I_GND

Ground pin current

I_OUT= 500 mA

I_OUT= 500 mA, –40°C ≤ T_J

≤ 125°C

V_SD< 0.18 V, –40°C ≤ T_J≤

125°C

0.5

V_SD< 0.4 V

0.05

800

0.8

0.05

800

0.8

I_OUT(PK)

Peak output current

Short circuit current

V_OUT≥ V_OUT(NOM)− 5%

600

I_OUT(MAX)

R_L= 0 (Steady State)⁽²⁾

1000

BW = 100 Hz to 100 kHz,

Output noise voltage

(RMS)

e_n

C_OUT= 10 µF, C_BYPASS

.01 µF, V_OUT= 2.5 V

µV_(RMS)

ΔV_OUT/ΔV_IN

ΔV_OUT/ΔT_D

Ripple Rejection

f = 1 kHz, C_OUT= 10 µF

Output voltage

temperature coefficient

See⁽³⁾, –40°C ≤ T_J≤ 125°C

ppm/°C

(1) Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation using

Statistical Quality Control (SQC) methods. The limits are used to calculate TI’s Average Outgoing Quality Level (AOQL).

(2) See Typical Characteristics.

(3) Temperature coefficient is defined as the maximum (worst-case) change divided by the total temperature range.

Submit Documentation Feedback

Product Folder Links: LP2989LV

LP2989LV

SNVS086K –MAY 2000–REVISED JULY 2015

www.ti.com

Electrical Characteristics (continued)

Unless otherwise specified: T_J= 25°C, V_IN= V_OUT(NOM)+ 1 V, I_OUT= 1 mA, C_OUT= 4.7 µF, C_IN= 2.2 µF, V_SD= 2 V.

LP2989LVAI-X.X⁽¹⁾

LP2989LVI-X.X⁽¹⁾

PARAMETER

SHUTDOWN INPUT

TEST CONDITIONS

UNIT

MIN

TYP

MAX

MIN

TYP

MAX

V_H= Output ON

1.4

V_H= Output ON, –40°C ≤ T_J

≤ 125°C

1.6

V_SD

SD Input voltage

SD Input current

V_L= Output OFF

0.5

0.001

0.5

0.001

V_L= Output OFF, I_IN≤ 2 µA,

–40°C ≤ T_J≤ 125°C

0.18

−1

0.18

−1

V_SD= 0

V_SD= 0, –40°C ≤ T_J≤

125°C

I_SD

µA

V_SD= 5 V

V_SD= 5 V, –40°C ≤ T_J≤

125°C

ERROR COMPARATOR

V_OH= 16 V

0.001

I_OH

Output “HIGH” leakage

V_OH= 16 V, –40°C ≤ T_J≤

125°C

V_IN= V_OUT(NOM)− 0.5 V,

I_OUT(COMP)= 150 µA

150

220

350

150

220

350

V_OL

Output “LOW” voltage

Upper threshold voltage

V_IN= V_OUT(NOM)− 0.5 V,

I_OUT(COMP)= 150 µA, –40°C

≤ T_J≤ 125°C

−6

−8.3

−8.9

−13

−4.8

−6.6

−3.5

−2.5

−4.9

−3

−6

−8.3

−8.9

−13

−4.8

−6.6

−3.5

−2.5

−4.9

V_THR(MAX)

%V_OUT

–40°C ≤ T_J≤ 125°C

V_THR(MIN)

HYST

Lower threshold voltage

Hysteresis

−3 %V_OUT

Submit Documentation Feedback

Product Folder Links: LP2989LV

LP2989LV

www.ti.com

SNVS086K –MAY 2000–REVISED JULY 2015

6.6 Typical Characteristics

Unless otherwise specified: T_A= 25°C, C_OUT= 10 µF, C_IN= 2.2 µF, SD is tied to V_IN, V_IN= V_O(NOM)+ 1 V, I_L= 1 mA,

V_OUT= 1.8 V.

Figure 1. I_GNDvs Shutdown

Figure 2. I_GNDvs Shutdown

Figure 3. I_GNDvs Shutdown

Figure 4. I_GNDvs Shutdown

Figure 5. Ground Pin Current vs Load Current

Figure 6. GND Pin Current vs Temperature and Load

Submit Documentation Feedback

Product Folder Links: LP2989LV

LP2989LV

SNVS086K –MAY 2000–REVISED JULY 2015

www.ti.com

Typical Characteristics (continued)

Unless otherwise specified: T_A= 25°C, C_OUT= 10 µF, C_IN= 2.2 µF, SD is tied to V_IN, V_IN= V_O(NOM)+ 1 V, I_L= 1 mA,

V_OUT= 1.8 V.

Figure 7. Short-Circuit Current vs Temperature

Figure 8. Short-Circuit Current

Figure 10. Minimum V_INvs Load Current

Figure 9. Short-Circuit Current

1.81

1.805

1.8

1.795

1.79

-25

20 35 50 65

125

110

-40

-10

TEMPERATURE (^oC)

Figure 11. V_OUTvs Junction Temperature (T_J)

Submit Documentation Feedback

Product Folder Links: LP2989LV

LP2989LV

www.ti.com

SNVS086K –MAY 2000–REVISED JULY 2015

7 Detailed Description

7.1 Overview

The LP2989LV device is a very high-accuracy micro-power voltage regulator with low quiescent current (75 μA

typical) and low dropout voltage (typical 40 mV at light loads and 380 mV at 100 mA). It is ideally suited for use

in battery-powered systems. The LP2989LV block diagram contains several features, including:

•

Very high-accuracy 1.23-V reference

SHUTDOWN input

ERROR flag output

Internal protection circuitry, such as foldback current limit, and thermal shutdown.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 High-Accuracy Output Voltage

With special careful design to minimize all contributions to the output voltage error, the LP2989LV distinguishes

itself as a very high output-voltage-accuracy micropower LDO. This includes a tight initial tolerance (0.75%

typical, A grade), extremely good line regulation (0.005%/V typical), and a very low output-noise voltage

(10 µV_RMStypical), making the device an ideal low-power voltage reference.

7.3.2 Sleep Mode

When pulling SHUTDOWN pin to low levels, the LP2989LV enters shutdown mode, and a very low quiescent

current is consumed. This function is designed for applications which needs a shutdown mode to effectively

enhance battery life cycle.

7.3.3 Error Detection Comparator Output

The LP2989LV generates a logic low output whenever its output falls out of regulation by more than

approximately 5%. Refer to Application and Implementation for more details.

7.3.4 Short Circuit Protection (Current Limit)

The internal current limit circuit is used to protect the LDO against high-load current faults or shorting events. The

LDO is not designed to operate in a steady-state current limit. During a current-limit event, the LDO sources

constant current. Therefore, the output voltage falls when load impedance decreases. Note also that if a current

limit occurs and the resulting output voltage is low, excessive power may be dissipated across the LDO, resulting

in a thermal shutdown of the output. A foldback feature limits the short-circuit current to protect the regulator from

damage under all load conditions. If OUT is forced below 0 V before EN goes high and the load current required

exceeds the foldback current limit, the device may not start correctly.

Submit Documentation Feedback

Product Folder Links: LP2989LV

LP2989LV

SNVS086K –MAY 2000–REVISED JULY 2015

www.ti.com

Feature Description (continued)

7.3.5 Thermal Protection

The device contains a thermal shutdown protection circuit to turn off the output current when excessive heat is

dissipated in the LDO. The thermal time-constant of the semiconductor die is fairly short, and thus the output

cycles on and off at a high rate when thermal shutdown is reached until the power dissipation is reduced. The

internal protection circuitry of the device is designed to protect against thermal overload conditions. The circuitry

is not intended to replace proper heat sinking. Continuously running the device into thermal shutdown degrades

its reliability.

7.4 Device Functional Modes

7.4.1 Operation With 16 V ≥ V_IN> V_OUT(TARGET)+ 1 V

The device operates if the input voltage is equal to, or exceeds V_OUT(TARGET)+ 1 V. At input voltages below the

minimum V_INrequirement, the devices does not operate correctly, and output voltage may not reach target value.

7.4.2 Operation with Shutdown Control

If the voltage on the SHUTDOWN pin is less than 0.18 V, the output is ensured to be OFF. When the voltage on

the SHUTDOWN pin is more than 1.6 V the output is ensured to be ON. Operating with the SHUTDOWN pin

voltage between 0.18 V and 1.6 V is strongly discouraged as the status of the output is not ensured.

7.4.3 Shutdown Input Operation

The LP2989LV is shut off by driving the SHUTDOWN pin low, and turned on by pulling it high. If this feature is

not to be used, the SHUTDOWN must be tied to V_INto keep the regulator output on at all times.

To assure proper operation, the signal source used to drive the Shutdown input must be able to swing above and

below the specified turn-on/turn-off voltage thresholds listed in Electrical Characteristics under V_SD

To prevent mis-operation, the turnon (and turnoff) voltage signals applied to the SHUTDOWN input must have a

slew rate which is ≥ 40 mV/µs.

CAUTION

The regulator output voltage cannot be ensured if a slow-moving AC (or DC) signal is

applied that is in the range between the specified turn-on and turn-off voltages listed

under the electrical specification V_SD(see Electrical Characteristics ).

Submit Documentation Feedback

Product Folder Links: LP2989LV

LP2989LV

www.ti.com

SNVS086K –MAY 2000–REVISED JULY 2015

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The LP2989LV is a linear voltage regulator operating from 2.1 V to 16 V on the input and regulates voltages

between 2.5 V to 5 V with 0.75% accuracy and 500-mA maximum output current. Efficiency is defined by the

ratio of output voltage to input voltage because the LP2989LV is a linear voltage regulator. To achieve high

efficiency, the dropout voltage (V_IN– V_OUT) must be as small as possible, thus requiring a very low dropout LDO.

Successfully implementing an LDO in an application depends on the application requirements. If the

requirements are simply input voltage and output voltage, compliance specifications (such as internal power

dissipation or stability) must be verified to ensure a solid design. If timing, start-up, noise, PSRR, or any other

transient specification is required, the design becomes more challenging.

8.2 Typical Application

*Capacitance values shown are minimum required to assure stability, but may be increased without limit. Larger

output capacitor provides improved dynamic response. See the Output Capacitor section.

**SHUTDOWN must be actively terminated (see the Shutdown Input Operation section). Tie to IN (pin 4) if not use.

Figure 12. Typical Application Schematic

8.2.1 Design Requirements

For typical linear regulator applications, use the parameters in Table 1

Table 1. Design Parameters

DESIGN PARAMETER

Input voltage

DESIGN REQUIREMENT

6.5 V, ±10%,

Output voltage

5 V, ±1%

Output current

500 mA (maximum), 1 mA (minimum)

18 μV_(RMS)typical

RMS noise, 100 Hz to 100 kHz

PSRR at 1 kHz

60 dB typical

Submit Documentation Feedback

Product Folder Links: LP2989LV

LP2989LV

SNVS086K –MAY 2000–REVISED JULY 2015

www.ti.com

8.2.2 Detailed Design Procedure

At 500-mA loading, the dropout of the LP2989LV has 650-mV maximum dropout over temperature, thus an

1500-mV headroom is sufficient for operation over both input and output voltage accuracy. The efficiency of the

LP2989LV in this configuration is V_OUT/ V_IN= 76.9%. To achieve the smallest form factor, the WSON package is

selected. Input and output capacitors are selected in accordance with the capacitor recommendations. Ceramic

capacitances of 2.2 μF for the input and one 4.7-μF capacitor for the output are selected. With an efficiency of

76.9% and a 500-mA maximum load, the internal power dissipation is 750 mW, which corresponds to a 26.1°C

junction temperature rise for the WSON package. With an 85°C maximum ambient temperature, the junction

temperature is at 111.1°C. To minimize noise, a bypass capacitance (C_BYPASS) of 0.01 µF is placed from the

BYPASS pin (device pin 1) to device ground (device pin 3).

8.2.2.1 WSON Package Devices

The LP2989LV is offered in the 8-lead WSON surface mount package to allow for increased power dissipation

compared to the SOIC package. For details on thermal performance as well as mounting and soldering

specifications, refer to Application Note AN-1187 Leadless Leadframe Package (LLP) (SNOA401).

For output voltages ≥ 2 V, see LP2989LV (SNVS083) data sheet.

8.2.2.2 External Capacitors

Like any low-dropout regulator, the LP2989LV requires external capacitors for regulator stability. These

capacitors must be correctly selected for good performance.

8.2.2.2.1 Input Capacitor

An input capacitor whose value is at least 2.2 µF is required between the LP2989LV input and ground (the

amount of capacitance may be increased without limit).

Characterization testing performed on the LP2989LV has shown that if the value of actual input capacitance

drops below about 1.5 µF, an unstable operating condition may result. Therefore, the next larger standard size

(2.2 µF) is specified as the minimum required input capacitance. Capacitor tolerance and temperature variation

must be considered when selecting a capacitor (see Capacitor Characteristics section) to assure the minimum

requirement of 1.5 µF is met over all operating conditions.

The input capacitor must be located at a distance of not more than 0.5 inches from the input pin and returned to

a clean analog ground. Any good quality ceramic or tantalum may be used for this capacitor, assuming the

minimum capacitance requirement is met.

8.2.2.2.2 Output Capacitor

The LP2989LV requires a ceramic output capacitor whose value is at least 10 µF. The actual amount of

capacitance on the output must never drop below about 7 µF or unstable operation may result. For this reason,

capacitance tolerance and temperature characteristics must be considered when selecting an output capacitor.

The LP2989LV is designed specifically to work with ceramic output capacitors, using circuitry which allows the

regulator to be stable across the entire range of output current with an output capacitor whose ESR is as low as

4 mΩ. It may also be possible to use Tantalum or film capacitors at the output, but these are not as attractive for

reasons of size and cost (see Capacitor Characteristics).

The output capacitor must meet the requirement for minimum amount of capacitance and also have an

equivalent series resistance (ESR) value which is within the stable range. Curves are provided which show the

stable ESR range as a function of load current (see Figure 13).

Submit Documentation Feedback

Product Folder Links: LP2989LV

LP2989LV

www.ti.com

SNVS086K –MAY 2000–REVISED JULY 2015

Figure 13. Stable Region for Output Capacitor ESR

NOTE

Important: The output capacitor must maintain its ESR within the stable region over the

full operating temperature range of the application to assure stability.

It is important to remember that capacitor tolerance and variation with temperature must be considered when

selecting an output capacitor so that the minimum required amount of output capacitance is provided over the full

operating temperature range. (See Capacitor Characteristics.)

The output capacitor must be located not more than 0.5 inches from the OUT pin and returned to a clean analog

ground.

8.2.2.2.3 Noise Bypass Capacitor

Connecting a 10-nF capacitor to the BYPASS pin significantly reduces noise on the regulator output. However,

the capacitor is connected directly to a high-impedance circuit in the bandgap reference.

Because this circuit has only a few microamperes flowing in it, any significant loading on this node causes the

regulated output voltage to drop. For this reason, DC leakage current through the noise bypass capacitor must

never exceed 100 nA, and must be kept as low as possible for best output voltage accuracy.

The types of capacitors best suited for the noise bypass capacitor are ceramic and film. High-quality ceramic

capacitors with either NPO or COG dielectric typically have very low leakage. 10-nF polypropolene and

polycarbonate film capacitors are available in small surface-mount packages and typically have extremely low

leakage current.

8.2.2.3 Capacitor Characteristics

8.2.2.3.1 Ceramic

The LP2989LV was designed to work with ceramic capacitors on the output to take advantage of the benefits

they offer: for capacitance values in the 10 µF range, ceramics are the least expensive and also have the lowest

ESR values (which makes them best for eliminating high-frequency noise). The ESR of a typical 10-µF ceramic

capacitor is in the range of 5 mΩ to 10 mΩ, which easily meets the ESR limits required for stability by the

LP2989LV.

One disadvantage of ceramic capacitors is that their capacitance can vary with temperature. Many large-value

ceramic capacitors (≥ 2.2 µF) are manufactured with the Z5U or Y5V temperature characteristic, which results in

the capacitance dropping by more than 50% as the temperature goes from 25°C to 85°C.

This could cause problems if a 10-µF Y5V capacitor were used on the output because it drops down to

approximately 5 µF at high ambient temperatures (which could cause the LP2989LV to oscillate). Another

significant problem with Z5U and Y5V dielectric devices is that the capacitance drops severely with applied

voltage. A typical Z5U or Y5V capacitor can lose 60% of its rated capacitance with half of the rated voltage

applied to it.

For these reasons, X7R and X5R type ceramic capacitors must be used on the input and output of the

LP2989LV.

Submit Documentation Feedback

Product Folder Links: LP2989LV

LP2989LV

SNVS086K –MAY 2000–REVISED JULY 2015

www.ti.com

8.2.2.3.2 Tantalum

Tantalum output capacitors are not recommended for use with the LP2989LV; they are less desirable than

ceramics for use as output capacitors because they are typically more expensive when comparing equivalent

capacitance and voltage ratings in the 1 µF to 10 µF range

Another important consideration is that tantalum capacitors have higher ESR values than equivalent size

ceramics; while it may be possible to find a Tantalum capacitor with an ESR value within the stable range, it

would have to be larger in capacitance (which means bigger and more costly) than a ceramic capacitor with the

same ESR value.

Most 10-µF tantalum capacitors have ESR values higher than 0.5 Ω maximum limit required to make the

LP2989LV stable. Also note that the ESR of a typical tantalum increases about 2:1 as the temperature goes from

25°C down to −40°C, so some guard band must be allowed.

8.2.2.3.3 Film

Polycarbonate and polypropelene film capacitors have excellent electrical performance: their ESR is the lowest of

the three types listed, their capacitance is very stable with temperature, and DC leakage current is extremely low.

One disadvantage is that film capacitors are larger in physical size than ceramic or tantalum which makes film a

poor choice for either input or output capacitors.

However, their low leakage makes them a good choice for the noise bypass capacitor. Because the required

amount of capacitance is only 0.01 µF, small surface-mount film capacitors are available in this size.

8.2.2.4 Reverse Input-Output Voltage

The PNP power transistor used as the pass element in the LP2989LV has an inherent diode connected between

the regulator output and input.

During normal operation (where the input voltage is higher than the output) this diode is reverse-biased.

However, if the output is pulled above the input, this diode turns on, and current flows into the regulator output.

In such cases, a parasitic SCR can latch which allows high current to flow into V_INcan damage the part.

In any application where the output may be pulled above the input, an external Schottky diode must be

connected from V_INto V_OUT(cathode on V_IN, anode on V_OUT), to limit the reverse voltage across the LP2989LV to

0.3 V (see Absolute Maximum Ratings).

8.2.3 Application Curves

Figure 15. Load Transient Response

Figure 14. Line Transient Response

Submit Documentation Feedback

Product Folder Links: LP2989LV

LP2989LV

www.ti.com

SNVS086K –MAY 2000–REVISED JULY 2015

9 Power Supply Recommendations

The LP2989LV is designed to operate from an input voltage supply range from 2.1 V to 16 V. The input voltage

range provides adequate headroom for the device to have a regulated output. This input supply must be well

regulated. If the input supply is noisy, additional input capacitors with low ESR can help improve the output noise

performance.

Submit Documentation Feedback

Product Folder Links: LP2989LV

LP2989LV

SNVS086K –MAY 2000–REVISED JULY 2015

www.ti.com

10 Layout

10.1 Layout Guidelines

For best overall performance, place all circuit components on the same side of the circuit board and as near as

practical to the respective LDO pin connections. Place ground return connections to the input and output

capacitor, and to the LDO ground pin as close to each other as possible, connected by a wide, component-side,

copper surface. The use of vias and long traces to create LDO circuit connections is strongly discouraged and

negatively affects system performance. This grounding and layout scheme minimizes inductive parasitics, and

thereby reduces load-current transients, minimizes noise, and increases circuit stability. A ground reference

plane is also recommended and is either embedded in the PCB itself or located on the bottom side of the PCB

opposite the components. This reference plane serves to assure accuracy of the output voltage, shield noise,

and behaves similarly to a thermal plane to spread (or sink) heat from the LDO device. In most applications, this

ground plane is necessary to meet thermal requirements.

10.2 Layout Example

BYPASS

N/C

SHUTDOWN

ERROR

Error Pullup

Resistor

V_OUT

Ground

GROUND

SENSE

Input

Capacitor

V_OUT

OUT

V_IN

Output

Capacitor

Figure 16. LP2989LV Layout Example

10.2.1 Thermal Considerations

CAUTION

Due to the limited power dissipation characteristics of the available SOIC (D) and

WSON (NGN) packages, all possible combinations of output current (IOUT), input

voltage (VIN), and ambient temperatures (TA) cannot be ensured.

Power dissipation, PD is calculated from the following formula:

P_D= ((V_IN– V_OUT) × I_OUT

)

(1)

The LP2989LV regulator has internal thermal limiting designed to protect the device during overload conditions.

For continuous normal conditions, the recommended maximum operating junction temperature is 125°C. It is

important to give careful consideration to all sources of thermal resistance from junction to ambient. Additional

heat sources mounted nearby must also be considered.

For surface-mount devices, heat sinking is accomplished by using the heat-spreading capabilities of the PC

board and its copper traces. Copper board stiffeners and plated through-holes can also be used to spread the

heat generated by power devices.

Submit Documentation Feedback

Product Folder Links: LP2989LV

LP2989LV

www.ti.com

SNVS086K –MAY 2000–REVISED JULY 2015

Layout Example (continued)

Example: Given an output voltage of 1.8 V, an input voltage range of 4 V to 6 V, a maximum output current of

100 mA, and a maximum ambient temperature of 50°C, what is the maximum operating junction temperature?

The maximum power dissipated by the device (P_D(MAX)) is found using the formula in Equation 2:

P_D(MAX)= ((V_IN(MAX)– V_OUT) × I_OUT(MAX

)

(2)

Using Equation 2, the result is:

P_D(MAX)= ((6 V – 1.8 V) × 100 mA ) = 0.42 W

when

•

I_OUT(MAX) = 100 mA

V_IN(MAX)= 6 V

V_OUT= 1.8 V

Using the 8-pin SOIC (D) package, the LP2989LV junction-to-ambient thermal resistance (R_θJA) has a rating of

114.5°C/W using the standard JEDEC JESD51-7 PCB (High-K) circuit board.

T_RISE= P_D(MAX)× R_θJA

(3)

Thus, The junction temperature rise above ambient (T_RISE) using the formula in Equation 3 is:

T_RISE= 0.42 W × 114.5°C/W = 48.1°C

The junction temperature rise can then be added to the maximum ambient temperature to find the estimated

operating junction temperature (T_J) using the formula in Equation 4:

T_J(MAX)= T_A(MAX)+ T_RISE

(4)

which gives the following results:

T_J(MAX)= 50°C + 48.1°C = 98.1°C

Submit Documentation Feedback

Product Folder Links: LP2989LV

LP2989LV

SNVS086K –MAY 2000–REVISED JULY 2015

www.ti.com

11 Device and Documentation Support

11.1 Documentation Support

11.1.1 Related Documentation

For related documentation see the following:

LP2989 (SNVS083) data sheet

Application Note AN-1187 Leadless Leadframe Package (LLP) (SNOA401).

11.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

11.3 Trademarks

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.4 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

11.5 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

Submit Documentation Feedback

Product Folder Links: LP2989LV

LP2989LV

www.ti.com

SNVS086K –MAY 2000–REVISED JULY 2015

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Submit Documentation Feedback

Product Folder Links: LP2989LV

PACKAGE OPTION ADDENDUM

www.ti.com

16-Oct-2015

PACKAGING INFORMATION

Orderable Device

LP2989AILD-1.8/NOPB

LP2989AILDX-1.8/NOPB

LP2989AIM-1.8

Status Package Type Package Pins Package

Eco Plan

Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(6)

(3)

(4/5)

LIFEBUY

WSON

SOIC

WSON

SOIC

NGN

1000

Green (RoHS

& no Sb/Br)

CU SN

Call TI

CU SN

Call TI

CU SN

Level-3-260C-168 HR

Call TI

-40 to 125

L01EA

LIFEBUY

NRND

NGN

4500

Green (RoHS

& no Sb/Br)

L01EA

TBD

-40 to 125

2989A

IM1.8

LP2989AIM-1.8/NOPB

LP2989AIMX-1.8/NOPB

LP2989ILD-1.8/NOPB

LP2989IM-1.8

ACTIVE

LIFEBUY

NRND

Green (RoHS

& no Sb/Br)

Level-1-260C-UNLIM

Level-3-260C-168 HR

Call TI

2989A

IM1.8

2500

1000

Green (RoHS

& no Sb/Br)

2989A

IM1.8

NGN

Green (RoHS

& no Sb/Br)

L01EA

TBD

2989

IM1.8

LP2989IM-1.8/NOPB

LP2989IMX-1.8/NOPB

ACTIVE

Green (RoHS

& no Sb/Br)

Level-1-260C-UNLIM

2989

IM1.8

2500

Green (RoHS

& no Sb/Br)

2989

IM1.8

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

16-Oct-2015

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

⁽⁶⁾Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

17-Jun-2015

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

LP2989AILD-1.8/NOPB

LP2989AIMX-1.8/NOPB

LP2989ILD-1.8/NOPB

LP2989IMX-1.8/NOPB

WSON

SOIC

NGN

1000

2500

1000

2500

178.0

330.0

178.0

330.0

12.4

4.3

6.5

4.3

6.5

4.3

5.4

4.3

5.4

1.3

2.0

1.3

2.0

8.0

12.0

WSON

SOIC

NGN

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

17-Jun-2015

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

LP2989AILD-1.8/NOPB

LP2989AIMX-1.8/NOPB

LP2989ILD-1.8/NOPB

LP2989IMX-1.8/NOPB

WSON

SOIC

NGN

1000

2500

1000

2500

213.0

367.0

213.0

367.0

191.0

367.0

191.0

367.0

55.0

35.0

55.0

35.0

WSON

SOIC

NGN

Pack Materials-Page 2

MECHANICAL DATA

NGN0008A

LDC08A (Rev B)

www.ti.com

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other

changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest

issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and

complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale

supplied at the time of order acknowledgment.

TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary

to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily

performed.

TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and

applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide

adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or

other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information

published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or

endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the

third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration

and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered

documentation. Information of third parties may be subject to additional restrictions.

Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service

voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.

TI is not responsible or liable for any such statements.

Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements

concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support

that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which

anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause

harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use

of any TI components in safety-critical applications.

In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to

help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and

requirements. Nonetheless, such components are subject to these terms.

No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties

have executed a special agreement specifically governing such use.

Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in

military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components

which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and

regulatory requirements in connection with such use.

TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of

non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.

Products

Applications

Audio

www.ti.com/audio

amplifier.ti.com

dataconverter.ti.com

www.dlp.com

Automotive and Transportation www.ti.com/automotive

Communications and Telecom www.ti.com/communications

Amplifiers

Data Converters

DLP® Products

DSP

Computers and Peripherals

Consumer Electronics

Energy and Lighting

Industrial

www.ti.com/computers

www.ti.com/consumer-apps

www.ti.com/energy

dsp.ti.com

Clocks and Timers

Interface

www.ti.com/clocks

interface.ti.com

logic.ti.com

www.ti.com/industrial

www.ti.com/medical

Medical

Logic

Security

www.ti.com/security

Power Mgmt

Microcontrollers

RFID

power.ti.com

Space, Avionics and Defense

Video and Imaging

www.ti.com/space-avionics-defense

www.ti.com/video

microcontroller.ti.com

www.ti-rfid.com

www.ti.com/omap

OMAP Applications Processors

Wireless Connectivity

TI E2E Community

e2e.ti.com

www.ti.com/wirelessconnectivity

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

LP2989LV [TI]

相关型号：

LP2989LV_15

LP298AIM-2.8

LP298IM-1.8

LP2992

LP2992

LP2992AILD-1.5

LP2992AILD-1.5

LP2992AILD-1.5/NOPB

LP2992AILD-1.5/NOPB

LP2992AILD-1.8

LP2992AILD-1.8

LP2992AILD-1.8/NOPB