LP2997MRX/NOPB [TI]
DDR-II 终止稳压器 | DDA | 8 | 0 to 125;
| 型号： | LP2997MRX/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DDR-II 终止稳压器 | DDA | 8 | 0 to 125 双倍数据速率 光电二极管 接口集成电路 稳压器 |
| 文件： | 总25页 (文件大小：1155K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LP2997
www.ti.com
SNVS295F –MAY 2004–REVISED APRIL 2013
LP2997 DDR-II Termination Regulator
Check for Samples: LP2997
1
FEATURES
DESCRIPTION
The LP2997 linear regulator is designed to meet the
JEDEC SSTL-18 specifications for termination of
DDR-II memory. The device contains a high-speed
operational amplifier to provide excellent response to
load transients. The output stage prevents shoot
through while delivering 500mA continuous current
and transient peaks up to 900mA in the application as
required for DDR-II SDRAM termination. The LP2997
also incorporates a VSENSE pin to provide superior
load regulation and a VREF output as a reference for
the chipset and DIMMs.
2
•
•
•
•
•
•
•
•
Source and Sink Current
Low Output Voltage Offset
No External Resistors Required
Linear Topology
Suspend to Ram (STR) Functionality
Low External Component Count
Thermal Shutdown
Available in SOIC-8, SO PowerPAD-8 Packages
An additional feature found on the LP2997 is an
active low shutdown (SD) pin that provides Suspend
To RAM (STR) functionality. When SD is pulled low
APPLICATIONS
•
•
DDR-II Termination Voltage
SSTL-18 Termination
the VTT output will tri-state providing
a
high
impedance output, but, VREF will remain active. A
power savings advantage can be obtained in this
mode through lower quiescent current.
Typical Application Circuit
LP2997
0.9V
=
VREF
VREF
SD
AV
SD
+
+
CREF
AVIN = 2.5V
IN
V SENSE
VTT
VDDQ
PV
VDDQ = 1.8V
V TT= 0.9V
IN
+
GND
CIN
C OUT
Figure 1. Typical Application Circuit
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2013, Texas Instruments Incorporated
LP2997
SNVS295F –MAY 2004–REVISED APRIL 2013
www.ti.com
Connection Diagram
1
1
2
3
4
8
7
6
5
8
7
6
5
VTT
VTT
GND
GND
SD
2
PVIN
AVIN
VDDQ
PVIN
AVIN
VDDQ
SD
GND
3
VSENSE
VSENSE
VREF
4
VREF
Figure 2. SO PowerPAD-8 Layout
See Package Number DDA (R-PDSO-G8)
Figure 3. SOIC-8 Layout
See Package Number D0008A
PIN DESCRIPTIONS
SOIC-8 Pin or
SO PowerPAD-8 Pin
Name
Function
1
2
3
4
5
6
7
8
GND
SD
Ground
Shutdown
VSENSE
VREF
VDDQ
AVIN
PVIN
VTT
Feedback pin for regulating VTT.
Buffered internal reference voltage of VDDQ/2
Input for internal reference equal to VDDQ/2
Analog input pin
Power input pin
Output voltage for connection to termination resistors
Exposed pad thermal connection Connect to Ground
EP
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)(2)
AVIN to GND
−0.3V to +6V
-0.3V to AVIN
−0.3V to +6V
−65°C to +150°C
150°C
PVIN to GND
VDDQ(3)
Storage Temp. Range
Junction Temperature
Lead Temperature (Soldering, 10 sec)
260°C
SOIC-8 Thermal Resistance (θJA
)
151°C/W
SO PowerPAD-8 Thermal Resistance (θJA
)
43°C/W
Minimum ESD Rating(4)
1kV
(1) Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating range indicates conditions for which
the device is intended to be functional, but does not ensure specific performance limits. For specific specifications and test conditions
see Electrical Characteristics. The specified specifications apply only for the test conditions listed. Some performance characteristics
may degrade when the device is not operated under the listed test conditions.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) VDDQ voltage must be less than 2 x (AVIN - 1) or 6V, whichever is smaller.
(4) The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin.
Operating Range
Junction Temp. Range(1)
0°C to +125°C
2.2V to 5.5V
AVIN to GND
(1) At elevated temperatures, devices must be derated based on thermal resistance. The device in the SOIC-8 package must be derated at
θJA = 151.2° C/W junction to ambient with no heat sink.
2
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SNVS295F –MAY 2004–REVISED APRIL 2013
Electrical Characteristics
Specifications with standard typeface are for TJ = 25°C and limits in boldface type apply over the full Operating
Temperature Range (TJ = 0°C to +125°C)(1). Unless otherwise specified, AVIN = 2.5V, PVIN = 1.8V, VDDQ = 1.8V.
Symbol
Parameter
VREF Voltage
Conditions
Min
Typ
Max
Units
V
VREF
PVIN = VDDQ = 1.7V
PVIN = VDDQ = 1.8V
PVIN = VDDQ = 1.9V
0.837
0.887
0.936
0.860
0.910
0.959
0.887
0.937
0.986
ZVREF
VTT
VREF Output Impedance
VTT Output Voltage
IREF = -30 to +30 μA
2.5
kΩ
IOUT = 0A
PVIN = VDDQ = 1.7V
PVIN = VDDQ = 1.8V
PVIN = VDDQ = 1.9V
IOUT = ±0.5A(2)
0.822
0.874
0.923
0.856
0.908
0.957
0.887
0.939
0.988
V
PVIN = VDDQ = 1.7V
PVIN = VDDQ = 1.8V
PVIN = VDDQ = 1.9V
0.828
0.878
0.928
0.856
0.908
0.957
0.890
0.940
0.990
VosTT/VTT
VTT Output Voltage Offset
IOUT = 0A
IOUT = -0.5A
IOUT = +0.5A
-25
-25
-25
0
0
0
25
25
25
(VREF-VTT
)
mV
IQ
Quiescent Current(3)
IOUT = 0A(3)
320
100
115
500
µA
kΩ
µA
ZVDDQ
ISD
VDDQ Input Impedance
Quiescent Current in
Shutdown(3)
SD = 0V
150
5
IQ_SD
VIH
Shutdown Leakage Current SD = 0V
2
µA
V
Minimum Shutdown High
Level
1.9
VIL
Maximum Shutdown Low
Level
0.8
V
ISENSE
TSD
VSENSE Input Current
13
165
10
nA
Thermal Shutdown
See(4)
Celsius
Celsius
TSD_HYS
Thermal Shutdown
Hysteresis
(1) Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation using
Statistical Quality Control (SQC) methods. The limits are used to calculate Average Outgoing Quality Level (AOQL).
(2) VTT load regulation is tested by using a 10 ms current pulse and measuring VTT
.
(3) Quiescent current defined as the current flow into AVIN.
(4) The maximum allowable power dissipation is a function of the maximum junction temperature, TJ(MAX), the junction to ambient thermal
resistance, θJA, and the ambient temperature, TA. Exceeding the maximum allowable power dissipation will cause excessive die
temperature and the regulator will go into thermal shutdown.
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Typical Performance Characteristics
Iq vs AVIN in SD
Iq vs AVIN
400
350
300
250
200
150
100
50
1050
900
750
600
450
300
150
0
2
2
0
2.5
3
3.5
4
4.5
5
5.5
2
0
2
2.5
3
3.5
4
4.5
5
5.5
AVIN (V)
AVIN (V)
Figure 4.
Figure 5.
VIH and VIL
VREF vs VDDQ
4
3.5
3
3
2.5
2
2.5
2
1.5
1
1.5
1
0.5
0
0.5
2.5
3
3.5
4
4.5
5
5.5
1
2
3
4
5
6
AVIN (V)
VDDQ (V)
Figure 6.
Figure 7.
VTT vs VDDQ
Iq vs AVIN in SD Temperature
3
2.5
2
400
350
300
250
200
150
100
50
0oC
125oC
1.5
1
0.5
0
1
2
3
4
5
6
2.5
3
3.5
4
4.5
5
5.5
VDDQ (V)
AVIN (V)
Figure 8.
Figure 9.
4
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Typical Performance Characteristics (continued)
Maximum Sourcing Current vs AVIN
(VDDQ = 1.8V, PVIN = 1.8V)
Iq vs AVIN Temperature
1050
900
750
600
450
300
150
0
1.4
1.2
1
85oC
25oC
0.8
0.6
0.4
0.2
0
0oC
2
2.5
3
3.5
4
4.5
5
5.5
2
2.5
3
3.5
4
4.5
5
5.5
AVIN (V)
AVIN (V)
Figure 10.
Figure 11.
Maximum Sinking Current vs AVIN
(VDDQ = 1.8V)
2.4
2.2
2
1.8
1.6
1.4
1.2
1
2
2.5
3
3.5
4
4.5
5
5.5
AVIN (V)
Figure 12.
Block Diagram
VDDQ
AVIN
PVIN
SD
50k
50k
-
+
-
VREF
VTT
+
VSENSE
GND
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LP2997
SNVS295F –MAY 2004–REVISED APRIL 2013
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DESCRIPTION
The LP2997 is a linear bus termination regulator designed to meet the JEDEC requirements of SSTL-18. The
output, VTT is capable of sinking and sourcing current while regulating the output voltage equal to VDDQ / 2. The
output stage has been designed to maintain excellent load regulation while preventing shoot through. The
LP2997 also incorporates two distinct power rails that separates the analog circuitry from the power output stage.
This allows a split rail approach to be utilized to decrease internal power dissipation. It also permits the LP2997
to provide a termination solution for the next generation of DDR-SDRAM memory (DDRII).
Pin Descriptions
AVIN AND PVIN AVIN and PVIN are the input supply pins for the LP2997. AVIN is used to supply all the internal control circuitry. PVIN,
however, is used exclusively to provide the rail voltage for the output stage used to create VTT. These pins have the capability to work off
separate supplies, under the condition that AVIN is always greater than or equal to PVIN. For SSTL-18 applications, it is recommended to
connect PVIN to the 1.8V rail used for the memory core and AVIN to a rail within its operating range of 2.2V to 5.5V (typically a 2.5V
supply). PVIN should always be used with either a 1.8V or 2.5V rail. This prevents the thermal limit from tripping because of excessive
internal power dissipation. If the junction temperature exceeds the thermal shutdown than the part will enter a shutdown state identical to
the manual shutdown where VTT is tri-stated and VREF remains active. A lower rail such as 1.5V can be used but it will reduce the maximum
output current, therefore it is not recommended for most termination schemes.
VDDQ VDDQ is the input used to create the internal reference voltage for regulating VTT. The reference voltage is generated from a resistor
divider of two internal 50kΩ resistors. This ensures that VTT will track VDDQ / 2 precisely. The optimal implementation of VDDQ is as a
remote sense. This can be achieved by connecting VDDQ directly to the 1.8V rail at the DIMM instead of PVIN. This ensures that the
reference voltage tracks the DDR memory rails precisely without a large voltage drop from the power lines. For SSTL-18 applications
VDDQ will be a 1.8V signal, which will create a 0.9V termination voltage at VTT (See Electrical Characteristics Table for exact values of VTT
over temperature).
VSENSE The purpose of the sense pin is to provide improved remote load regulation. In most motherboard applications the termination
resistors will connect to VTT in a long plane. If the output voltage was regulated only at the output of the LP2997 then the long trace will
cause a significant IR drop resulting in a termination voltage lower at one end of the bus than the other. The VSENSE pin can be used to
improve this performance, by connecting it to the middle of the bus. This will provide a better distribution across the entire termination bus.
If remote load regulation is not used then the VSENSE pin must still be connected to VTT. Care should be taken when a long VSENSE trace is
implemented in close proximity to the memory. Noise pickup in the VSENSE trace can cause problems with precise regulation of VTT. A small
0.1uF ceramic capacitor placed next to the VSENSE pin can help filter any high frequency signals and preventing errors.
SHUTDOWN The LP2997 contains an active low shutdown pin that can be used for suspend to RAM functionality. In this condition the VTT
output will tri-state while the VREF output remains active providing a constant reference signal for the memory and chipset. During shutdown
VTT should not be exposed to voltages that exceed PVIN. With the shutdown pin asserted low the quiescent current of the LP2997 will drop,
however, VDDQ will always maintain its constant impedance of 100kΩ for generating the internal reference. Therefore, to calculate the total
power loss in shutdown both currents need to be considered. For more information refer to the Thermal Dissipation section. The shutdown
pin also has an internal pull-up current; therefore, to turn the part on the shutdown pin can either be connected to AVIN or left open
VREF VREF provides the buffered output of the internal reference voltage VDDQ / 2. This output should be used to provide the reference
voltage for the Northbridge chipset and memory. Since these inputs are typically an extremely high impedance, there should be little current
drawn from VREF. For improved performance, an output bypass capacitor can be used, located close to the pin, to help with noise. A
ceramic capacitor in the range of 0.1 µF to 0.01 µF is recommended. This output remains active during the shutdown state and thermal
shutdown events for the suspend to RAM functionality.
VTT VTT is the regulated output that is used to terminate the bus resistors. It is capable of sinking and sourcing current while regulating the
output precisely to VDDQ / 2. The LP2997 is designed to handle continuous currents of up to +/- 0.5A with excellent load regulation. If a
transient is expected to last above the maximum continuous current rating for a significant amount of time, then the bulk output capacitor
should be sized large enough to prevent an excessive voltage drop. If the LP2997 is to operate in elevated temperatures for long durations
care should be taken to ensure that the maximum junction temperature is not exceeded. Proper thermal de-rating should always be used.
(Please refer to the Thermal Dissipation section) If the junction temperature exceeds the thermal shutdown point than VTT will tri-state until
the part returns below the temperature hysteresis trip-point
COMPONENT SELECTIONS
INPUT CAPACITOR
The LP2997 does not require a capacitor for input stability, but it is recommended for improved performance
during large load transients to prevent the input rail from dropping. The input capacitor should be located as
close as possible to the PVIN pin. Several recommendations exist dependent on the application required. A
typical value recommended for AL electrolytic capacitors is 22 µF. Ceramic capacitors can also be used. A value
in the range of 10 µF with X5R or better would be an ideal choice. The input capacitance can be reduced if the
LP2997 is placed close to the bulk capacitance from the output of the 1.8V DC-DC converter. For the AVIN pin, a
small 0.1uF ceramic capacitor is sufficient to prevent excessive noise from coupling into the device.
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OUTPUT CAPACITOR
The LP2997 has been designed to be insensitive of output capacitor size or ESR (Equivalent Series Resistance).
This allows the flexibility to use any capacitor desired. The choice for output capacitor will be determined solely
on the application and the requirements for load transient response of VTT. As a general recommendation the
output capacitor should be sized above 100 µF with a low ESR for SSTL applications with DDR-SDRAM. The
value of ESR should be determined by the maximum current spikes expected and the extent at which the output
voltage is allowed to droop. Several capacitor options are available on the market and a few of these are
highlighted below:
AL - It should be noted that many aluminum electrolytics only specify impedance at a frequency of 120 Hz, which
indicates they have poor high frequency performance. Only aluminum electrolytics that have an impedance
specified at a higher frequency (100 kHz) should be used for the LP2997. To improve the ESR several AL
electrolytics can be combined in parallel for an overall reduction. An important note to be aware of is the extent
at which the ESR will change over temperature. Aluminum electrolytic capacitors can have their ESR rapidly
increase at cold temperatures.
Ceramic - Ceramic capacitors typically have a low capacitance, in the range of 10 to 100 µF range, but they have
excellent AC performance for bypassing noise because of very low ESR (typically less than 10 mΩ). However,
some dielectric types do not have good capacitance characteristics as a function of voltage and temperature.
Because of the typically low value of capacitance it is recommended to use ceramic capacitors in parallel with
another capacitor such as an aluminum electrolytic. A dielectric of X5R or better is recommended for all ceramic
capacitors.
Hybrid - Several hybrid capacitors such as OS-CON and SP are available from several manufacturers. These
offer a large capacitance while maintaining a low ESR. These are the best solution when size and performance
are critical, although their cost is typically higher than any other capacitors.
Thermal Dissipation
Since the LP2997 is a linear regulator any current flow from VTT will result in internal power dissipation
generating heat. To prevent damaging the part from exceeding the maximum allowable junction temperature,
care should be taken to derate the part dependent on the maximum expected ambient temperature and power
dissipation. The maximum allowable internal temperature rise (TRmax) can be calculated given the maximum
ambient temperature (TAmax) of the application and the maximum allowable junction temperature (TJmax).
TRmax = TJmax − TAmax
(1)
From this equation, the maximum power dissipation (PDmax) of the part can be calculated:
PDmax = TRmax / θJA
(2)
The θJA of the LP2997 will be dependent on several variables: the package used; the thickness of copper; the
number of vias and the airflow. For instance, the θJA of the SOIC-8 is 163°C/W with the package mounted to a
standard 8x4 2-layer board with 1oz. copper, no airflow, and 0.5W dissipation at room temperature. This value
can be reduced to 151.2°C/W by changing to a 3x4 board with 2 oz. copper that is the JEDEC standard.
Figure 13 shows how the θJA varies with airflow for the two boards mentioned.
180
170
160
150
140
130
120
110
100
90
SOP Board
JEDEC Board
80
0
200
400
600
800
1000
AIRFLOW (Linear Feet per Minute)
Figure 13. θJA vs Airflow (SOIC-8)
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Additional improvements can be made by the judicious use of vias to connect the part and dissipate heat to an
internal ground plane. Using larger traces and more copper on the top side of the board can also help. With
careful layout it is possible to reduce the θJA further than the nominal values shown in Figure 13.
Optimizing the θJA and placing the LP2997 in a section of a board exposed to lower ambient temperature allows
the part to operate with higher power dissipation. The internal power dissipation can be calculated by summing
the three main sources of loss: output current at VTT, either sinking or sourcing, and quiescent current at AVIN
and VDDQ. During the active state (when shutdown is not held low) the total internal power dissipation can be
calculated from the following equations:
PD = PAVIN + PVDDQ + PVTT
(3)
Where,
PAVIN = IAVIN * VAVIN
PVDDQ = VVDDQ * IVDDQ = VVDDQ x RVDDQ
(4)
(5)
2
To calculate the maximum power dissipation at VTT both conditions at VTT need to be examined, sinking and
sourcing current. Although only one equation will add into the total, VTT cannot source and sink current
simultaneously.
PVTT = VVTT x ILOAD (Sinking) or
(6)
(7)
PVTT = ( VPVIN - VVTT) x ILOAD (Sourcing)
The power dissipation of the LP2997 can also be calculated during the shutdown state. During this condition the
output VTT will tri-state, therefore that term in the power equation will disappear as it cannot sink or source any
current (leakage is negligible). The only losses during shutdown will be the reduced quiescent current at AVIN
and the constant impedance that is seen at the VDDQ pin.
PD = PAVIN + PVDDQ
PAVIN = IAVIN x VAVIN
(8)
(9)
2
PVDDQ = VVDDQ * IVDDQ = VVDDQ x RVDDQ
(10)
Typical Application Circuits
Several different application circuits have been shown to illustrate some of the options that are possible in
configuring the LP2997. Graphs of the individual circuit performance can be found in the Typical Performance
Characteristics section in the beginning of the datasheet. These curves illustrate how the maximum output
current is affected by changes in AVIN and PVIN.
Figure 14 shows the recommended circuit configuration for DDR-II applications. The output stage is connected to
the 1.8V rail and the AVIN pin can be connected to either a 2.5V, 3.3V or 5V rail.
This circuit permits termination in a minimum amount of board space and component count. Capacitor selection
can be varied depending on the number of lines terminated and the maximum load transient. However, with
motherboards and other applications where VTT is distributed across a long plane it is advisable to use multiple
bulk capacitors and addition to high frequency decoupling. The bulk output capacitors should be situated at both
ends of the VTT plane for optimal placement. Large aluminum electrolytic capacitors are used for their low ESR
and low cost.
LP2997
VREF = 0.9V
VREF
SD
SD
+
0.01 mF
AVIN
AVIN = 2.5V
VSENSE
VTT
DD
Q
V
PVIN
DD
Q
V
= 1.8V
VTT = 0.9V
+
+
22
mF
0
GND
47 mF
Figure 14. Recommended DDR-II Termination
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PCB Layout Considerations
1. The input capacitor for the power rail should be placed as close as possible to the PVIN pin.
2. VSENSE should be connected to the VTT termination bus at the point where regulation is required. For
motherboard applications an ideal location would be at the center of the termination bus.
3. VDDQ can be connected remotely to the VDDQ rail input at either the DIMM or the Chipset. This provides the
most accurate point for creating the reference voltage.
4. For improved thermal performance excessive top side copper should be used to dissipate heat from the
package. Numerous vias from the ground connection to the internal ground plane will help. Additionally these
can be located underneath the package if manufacturing standards permit.
5. Care should be taken when routing the VSENSE trace to avoid noise pickup from switching I/O signals. A
0.1uF ceramic capacitor located close to the
can also be used to filter any unwanted high frequency
SENSE
signal. This can be an issue especially if long SENSE traces are used.
6. VREF should be bypassed with a 0.01 µF or 0.1 µF ceramic capacitor for improved performance. This
capacitor should be located as close as possible to the VREF pin.
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REVISION HISTORY
Changes from Revision E (April 2013) to Revision F
Page
•
Changed layout of National Data Sheet to TI format ............................................................................................................ 9
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PACKAGE OPTION ADDENDUM
www.ti.com
2-Sep-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
95
95
95
95
(1)
(2)
(3)
(4/5)
(6)
LP2997M
NRND
SOIC
SOIC
D
8
8
8
8
8
8
Non-RoHS
& Green
Call TI
Level-1-235C-UNLIM
Level-1-260C-UNLIM
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-1-260C-UNLIM
0 to 125
0 to 125
0 to 125
0 to 125
0 to 125
0 to 125
L2997
M
LP2997M/NOPB
LP2997MR
ACTIVE
D
RoHS & Green
SN
Call TI
L2997
M
Samples
NRND SO PowerPAD
ACTIVE SO PowerPAD
ACTIVE SO PowerPAD
DDA
DDA
DDA
D
Non-RoHS
& Green
L2997
MR
LP2997MR/NOPB
LP2997MRX/NOPB
LP2997MX/NOPB
RoHS & Green
NIPDAU | SN
NIPDAU | SN
SN
(L2997, LP2997)
MR
Samples
Samples
Samples
2500 RoHS & Green
2500 RoHS & Green
(L2997, LP2997)
MR
ACTIVE
SOIC
L2997
M
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
2-Sep-2022
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Sep-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LP2997MRX/NOPB
LP2997MRX/NOPB
LP2997MX/NOPB
SO
PowerPAD
DDA
DDA
D
8
8
8
2500
2500
2500
330.0
330.0
330.0
12.4
12.5
12.4
6.5
6.4
6.5
5.4
5.2
5.4
2.0
2.1
2.0
8.0
8.0
8.0
12.0
12.0
12.0
Q1
Q1
Q1
SO
PowerPAD
SOIC
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Sep-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LP2997MRX/NOPB
LP2997MRX/NOPB
LP2997MX/NOPB
SO PowerPAD
SO PowerPAD
SOIC
DDA
DDA
D
8
8
8
2500
2500
2500
356.0
340.5
367.0
356.0
338.1
367.0
35.0
20.6
35.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Sep-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
LP2997M
LP2997M
D
SOIC
SOIC
8
8
8
8
8
8
8
8
95
95
95
95
95
95
95
95
495
495
8
8
8
8
8
8
8
8
4064
4064
4064
4064
4064
4064
630
3.05
3.05
3.05
3.05
3.05
3.05
4.32
3.05
D
LP2997M/NOPB
LP2997MR
D
SOIC
495
DDA
DDA
DDA
DDA
DDA
HSOIC
HSOIC
HSOIC
HSOIC
HSOIC
495
LP2997MR
495
LP2997MR/NOPB
LP2997MR/NOPB
LP2997MR/NOPB
495
507.79
495
4064
Pack Materials-Page 3
PACKAGE OUTLINE
DDA0008A
PowerPADTM SOIC - 1.7 mm max height
S
C
A
L
E
2
.
4
0
0
PLASTIC SMALL OUTLINE
C
6.2
5.8
TYP
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
6X 1.27
8
1
2X
5.0
4.8
3.81
NOTE 3
4
5
0.51
8X
0.31
4.0
3.8
1.7 MAX
B
0.25
C A B
NOTE 4
0.25
0.10
TYP
SEE DETAIL A
5
4
EXPOSED
THERMAL PAD
0.25
2.34
2.24
GAGE PLANE
0.15
0.00
0 - 8
1.27
0.40
1
8
DETAIL A
TYPICAL
2.34
2.24
4218825/A 05/2016
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MS-012.
www.ti.com
EXAMPLE BOARD LAYOUT
DDA0008A
PowerPADTM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
(2.95)
NOTE 9
SOLDER MASK
DEFINED PAD
(2.34)
SOLDER MASK
OPENING
SEE DETAILS
8X (1.55)
1
8
8X (0.6)
(2.34)
SOLDER MASK
SYMM
(1.3)
TYP
OPENING
(4.9)
NOTE 9
6X (1.27)
5
4
(R0.05) TYP
METAL COVERED
BY SOLDER MASK
SYMM
(5.4)
(
0.2) TYP
VIA
(1.3) TYP
LAND PATTERN EXAMPLE
SCALE:10X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4218825/A 05/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DDA0008A
PowerPADTM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
(2.34)
BASED ON
0.125 THICK
STENCIL
(R0.05) TYP
8X (1.55)
1
8
8X (0.6)
(2.34)
SYMM
BASED ON
0.125 THICK
STENCIL
6X (1.27)
5
4
METAL COVERED
BY SOLDER MASK
SYMM
(5.4)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
2.62 X 2.62
2.34 X 2.34 (SHOWN)
2.14 X 2.14
0.125
0.150
0.175
1.98 X 1.98
4218825/A 05/2016
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DDA0008D
PowerPADTM SOIC - 1.7 mm max height
S
C
A
L
E
2
.
4
0
0
PLASTIC SMALL OUTLINE
C
6.2
5.8
TYP
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
6X 1.27
8
1
2X
5.0
4.8
3.81
NOTE 3
4
5
0.51
8X
0.31
4.0
3.8
1.7 MAX
B
0.1
C A
B
NOTE 4
0.25
0.10
TYP
SEE DETAIL A
5
4
EXPOSED
THERMAL PAD
0.25
2.287
1.673
GAGE PLANE
0.15
0.00
0 - 8
1.27
0.40
1
8
DETAIL A
TYPICAL
2.287
1.673
4218820/A 12/2022
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MS-012, variation BA.
www.ti.com
EXAMPLE BOARD LAYOUT
DDA0008D
PowerPADTM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
(2.95)
NOTE 9
SOLDER MASK
DEFINED PAD
(2.287)
SOLDER MASK
OPENING
SEE DETAILS
8X (1.55)
1
8
8X (0.6)
(4.9)
NOTE 9
SYMM
(2.287)
(1.3)
SOLDER MASK
TYP
OPENING
6X (1.27)
5
4
(
0.2) TYP
VIA
SYMM
(5.4)
(R0.05) TYP
METAL COVERED
BY SOLDER MASK
(1.3) TYP
LAND PATTERN EXAMPLE
SCALE:10X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4218820/A 12/2022
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
DDA0008D
PowerPADTM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
(2.287)
BASED ON
0.125 THICK
STENCIL
8X (1.55)
(R0.05) TYP
1
8
8X (0.6)
(2.287)
BASED ON
0.127 THICK
STENCIL
SYMM
6X (1.27)
5
4
METAL COVERED
BY SOLDER MASK
SEE TABLE FOR
SYMM
(5.4)
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
2.557 X 2.557
2.287 X 2.287 (SHOWN)
2.088 X 2.088
0.125
0.150
0.175
1.933 X 1.933
4218820/A 12/2022
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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