LP2998QMRE/NOPB [TI]
用于汽车应用的 DDR 终端稳压器 | DDA | 8 | -40 to 125;
| 型号： | LP2998QMRE/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 用于汽车应用的 DDR 终端稳压器 | DDA | 8 | -40 to 125 双倍数据速率 光电二极管 接口集成电路 稳压器 |
| 文件： | 总37页 (文件大小：2390K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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LP2998, LP2998-Q1
SNVS521K –DECEMBER 2007–REVISED AUGUST 2014
LP2998/LP2998-Q1 DDR Termination Regulator
1 Features
3 Description
The LP2998 linear regulator is designed to meet
1
•
AEC-Q100 Test Guidance with the following
results (SO PowerPAD-8):
JEDEC SSTL-2 and JEDEC SSTL-18 specifications
for termination of DDR-SDRAM and DDR2 memory.
The device also supports DDR3 and DDR3L VTT bus
termination with VDDQ min of 1.35 V. The device
contains a high-speed operational amplifier to provide
excellent response to load transients. The output
stage prevents shoot through while delivering 1.5 A
continuous current and transient peaks up to 3 A in
the application as required for DDR-SDRAM
–
–
Device HBM ESD Classification Level H1C
Junction Temperature Range –40°C to 125°C
•
•
•
•
•
•
•
•
1.35 V Minimum VDDQ
Source and Sink Current
Low Output Voltage Offset
No External Resistors Required
Linear Topology
termination. The LP2998 also incorporates
a
VSENSE pin to provide superior load regulation and
a VREF output as a reference for the chipset and
DIMMs.
Suspend to Ram (STR) Functionality
Low External Component Count
Thermal Shutdown
An additional feature found on the LP2998 is an
active low shutdown (SD) pin that provides Suspend
To RAM (STR) functionality. When SD is pulled low
2 Applications
the VTT output will tri-state providing
a
high
•
DDR1, DDR2, DDR3, and DDR3L Termination
Voltage
impedance output, but, VREF will remain active. A
power savings advantage can be obtained in this
mode through lower quiescent current.
•
•
•
•
•
Automotive Infotainment
FPGA
Device Information(1)
Industrial/Medical PC
SSTL-18, SSTL-2, and SSTL-3 Termination
HSTL Termination
PART NUMBER
LP2998
PACKAGE
SO PowerPAD™ (8) 4.89 mm x 3.90 mm
SOIC (8) 4.90 mm x 3.91 mm
SO PowerPAD™ (8) 4.89 mm x 3.90 mm
BODY SIZE (NOM)
LP2998
LP2998-Q1
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
4 Simplified Schematic
LP2998
V
= 0.75V
REF
V
REF
SD
V
SD
+
+
C
REF
V
= 1.5V
= 2.5V
DDQ
DDQ
V
DD
AV
IN
PV
IN
V
SENSE
V
TT
= 0.75V
V
TT
+
GND
C
C
OUT
IN
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LP2998, LP2998-Q1
SNVS521K –DECEMBER 2007–REVISED AUGUST 2014
www.ti.com
Table of Contents
8.2 Functional Block Diagram ...................................... 11
8.3 Feature Description................................................. 11
8.4 Device Functional Modes........................................ 11
Application and Implementation ........................ 13
9.1 Application Information .......................................... 13
9.2 Typical Application .................................................. 15
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Simplified Schematic............................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
6.1 Pin Descriptions ........................................................ 3
Specifications......................................................... 5
7.1 Absolute Maximum Ratings ..................................... 5
7.2 Handling Ratings: LP2998 ........................................ 5
7.3 Handling Ratings: LP2998-Q1 .................................. 5
7.4 Recommended Operating Conditions....................... 5
7.5 Thermal Information.................................................. 5
7.6 Electrical Characteristics........................................... 6
7.7 Typical Characteristics.............................................. 8
Detailed Description ............................................ 11
8.1 Overview ................................................................. 11
9
10 Power Supply Recommendations ..................... 20
11 Layout................................................................... 20
11.1 Layout Guidelines ................................................. 20
11.2 Layout Examples................................................... 21
12 Device and Documentation Support ................. 22
12.1 Related Links ........................................................ 22
12.2 Trademarks........................................................... 22
12.3 Electrostatic Discharge Caution............................ 22
12.4 Glossary................................................................ 22
7
13 Mechanical, Packaging, and Orderable
8
Information ........................................................... 22
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision J (December 2013) to Revision K
Page
•
•
Added DDR3 support throughout datasheet .......................................................................................................................... 1
Changed formatting to match new TI datasheet guidelines; added Device Information and Handling Ratings tables,
Power Supply, Layout Examples, and Device and Documentation Support sections; reformatted Detailed
Description and Application and Implementation sections. ................................................................................................... 1
•
•
Changed Electrical Char table condition statement .............................................................................................................. 6
Changed Electrical Char table condition statement .............................................................................................................. 7
Changes from Revision I (April 2013) to Revision J
Page
•
•
Added AEC-Q100 Test Guidance .......................................................................................................................................... 1
Changed layout of National Data Sheet to TI format ........................................................................................................... 20
2
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Copyright © 2007–2014, Texas Instruments Incorporated
Product Folder Links: LP2998 LP2998-Q1
LP2998, LP2998-Q1
www.ti.com
SNVS521K –DECEMBER 2007–REVISED AUGUST 2014
6 Pin Configuration and Functions
SO PowerPAD
8-LEAD DDA
TOP VIEW
1
2
3
4
8
7
6
5
VTT
GND
PVIN
AVIN
VDDQ
SD
VSENSE
VREF
GND
SOIC
8-LEAD D
TOP VIEW
1
2
3
4
8
7
6
5
VTT
GND
SD
PVIN
AVIN
VDDQ
VSENSE
VREF
Pin Functions
PIN
NUMBER
TYPE
GND
SD
DESCRIPTION
Ground
1
2
3
4
5
6
7
8
Shutdown
VSENSE
VREF
VDDQ
AVIN
PVIN
VTT
Feedback pin for regulating VTT.
Buffered internal reference voltage of VDDQ/2
Input for internal reference equal to VDDQ/2
Analog input pin
Power input pin
Output voltage for connection to termination resistors
Exposed pad thermal connection. Connect to Ground.
EP
6.1 Pin Descriptions
AVIN AND PVIN AVIN and PVIN are the input supply pins for the LP2998. AVIN is used to supply all the internal control circuitry. PVIN,
however, is used exclusively to provide the rail voltage for the output stage used to create VTT. These pins have the
capability to work off separate supplies depending on the application. Higher voltages on PVIN will increase the
maximum continuous output current because of output RDSON limitations at voltages close to VTT. The disadvantage
of high values of PVIN is that the internal power loss will also increase, thermally limiting the design. For SSTL-2
applications, a good compromise would be to connect the AVIN and PVIN directly together at 2.5 V. This eliminates the
need for bypassing the two supply pins separately. The only limitation on input voltage selection is that PVIN must be
equal to or lower than AVIN. It is recommended to connect PVIN to voltage rails equal to or less than 3.3 V to prevent
the thermal limit from tripping because of excessive internal power dissipation. If the junction temperature exceeds the
thermal shutdown than the part will enter a shutdown state identical to the manual shutdown where VTT is tri-stated and
VREF remains active.
VDDQ
VDDQ is the input used to create the internal reference voltage for regulating VTT. The reference voltage is generated
from a resistor divider of two internal 50 kΩ resistors. This ensures that VTT will track VDDQ / 2 precisely. The optimal
implementation of VDDQ is as a remote sense. This can be achieved by connecting VDDQ directly to the 2.5 V rail at
the DIMM instead of AVIN and PVIN. This ensures that the reference voltage tracks the DDR memory rails precisely
without a large voltage drop from the power lines. For SSTL-2 applications VDDQ will be a 2.5 V signal, which will
create a 1.25 V termination voltage at VTT (See Electrical Characteristics Table for exact values of VTT over
temperature).
Copyright © 2007–2014, Texas Instruments Incorporated
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SNVS521K –DECEMBER 2007–REVISED AUGUST 2014
www.ti.com
Pin Descriptions (continued)
The purpose of the sense pin is to provide improved remote load regulation. In most motherboard applications the
termination resistors will connect to VTT in a long plane. If the output voltage was regulated only at the output of the
VSENSE
LP2998 then the long trace will cause a significant IR drop resulting in a termination voltage lower at one end of the bus
than the other. The VSENSE pin can be used to improve this performance, by connecting it to the middle of the bus. This
will provide a better distribution across the entire termination bus. If remote load regulation is not used then the VSENSE
pin must still be connected to VTT. Care should be taken when a long VSENSE trace is implemented in close proximity to
the memory. Noise pickup in the VSENSE trace can cause problems with precise regulation of VTT. A small 0.1 uF
ceramic capacitor placed next to the VSENSE pin can help filter any high frequency signals and preventing errors.
SHUTDOWN
The LP2998 contains an active low shutdown pin that can be used to tri-state VTT. During shutdown VTT should not be
exposed to voltages that exceed AVIN. With the shutdown pin asserted low the quiescent current of the LP2998 will
drop, however, VDDQ will always maintain its constant impedance of 100 kΩ for generating the internal reference.
Therefore, to calculate the total power loss in shutdown both currents need to be considered. For more information refer
to the Thermal Dissipation section. The shutdown pin also has an internal pull-up current, therefore to turn the part on
the shutdown pin can either be connected to AVIN or left open.
VREF
VREF provides the buffered output of the internal reference voltage VDDQ / 2. This output should be used to provide the
reference voltage for the Northbridge chipset and memory. Since these inputs are typically an extremely high
impedance, there should be little current drawn from VREF. For improved performance, an output bypass capacitor can
be used, located close to the pin, to help with noise. A ceramic capacitor in the range of 0.1 µF to 0.01 µF is
recommended. This output remains active during the shutdown state and thermal shutdown events for the suspend to
RAM functionality.
VTT
VTT is the regulated output that is used to terminate the bus resistors. It is capable of sinking and sourcing current while
regulating the output precisely to VDDQ / 2. The LP2998 is designed to handle peak transient currents of up to ± 3 A
with a fast transient response. The maximum continuous current is a function of VIN and can be viewed in the Typical
Characteristics section. If a transient is expected to last above the maximum continuous current rating for a significant
amount of time then the output capacitor should be sized large enough to prevent an excessive voltage drop. Despite
the fact that the LP2998 is designed to handle large transient output currents it is not capable of handling these for long
durations, under all conditions. The reason for this is the standard packages are not able to thermally dissipate the heat
as a result of the internal power loss. If large currents are required for longer durations, then care should be taken to
ensure that the maximum junction temperature is not exceeded. Proper thermal derating should always be used (please
refer to the Thermal Dissipation section). If the junction temperature exceeds the thermal shutdown point than VTT will
tri-state until the part returns below the hysteretic trip-point.
4
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Product Folder Links: LP2998 LP2998-Q1
LP2998, LP2998-Q1
www.ti.com
SNVS521K –DECEMBER 2007–REVISED AUGUST 2014
7 Specifications
7.1 Absolute Maximum Ratings
(1)(2)
over operating free-air temperature range (unless otherwise noted)
MIN
−0.3
–0.3
−0.3
MAX
6
UNIT
V
AVIN to GND
PVIN to GND
VDDQ(3)
AVIN
6
V
V
Junction temperature
Lead temperature (soldering, 10 sec)
150
260
°C
°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(3) VDDQ voltage must be less than 2 x (AVIN - 1) or 6V, whichever is smaller.
7.2 Handling Ratings: LP2998
MIN
MAX
UNIT
Tstg
Storage temperature range
Electrostatic discharge
−65
150
°C
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins(1)
V(ESD)
−1000
1000
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
7.3 Handling Ratings: LP2998-Q1
MIN
MAX
UNIT
Tstg
Storage temperature range
Electrostatic discharge
−65
150
°C
V
V(ESD)
Human body model (HBM), per AEC Q100-002(1)
−1000
1000
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification. The LP2998-Q1 is
rated at AEC-Q100 ESD HBM Classification Level H1C.
7.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
–40
2.2
0
NOM
MAX
125
UNIT
°C
V
Junction temperature(1)
AVIN to GND
5.5
PVIN supply voltage
SD input voltage
AVIN
AVIN
V
0
V
(1) At elevated temperatures, devices must be derated based on thermal resistance.
7.5 Thermal Information
LP2998/LP2998-Q1
SO PowerPAD
8 PINS
LP2998
THERMAL METRIC(1)
SOIC
8 PINS
151
UNIT
RθJA
Junction-to-ambient thermal resistance
43
°C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Copyright © 2007–2014, Texas Instruments Incorporated
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SNVS521K –DECEMBER 2007–REVISED AUGUST 2014
www.ti.com
7.6 Electrical Characteristics
Typical limits tested at TJ = 25°C. Minimum and maximum limits apply over the full operating junction temperature range (TJ =
–40°C to 125°C).(1) Unless otherwise specified, AVIN = PVIN = 2.5 V, VDDQ = 2.5 V.(2)
PARAMETER
TEST CONDITIONS
VIN = VDDQ = 2.3 V
MIN
1.135
1.235
1.335
0.837
0.887
0.936
0.669
0.743
0.793
TYP
1.158
1.258
1.358
0.860
0.910
0.959
0.684
0.758
0.808
2.5
MAX
1.185
1.285
1.385
0.887
0.937
0.986
0.699
0.773
0.823
UNIT
VREF voltage (DDR I)
VIN = VDDQ = 2.5 V
VIN = VDDQ = 2.7 V
PVIN = VDDQ = 1.7 V
PVIN = VDDQ = 1.8 V
PVIN = VDDQ = 1.9 V
PVIN = VDDQ = 1.35V
PVIN = VDDQ = 1.5V
PVIN = VDDQ = 1.6V
IREF = –30 to 30 µA
IOUT = 0 A
VREF
VREF voltage (DDR II)
V
VREF Voltage (DDR III)
VREF Output Impedance
ZVREF
kΩ
VIN = VDDQ = 2.3 V
VIN = VDDQ = 2.5 V
VIN = VDDQ = 2.7 V
IOUT = ±1.5 A
1.120
1.210
1.320
1.159
1.259
1.359
1.190
1.290
1.390
(3)
VTT
VTT Output Voltage (DDR I)
V
VIN = VDDQ = 2.3 V
VIN = VDDQ = 2.5 V
VIN = VDDQ = 2.7 V
IOUT = 0 A, AVIN = 2.5 V
PVIN = VDDQ = 1.7 V
PVIN = VDDQ = 1.8 V
PVIN = VDDQ = 1.9 V
IOUT = ±0.5A, AVIN = 2.5 V
PVIN = VDDQ = 1.7 V
PVIN = VDDQ = 1.8 V
PVIN = VDDQ = 1.9 V
IOUT = 0A, AVIN = 2.5 V
PVIN = VDDQ = 1.35V
PVIN = VDDQ = 1.5 V
PVIN = VDDQ = 1.6 V
1.125
1.225
1.325
1.159
1.259
1.359
1.190
1.290
1.390
0.822
0.874
0.923
0.856
0.908
0.957
0.887
0.939
0.988
(3)
VTT Output Voltage (DDR II)
V
0.820
0.870
0.920
0.856
0.908
0.957
0.890
0.940
0.990
0.656
0.731
0.781
0.677
0.752
0.802
0.698
0.773
0.823
IOUT = 0.2 A, AVIN = 2.5V
PVIN = VDDQ = 1.35V
0.667
0.641
0.740
0.731
0.790
0.781
0.688
0.673
0.763
0.752
0.813
0.802
0.710
0.694
0.786
0.773
0.836
0.823
IOUT = -0.2A, AVIN = 2.5V
PVIN = VDDQ = 1.35V
(3)
VTT Output Voltage (DDR III)
V
IOUT = 0.4 A, AVIN = 2.5 V
PVIN = VDDQ = 1.5 V
IOUT = –0.4 A, AVIN = 2.5 V
PVIN = VDDQ = 1.5 V
IOUT = 0.5 A, AVIN = 2.5 V
PVIN = VDDQ = 1.6 V
IOUT = –0.5 A, AVIN = 2.5 V
PVIN = VDDQ = 1.6 V
(1) Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation using
Statistical Quality Control (SQC) methods. The limits are used to calculate Texas Instruments' Average Outgoing Quality Level (AOQL).
(2) VIN is defined as VIN = AVIN = PVIN.
(3) VTT load regulation is tested by using a 10 ms current pulse and measuring VTT
.
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www.ti.com
SNVS521K –DECEMBER 2007–REVISED AUGUST 2014
Electrical Characteristics (continued)
Typical limits tested at TJ = 25°C. Minimum and maximum limits apply over the full operating junction temperature range (TJ =
–40°C to 125°C).(1) Unless otherwise specified, AVIN = PVIN = 2.5 V, VDDQ = 2.5 V.(2)
PARAMETER
TEST CONDITIONS
IOUT = 0 A
MIN
–30
–30
–30
–30
–30
–30
–30
–30
–30
–30
TYP
0
MAX
30
UNIT
VTT Output Voltage Offset (VREF
–
–
IOUT = –1.5 A
IOUT = 1.5 A
IOUT = 0 A
0
30
(3)
VTT) for DDR I
0
30
0
30
VTT Output Voltage Offset (VREF
IOUT = –0.5 A
IOUT = 0.5 A
IOUT = 0 A
0
30
(3)
VTT) for DDR II
VOSVtt
mV
0
30
0
30
IOUT = ±0.2 A
IOUT = ±0.4 A
IOUT = ±0.5 A
IOUT = 0 A
0
30
VTT Output Voltage Offset (VREF
–
(3)
VTT) for DDR III
0
30
0
30
(4)
IQ
Quiescent Current
320
100
115
2
500
µA
ZVDDQ
VDDQ Input Impedance
kΩ
(4)
ISD
IQ_SD
VIH
Quiescent current in shutdown
Shutdown leakage current
SD = 0 V
SD = 0 V
150
5
µA
V
Minimum Shutdown High Level
Maximum Shutdown Low Level
1.9
VIL
0.8
10
SD = 0 V
VTT = 1.25 V
Iv
VTT leakage current in shutdown
VSENSE Input current
1
µA
nA
ISENSE
TSD
13
165
10
(5)
Thermal Shutdown
°C
TSD_HYS Thermal Shutdown Hysteresis
(4) Quiescent current defined as the current flow into AVIN.
(5) The maximum allowable power dissipation is a function of the maximum junction temperature, TJ(MAX), the junction to ambient thermal
resistance, RθJA, and the ambient temperature, TA. Exceeding the maximum allowable power dissipation will cause excessive die
temperature and the regulator will go into thermal shutdown.
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7.7 Typical Characteristics
Unless otherwise specified AVIN = PVIN = 2.5 V.
400
350
300
250
200
150
100
50
1050
900
750
600
450
300
150
0
2
2
0
2.5
3
3.5
4
4.5
5
5.5
2
2.5
3
3.5
4
4.5
5
5.5
30
6
AVIN (V)
AVIN (V)
Figure 1. IQ vs AVIN In SD
Figure 2. IQ vs AvIN
4
3.5
3
1.40
1.35
1.30
1.25
1.20
1.15
1.10
2.5
2
1.5
1
0.5
2.5
3
3.5
4
4.5
5
5.5
-30
-20
-10
0
10
20
AVIN (V)
IREF (uA)
Figure 3. VIH and VIL
Figure 4. VREF vs IREF
3
2.5
2
3
2.5
2
1.5
1
1.5
1
0.5
0
0.5
0
1
2
3
4
5
6
0
1
2
3
4
5
VDDQ (V)
VDDQ (V)
Figure 5. VREF vs VDDQ
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Figure 6. VTT vs VDDQ
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SNVS521K –DECEMBER 2007–REVISED AUGUST 2014
Typical Characteristics (continued)
Unless otherwise specified AVIN = PVIN = 2.5 V.
400
1050
25oC
350
900
-40°C
300
750
-40oC
600
250
200
150
100
50
85oC
25°C
85°C
125oC
450
125°C
300
150
0
2
2.5
3
3.5
4
4.5
5
5.5
2
2.5
3
3.5
4
4.5
5
5.5
AV (V)
IN
AV (V)
IN
Figure 8. IQ vs AVIN Over Temperature
Figure 7. ISD vs AVIN Over Temperature
1.4
1.8
1.2
1
1.7
1.6
1.5
1.4
1.3
1.2
1.1
0.8
0.6
0.4
0.2
0
2
2.5
3
3.5
4
4.5
5
5.5
2
2.5
3
3.5
4
4.5
5
5.5
AVIN (V)
AVIN (V)
VDDQ = 2.5 V
PVIN = 1.8 V
VDDQ = 2.5 V
PVIN = 2.5 V
Figure 9. Maximum Sourcing Current vs AVIN
Figure 10. Maximum Sourcing Current vs AVIN
3
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
2.8
2.6
2.4
2.2
2
3
3.5
4
4.5
5
5.5
2
2.5
3
3.5
4
4.5
5
5.5
AVIN (V)
AVIN (V)
VDDQ = 2.5 V
PVIN = 3.3 V
VDDQ = 2.5 V
Figure 11. Maximum Sourcing Current vs AVIN
Figure 12. Maximum Sinking Current vs AVIN
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Typical Characteristics (continued)
Unless otherwise specified AVIN = PVIN = 2.5 V.
1.4
2.4
2.2
2
1.2
1
0.8
0.6
0.4
0.2
0
1.8
1.6
1.4
1.2
1
2
2.5
3
3.5
4
4.5
5
5.5
2
2.5
3
3.5
4
4.5
5
5.5
AVIN (V)
AVIN (V)
VDDQ = 1.8 V
PVIN = 1.8 V
VDDQ = 1.8 V
Figure 13. Maximum Sourcing Current vs AVIN
Figure 14. Maximum Sinking Current vs AVIN
3
2.8
2.6
2.4
2.2
2
3
3.5
4
4.5
5
5.5
AVIN (V)
VDDQ = 1.8 V
PVIN = 3.3 V
Figure 15. Maximum Sourcing Current vs AVIN
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8 Detailed Description
8.1 Overview
The LP2998 linear regulator is designed to meet JEDEC SSTL-2 and JEDEC SSTL-18 specifications for
termination of DDR-SDRAM and DDR2 memory. The device also supports DDR3 and DDR3L VTT bus
termination with VDDQ min of 1.35 V. The device contains a high-speed operational amplifier to provide excellent
response to load transients. The output stage prevents shoot through while delivering 1.5 A continuous current
and transient peaks up to 3 A in the application as required for DDR-SDRAM termination.
8.2 Functional Block Diagram
VDDQ
AVIN
PVIN
SD
50k
50k
-
+
-
VREF
VTT
+
VSENSE
GND
8.3 Feature Description
The LP2998 is a linear bus termination regulator designed to meet the JEDEC requirements of SSTL-2 and
SSTL-18. The output, VTT is capable of sinking and sourcing current while regulating the output voltage equal to
VDDQ / 2. The output stage has been designed to maintain excellent load regulation while preventing shoot
through. The LP2998 also incorporates two distinct power rails that separates the analog circuitry from the power
output stage. This allows a split rail approach to be utilized to decrease internal power dissipation. It also permits
the LP2998 to provide a termination solution for DDR3-SDRAM and DDR3L-SDRAM memory.
8.4 Device Functional Modes
The LP2998 can also be used to provide a termination voltage for other logic schemes such as SSTL-3 or HSTL.
Series Stub Termination Logic (SSTL) was created to improve signal integrity of the data transmission across the
memory bus. This termination scheme is essential to prevent data error from signal reflections while transmitting
at high frequencies encountered with DDR-SDRAM. The most common form of termination is Class II single
parallel termination. This involves one RS series resistor from the chipset to the memory and one RT termination
resistor. Typical values for RS and RT are 25 Ω, although these can be changed to scale the current
requirements from the LP2998. This implementation can be seen below in Figure 16.
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Device Functional Modes (continued)
VDD
VTT
RT
MEMORY
RS
CHIPSET
VREF
Figure 16. SSTL-Termination Scheme
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9 Application and Implementation
9.1 Application Information
9.1.1 Input Capacitor
The LP2998 does not require a capacitor for input stability, but it is recommended for improved performance
during large load transients to prevent the input rail from dropping. The input capacitor should be located as
close as possible to the PVIN pin. Several recommendations exist dependent on the application required. A
typical value recommended for AL electrolytic capacitors is 50 µF. Ceramic capacitors can also be used, a value
in the range of 10 µF with X5R or better would be an ideal choice. The input capacitance can be reduced if the
LP2998 is placed close to the bulk capacitance from the output of the 2.5 V DC-DC converter. If the two supply
rails (AVIN and PVIN) are separated then the 47 uF capacitor should be placed as close to possible to the PVIN
rail. An additional 0.1 uF ceramic capacitor can be placed on the AVIN rail to prevent excessive noise from
coupling into the device.
9.1.2 Output Capacitor
The LP2998 has been designed to be insensitive of output capacitor size or ESR (Equivalent Series Resistance).
This allows the flexibility to use any capacitor desired. The choice for output capacitor will be determined solely
on the application and the requirements for load transient response of VTT. As a general recommendation the
output capacitor should be sized above 100 µF with a low ESR for SSTL applications with DDR-SDRAM. The
value of ESR should be determined by the maximum current spikes expected and the extent at which the output
voltage is allowed to droop. Several capacitor options are available on the market and a few of these are
highlighted below:
AL - It should be noted that many aluminum electrolytics only specify impedance at a frequency of 120 Hz, which
indicates they have poor high frequency performance. Only aluminum electrolytics that have an impedance
specified at a higher frequency (between 20 kHz and 100 kHz) should be used for the LP2998. To improve the
ESR several AL electrolytics can be combined in parallel for an overall reduction. An important note to be aware
of is the extent at which the ESR will change over temperature. Aluminum electrolytic capacitors can have their
ESR rapidly increase at cold temperatures.
Ceramic - Ceramic capacitors typically have a low capacitance, in the range of 10 to 100 µF range, but they have
excellent AC performance for bypassing noise because of very low ESR (typically less than 10 mΩ). However,
some dielectric types do not have good capacitance characteristics as a function of voltage and temperature.
Because of the typically low value of capacitance it is recommended to use ceramic capacitors in parallel with
another capacitor such as an aluminum electrolytic. A dielectric of X5R or better is recommended for all ceramic
capacitors.
Hybrid - Several hybrid capacitors such as OS-CON and SP are available from several manufacturers. These
offer a large capacitance while maintaining a low ESR. These are the best solution when size and performance
are critical, although their cost is typically higher than any other capacitor.
9.1.3 Thermal Dissipation
Since the LP2998 is a linear regulator any current flow from VTT will result in internal power dissipation
generating heat. To prevent damaging the part from exceeding the maximum allowable junction temperature,
care should be taken to derate the part dependent on the maximum expected ambient temperature and power
dissipation. The maximum allowable internal temperature rise (TRmax) can be calculated given the maximum
ambient temperature (TAmax) of the application and the maximum allowable junction temperature (TJmax).
TRmax = TJmax − TAmax
(1)
From this equation, the maximum power dissipation (PDmax) of the part can be calculated:
PDmax = TRmax / RθJA
(2)
The RθJA of the LP2998 will be dependent on several variables: the package used; the thickness of copper; the
number of vias and the airflow.
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Application Information (continued)
180
170
160
150
140
130
120
110
100
90
SOP Board
JEDEC Board
80
0
200
400
600
800
1000
AIRFLOW (Linear Feet per Minute)
Figure 17. RθJA vs Airflow (SOIC-8)
Additional improvements can be made by the judicious use of vias to connect the part and dissipate heat to an
internal ground plane. Using larger traces and more copper on the top side of the board can also help. With
careful layout it is possible to reduce the RθJA further than the nominal values shown in Figure 17.
Layout is also extremely critical to maximize the output current with the SO PowerPAD package. By simply
placing vias under the DAP the θJA can be lowered significantly.
Additional improvements in lowering the RθJA can also be achieved with a constant airflow across the package.
Maintaining the same conditions as above and utilizing the 2x2 via array, Figure 18 shows how the RθJA varies
with airflow.
51
50
49
48
47
46
45
0
100
200
300
400
500
600
AIRFLOW (Linear Feet Per Minute)
Figure 18. RΘJA vs Airflow Speed (Jedec Board with 4 Vias)
Optimizing the R
and placing the LP2998 in a section of a board exposed to lower ambient temperature
θJA
allows the part to operate with higher power dissipation. The internal power dissipation can be calculated by
summing the three main sources of loss: output current at VTT, either sinking or sourcing, and quiescent current
at AVIN and VDDQ. During the active state (when shutdown is not held low) the total internal power dissipation
can be calculated from the following equations:
PD = PAVIN + PVDDQ + PVTT
PAVIN = IAVIN * VAVIN
(3)
(4)
(5)
PVDDQ = VVDDQ * IVDDQ = VVDDQ2 x RVDDQ
To calculate the maximum power dissipation at VTT both conditions at VTT need to be examined, sinking, and
sourcing current. Although only one equation will add into the total, VTT cannot source and sink current
simultaneously.
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Application Information (continued)
PVTT = VVTT x ILOAD (Sinking) or
(6)
(7)
PVTT = ( VPVIN - VVTT) x ILOAD (Sourcing)
The power dissipation of the LP2998 can also be calculated during the shutdown state. During this condition the
output VTT will tri-state, therefore that term in the power equation will disappear as it cannot sink or source any
current (leakage is negligible). The only losses during shutdown will be the reduced quiescent current at AVIN
and the constant impedance that is seen at the VDDQ pin.
PD = PAVIN + PVDDQ
(8)
(9)
PAVIN = IAVIN x VAVIN
PVDDQ = VVDDQ * IVDDQ = VVDDQ2 x RVDDQ
(10)
9.2 Typical Application
Several different application circuits are shown below to illustrate some of the options that are possible in
configuring the LP2998. Graphs of the individual circuit performance can be found in the Typical Characteristics
section. These curves illustrate how the maximum output current is affected by changes in AVIN and PVIN.
LP2998
VREF = 0.75V
VREF
SD
SD
+
0.01PF
VDDQ
VDDQ = 1.5V
VSENSE
AVIN
PVIN
VDD = 2.5V
VTT
VTT = 0.75V
+
+
GND
47PF
220PF
Figure 19. Typical Application Circuit
9.2.1 DDR-III Applications
With the separate VDDQ pin and an internal resistor divider it is possible to use the LP2998 in applications
utilizing DDR-III memory. The output stage is connected to the 1.5 V rail and the AVIN pin can be connected to a
2.2 V to 5.5 V rail.
LP2998
VREF = 0.75V
VREF
SD
SD
+
CREF
VDDQ
VDDQ = 1.5V
VSENSE
AVIN
PVIN
AVIN = 2.2V to 5.5V
PVIN = 1.5V
VTT
VTT = 0.75V
+
+
GND
COUT
CIN
Figure 20. Recommended DDR-III Termination
If it is not desirable to use the 1.5 V - 2.5 V rail it is possible to connect the output stage to a 3.3 V rail. Care
should be taken to not exceed the maximum junction temperature as the thermal dissipation increases with lower
VTT output voltages. For this reason it is not recommended to power PVIN off a rail higher than the nominal 3.3
V. The advantage of this configuration is that it has the ability to source and sink a higher maximum continuous
current.
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Typical Application (continued)
9.2.2 DDR-II Applications
With the separate VDDQ pin and an internal resistor divider it is possible to use the LP2998 in applications
utilizing DDR-II memory. Figure 21 and Figure 22 show several implementations of recommended circuits with
output curves displayed in the Typical Characteristics. Figure 21 shows the recommended circuit configuration
for DDR-II applications. The output stage is connected to the 1.8 V rail and the AVIN pin can be connected to
either a 3.3 V or 5 V rail.
LP2998
V
REF
= 0.9V
V
REF
SD
SD
+
+
0.01 PF
AV = 2.5V
IN
AV
IN
V
= 1.8V
V
V
DDQ
DDQ
SENSE
PV
V
TT
= 0.9V
IN
V
TT
+
GND
220 PF
47 PF
Figure 21. Recommended DDR-II Termination
If it is not desirable to use the 1.8 V rail it is possible to connect the output stage to a 3.3 V rail. Care should be
taken to not exceed the maximum junction temperature as the thermal dissipation increases with lower VTT
output voltages. For this reason it is not recommended to power PVIN off a rail higher than the nominal 3.3 V.
The advantage of this configuration is that it has the ability to source and sink a higher maximum continuous
current.
LP2998
V
= 0.9V
V
REF
REF
SD
V
SD
+
+
C
REF
V
= 1.8V
DDQ
DDQ
AV = 3.3V or 5.5V
IN
AV
V
IN
IN
SENSE
PV = 3.3V
IN
PV
V
TT
V
= 0.9V
TT
+
GND
C
C
OUT
IN
Figure 22. DDR-II Termination with Higher Voltage Rails
9.2.3 SSTL-2 Applications
For the majority of applications that implement the SSTL-2 termination scheme it is recommended to connect all
the input rails to the 2.5 V rail. This provides an optimal trade-off between power dissipation and component
count and selection. An example of this circuit can be seen in Figure 23.
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Typical Application (continued)
LP2998
V
= 1.25V
REF
V
SD
V
SD
REF
+
+
C
C
REF
V
= 2.5V
= 2.5V
DDQ
DDQ
AV
V
DD
V
IN
IN
SENSE
V
PV
TT
V
= 1.25V
TT
+
GND
C
IN
OUT
Figure 23. Recommended SSTL-2 Implementation
If power dissipation or efficiency is a major concern then the LP2998 has the ability to operate on split power
rails. The output stage (PVIN) can be operated on a lower rail such as 1.8 V and the analog circuitry (AVIN) can
be connected to a higher rail such as 2.5 V, 3.3 V, or 5 V. This allows the internal power dissipation to be
lowered when sourcing current from VTT. The disadvantage of this circuit is that the maximum continuous current
is reduced because of the lower rail voltage, although it is adequate for all motherboard SSTL-2 applications.
Increasing the output capacitance can also help if periods of large load transients will be encountered.
LP2998
V
REF
= 1.25V
V
SD
REF
SD
+
+
C
REF
V
= 2.5V
V
DDQ
DDQ
AV
AV = 2.2V to 5.5V
IN
V
SENSE
IN
IN
PV = 1.8V
IN
PV
V
TT
= 1.25V
V
TT
+
GND
C
IN
C
OUT
Figure 24. Lower Power Dissipation SSTL-2 Implementation
The third option for SSTL-2 applications in the situation that a 1.8 V rail is not available and it is not desirable to
use 2.5 V, is to connect the LP2998 power rail to 3.3 V. In this situation AVIN will be limited to operation on the
3.3 V or 5 V rail as PVIN can never exceed AVIN. This configuration has the ability to provide the maximum
continuous output current at the downside of higher thermal dissipation. Care should be taken to prevent the
LP2998 from experiencing large current levels which cause the junction temperature to exceed the maximum.
Because of this risk it is not recommended to supply the output stage with a voltage higher than a nominal 3.3 V
rail.
LP2998
V
REF
= 1.25V
V
REF
SD
SD
+
+
C
REF
V
= 2.5V
V
DDQ
DDQ
AV = 3.3V or 5V
IN
AV
IN
V
SENSE
PV = 3.3V
IN
PV
V
TT
= 1.25V
IN
V
TT
+
GND
C
C
IN
OUT
Figure 25. SSTL-2 Implementation with Higher Voltage Rails
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Typical Application (continued)
9.2.4 Level Shifting
If standards other than SSTL-2 are required, such as SSTL-3, it may be necessary to use a different scaling
factor than 0.5 times VDDQ for regulating the output voltage. Several options are available to scale the output to
any voltage required. One method is to level shift the output by using feedback resistors from VTT to the VSENSE
pin. This has been illustrated in Figure 26 and Figure 27. Figure 26 shows how to use two resistors to level shift
VTT above the internal reference voltage of VDDQ/2. To calculate the exact voltage at VTT the following equation
can be used.
VTT = VDDQ/2 ( 1 + R1/R2)
(11)
LP2998
V
DDQ
V
DDQ
V
V
TT
AV
V
TT
DD
IN
IN
R
R
1
2
+
PV
V
SENSE
C
OUT
+
GND
C
IN
Figure 26. Increasing VTT by Level Shifting
Conversely, the R2 resistor can be placed between VSENSE and VDDQ to shift the VTT output lower than the
internal reference voltage of VDDQ/2. The equations relating VTT and the resistors can be seen below:
VTT = VDDQ/2 (1 - R1/R2)
(12)
LP2998
R
R
2
1
V
V
DDQ
DDQ
V
SENSE
V
AV
DD
IN
IN
V
TT
V
TT
PV
+
+
C
OUT
C
GND
IN
Figure 27. Decreasing VTT by Level Shifting
9.2.4.1 Output Capacitor Selection
For applications utilizing the LP2998 to terminate SSTL-2 I/O signals the typical application circuit shown in
Figure 28 can be implemented.
LP2998
V
= 0.9V
V
REF
REF
SD
AV
SD
+
+
C
REF
AV = 2.5V
IN
IN
V
VSENSE
V
= 1.8V
DDQ
DDQ
PV
IN
V
= 0.9V
V
TT
TT
+
GND
C
OUT
C
IN
Figure 28. Typical SSTL-2 Application Circuit
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Typical Application (continued)
This circuit permits termination in a minimum amount of board space and component count. Capacitor selection
can be varied depending on the number of lines terminated and the maximum load transient. However, with
motherboards and other applications where VTT is distributed across a long plane it is advisable to use multiple
bulk capacitors and addition to high frequency decoupling. Figure 29 shown below depicts an example circuit
where 2 bulk output capacitors could be situated at both ends of the VTT plane for optimal placement. Large
aluminum electrolytic capacitors are used for their low ESR and low cost.
LP2998
V
= 1.25V
REF
V
SD
SD
REF
+
0.01 PF
V
V
= 2.5V
DDQ
DDQ
V
DD
= 2.5V
AV
PV
IN
V
SENSE
IN
V
TT
V
TT
= 1.25V
+
+
+
GND
47 PF
330 PF
330 PF
Figure 29. Typical SSTL-2 Application Circuit for Motherboards
In most PC applications an extensive amount of decoupling is required because of the long interconnects
encountered with the DDR-SDRAM DIMMs mounted on modules. As a result bulk aluminum electrolytic
capacitors in the range of 1000 µF are typically used.
9.2.5 HSTL Applications
The LP2998 can be easily adapted for HSTL applications by connecting VDDQ to the 1.5 V rail. This will produce
a VTT and VREF voltage of approximately 0.75 V for the termination resistors. AVIN and PVIN should be
connected to a 2.5 V rail for optimal performance.
LP2998
V
= 0.75V
REF
V
REF
SD
V
SD
+
+
C
REF
V
= 1.5V
DDQ
DDQ
V
DD
= 2.5V
AV
IN
PV
IN
V
SENSE
V
TT
= 0.75V
V
TT
+
GND
C
C
OUT
IN
Figure 30. HSTL Application
9.2.6 QDR Applications
Quad data rate (QDR) applications utilize multiple channels for improved memory performance. However, this
increase in bus lines has the effect of increasing the current levels required for termination. The recommended
approach in terminating multiple channels is to use a dedicated LP2998 for each channel. This simplifies layout
and reduces the internal power dissipation for each regulator. Separate VREF signals can be used for each DIMM
bank from the corresponding regulator with the chipset reference provided by a local resistor divider or one of the
LP2998 signals. Because VREF and VTT are expected to track and the part to part variations are minor, there
should be little difference between the reference signals of each LP2998.
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10 Power Supply Recommendations
There are several recommendations for the LP2998 input power supply. An input capacitor is not required but is
recommended for improved performance during large load transients to prevent the input rail from dropping. The
input capacitor should be located as close as possible to the PVIN pin. Several recommendations exist
dependent on the application required. A typical value recommended for AL electrolytic capacitors is 50 µF.
Ceramic capacitors can also be used, a value in the range of 10 µF with X5R or better would be an ideal choice.
The input capacitance can be reduced if the LP2998 is placed close to the bulk capacitance from the output of
the 2.5 V DC-DC converter. If the two supply rails (AVIN and PVIN) are separated then the 47 uF capacitor
should be placed as close to possible to the PVIN rail. An additional 0.1 uF ceramic capacitor can be placed on
the AVIN rail to prevent excessive noise from coupling into the device.
11 Layout
11.1 Layout Guidelines
1. The input capacitor for the power rail should be placed as close as possible to the PVIN pin.
2. VSENSE should be connected to the VTT termination bus at the point where regulation is required. For
motherboard applications an ideal location would be at the center of the termination bus.
3. VDDQ can be connected remotely to the VDDQ rail input at either the DIMM or the Chipset. This provides the
most accurate point for creating the reference voltage.
4. For improved thermal performance excessive top side copper should be used to dissipate heat from the
package. Numerous vias from the ground connection to the internal ground plane will help. Additionally these
can be located underneath the package if manufacturing standards permit.
5. Care should be taken when routing the VSENSE trace to avoid noise pickup from switching I/O signals. A 0.1
µF ceramic capacitor located close to the
can also be used to filter any unwanted high frequency
SENSE
signal. This can be an issue especially if long SENSE traces are used.
6. VREF should be bypassed with a 0.01 µF or 0.1 µF ceramic capacitor for improved performance. This
capacitor should be located as close as possible to the VREF pin.
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11.2 Layout Examples
Figure 31 and Figure 32 are layout examples for the LP2998/Q1. These examples are taken from the
LP2998EVM.
Figure 31. LP2998EVM SO PowerPAD Layout Example (Front)
Figure 32. LP2998EVM SO PowerPAD Layout Example (Back)
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12 Device and Documentation Support
12.1 Related Links
Table 1 lists quick access links. Categories include technical documents, support and community resources,
tools and software, and quick access to sample or buy.
Table 1. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
SAMPLE & BUY
LP2998
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
LP2998-Q1
12.2 Trademarks
PowerPAD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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23-Jun-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LP2998MA/NOPB
LP2998MAE/NOPB
LP2998MAX/NOPB
LP2998MR/NOPB
LP2998MRE/NOPB
LP2998MRX/NOPB
LP2998QMR/NOPB
LP2998QMRE/NOPB
LP2998QMRX/NOPB
ACTIVE
SOIC
SOIC
SOIC
D
8
8
8
8
8
8
8
8
8
95
RoHS & Green
RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
LP2998
MA
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
ACTIVE
ACTIVE
D
250
SN
LP2998
MA
D
2500 RoHS & Green
SN
LP2998
MA
ACTIVE SO PowerPAD
ACTIVE SO PowerPAD
ACTIVE SO PowerPAD
ACTIVE SO PowerPAD
ACTIVE SO PowerPAD
ACTIVE SO PowerPAD
DDA
DDA
DDA
DDA
DDA
DDA
95
RoHS & Green
RoHS & Green
NIPDAU | SN
NIPDAU | SN
NIPDAU | SN
NIPDAU | SN
NIPDAU | SN
Call TI | SN
LP2998
MR
250
LP2998
MR
2500 RoHS & Green
LP2998
MR
95
RoHS & Green
RoHS & Green
LP2998
Q1MR
250
LP2998
Q1MR
2500 RoHS & Green
LP2998
Q1MR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
23-Jun-2023
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF LP2998, LP2998-Q1 :
Catalog : LP2998
•
Automotive : LP2998-Q1
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Sep-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LP2998MAE/NOPB
LP2998MAX/NOPB
LP2998MRE/NOPB
SOIC
SOIC
D
D
8
8
8
250
2500
250
178.0
330.0
330.0
12.4
12.4
12.5
6.5
6.5
6.4
5.4
5.4
5.2
2.0
2.0
2.1
8.0
8.0
8.0
12.0
12.0
12.0
Q1
Q1
Q1
SO
DDA
PowerPAD
LP2998MRE/NOPB
LP2998MRX/NOPB
LP2998MRX/NOPB
LP2998QMRE/NOPB
LP2998QMRE/NOPB
LP2998QMRX/NOPB
SO
PowerPAD
DDA
DDA
DDA
DDA
DDA
DDA
8
8
8
8
8
8
250
2500
2500
250
178.0
330.0
330.0
330.0
178.0
330.0
12.4
12.4
12.5
12.5
12.4
12.4
6.5
6.5
6.4
6.4
6.5
6.5
5.4
5.4
5.2
5.2
5.4
5.4
2.0
2.0
2.1
2.1
2.0
2.0
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
Q1
Q1
SO
PowerPAD
SO
PowerPAD
SO
PowerPAD
SO
PowerPAD
250
SO
2500
PowerPAD
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Sep-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LP2998MAE/NOPB
LP2998MAX/NOPB
LP2998MRE/NOPB
LP2998MRE/NOPB
LP2998MRX/NOPB
LP2998MRX/NOPB
LP2998QMRE/NOPB
LP2998QMRE/NOPB
LP2998QMRX/NOPB
SOIC
D
8
8
8
8
8
8
8
8
8
250
2500
250
208.0
367.0
340.5
208.0
356.0
340.5
340.5
208.0
356.0
191.0
367.0
338.1
191.0
356.0
338.1
338.1
191.0
356.0
35.0
35.0
20.6
35.0
35.0
20.6
20.6
35.0
35.0
SOIC
D
SO PowerPAD
SO PowerPAD
SO PowerPAD
SO PowerPAD
SO PowerPAD
SO PowerPAD
SO PowerPAD
DDA
DDA
DDA
DDA
DDA
DDA
DDA
250
2500
2500
250
250
2500
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Sep-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
LP2998MA/NOPB
LP2998MR/NOPB
LP2998MR/NOPB
LP2998QMR/NOPB
LP2998QMR/NOPB
D
SOIC
8
8
8
8
8
95
95
95
95
95
495
507.79
495
8
8
8
8
8
4064
630
3.05
4.32
3.05
4.32
3.05
DDA
DDA
DDA
DDA
HSOIC
HSOIC
HSOIC
HSOIC
4064
630
507.79
495
4064
Pack Materials-Page 3
PACKAGE OUTLINE
DDA0008A
PowerPADTM SOIC - 1.7 mm max height
S
C
A
L
E
2
.
4
0
0
PLASTIC SMALL OUTLINE
C
6.2
5.8
TYP
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
6X 1.27
8
1
2X
5.0
4.8
3.81
NOTE 3
4
5
0.51
8X
0.31
4.0
3.8
1.7 MAX
B
0.25
C A B
NOTE 4
0.25
0.10
TYP
SEE DETAIL A
5
4
EXPOSED
THERMAL PAD
0.25
2.34
2.24
GAGE PLANE
0.15
0.00
0 - 8
1.27
0.40
1
8
DETAIL A
TYPICAL
2.34
2.24
4218825/A 05/2016
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MS-012.
www.ti.com
EXAMPLE BOARD LAYOUT
DDA0008A
PowerPADTM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
(2.95)
NOTE 9
SOLDER MASK
DEFINED PAD
(2.34)
SOLDER MASK
OPENING
SEE DETAILS
8X (1.55)
1
8
8X (0.6)
(2.34)
SOLDER MASK
SYMM
(1.3)
TYP
OPENING
(4.9)
NOTE 9
6X (1.27)
5
4
(R0.05) TYP
METAL COVERED
BY SOLDER MASK
SYMM
(5.4)
(
0.2) TYP
VIA
(1.3) TYP
LAND PATTERN EXAMPLE
SCALE:10X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4218825/A 05/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DDA0008A
PowerPADTM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
(2.34)
BASED ON
0.125 THICK
STENCIL
(R0.05) TYP
8X (1.55)
1
8
8X (0.6)
(2.34)
SYMM
BASED ON
0.125 THICK
STENCIL
6X (1.27)
5
4
METAL COVERED
BY SOLDER MASK
SYMM
(5.4)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
2.62 X 2.62
2.34 X 2.34 (SHOWN)
2.14 X 2.14
0.125
0.150
0.175
1.98 X 1.98
4218825/A 05/2016
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DDA0008D
PowerPADTM SOIC - 1.7 mm max height
S
C
A
L
E
2
.
4
0
0
PLASTIC SMALL OUTLINE
C
6.2
5.8
TYP
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
6X 1.27
8
1
2X
5.0
4.8
3.81
NOTE 3
4
5
0.51
8X
0.31
4.0
3.8
1.7 MAX
B
0.1
C A
B
NOTE 4
0.25
0.10
TYP
SEE DETAIL A
5
4
EXPOSED
THERMAL PAD
0.25
2.287
1.673
GAGE PLANE
0.15
0.00
0 - 8
1.27
0.40
1
8
DETAIL A
TYPICAL
2.287
1.673
4218820/A 12/2022
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MS-012, variation BA.
www.ti.com
EXAMPLE BOARD LAYOUT
DDA0008D
PowerPADTM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
(2.95)
NOTE 9
SOLDER MASK
DEFINED PAD
(2.287)
SOLDER MASK
OPENING
SEE DETAILS
8X (1.55)
1
8
8X (0.6)
(4.9)
NOTE 9
SYMM
(2.287)
(1.3)
SOLDER MASK
TYP
OPENING
6X (1.27)
5
4
(
0.2) TYP
VIA
SYMM
(5.4)
(R0.05) TYP
METAL COVERED
BY SOLDER MASK
(1.3) TYP
LAND PATTERN EXAMPLE
SCALE:10X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4218820/A 12/2022
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
DDA0008D
PowerPADTM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
(2.287)
BASED ON
0.125 THICK
STENCIL
8X (1.55)
(R0.05) TYP
1
8
8X (0.6)
(2.287)
BASED ON
0.127 THICK
STENCIL
SYMM
6X (1.27)
5
4
METAL COVERED
BY SOLDER MASK
SEE TABLE FOR
SYMM
(5.4)
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
2.557 X 2.557
2.287 X 2.287 (SHOWN)
2.088 X 2.088
0.125
0.150
0.175
1.933 X 1.933
4218820/A 12/2022
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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