LP3470A [TI]
具有可编程延迟和 1% 复位阈值的超低功耗低电平有效复位 IC;
| 型号： | LP3470A |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有可编程延迟和 1% 复位阈值的超低功耗低电平有效复位 IC |
| 文件： | 总23页 (文件大小：1520K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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LP3470A
ZHCSKC9B –JULY 2019–REVISED NOVEMBER 2019
具有可编程延迟和 1% 复位阈值的 LP3470A 超低功耗电压监控器
1 特性
3 说明
1
•
与 LP3470 引脚对引脚兼容
5 引脚 SOT-23 封装
微功耗电压监控电路 LP3470A 器件设计用于在 1% 的
过热复位阈值内监测电压，与 TI 现有的 LP3470 器件
引脚对引脚兼容。LP3470A 器件提供精确的毫微功耗
电压监控，具有可编程延迟功能。
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漏极开路复位输出
使用外部电容器的可编程复位超时周期
不受 VCC 短时瞬变干扰
当 VCC 电源电压低于复位阈值时，LP3470A 将发出
复位信号。使用外部电容器可调节复位超时周期。
VCC 升至阈值电压以上且加一定迟滞后，在某一间隔
（可通过外部电容器编程）复位保持有效。
±1% 复位阈值精度（典型值）
超低静态电流（0.3µA 典型值）
复位有效低至 VCC = 0.95V
2 应用
有关可用复位阈值电压选项的信息，请参阅机械、封装
和可订购信息。
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关键 µP 和 µC 电源监视
智能仪表
器件信息(1)
计算机
器件型号
LP3470A
封装
SOT-23 (5)
封装尺寸（标称值）
便携式和电池供电类设备
楼宇自动化：楼宇安全系统、视频监控
工厂自动化：现场发送器、位置和接近传感器
电机驱动器
1.60mm × 2.90mm
(1) 要了解所有可用封装，请参阅数据表末尾的“封装选项附录”。
基本工作电路
LP3470A 典型电源电流
0.6
25°C
0.55
-40°C
125°C
IN LDO OUT
0.5
0.45
0.4
VCC
VCC VCC1
Microcontroller
0.35
0.3
RESET
LP3470A
SRT
RESET
0.25
0.2
GND
0.15
0.1
0.05
1
2
3
4
5 6
VCC (V)
7
8
9
10
Iq_v
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNVSBF5
LP3470A
ZHCSKC9B –JULY 2019–REVISED NOVEMBER 2019
www.ti.com.cn
目录
8.3 Feature Description................................................... 9
8.4 Device Functional Modes........................................ 11
Application and Implementation ........................ 12
9.1 Application Information............................................ 12
9.2 Typical Application ................................................. 12
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 4
Specifications......................................................... 5
7.1 Absolute Maximum Ratings ...................................... 5
7.2 ESD Ratings ............................................................ 5
7.3 Recommended Operating Conditions....................... 5
7.4 Thermal Information.................................................. 5
7.5 Electrical Characteristics........................................... 6
7.6 Timing Requirements................................................ 6
7.7 Typical Characteristics ............................................. 7
Detailed Description .............................................. 9
8.1 Overview ................................................................... 9
8.2 Functional Block Diagram ......................................... 9
9
10 Power Supply Recommendations ..................... 14
11 Layout................................................................... 14
11.1 Layout Guidelines ................................................. 14
11.2 Layout Example .................................................... 14
12 器件和文档支持 ..................................................... 15
12.1 接收文档更新通知 ................................................. 15
12.2 支持资源................................................................ 15
12.3 商标....................................................................... 15
12.4 静电放电警告......................................................... 15
12.5 Glossary................................................................ 15
13 机械、封装和可订购信息....................................... 15
8
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision A (October 2019) to Revision B
Page
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已更改 将超低静态电流从 0.35 更改为 0.3 以与“电气特性”表保持一致 .................................................................................. 1
Changed the typical value of ICC in the Electrical Characteristics table from 300 to 0.3 to match with the units of µA......... 6
Changes from Original (July 2019) to Revision A
Page
•
首次公开发布 .......................................................................................................................................................................... 1
2
Copyright © 2019, Texas Instruments Incorporated
LP3470A
www.ti.com.cn
ZHCSKC9B –JULY 2019–REVISED NOVEMBER 2019
5 Device Comparison Table
PART NUMBER
LP3470A263
LP3470A275
LP3470A293
LP3470A308
LP3470A365
LP3470A400
LP3470A438
LP3470A463
VIT- (typ) (VCC RAMPING DOWN)
VIT+ (typ) (VCC RAMPING UP)
2.63 V
2.75 V
2.93 V
3.08 V
3.65 V
4.0 V
2.73 V
2.85 V
3.03 V
3.28 V
3.85 V
4.2 V
4.38 V
4.63 V
4.58 V
4.83 V
Copyright © 2019, Texas Instruments Incorporated
3
LP3470A
ZHCSKC9B –JULY 2019–REVISED NOVEMBER 2019
www.ti.com.cn
6 Pin Configuration and Functions
DBV Package
5-Pin SOT-23
Top View
SOT-23 (5)
DBV (5)
Top View
SRT
GND
VCC1
RESET
1
5
2
3
VCC
4
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
NO.
NAME
Set reset time-out. Connect a capacitor between this pin and ground to select the reset time-out period (tD).
tD = 619 × C1 (CSRT in µF and tD in ms). If no capacitor is connected, leave this pin floating.
1
SRT
I
2
3
4
GND
VCC1
VCC
—
Ground pin.
I
I
Can be connected to VCC or left floating. DO NOT CONNECT TO GND.
Supply voltage, and reset threshold monitor input.
Open-drain, active-low reset output. Connect to an external pullup resistor. RESET changes from high to low
whenever the monitored voltage (VCC) drops below the reset threshold voltage (VIT-). Once VCC exceeds
the reset threshold (VIT-) + hysteresis (VHYS), RESET remains low for the reset time-out period (tD) and then
deasserts to logic high.
5
RESET
O
4
Copyright © 2019, Texas Instruments Incorporated
LP3470A
www.ti.com.cn
ZHCSKC9B –JULY 2019–REVISED NOVEMBER 2019
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range, unless otherwise noted(1)
MIN
–0.3
–0.3
–0.3
MAX
12
UNIT
VCC
Voltage
RESET
12
V
SRT
5.5
Current
RESET
±70
150
150
mA
°C
Operating junction temperature, TJ
Storage, Tstg
–40
–65
Temperature(2)
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) As a result of the low dissipated power in this device, it is assumed that TJ = TA.
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-
001(1)
± 2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification
JESD22-C101(2)
± 750
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
0.95
0
NOM
MAX
10
UNIT
V
VCC
Input supply voltage
VRESET, VRESET
IRESET, IRESET
TJ
RESET pin voltage
10
V
RESET pin current
0
±5
mA
°C
Junction temperature (free air temperature)
–40
125
7.4 Thermal Information
LP3470A
DBV (SOT23-5)
5 PINS
187.5
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
109.2
92.8
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
35.4
ψJB
92.5
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2019, Texas Instruments Incorporated
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ZHCSKC9B –JULY 2019–REVISED NOVEMBER 2019
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7.5 Electrical Characteristics
At 0.95 V ≤ VCC ≤ 10 V, SRT = Open, RESET pull-up resistor (Rpull-up) = 100 kΩ to VCC, output reset load (CLOAD) = 10 pF and
over the operating free-air temperature range – 40°C to 125°C, unless otherwise noted. Typical values are at TJ = 25°C.
PARAMETER
Input supply voltage
TEST CONDITIONS
MIN
0.95
–1.5
175
75
TYP
MAX UNIT
VCC
10
1.5
V
VIT-
Negative-going input threshold accuracy
Hysteresis on VIT- pin
-40°C to 125°C
1
200
100
%
VHYS
VHYS
VIT- = 3.08 V to 4.63 V
VIT- = 2.64 V to 2.93 V
VCC = 0.95 V < VCC < 10 V
225
125
mV
mV
Hysteresis on VIT- pin
(1)
ICC
Supply current into VCC pin
VCC > VIT+
0.3
1
µA
TA = -40°C to 125°C
(2)
RSRT
VPOR
SRT pin internal resistance
350
500
650
950
kΩ
VOL(max) = 0.2 V
IOUT (Sink) = 5.6 uA
Power on Reset Voltage(3)
mV
1.5 V < VCC < 5 V
VCC < VIT-
IOUT(Sink) = 2 mA
Low level output voltage
VOL
200
90
mV
nA
RESET pin in High Impedance,
VCC = VRESET = 5.5 V
VIT+ < VCC
Ilkg(OD) Open-Drain output leakage current
(1) VIT+ = VHYS + VIT-
(2) This parameter is guranteed by design and characterization
(3) VPOR is the minimum VDD voltage level for a controlled output state. VDD slew rate ≤ 100mV/µs
7.6 Timing Requirements
At 0.95 V ≤ VCC ≤ 10 V, SRT = Open, RESET pull-up resistor (Rpull-up) = 100 kΩ to VCC, output reset load (CLOAD) = 10 pF and
over the operating free-air temperature range – 40°C to 125°C, VCC slew rate < 100mV / us, unless otherwise noted. Typical
values are at TJ = 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Propagation detect delay for VCC falling
below VIT-
(1)
tP_HL
VCC = VIT+ to (VIT-) - 10%
15
30
µs
SRT pin = open
VCC = (VIT- -1V) to (VIT+ + 1V)
50
µs
tD
Reset time delay
SRT pin = 10 nF(2)(3)
SRT pin = 1 µF(2)(3)
5% VIT- overdrive(3)(4)
6.2
619
10
ms
ms
µs
tGI_VIT-
Glitch immunity VIT-
(1) tP_HL measured from threhold trip point (VIT-) to VOL
(2) Ideal capacitor
(3) Parameter is guranteed by design.
(4) Overdrive % = [(VCC/ VIT-) - 1] × 100%
6
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LP3470A
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ZHCSKC9B –JULY 2019–REVISED NOVEMBER 2019
7.7 Typical Characteristics
Typical characteristics show the typical performance of the LP3470A device. Test conditions are at TA = TJ = 25°C (unless
otherwise noted).
10
9
8
7
6
5
4
3
2
1
0
0.6
0.55
0.5
25°C
-40°C
125°C
25°C
-40°C
125°C
0.45
0.4
0.35
0.3
0.25
0.2
0.15
0.1
0.05
1
2
3
4
5 6
VCC (V)
7
8
9
10
0
1
2
3
4
5
VCC (V)
6
7
8
9
10
Iq_v
VCC_
图 1. Supply Current vs Supply Voltage
图 2. Output Voltage vs Supply Voltage for LP3470A293
0.34
0.32
0.3
50
45
40
35
30
25
20
15
25°C
-40°C
125°C
0.28
0.26
0.24
0.22
0.2
0.18
0.16
0.14
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
VIT-
VCC (V)
VOL_
图 4. Negative-going Input Threshold VIT- Accuracy vs
图 3. Low Level Output Voltage vs Supply Voltage
Temperature
479
0.6
0.55
0.5
478.5
478
477.5
477
0.45
0.4
476.5
476
0.35
0.3
475.5
475
0.25
0.2
474.5
474
0.15
0.1
473.5
473
0.05
0
472.5
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
RSRT
VITp
图 6. SRT Pin Internal Resistance Overtemperature
图 5. Positive-going Input Threshold VIT+ Accuracy vs
Temperature
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Typical Characteristics (接下页)
Typical characteristics show the typical performance of the LP3470A device. Test conditions are at TA = TJ = 25°C (unless
otherwise noted).
600
500
400
300
200
100
0
5
4.5
4
25°C
-40°C
125°C
25°C
-40°C
125°C
3.5
3
2.5
2
1.5
1
0.5
0.01
0.02 0.03 0.050.07 0.1
0.2 0.3
0.5 0.7
1
1
2
3
4
Capacitor Value (µF)
5
6
7
8 9 10
Capacitor Value (µF)
Dela
Dela
图 7. Reset Time Delay vs Small Capacitor Values
图 8. Reset Time Delay vs Large Capacitor Values
8
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LP3470A
www.ti.com.cn
ZHCSKC9B –JULY 2019–REVISED NOVEMBER 2019
8 Detailed Description
8.1 Overview
The LP3470A micropower voltage supervisory circuit provides a simple solution to monitor the power supplies in
microprocessor and digital systems and provides a reset controlled by the factory-programmed reset threshold
on the VCC supply voltage pin. When the voltage declines below the reset threshold, the reset signal is asserted
and remains asserted for an interval programmed by an external capacitor after VCC has risen above the
threshold voltage. The reset threshold options are 2.63 V, 2.75 V, 2.93 V, 3.08 V, 3.65 V, 4 V, 4.38 V, 4.63 V.
8.2 Functional Block Diagram
VCC1
+
VCC
RESET
LOGIC
TIMER
œ
Reference
RESET
GND
RSRT
SRT
GND
8.3 Feature Description
8.3.1 RESET Time-Out Period
The reset time delay can be set to a minimum value of 50 µs by leaving the SRT pin floating, or a maximum
value of approximately 6.2 seconds by connecting 10 µF delay capacitor. The reset time delay (tD) can be
programmed by connecting a capacitor no larger than 10 µF between SRT pin and GND.
The relationship between external capacitor (CSRT) in Farads at SRT pin and the time delay (tD) in seconds is
given by 公式 1.
tD = -ln (0.29) x RSRT x CSRT + tD (no cap)
(1)
(2)
(3)
公式 1 is simplified to 公式 2 by plugging RSRT and tD(no cap) given in Electrical Characteristics section:
tD = 618937 x CSRT + 50 µs
公式 3 solves for external capacitor value (CSRT) in units of Farads where tD is in units of seconds
CSRT = (tD- 50 µs) ÷ 618937
The reset delay varies according to three variables: the external capacitor variance (CSRT), SRT pin internal
resistance (RSRT) provided in the Electrical Characteristics table, and a constant. The minimum and maximum
variance due to the constant is shown in Equation 5 and Equation 6.
tD (minimum) = -ln (0.36) x RSRT (min) x CSRT (min) + tD (no cap, min)
tD (maximum) = -ln (0.26) x RSRT (max) x CSRT (max) + tD (no cap, max)
(4)
(5)
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Feature Description (接下页)
The recommended maximum delay capacitor for the LP3470A is limited to 10 µF as this ensures there is enough
time for the capacitor to fully discharge when the reset condition occurs. When a voltage fault occurs, the
previously charged up capacitor discharges, and if the monitored voltage returns from the fault condition before
the delay capacitor discharges completely, the delay capacitor will begin charging from a voltage above zero and
the reset delay will be shorter than expected. Larger delay capacitors can be used so long as the capacitor has
enough time to fully discharge during the duration of the voltage fault.
8.3.2 RESET Output
In applications like microprocessor (µP) systems, errors might occur in system operation during power up, power
down, or brownout conditions. It is imperative to monitor the power supply voltage to prevent these errors from
occurring.
The LP3470A asserts a reset signal whenever the VCC supply voltage is below a threshold (VIT-) voltage.
RESET is ensured to be a logic low for VCC > 0.95 V. Once VCC exceeds the reset threshold plus a hysteresis
voltage, the reset is kept asserted for a time period (tD) programmed by an external capacitor (CSRT); after this
interval RESET goes to logic high. If a brownout condition occurs (monitored voltage falls below the reset
threshold), RESET goes low. When VCC returns above the reset threshold plus a hysteresis voltage, RESET
remains low for a time period tD before going to logic high. 图 9 shows this behavior.
VIT+
VIT-
VHYS
VCC
VCCmin
VCC(0v)
tD
tD
tP_HL
VOH
RESET
VOL
图 9. RESET Output Timing Diagram
8.3.3 Pull-up Resistor Selection
The RESET output structure of the LP3470A is an open-drain N-channel MOSFET switch. A pull-up resistor
(Rpull-up) must be connected to VCC to keep the output logic high when RESET is not asserted.
Connect the pull-up resistor to the desired pull-up voltage source and RESET can be pulled up to any voltage up
to 10 V independent of the VCC voltage. To ensure proper voltage levels, give some consideration when
choosing the pull-up resistor values. Rpull-up must be large enough to limit the current through the output within
the recommended operating conditions. The pull-up resistor value determines the actual VOL, the output
capacitive loading, and the output leakage current (ILKG(OD)). A typical pull-up resistor value of 20 kΩ is sufficient
in most applications.
8.3.4 VCC Transient Immunity
The LP3470A is immune to quick voltage transients or excursions on VCC. Sensitivity to transients depends on
both pulse duration and overdrive. Overdrive is defined by how much VCC deviates from the specified threshold.
Threshold overdrive is calculated as a percent of the threshold in question, as shown in 公式 6. A 0.1-µF bypass
capacitor mounted close to VCC provides additional transient immunity.
Overdrive = | (VCC / VIT- – 1) × 100% |
(6)
10
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Feature Description (接下页)
VCC
VIT+
VIT-
VHYS
Overdrive
Pulse
Duration
图 10. Overdrive vs Pulse Duration
8.4 Device Functional Modes
8.4.1 RESET Output Low
When the VCC supply voltage is below the reset threshold (VIT-), the RESET pin will output logic low. RESET is
ensured to be a logic low for VCC > 0.95 V.
8.4.2 RESET Output High
When the VCC supply voltage exceeds the reset threshold (VIT-) plus the hysteresis voltage (VHYS), the RESET
remains asserted for a time period (tD) programmed by an external capacitor (CSRT); after this interval RESET
goes to logic high.
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9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The LP3470A is a micropower CMOS voltage supervisor that is ideal for use in battery-powered microprocessor
and other digital systems. It is small in size and provides voltage monitoring and supervisory functions with nano-
Iq and programmable delay, making it a good solution in a variety of applications. The LP3470A is available in
six standard reset threshold voltage options, and the reset time-out period is adjustable using an external
capacitor providing maximum flexibility in any application. This device can ensure system reliability and ensures
that a connected microprocessor will operate only when a minimum voltage supply is satisfied.
9.2 Typical Application
The LP3470A can be used as a simple supervisor circuit to monitor the input supply to a microprocessor as
shown in 图 11.
IN LDO OUT
VCC
VCC VCC1
Microcontroller
RESET
LP3470A
SRT
RESET
GND
图 11. Power-On Reset Circuit
9.2.1 Design Requirements
For this design example, use the parameters listed in 表 1 as the input parameters.
表 1. Design Parameters
DESIGN PARAMETER
Input supply voltage
EXAMPLE VALUE
0.95 to 10 V
Reset threshold voltage
2.63 V, 2.75 V, 2.93 V, 3.08 V, 3.65 V, 4 V, 4.38 V, 4.63 V
External pullup resistor
0.68 to 68 kΩ
CSRT = 1 nF
619 µs
External reset time-out period capacitor
Reset time-out period
9.2.2 Detailed Design Procedure
The minimum application circuit requires the LP3470A Power-On Reset Circuit IC and a pullup resistor
connecting the reset pin to VCC. The reset delay can be programmed with an additional capacitor connected
from the SRT pin to GND. See RESET Time-Out Period and Pull-up Resistor Selection for information on
choosing specific values for components.
12
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ZHCSKC9B –JULY 2019–REVISED NOVEMBER 2019
9.2.3 Application Curves
Two capacitor values for CSRT (0.1 µF and 1 µF) are used as examples to show the programmability of the
output time delay as shown in 图 12 and 图 13.
VDD
VDD
Reset Delay (tD) = 5.8 ms
Reset Delay (tD)= 654 ms
RESET
RESET
图 12. Reset Delay Time with 0.1-µF Capacitor at SRT
图 13. Reset Delay Time with 1-µF Capacitor at SRT
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13
LP3470A
ZHCSKC9B –JULY 2019–REVISED NOVEMBER 2019
www.ti.com.cn
10 Power Supply Recommendations
The input of the LP3470A is designed to handle up to the supply voltage absolute maximum rating of 12 V. If the
input supply is susceptible to any large transients above the maximum rating, then take extra precautions. An
input capacitor is optional but not required to help avoid false reset output triggers due to noise.
11 Layout
11.1 Layout Guidelines
•
Good analog design practice recommends placing a minimum of 0.1-µF ceramic capacitor as near as
possible to the VCC pin.
•
•
Place components as close as possible to the IC
Keep traces short between the IC and the CSRT capacitor to ensure the timing delay is as accurate as
possible.
•
For VCC slew rate > 100 mV/µs, increase input capacitance and pull-up resistor value
11.2 Layout Example
图 14 shows a layout example.
图 14. LP3470A Layout Example
14
版权 © 2019, Texas Instruments Incorporated
LP3470A
www.ti.com.cn
ZHCSKC9B –JULY 2019–REVISED NOVEMBER 2019
12 器件和文档支持
12.1 接收文档更新通知
要接收文档更新通知，请导航至 ti.com. 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产品
信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.2 支持资源
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.3 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2019, Texas Instruments Incorporated
15
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LP3470A263DBVR
LP3470A275DBVR
LP3470A293DBVR
LP3470A308DBVR
LP3470A365DBVR
LP3470A400DBVR
LP3470A438DBVR
LP3470A463DBVR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
5
5
5
5
5
5
5
5
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
D263
D275
D293
D308
D365
D400
D438
D463
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Dec-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LP3470A263DBVR
LP3470A275DBVR
LP3470A293DBVR
LP3470A308DBVR
LP3470A365DBVR
LP3470A400DBVR
LP3470A438DBVR
LP3470A463DBVR
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
5
5
5
5
5
5
5
5
3000
3000
3000
3000
3000
3000
3000
3000
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Dec-2019
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LP3470A263DBVR
LP3470A275DBVR
LP3470A293DBVR
LP3470A308DBVR
LP3470A365DBVR
LP3470A400DBVR
LP3470A438DBVR
LP3470A463DBVR
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
5
5
5
5
5
5
5
5
3000
3000
3000
3000
3000
3000
3000
3000
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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相关型号：
LP3470IM5-2.63/NOPB
IC 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO5, SOT-23, 5 PIN, Power Management Circuit
NSC
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