LP38513TJ-ADJ/NOPB [TI]
具有低噪声和使能功能的 3A、可调节超低压降稳压器 | NDQ | 5 | -40 to 125;
| 型号： | LP38513TJ-ADJ/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有低噪声和使能功能的 3A、可调节超低压降稳压器 | NDQ | 5 | -40 to 125 输出元件 稳压器 调节器 |
| 文件： | 总18页 (文件大小：1103K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LP38513-ADJ
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SNVS514C –JANUARY 2009–REVISED APRIL 2013
LP38513-ADJ 3A Fast-Transient Response Adjustable Low-Dropout Linear Voltage
Regulator
Check for Samples: LP38513-ADJ
1
FEATURES
APPLICATIONS
2
•
2.25V to 5.5V Input Voltage Range
•
•
•
•
•
•
Digital Core ASICs, FPGAs, and DSPs
Servers
•
Adjustable Output Voltage Range of 0.5V to
4.5V
Routers and Switches
Base Stations
•
•
3.0A Output Load Current
±2.0% Accuracy over Line, Load, and Full-
Temperature Range from -40°C to +125°C
Storage Area Networks
DDR2 Memory
•
•
•
Stable with tiny 10 µF ceramic capacitors
Enable pin
DESCRIPTION
The LP38513-ADJ Fast-Transient Response Low-
Dropout Voltage Regulator offers the highest-
performance in meeting AC and DC accuracy
requirements for powering Digital Cores. The
LP38513-ADJ uses a proprietary control loop that
enables extremely fast response to change in line
conditions and load demands. Output Voltage DC
accuracy at 2.5% over line, load and full temperature
range from -40°C to +125°C. The LP38513-ADJ is
designed for inputs from the 2.5V, 3.3V, and 5.0V rail,
is stable with 10 μF ceramic capacitors, and has an
adjustable output voltage. The LP38513-ADJ
provides excellent transient performance to meet the
demand of high performance digital core ASICs,
DSPs, and FPGAs found in highly-intensive
applications such as servers, routers/switches, and
base stations.
Typically less than 1 µA of Ground pin current
when Enable pin is low
•
•
25dB of PSRR at 100 kHz
Over-Temperature and Over-Current
Protection
•
TO-263 THIN 5-Pin Surface Mount Package
Typical Application Circuit
IN
V
OUT
V
OUT
IN
C
10 mF
Ceramic
IN
R1
R2
LP38513-ADJ
ON
OFF
C
FF
C
OUT
10 mF
Ceramic
V
EN
EN
ADJ
GND
GND
GND
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009–2013, Texas Instruments Incorporated
LP38513-ADJ
SNVS514C –JANUARY 2009–REVISED APRIL 2013
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
Connection Diagram
Top View
EN 1
Exposed
DAP
IN 2
GND 3
OUT 4
ADJ 5
See Package Number NDQ0005A
Pin Descriptions for TO-263 THIN Package
Pin #
Pin Name
Function
Enable. Pull high to enable the output, low to disable the output. This pin has no internal bias and
must be tied to the input voltage, or actively driven.
1
EN
2
3
4
5
IN
Input Supply Pin
GND
OUT
ADJ
Ground
Regulated Output Voltage Pin
The feedback to the internal Error Amplifier to set the output voltage
The TO-263 THIN DAP connection is used as a thermal connection to remove heat from the device
to an external heat-sink in the form of the copper area on the printed circuit board. The DAP is
physically connected to backside of the die, but is not internally connected to device ground. The
DAP should be soldered to the Ground Plane copper..
DAP
DAP
2
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SNVS514C –JANUARY 2009–REVISED APRIL 2013
(1)
ABSOLUTE MAXIMUM RATINGS
Storage Temperature Range
−65°C to +150°C
(2)
Soldering Temperature
Thin TO-263
260°C, 10s
±2 kV
(3)
ESD Rating
(4)
Power Dissipation
Internally Limited
-0.3V to +6.0V
-0.3V to +6.0V
-0.3V to +6.0V
-0.3V to +6.0V
Internally Limited
Input Pin Voltage (Survival)
Enable Pin Voltage (Survival)
Output Pin Voltage (Survival)
ADJ Pin Voltage (Survival)
IOUT (Survival)
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but does not specific performance limits. For specifications and conditions, see the
Electrical Characteristics.
(2) Refer to JEDEC J-STD-020C for surface mount device (SMD) package reflow profiles and conditions. Unless otherwise stated, the
temperatures and times are for Sn-Pb (STD) only.
(3) The human body model (HBM) is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. Test method is per JESD22-
A114.
(4) Device operation must be evaluated, and derated as needed, based on ambient temperature (TA), power dissipation (PD), maximum
allowable operating junction temperature (TJ(MAX)), and package thermal resistance (θJA). The typical θJA rating given is worst case
based on minimum land area on two-layer PCB (EIA/JESD51-3). See POWER DISSIPATION/HEAT-SINKING for details.
(1)
OPERATING RATINGS
Input Supply Voltage, VIN
Output Voltage, VOUT
Enable Input Voltage, VEN
Output Current (DC)
2.25V to 5.5V
VADJ to 5V
0.0V to 5.5V
1 mA to 3A
(2)
Junction Temperature
−40°C to +125°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but does not specific performance limits. For specifications and conditions, see the
Electrical Characteristics.
(2) Device operation must be evaluated, and derated as needed, based on ambient temperature (TA), power dissipation (PD), maximum
allowable operating junction temperature (TJ(MAX)), and package thermal resistance (θJA). The typical θJA rating given is worst case
based on minimum land area on two-layer PCB (EIA/JESD51-3). See POWER DISSIPATION/HEAT-SINKING for details.
Copyright © 2009–2013, Texas Instruments Incorporated
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ELECTRICAL CHARACTERISTICS
Unless otherwise specified: VIN= 2.50V, VOUT = VADJ, IOUT= 10 mA, CIN= 10 µF, COUT= 10 µF, VEN= 2.0V. Limits in standard
type are for TJ= 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to +125°C.
Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent the most
likely parametric norm at TJ= 25°C, and are provided for reference purposes only.
Symbol
Parameter
Conditions
Min
Typ
500.
1
Max
Units
2.25V ≤ VIN ≤ 5.5V
10 mA ≤ IOUT ≤ 3A
2.25V ≤ VIN ≤ 5.5V
495.0
490.0
505.0
510.0
(1)
VADJ
VADJ Accuracy
mV
IADJ
ADJ Pin Bias Current
VADJ Line Regulation
-
-
nA
0.03
0.06
(2) (1)
(3) (1)
ΔVADJ/ΔVIN
2.25V ≤ VIN ≤ 5.5V
-
-
%/V
0.15
0.20
ΔVADJ/ΔIOUT VADJ Load Regulation
10 mA ≤ IOUT ≤ 3A
IOUT = 3A
-
-
-
-
%/A
mV
(4)
VDO
Dropout Voltage
-
470
10
12
IOUT = 10 mA
8
Ground Pin Current, Output
Enabled
mA
14
16
IGND
IOUT = 3A
-
12
Ground Pin Current, Output
Disabled
5
10
VEN = 0.50V
VOUT = 0V
-
-
1
µA
A
ISC
Short Circuit Current
5.2
-
Enable Input
VEN rising from <0.5V until
VOUT = ON
0.90
0.80
1.50
1.60
VEN(ON)
Enable ON Voltage Threshold
1.20
1.00
V
VEN falling from 1.6V until
VOUT = OFF
0.70
0.60
1.30
1.40
VEN(OFF)
VEN(HYS)
Enable OFF Voltage Threshold
Enable Voltage Hysteresis
VEN(ON) - VEN(OFF)
VEN = VIN
-
-
-
200
1
-
-
-
mV
nA
IEN
Enable Pin Current
VEN = 0V
-1
Time from VEN < VEN(TH) to
VOUT = OFF, ILOAD = 3A
td(OFF)
Turn-off delay
Turn-on delay
-
-
5
5
-
-
µs
Time from VEN >VEN(TH) to
VOUT = ON, ILOAD = 3A
td(ON)
AC Parameters
VIN = 2.5V
f = 120Hz
-
-
73
70
-
-
PSRR
Ripple Rejection
dB
VIN = 2.5V
f = 1 kHz
ρn(l/f)
Output Noise Density
Output Noise Voltage
f = 120Hz
-
-
0.4
25
-
-
µV/√Hz
en
BW = 10Hz - 100kHz
µVRMS
Thermal Characteristics
TSD
Thermal Shutdown
TJ rising
-
-
165
10
-
-
°C
ΔTSD
Thermal Shutdown Hysteresis
Thermal Resistance
Junction to Ambient
TJ falling from TSD
θJ-A
θJ-C
TO-263 THIN
TO-263 THIN
-
-
67
2
-
-
°C/W
°C/W
(5)
Thermal Resistance
Junction to Case
(1) The line and load regulation specification contains only the typical number. However, the limits for line and load regulation are included
in the output voltage tolerance specification.
(2) Line regulation is defined as the change in VADJ from the nominal value due to change in the voltage at the input.
(3) Load regulation is defined as the change in VADJ from the nominal value due to change in the load current at the output.
(4) Dropout voltage (VDO) is typically defined as the input to output voltage differential (VIN - VOUT) where the input voltage is low enough to
cause the output voltage to drop 2%. For the LP38513-ADJ, the minimum operating voltage of 2.25V is the limiting factor when the
programed output voltage is less than typically 1.80V.
(5) Device operation must be evaluated, and derated as needed, based on ambient temperature (TA), power dissipation (PD), maximum
allowable operating junction temperature (TJ(MAX)), and package thermal resistance (θJA). The typical θJA rating given is worst case
based on minimum land area on two-layer PCB (EIA/JESD51-3). See POWER DISSIPATION/HEAT-SINKING for details.
4
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SNVS514C –JANUARY 2009–REVISED APRIL 2013
TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise specified: TJ = 25°C, VIN = 2.50V, VOUT = VADJ, VEN = 2.0V, CIN = 10 µF, COUT = 10 µF, IOUT = 10 mA.
VADJ
vs
Temperature
VOUT
vs
VIN
Figure 1.
Figure 2.
Ground Pin Current (IGND
)
Ground Pin Current (IGND)
vs
vs
VIN
Temperature
Figure 3.
Figure 4.
Ground Pin Current (IGND
)
Enable Threshold
vs
Temperature
vs
Temperature
Figure 5.
Figure 6.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise specified: TJ = 25°C, VIN = 2.50V, VOUT = VADJ, VEN = 2.0V, CIN = 10 µF, COUT = 10 µF, IOUT = 10 mA.
VOUT
Load regulation
vs
vs
VEN
Temperature
Figure 7.
Figure 8.
Line Regulation
vs
Temperature
Current Limit
vs
Temperature
Figure 9.
Figure 10.
Load Transient, 10mA to 3A
VOUT = VADJ, COUT = 10 μF Ceramic
Load Transient, 10 mA to 3A
VOUT = 1.20V, COUT = 10 μF Ceramic
Figure 11.
Figure 12.
6
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SNVS514C –JANUARY 2009–REVISED APRIL 2013
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise specified: TJ = 25°C, VIN = 2.50V, VOUT = VADJ, VEN = 2.0V, CIN = 10 µF, COUT = 10 µF, IOUT = 10 mA.
Load Transient, 1A to 3A
VOUT = 1.20V, COUT = 10 μF Ceramic
Line Transient
VOUT = VADJ, COUT = 10 μF Ceramic
Figure 13.
Figure 14.
Line Transient
VOUT = 1.20V, COUT = 10 μF Ceramic
PSRR, IOUT = 100 mA
VOUT = VADJ, COUT = 10 μF Ceramic
Figure 15.
Figure 16.
PSRR, IOUT = 3.0A
VOUT = VADJ, COUT = 10 μF Ceramic
Output Noise Density
VOUT = VADJ, COUT = 10 μF Ceramic
Figure 17.
Figure 18.
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BLOCK DIAGRAM
IN
OUT
Thermal
Limit
Current
Limit
EN
V
REF
ADJ
GND
LP38513-ADJ
8
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SNVS514C –JANUARY 2009–REVISED APRIL 2013
APPLICATION INFORMATION
EXTERNAL CAPACITORS
Like any low-dropout regulator, external capacitors are required to assure stability. These capacitors must be
correctly selected for proper performance.
Input Capacitor
A ceramic input capacitor of at least 10 µF is required. For general usage across all load currents and operating
conditions, a 10 µF ceramic input capacitor will provide satisfactory performance.
Output Capacitor
A ceramic capacitor with a minimum value of 10 µF is required at the output pin for loop stability. It must be
located less than 1 cm from the device and connected directly to the output and ground pin using traces which
have no other currents flowing through them. As long as the minimum of 10 µF ceramic is met, there is no
limitation on any additional capacitance.
X7R and X5R dielectric ceramic capacitors are strongly recommended, as they typically maintain a capacitance
range within ±20% of nominal over full operating ratings of temperature and voltage. Of course, they are typically
larger and more costly than Z5U/Y5U types for a given voltage and capacitance.
Z5U and Y5V dielectric ceramics are not recommended as the capacitance will drop severely with applied
voltage. A typical Z5U or Y5V capacitor can lose 60% of its rated capacitance with half of the rated voltage
applied to it. The Z5U and Y5V also exhibit a severe temperature effect, losing more than 50% of nominal
capacitance at high and low limits of the temperature range.
Application Information
REVERSE VOLTAGE
A reverse voltage condition will exist when the voltage at the output pin is higher than the voltage at the input pin.
Typically this will happen when VIN is abruptly taken low and COUT continues to hold a sufficient charge such that
the input to output voltage becomes reversed. A less common condition is when an alternate voltage source is
connected to the output.
There are two possible paths for current to flow from the output pin back to the input during a reverse voltage
condition.
While VIN is high enough to keep the control circuity alive, and the Enable pin is above the VEN(ON) threshold, the
control circuitry will attempt to regulate the output voltage. Since the input voltage is less than the programmed
output voltage, the control circuit will drive the gate of the pass element to the full on condition when the output
voltage begins to fall. In this condition, reverse current will flow from the output pin to the input pin, limited only
by the RDS(ON) of the pass element and the output to input voltage differential. Discharging an output capacitor up
to 1000 µF in this manner will not damage the device as the current will rapidly decay. However, continuous
reverse current should be avoided. When the Enable is low this condition will be prevented.
The internal PFET pass element in the LP38513-ADJ has an inherent parasitic diode. During normal operation,
the input voltage is higher than the output voltage and the parasitic diode is reverse biased. However, if the
output voltage to input voltage differential is more than 500 mV (typical) the parasitic diode becomes forward
biased and current flows from the output pin to the input pin through the diode. The current in the parasitic diode
should be limited to less than 1A continuous and 5A peak.
If used in a dual-supply system where the regulator output load is returned to a negative supply, the output pin
must be diode clamped to ground. A Schottky diode is recommended for this protective clamp.
SHORT-CIRCUIT PROTECTION
The LP38513-ADJ is short circuit protected, and in the event of a peak over-current condition the short-circuit
control loop will rapidly drive the output PMOS pass element off. Once the power pass element shuts down, the
control loop will rapidly cycle the output on and off until the average power dissipation causes the thermal
shutdown circuit to respond to servo the on/off cycling to a lower frequency. Please refer to the POWER
DISSIPATION/HEAT-SINKING section for power dissipation calculations.
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SETTING THE OUTPUT VOLTAGE
The output voltage is set using the external resistive divider R1 and R2. The output voltage is given by the
formula:
VOUT = VADJ x (1 + (R1/R2))
(1)
The resistors used for R1 and R2 should be high quality, tight tolerance, and with matching temperature
coefficients. It is important to remember that, although the value of VADJ is specified, the final value of VOUT is
not. The use of low quality resistors for R1 and R2 can easily produce a VOUT value that is unacceptable.
It is recommended that the values selected for R1 and R2 are such that the parallel value is less than 1.00 kΩ.
This is to reduce the possibility of any internal parasitic capacitances on the ADJ pin from creating an
undesirable phase shift that may interfere with device stability.
( (R1 x R2) / (R1 + R2) ) ≤ 1.00 kΩ
(2)
FEED FORWARD CAPACITOR, CFF
When using a ceramic capacitor for COUT, the typical ESR value will be too small to provide any meaningful
positive phase compensation, FZ, to offset the internal negative phase shifts in the gain loop.
FZ = 1 / (2 x π x COUT x ESR)
(3)
A capacitor placed across the gain resistor R1 will provide additional phase margin to improve load transient
response of the device. This capacitor, CFF, in parallel with R1, will form a zero in the loop response given by the
formula:
FZ = 1 / (2 x π x CFF x R1)
(4)
For optimum load transient response select CFF so the zero frequency, FZ, falls between 20 kHz and 40 kHz.
CFF = 1 / (2 x π x R1 x FZ)
(5)
The phase lead provided by CFF diminishes as the DC gain approaches unity, or VOUT approaches VADJ. This is
because CFF also forms a pole with a frequency of:
FP = 1 / (2 x π x CFF x (R1 || R2) )
(6)
It's important to note that at higher output voltages, where R1 is much larger than R2, the pole and zero are far
apart in frequency. At lower output voltages the frequency of the pole and the zero mover closer together. The
phase lead provided from CFF diminishes quickly as the output voltage is reduced, and has no effect when VOUT
= VADJ. For this reason, relying on this compensation technique alone is adequate only for higher output
voltages.
Table 1 lists some suggested, best fit, standard ±1% resistor values for R1 and R2, and a standard ±10%
capacitor values for CFF, for a range of VOUT values. Other values of R1, R2, and CFF are available that will give
similar results.
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Table 1.
VOUT
R1
R2
CFF
FZ
0.80V
1.00V
1.20V
1.50V
1.80V
2.00V
2.50V
3.00V
3.30V
1.07 kΩ
1.00 kΩ
1.40 kΩ
2.00 kΩ
2.94 kΩ
1.02 kΩ
1.02 kΩ
1.00 kΩ
2.00 kΩ
1.78 kΩ
1.00 kΩ
1.00 kΩ
1.00 kΩ
1.13 kΩ
340Ω
4700 pF
4700 pF
3300 pF
2700 pF
1500 pF
4700 pF
4700 pF
4700 pF
2700 pF
31.6 kHz
33.8 kHz
34.4 kHz
29.5 kHz
36.1 kHz
33.2 kHz
33.2 kHz
33.8 kHz
29.5 kHz
255Ω
200Ω
357Ω
Please refer to Application Note AN-1378 Method For Calculating Output Voltage Tolerances in Adjustable
Regulators SNVA112 for additional information on how resistor tolerances affect the calculated VOUT value.
ENABLE OPERATION
The Enable ON threshold is typically 1.2V, and the OFF threshold is typically 1.0V. To ensure reliable operation
the Enable pin voltage must rise above the maximum VEN(ON) threshold and must fall below the minimum VEN(OFF)
threshold. The Enable threshold has typically 200mV of hysteresis to improve noise immunity.
The Enable pin (EN) has no internal pull-up or pull-down to establish a default condition and, as a result, this pin
must be terminated either actively or passively.
If the Enable pin is driven from a single ended device (such as the collector of a discrete transistor) a pull-up
resistor to VIN, or a pull-down resistor to ground, will be required for proper operation. A 1 kΩ to 100 kΩ resistor
can be used as the pull-up or pull-down resistor to establish default condition for the EN pin. The resistor value
selected should be appropriate to swamp out any leakage in the external single ended device, as well as any
stray capacitance.
If the Enable pin is driven from a source that actively pulls high and low (such as a CMOS rail to rail comparator
output), the pull-up, or pull-down, resistor is not required.
If the application does not require the Enable function, the pin should be connected directly to the adjacent VIN
pin.
POWER DISSIPATION/HEAT-SINKING
A heat-sink may be required depending on the maximum power dissipation (PD(MAX)), maximum ambient
temperature (TA(MAX))of the application, and the thermal resistance (θJA) of the package. Under all possible
conditions, the junction temperature (TJ) must be within the range specified in the Operating Ratings. The total
power dissipation of the device is given by:
PD = ( (VIN−VOUT) x IOUT) + ((VIN) x IGND
)
(7)
where IGND is the operating ground current of the device (specified under Electrical Characteristics).
The maximum allowable junction temperature rise (ΔTJ) depends on the maximum expected ambient
temperature (TA(MAX)) of the application, and the maximum allowable junction temperature (TJ(MAX)):
ΔTJ = TJ(MAX) − TA(MAX)
(8)
The maximum allowable value for junction to ambient Thermal Resistance, θJA, can be calculated using the
formula:
θJA = ΔTJ / PD(MAX)
(9)
11
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LP38513-ADJ is available in the TO-263 THIN surface mount package. For a comparison of the TO-263 THIN
package to the standard TO-263 package see Application Note AN-1797 TO-263 THIN Package SNVA328. The
thermal resistance depends on amount of copper area, or heat sink, and on air flow. See Application Note AN-
1520 A Guide to Board Layout for Best Thermal Resistance for Exposed Packages SNVA183 for guidelines.
Heat-Sinking the TO-263 THIN Package
The DAP of the TO-263 THIN package is soldered to the copper plane for heat sinking. The TO-263 THIN
package has a θJA rating of 67°C/W, and a θJC rating of 2°C/W. The θJA rating of 67°C/W includes the device
DAP soldered to an area of 0.055 square inches (0.22 in x 0.25 in) of 1 ounce copper on a two sided PCB, with
no airflow. See JEDEC standard EIA/JESD51-3 for more information.
Figure 19 shows a curve for the θJA of TO-263 THIN package for different thermal via counts under the exposed
DAP, using a four layer PCB for heat sinking. The thermal vias connect the copper area directly under the
exposed DAP to the first internal copper plane only. See JEDEC standards EIA/JESD51-5 and EIA/JESD51-7 for
more information.
Figure 19. θJA vs Thermal Via Count for the TO-263 THIN Package on 4–Layer PCB
Figure 20 shows the thermal performance when the Thin TO-263 is mounted to a two layer PCB where the
copper area is predominately directly under the exposed DAP. .As shown in the figure, increasing the copper
area beyond 1 square inch produces very little improvement.
Figure 20. θJA vs Copper Area for the TO-263 THIN Package
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REVISION HISTORY
Changes from Revision B (April 2013) to Revision C
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 12
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LP38513TJ-ADJ/NOPB
ACTIVE
TO-263
NDQ
5
1000 RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
LP38513
TJ-ADJ
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-May-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LP38513TJ-ADJ/NOPB TO-263
NDQ
5
1000
330.0
24.4
10.6
15.4
2.45
12.0
24.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-May-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
TO-263 NDQ
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 35.0
LP38513TJ-ADJ/NOPB
5
1000
Pack Materials-Page 2
MECHANICAL DATA
NDQ0005A
TJ5A (Rev F)
www.ti.com
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