LP38691QSDX-ADJ/NOPB [TI]
汽车类 500mA、10V、可调节低压降稳压器 | NGG | 6 | -40 to 125;
| 型号： | LP38691QSDX-ADJ/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类 500mA、10V、可调节低压降稳压器 | NGG | 6 | -40 to 125 稳压器 |
| 文件： | 总27页 (文件大小：1677K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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LP38691-ADJ, LP38693-ADJ, LP38691-ADJ-Q1, LP38693-ADJ-Q1
ZHCSAZ8K –JANUARY 2005–REVISED JANUARY 2016
LP3869x-ADJ/Q1 500mA 低压降 CMOS 线性稳压器
使用陶瓷输出电容器可保持稳定
1 特性
3 说明
1
•
•
宽输入电压范围：2.7V 至 10V
LP3869x-ADJ 低压降 CMOS 线性稳压器具有精度为
2% 的基准电压和极低压降（在负载电流为 500mA、
VOUT = 5V 时为 250mV），并且采用超低等效串联电
阻 (ESR) 陶瓷输出电容，可提供出色的交流性能。
所有超薄型小外形尺寸无引线封装 (WSON) 选项均
作为 AEC-Q100 1 级器件可用
•
•
•
输出电压范围：1.25V 至 9V
2% 调节 (ADJ) 引脚电压精度 (25°C)
此稳压器采用低热阻的 WSON 和 SOT-223 封装，即
使在周围温度较高的环境下也可实现满电流运行。
低压降电压：500mA 时为 250mV
（5V 输出典型值）
•
•
•
•
•
•
•
精密（已调整）带隙基准
P 型金属氧化物半导体 (PMOS) 功率晶体管的使用意
味着无需直流基极驱动电流对其进行偏置，因此无论负
载电流、输入电压或者运行温度为何，接地引脚电流均
可保持在 100μA 以下。
可保证 –40°C 至 +125°C 温度范围内的技术规格
1µA 关闭状态静态电流
热过载保护
折返电流限制
器件信息(1)
接地 (GND) 引脚电流：满载时为 55µA（典型值）
使能 (EN) 引脚 (LP38693-ADJ)
器件型号
封装
WSON (6)
封装尺寸（标称值）
3.00mm × 3.00mm
6.50mm x 3.56mm
3.00mm × 3.00mm
LP38691-ADJ
SOT-223 (5)
WSON (6)
2 应用范围
LP38693-ADJ
•
•
•
•
硬盘驱动器
笔记本电脑
电池供电设备
便携式仪表
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
典型应用电路
V
IN
V
OUT
IN
OUT
ADJ
[t38691
-!5W
R1
GND
1 mF *
1 mF *
R2
V
IN
V
OUT
IN
OUT
ADJ
[t38693
-!5W
R1
EN
V
EN
GND
1 mF *
1 mF *
R2
VOUT = VADJ × (1 + R1/R2)
* 稳定状态下的最小值
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SNVS324
LP38691-ADJ, LP38693-ADJ, LP38691-ADJ-Q1, LP38693-ADJ-Q1
ZHCSAZ8K –JANUARY 2005–REVISED JANUARY 2016
www.ti.com.cn
目录
7.4 Device Functional Modes........................................ 12
Application and Implementation ........................ 13
8.1 Application Information............................................ 13
8.2 Typical Applications ............................................... 13
Power Supply Recommendations...................... 18
1
2
3
4
5
6
特性.......................................................................... 1
应用范围................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings: LP38691-ADJ, LP38693-ADJ............. 4
6.3 ESD Ratings: LP38691-ADJ-Q1, LP38693-ADJ-Q1. 4
6.4 Recommended Operating Conditions....................... 4
6.5 Thermal Information.................................................. 4
6.6 Electrical Characteristics........................................... 5
6.7 Typical Characteristics.............................................. 6
Detailed Description ............................................ 11
7.1 Overview ................................................................. 11
7.2 Functional Block Diagrams ..................................... 11
7.3 Feature Description................................................. 12
8
9
10 Layout................................................................... 18
10.1 Layout Guidelines ................................................. 18
10.2 Layout Examples................................................... 18
10.3 WSON Mounting ................................................... 19
11 器件和文档支持 ..................................................... 20
11.1 文档支持................................................................ 20
11.2 相关链接................................................................ 20
11.3 社区资源................................................................ 20
11.4 商标....................................................................... 20
11.5 静电放电警告......................................................... 20
11.6 Glossary................................................................ 20
12 机械、封装和可订购信息....................................... 20
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision J (October 2015) to Revision K
Page
•
Added Caution note to Foldback Current Limiting subsection ............................................................................................ 12
Changes from Revision I (April 2013) to Revision J
Page
•
已添加 器件信息和引脚配置与功能部分，ESD 额定值表，已更新；已添加特性描述，器件功能模式，应用和实施，电
源相关建议，布局，器件和文档支持以及机械、封装和可订购信息部分；已将文本和图片中的 Vin、Vout 和 Ven 引脚
名更新为 IN、OUT 和 EN；已修正说明中的文字冗余问题；已为参考设计添加顶部导航图标。........................................... 1
Changes from Revision H (April 2013) to Revision I
Page
•
•
Changed layout of National Data Sheet to TI format ........................................................................................................... 15
Changed layout of National Data Sheet to TI format .......................................................................................................... 19
2
Copyright © 2005–2016, Texas Instruments Incorporated
LP38691-ADJ, LP38693-ADJ, LP38691-ADJ-Q1, LP38693-ADJ-Q1
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ZHCSAZ8K –JANUARY 2005–REVISED JANUARY 2016
5 Pin Configuration and Functions
NGG Package
6-Pin WSON With Exposed Thermal Pad
LP38691-ADJ Top View
NGG Package
6-Pin WSON With Exposed Thermal Pad
LP38693-ADJ Top View
IN
IN
6
5
4
6 IN
IN
1
1
2
Exposed Pad
on Bottom
(DAP)
Exposed Pad
on Bottom
(DAP)
OUT
ADJ
OUT
5
4
GND 2
GND
ADJ
N/C 3
EN
3
NC - No internal connection
NDC Package
5-Pin SOT-223
LP38693-ADJ Top View
EN
ADJ
OUT
IN
1
2
3
4
5 GND
Pin Functions
PIN
LP38691-ADJ
WSON
LP38693-ADJ
I/O
DESCRIPTION
NAME
WSON
SOT-223
WSON Only - The DAP (exposed pad) functions as a thermal
connection when soldered to a copper plane. See WSON Mounting
section for more information.
DAP
√
—
2
√
3
2
—
—
I
The EN pin allows the part to be turned to an ON or OFF state by
pulling this pin high or low.
EN
1
5
Circuit ground for the regulator. For the SOT-223 package this is
thermally connected to the die and functions as a heat sink when the
soldered down to a large copper plane.
GND
—
This is the input supply voltage to the regulator. For WSON devices,
both IN pins must be tied together for full current operation (250 mA
maximum per pin).
IN
1, 6
1, 6
4
I
N/C
3
4
5
—
4
—
2
—
O
I
No internal connection.
The ADJ pin is used to set the regulated output voltage by connecting
it to the external resistors R1 and R2 (see 典型应用电路).
ADJ
OUT
5
3
Regulated output voltage.
Copyright © 2005–2016, Texas Instruments Incorporated
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN
MAX
UNIT
V(MAX) All pins (with respect to GND)
–0.3
12
V
V
V
(3)
IOUT
Internally limited
Internally limited
Power dissipation(4)
Junction temperature
Storage temperature, Tstg
–40
−65
150
150
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) If used in a dual-supply system where the regulator load is returned to a negative supply, the OUT pin must be diode clamped to
ground.
(4) At elevated temperatures, device power dissipation must be derated based on package thermal resistance and heatsink values (if a
heatsink is used). When using the WSON package, refer to Leadless Leadframe Package (LLP) (SNOA401) and the WSON Mounting
section in this data sheet. If power dissipation causes the junction temperature to exceed specified limits, the device will go into thermal
shutdown.
6.2 ESD Ratings: LP38691-ADJ, LP38693-ADJ
VALUE
UNIT
V(ESD)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
6.3 ESD Ratings: LP38691-ADJ-Q1, LP38693-ADJ-Q1
VALUE
UNIT
V(ESD)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002(1)
2000
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.4 Recommended Operating Conditions
MIN
2.7
NOM
MAX
10
UNIT
V
VIN supply voltage
Operating junction temperature
−40
125
°C
6.5 Thermal Information
LP3869x-ADJ
WSON
6 PINS
50.6
LP38693-ADJ
THERMAL METRIC(1)
SOT-223
5 PINS
68.5(3)
52.2
UNIT
(2)
RθJA
RθJC(top)
RθJB
Junction-to-ambient thermal resistance, High-K
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
44.4
24.9
13.0
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.4
5.5
ψJB
25.1
12.8
RθJC(bot)
5.4
n/a
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(2) Thermal resistance value RθJA is based on the EIA/JEDEC High-K printed circuit board defined by: JESD51-7 - High Effective Thermal
Conductivity Test Board for Leaded Surface Mount Packages.
(3) The PCB for the WSON (NGN) package RθJA includes thermal vias under the exposed thermal pad per EIA/JEDEC JESD51-5.
4
Copyright © 2005–2016, Texas Instruments Incorporated
LP38691-ADJ, LP38693-ADJ, LP38691-ADJ-Q1, LP38693-ADJ-Q1
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ZHCSAZ8K –JANUARY 2005–REVISED JANUARY 2016
6.6 Electrical Characteristics
Unless otherwise specified, limits apply for TJ = 25°C, VIN = VOUT + 1 V, CIN = COUT = 10 µF, ILOAD = 10 mA. Minimum and
maximum limits are specified through testing, statistical correlation, or design.
PARAMETER
TEST CONDITIONS
VIN = 2.7 V
MIN
TYP(1)
MAX
UNIT
1.225
1.25
1.275
3.2 V ≤ VIN ≤ 10 V, 100 µA < IL < 0.5 A
1.25
VADJ
ADJ pin voltage
V
3.2 V ≤ VIN ≤ 10 V, 100 µA < IL < 0.5 A
Full operating temperature range
1.2
1.3
0.1
VOUT + 0.5 V ≤ VIN ≤ 10 V
IL = 25 mA
0.03
1.8
Output voltage line
regulation(2)
ΔVOUT/ΔVIN
%/V
%/A
VOUT + 0.5 V ≤ VIN ≤ 10 V
IL = 25 mA
Full operating temperature range
1 mA < IL < 0.5 A
VIN = VOUT + 1 V
Output voltage load
regulation(3)
ΔVOUT/ΔIL
1 mA < IL < 0.5 A
VIN = VOUT + 1 V
5
Full operating temperature range
IL = 0.1 A
(VOUT = 2.5 V)
80
IL = 0.5 A
430
(VOUT = 2.5 V)
Full operating temperature
range
IL = 0.1 A
IL = 0.5 A
145
725
IL = 0.1 A
IL = 0.5 A
IL = 0.1 A
65
(VOUT = 3.3 V)
330
VDO
Dropout voltage(4)
mV
(VOUT = 3.3 V)
Full operating temperature
range
110
550
IL = 0.5 A
IL = 0.1 A
IL = 0.5 A
IL = 0.1 A
45
(VOUT = 5 V)
250
(VOUT = 5 V)
Full operating temperature
range
100
450
IL = 0.5 A
VIN ≤ 10 V, IL =100 µA – 0.5 A
55
VIN ≤ 10 V, IL =100 µA – 0.5 A
Full operating temperature range
IQ
Quiescent current
100
1
µA
VEN ≤ 0.4 V, (LP38693 Only)
0.001
VIN – VOUT ≤ 4 V
Full operating temperature range
IL(MIN)
IFB
Minimum load current
100
VIN – VOUT > 5 V
VIN – VOUT < 4 V
350
850
Foldback current limit
Ripple rejection
mA
dB
VIN = VOUT + 2 V(DC), with 1 V(p-p) /
120-Hz Ripple
PSRR
TSD
55
Thermal shutdown activation
(junction temp)
160
°C
Thermal shutdown hysteresis
(junction temp)
TSD (HYST)
IADJ
10
0.01
0.7
ADJ input leakage current
VADJ = 0 V to 1.5 V, VIN = 10 V
–100
100
2
nA
µV/√Hz
µA
BW = 10 Hz to 10 kHz
VOUT = 3.3 V
en
Output noise
VOUT (LEAK)
Output leakage current
VOUT = VOUT(NOM) + 1 V at 10 VIN
0.5
(1) Typical numbers represent the most likely parametric norm for 25°C operation.
(2) Output voltage line regulation is defined as the change in output voltage from nominal value resulting from a change in input voltage.
(3) Output voltage load regulation is defined as the change in output voltage from nominal value as the load current increases from 1 mA to
full load.
(4) Dropout voltage is defined as the minimum input to output differential required to maintain the output within 100 mV of nominal value.
Copyright © 2005–2016, Texas Instruments Incorporated
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Electrical Characteristics (continued)
Unless otherwise specified, limits apply for TJ = 25°C, VIN = VOUT + 1 V, CIN = COUT = 10 µF, ILOAD = 10 mA. Minimum and
maximum limits are specified through testing, statistical correlation, or design.
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX
UNIT
Output = OFF state
Full operating temperature range
0.4
Output = ON state, VIN = 4 V
Full operating temperature range
1.8
3
Enable voltage (LP38693
Only)
VEN
V
Output = ON state, VIN = 6 V
Full operating temperature range
Output = ON state, VIN = 10 V
Full operating temperature range
4
EN pin leakage
(LP38693 only)
IEN
VEN = 0 V or 10 V, VIN = 10 V
–1
0.001
1
µA
=
6.7 Typical Characteristics
Unless otherwise specified: TJ = 25°C, CIN = COUT = 10 µF, EN pin is tied to IN (LP38693-ADJ only), VOUT = 1.25 V, VIN
VOUT 1 V, ILOAD = 10 mA.
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.0
0.8
0.6
0.4
C
= 10 mF
OUT
C
= 1 mF
OUT
0.2
0.0
10
100
1k
Cw9vÜ9b/ò (Iz)
10k
100k
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 1. Noise vs Frequency
Figure 2. Noise vs Frequency
70
60
50
40
30
20
10
0
1.5
C
OUT
= 100 mF
1.0
0.5
0.0
V
V
(DC) = 3.25V
IN
IN
(AC) = 1V(p-p)
C
= 10 mF
OUT
10
100
1k
Cw9vÜ9b/ò (Iz)
10k
100k
10
100
1k
10k
100k
Cw9vÜ9b/ò (Iz)
Figure 3. Noise vs Frequency
Figure 4. Ripple Rejection
6
Copyright © 2005–2016, Texas Instruments Incorporated
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ZHCSAZ8K –JANUARY 2005–REVISED JANUARY 2016
Typical Characteristics (continued)
Unless otherwise specified: TJ = 25°C, CIN = COUT = 10 µF, EN pin is tied to IN (LP38693-ADJ only), VOUT = 1.25 V, VIN
=
VOUT 1 V, ILOAD = 10 mA.
70
60
70
60
50
40
30
50
40
30
20
10
0
V
V
(DC) = 3.25V
IN
IN
V
V
(DC) = 3.25V
20
10
0
IN
IN
(AC) = 1V(p-p)
(AC) = 1V(p-p)
C
OUT
= 1 mF
C
= 100 mF
OUT
10
100
1k
Cw9vÜ9b/ò (Iz)
10k
100k
10
100
1k
Cw9vÜ9b/ò (Iz)
10k
100k
Figure 5. Ripple Rejection
Figure 6. Ripple Rejection
= 1.25V
0.4
0.2
0
V
OUT
20
10
0
C
OUT
= 100 mF
V
OUT
-0.2
-0.4
-0.6
-0.8
-1
-10
-20
4
3
2
1
V
IN
-50 -25
0
25
50
75 100 125
200 ms/DIV
TEMPERATURE (oC)
Figure 8. Line Transient Response
Figure 7. VREF vs Temperature
V
OUT
= 3.3V
V
OUT
= 1.25V
20
10
0
40
C
OUT
= 100 mF
C
OUT
= 10 mF
V
OUT
20
0
V
OUT
-10
-20
-20
-40
4
3
2
1
V
IN
5
4
3
V
IN
200 ms/DIV
200 ms/DIV
Figure 9. Line Transient Response
Figure 10. Line Transient Response
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Typical Characteristics (continued)
Unless otherwise specified: TJ = 25°C, CIN = COUT = 10 µF, EN pin is tied to IN (LP38693-ADJ only), VOUT = 1.25 V, VIN
VOUT 1 V, ILOAD = 10 mA.
=
V
OUT
= 3.3V
V
OUT
= 1.25V
100
50
100
50
C
OUT
= 10 mF
C
OUT
= 1 mF
V
OUT
V
OUT
0
0
-50
-100
-50
-100
4
3
2
1
V
IN
5
4
3
V
IN
100 ms/DIV
40 ms/DIV
Figure 11. Line Transient Response
Figure 12. Line Transient Response
200
100
0
V
= 3.3V
OUT
C
= 10 mF
OUT
100
C
OUT
= 1 mF
50
0
V
OUT
V
OUT
-100
-200
-50
-100
0.5
I
LOAD
5
4
3
V
IN
0.01
100 ms/DIV
40 ms/DIV
Figure 13. Line Transient Response
= 1 mF
Figure 14. Load Transient Response
400
2.3
2.1
1.9
1.7
1.5
1.3
1.1
0.9
0.7
0.5
C
OUT
V
= 10V
IN
200
0
V
OUT
-200
-400
V
IN
= 6V
= 4V
0.5
I
LOAD
V
IN
0.01
-50 -25
0
25
50
75 100 125
TEMPERATURE (oC)
10 ms/DIV
Figure 15. Load Transient Response
Figure 16. EN Voltage vs Temperature
8
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ZHCSAZ8K –JANUARY 2005–REVISED JANUARY 2016
Typical Characteristics (continued)
Unless otherwise specified: TJ = 25°C, CIN = COUT = 10 µF, EN pin is tied to IN (LP38693-ADJ only), VOUT = 1.25 V, VIN
=
VOUT 1 V, ILOAD = 10 mA.
-1.0
0.034
0.032
0.03
-1.5
-2.0
-2.5
-3.0
0.028
0.026
0.024
0.022
0.02
-3.5
-50 -25
0
25
50
75 100 125
-50 -25
0
25
50
75 100 125
TEMPERATURE (oC)
TEMPERATURE (oC)
Figure 18. Line Regulation vs Temperature
Figure 17. Load Regulation vs Temperature
VOUT = 1.25 V
VOUT = 1.8 V
Figure 19. VOUT vs VIN
Figure 20. VOUT vs VIN
Figure 21. VOUT vs. VIN, Power-up
Figure 22. VOUT vs. VEN, On (LP38693-ADJ only)
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Typical Characteristics (continued)
Unless otherwise specified: TJ = 25°C, CIN = COUT = 10 µF, EN pin is tied to IN (LP38693-ADJ only), VOUT = 1.25 V, VIN
VOUT 1 V, ILOAD = 10 mA.
=
2.6
2.5
2.4
-40°C
2.3
125°C
2.2
2.1
25°C
2
0
100
200
300
400
500
I
(mA)
OUT
Figure 24. MIN VOUT vs. IOUT
Figure 23. VOUT vs. VEN, Off (LP38693-ADJ only)
900
800
700
600
500
400
300
200
100
0
-40°C
125°C
25°C
0
100
200
300
(mA)
400
500
I
OUT
VOUT = 1.8 V
Figure 25. Dropout Voltage vs. IOUT
10
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7 Detailed Description
7.1 Overview
The LP3869x-ADJ devices are designed to meet the requirements of portable, battery-powered digital systems
providing an accurate output voltage with fast start-up. When disabled via a low logic signal at the enable pin
(EN), the power consumption is reduced to virtually zero (LP38693-ADJ only).
These LP3869x-ADJ devices perform well with a single 1-μF input capacitor and a single 1-μF ceramic output
capacitor.
7.2 Functional Block Diagrams
IN
P-FET
P-FET
-
MOSFET
DRIVER
+
ENABLE
LOGIC
N/C
FOLDBACK
CURRENT
LIMITING
OUT
THERMAL
SHUTDOWN
1.25-V
REFERENCE
ADJ
GND
Figure 26. LP38691 Functional Diagram (WSON)
IN
P-FET
P-FET
-
MOSFET
DRIVER
+
ENABLE
LOGIC
EN
FOLDBACK
CURRENT
LIMITING
OUT
ADJ
THERMAL
SHUTDOWN
1.25-V
REFERENCE
GND
Figure 27. LP38693 Functional Diagram (SOT-223, WSON)
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7.3 Feature Description
7.3.1 Enable (EN)
The LP38693-ADJ has an enable pin (EN) which allows an external control signal to turn the regulator output to
either an ON or OFF state. The Enable on/off threshold has no hysteresis. The voltage signal must rise and fall
cleanly, and promptly, through the on and off voltage thresholds. The EN pin voltage must be higher than the
VEN(MIN) threshold to ensure that the device is fully enabled under all operating conditions. The EN pin voltage
must be lower than the VEN(MAX) threshold to ensure that the device is fully disabled. The EN pin has no internal
pullup or pulldown to establish a default condition and, as a result, this pin must be terminated either actively or
passively. If the EN pin is driven from a source that actively pulls high and low, the drive voltage should not be
allowed to go below ground potential or higher than VIN. If the application does not require the enable function,
the EN pin should be connected directly to the IN pin.
7.3.2 Thermal Overload Protection (TSD
)
Thermal shutdown disables the output when the junction temperature rises to approximately 160°C which allows
the device to cool. When the junction temperature cools to approximately 150°C, the output circuitry enables.
Based on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may
cycle on and off. This thermal cycling limits the dissipation of the regulator and protects it from damage as a
result of overheating. The TSD circuitry of the LP38693 has been designed to protect against temporary thermal
overload conditions.
The TSD circuitry was not intended to replace proper heat-sinking. Continuously running the LP38693 device into
thermal shutdown degrades device reliability.
7.3.3 Foldback Current Limiting
Foldback current limiting is built into the LP3869x-ADJ devices which reduces the amount of output current the
part can deliver as the output voltage is reduced. The amount of load current is dependent on the differential
voltage between the VIN and VOUT. Typically, when this differential voltage exceeds 5 V, the load current will limit
at about 350 mA. When the VIN – VOUT differential is reduced below 4 V, load current is limited to about 850 mA.
CAUTION
When toggling the LP38693 Enable (EN) after the input voltage (VIN) is applied, the
foldback current limit circuitry is functional the first time that the EN pin is taken high.
The foldback current limit circuitry is non-functional the second, and subsequent, times
that the EN pin is taken high. Depending on the input and output capacitance values
the input inrush current may be higher than expected which can cause the input
voltage to droop.
If the EN pin is connected to the IN pin, the foldback current limit circuitry is functional
when VIN is applied if VIN starts from less than 0.4 V.
7.4 Device Functional Modes
7.4.1 Enable (EN)
The LP38693-ADJ may be switched to the ON or OFF state by logic input at the EN pin. A logic-high voltage on
the EN pin turns the device to the ON state. A logic-low voltage on the EN pin turns the device to the OFF state.
If the application does not require the shutdown feature, the EN pin must be tied to VIN to keep the regulator
output permanently in the ON state when power is applied.
To ensure proper operation, the signal source used to drive the EN input must be able to swing above and below
the specified turnon or turnoff voltage thresholds listed in the Electrical Characteristics section under VEN
.
12
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LP3869x-ADJ can provide 500 mA output current with 2.7 V to 10 V input. Adjustable output voltage in the
range of 1.25 V to 9 V. LP3869x-ADJ is stable with a 1-μF ceramic output capacitor. Typical output noise is
0.7 μVRMS at frequencies from 10 Hz to 10 kHz. Typical PSSR is 55 dB at 1 kHz.
8.2 Typical Applications
V
IN
V
OUT
IN
OUT
ADJ
[t38691
-!5W
R1
GND
1 mF *
1 mF *
R2
* Minimum value required for stability
Figure 28. LP38691-ADJ Typical Application
V
IN
V
OUT
IN
OUT
ADJ
[t38693
-!5W
R1
EN
V
EN
GND
1 mF *
1 mF *
R2
* Minimum value required for stability
Figure 29. LP38693-ADJ Typical Application
8.2.1 Design Requirements
For typical LDO CMOS linear regulators , use the parameters listed in Table 1.
Table 1. Design Parameters
DESIGN PARAMETERS
Input voltage range
Output range
EXAMPLE VALUE
2.7 V to 10 V
Adjustable
Output current
500 mA (maximum)
1 µF
Output capacitor range
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8.2.2 Detailed Design Procedure
8.2.2.1 Setting the Output Voltage
The output voltage is set using the external resistors R1 and R2 (see Typical Applications . The output voltage
will be given by Equation 1:
VOUT = VADJ × (1 + ( R1 / R2 ))
(1)
Because the part has a minimum load current requirement of 100 μA, it is recommended that R2 always be 12
kΩ or less to provide adequate loading. Even if a minimum load is always provided by other means, it is not
recommended that very high value resistors be used for R1 and R2 because it can make the ADJ node
susceptible to noise pickup. A maximum Ohmic value of 100 kΩ is recommended for R2 to prevent this from
occurring.
8.2.2.2 External Capacitors
In common with most regulators, the LP3869x-ADJ devices require an external capacitors for regulator stability.
The devices are specifically designed for portable applications requiring minimum board space and smallest
components. These capacitors must be correctly selected for good performance.
8.2.2.3 Input Capacitor
An input capacitor of at least 1 μF is required (ceramic recommended). The capacitor must be located not more
than one centimeter from the input pin and returned to a clean analog ground.
8.2.2.4 Output Capacitor
An output capacitor is required for loop stability. It must be located less than 1 centimeter from the device and
connected directly to the output and ground pins using traces which have no other currents flowing through them.
The minimum amount of output capacitance that can be used for stable operation is 1 μF. Ceramic capacitors
are recommended; the LP3869x-ADJ devices were designed for use with ultra-low equivalent series resistance
(ESR) capacitors. The LP3869x-ADJ is stable with any output capacitor ESR between 5 mΩ to 500 mΩ.
8.2.2.5 Capacitor Characteristics
It is important that capacitance tolerance and variation with temperature be taken into consideration when
selecting a capacitor so that the minimum required amount of capacitance is provided over the full operating
temperature range.
8.2.2.5.1 Ceramic Capacitors
For values of capacitance in the 10- to 100-μF range, ceramics are usually larger and more costly than tantalums
but give superior AC performance for bypassing high frequency noise because of very low ESR (typically less
than 10 mΩ). However, some dielectric types do not have good capacitance characteristics as a function of
voltage and temperature.
The LP3869x-ADJ is designed to work with ceramic capacitors on the output to take advantage of the benefits
they offer. For capacitance values in the range of 0.47 µF to 4.7 µF, ceramic capacitors are the smallest, least
expensive and have the lowest ESR values, thus making them best for eliminating high frequency noise. The
ESR of a typical 1-µF ceramic capacitor is in the range of 20 mΩ to 40 mΩ, which easily meets the ESR
requirement for stability for the LP3869x.
Z5U and Y5V dielectric ceramics have capacitance that drops severely with applied voltage. A typical Z5U or
Y5V capacitor can lose 60% of its rated capacitance with half of the rated voltage applied to it. The Z5U and Y5V
also exhibit a severe temperature effect, losing more than 50% of nominal capacitance at high and low limits of
the temperature range.
X7R and X5R dielectric ceramic capacitors are strongly recommended if ceramics are used, as they typically
maintain a capacitance range within ±20% of nominal over full operating ratings of temperature and voltage. Of
course, they are typically larger and more costly than Z5U/Y5U types for a given voltage and capacitance.
14
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8.2.2.5.2 Tantalum Capacitors
Solid tantalum capacitors have good temperature stability: a high-quality tantalum capacitor typically shows a
capacitance value that varies less than 10-15% across the full temperature range of -40°C to 125°C. ESR will
vary only about 2× going from the high to low temperature limits.
The increasing ESR at lower temperatures can cause oscillations when marginal quality capacitors are used (if
the ESR of the capacitor is near the upper limit of the stability range at room temperature).
8.2.2.6 RFI/EMI Susceptibility
Radio frequency interference (RFI) and electromagnetic interference (EMI) can degrade the performance of any
integrated circuit because of the small dimensions of the geometries inside the device. In applications where
circuit sources are present which generate signals with significant high frequency energy content (> 1 MHz), care
must be taken to ensure that this does not affect the device regulator.
If RFI/EMI noise is present on the input side of the regulator (such as applications where the input source comes
from the output of a switching regulator), good ceramic bypass capacitors must be used at the input pin of the
device.
If a load is connected to the device output which switches at high speed (such as a clock), the high-frequency
current pulses required by the load must be supplied by the capacitors on the device output. Because the
bandwidth of the regulator loop is less than 100 kHz, the control circuitry cannot respond to load changes above
that frequency. This means the effective output impedance of the device at frequencies above 100 kHz is
determined only by the output capacitors.
In applications where the load is switching at high speed, the output of the device may need RF isolation from
the load. It is recommended that some inductance be placed between the output capacitor and the load, and
good RF bypass capacitors be placed directly across the load.
PCB layout is also critical in high noise environments, because RFI/EMI is easily radiated directly into PC traces.
Noisy circuitry should be isolated from clean circuits where possible, and grounded through a separate path. At
MHz frequencies, ground planes begin to look inductive and RFI/ EMI can cause ground bounce across the
ground plane. In multi-layer PCB applications, care should be taken in layout so that noisy power and ground
planes do not radiate directly into adjacent layers which carry analog power and ground.
8.2.2.7 Output Noise
Noise is specified in two ways:
•
Spot Noise or Output Noise Density is the RMS sum of all noise sources, measured at the regulator
output, at a specific frequency (measured with a 1-Hz bandwidth). This type of noise is usually plotted on
a curve as a function of frequency.
•
Total Output Noise or Broad-Band Noise is the RMS sum of spot noise over a specified bandwidth,
usually several decades of frequencies.
Attention should be paid to the units of measurement. Spot noise is measured in units µV√Hz or nV√Hz, and total
output noise is measured in µVRMS
.
The primary source of noise in low-dropout regulators is the internal reference. Noise can be reduced in two
ways: by increasing the transistor area or by increasing the current drawn by the internal reference. Increasing
the area will decrease the chance of fitting the die into a smaller package. Increasing the current drawn by the
internal reference increases the total supply current (GND pin current).
8.2.2.8 Power Dissipation
Knowing the device power dissipation and proper sizing of the thermal plane connected to the tab or pad is
critical to ensuring reliable operation. Device power dissipation depends on input voltage, output voltage, and
load conditions and can be calculated with Equation 2.
PD(MAX) = (VIN(MAX) – VOUT) × IOUT(MAX)
(2)
Power dissipation can be minimized, and greater efficiency can be achieved, by using the lowest available
voltage drop option that would still be greater than the dropout voltage (VDO). However, keep in mind that higher
voltage drops result in better dynamic (that is, PSRR and transient) performance.
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On the WSON (DRV) package, the primary conduction path for heat is through the exposed power pad to the
PCB. To ensure the device does not overheat, connect the exposed pad, through thermal vias, to an internal
ground plane with an appropriate amount of copper PCB area .
On the VSSOP (DGK) and SOT-223 (NDC) packages, the primary conduction path for heat is through the pins to
the PCB.
The maximum allowable junction temperature (TJ(MAX)) determines maximum power dissipation allowed (PD(MAX)
)
for the device package.
Power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance
(RθJA) of the combined PCB and device package and the temperature of the ambient air (TA), according to
Equation 3 or Equation 4:
TJ(MAX) = TA(MAX) + (RθJA × PD(MAX)
PD(MAX) = (TJ(MAX) - TA(MAX)) / RθJA
)
(3)
(4)
Unfortunately, this RθJA is highly dependent on the heat-spreading capability of the particular PCB design, and
therefore varies according to the total copper area, copper weight, and location of the planes. The RθJA recorded
in Thermal Information is determined by the specific EIA/JEDEC JESD51-7 standard for PCB and copper-
spreading area, and is to be used only as a relative measure of package thermal performance. For a well-
designed thermal layout, RθJA is actually the sum of the package junction-to-case (bottom) thermal resistance
(RθJCbot) plus the thermal resistance contribution by the PCB copper area acting as a heat sink.
8.2.2.9 Estimating Junction Temperature
The EIA/JEDEC standard recommends the use of psi (Ψ) thermal characteristics to estimate the junction
temperatures of surface mount devices on a typical PCB board application. These characteristics are not true
thermal resistance values, but rather package specific thermal characteristics that offer practical and relative
means of estimating junction temperatures. These psi metrics are determined to be significantly independent of
copper-spreading area. The key thermal characteristics (ΨJT and ΨJB) are given in Thermal Information and are
used in accordance with Equation 5 or Equation 6.
TJ(MAX) = TTOP + (ΨJT × PD(MAX)
)
where
•
•
PD(MAX) is explained in Equation 2.
TTOP is the temperature measured at the center-top of the device package.
(5)
TJ(MAX) = TBOARD + (ΨJB × PD(MAX)
)
where
•
•
PD(MAX) is explained in Equation 2.
TBOARD is the PCB surface temperature measured 1-mm from the device package and centered on the
package edge.
(6)
For more information about the thermal characteristics ΨJT and ΨJB, see the TI Application Report
Semiconductor and IC Package Thermal Metrics (SPRA953), available for download at www.ti.com.
For more information about measuring TTOP and TBOARD, see the TI Application Report Using New Thermal
Metrics (SBVA025), available for download at www.ti.com.
For more information about the EIA/JEDEC JESD51 PCB used for validating RθJA, see the TI Application Report
Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs (SZZA017), available for
download at www.ti.com.
16
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8.2.2.10 Reverse Voltage
A reverse voltage condition will exist when the voltage at the OUT pin is higher than the voltage at the IN pin.
Typically this will happen when VIN is abruptly taken low and COUT continues to hold a sufficient charge such that
the input to output voltage becomes reversed. A less common condition is when an alternate voltage source is
connected to the output.
There are two possible paths for current to flow from the OUT pin back to IN during a reverse voltage condition.
1. While VIN is high enough to keep the control circuity alive, and the EN pin (LP38693-ADJ only) is above the
VEN(ON) threshold, the control circuitry will attempt to regulate the output voltage. If the input voltage is less
than the programmed output voltage, the control circuit will drive the gate of the pass element to the full ON
condition. In this condition, reverse current will flow from the OUT to the IN pin, limited only by the RDS(ON) of
the pass element and the output to input voltage differential. Discharging an output capacitor up to 1000 μF
in this manner will not damage the device as the current will rapidly decay. However, continuous reverse
current should be avoided. When the EN pin is low, this condition will be prevented.
2. The internal PFET pass element has an inherent parasitic diode. During normal operation, the input voltage
is higher than the output voltage and the parasitic diode is reverse biased. However, when VIN is below the
value where the control circuity is alive, or the EN pin is low (LP38693-ADJ only), and the output voltage is
more than 500 mV (typical) above the input voltage the parasitic diode becomes forward biased and current
flows from the output pin to the input pin through the diode. The current in the parasitic diode should be
limited to less than 1-A continuous and 5-A peak.
If used in a dual-supply system where the regulator output load is returned to a negative supply, the OUT pin
must be diode clamped to ground to limit the negative voltage transition. A Schottky diode is recommended
for this protective clamp.
8.2.3 Application Curve
V
OUT
= 1.25V
40
20
0
C
OUT
= 10 mF
V
OUT
-20
-40
4
3
2
1
V
IN
200 ms/DIV
Figure 30. Line Transient Response
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9 Power Supply Recommendations
The LP3869x-ADJ devices are designed to operate from an input supply voltage range of 2.7 V to 10 V. The
input supply should be well regulated and free of spurious noise. To ensure that the device output voltage is well
regulated, input supply should be at least VOUT + 0.5 V, or 2.7 V, whichever is higher. A minimum capacitor value
of 1-μF is required to be within 1 cm of the IN pin.
10 Layout
10.1 Layout Guidelines
Good PC layout practices must be used or instability can be induced because of ground loops and voltage drops.
The input and output capacitors must be directly connected to the input, output, and ground pins of the regulator
using traces which do not have other currents flowing in them (Kelvin connect).
The best way to do this is to lay out CIN and COUT near the device with short traces to the IN, OUT, and GND
pins. The regulator ground pin should be connected to the external circuit ground so that the regulator and its
capacitors have a "single point ground."
It should be noted that stability problems have been seen in applications where "vias" to an internal ground plane
were used at the ground points of the device and the input and output capacitors. This was caused by varying
ground potentials at these nodes resulting from current flowing through the ground plane. Using a single point
ground technique for the regulator and its capacitors fixed the problem. Because high current flows through the
traces going into VIN and coming from VOUT, Kelvin connect the capacitor leads to these pins so there is no
voltage drop in series with the input and output capacitors.
10.2 Layout Examples
VIA connect to ground
layer
VIA connect to
ground layer
GND
IN
GND
EN
1
2
3
8
7
6
IN
COUT
CIN
Exposed Pad
on Bottom
(DAP)
OUT
ADJ
CIN
R1
R2
R2
R1
COUT
Figure 31. SOT-223 Layout
Figure 32. WSON LP38693 Layout
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ZHCSAZ8K –JANUARY 2005–REVISED JANUARY 2016
10.3 WSON Mounting
The NGG0006A (No Pullback) 6-Lead WSON package requires specific mounting techniques which are detailed
in the TI Application ReportLeadless Leadframe Package (LLP) SNOA401. Referring to the section PCB Design
Recommendations, it should be noted that the pad style which should be used with the WSON package is the
NSMD (non-solder mask defined) type. Additionally, it is recommended the PCB terminal pads to be 0.2 mm
longer than the package pads to create a solder fillet to improve reliability and inspection.
The thermal dissipation of the WSON package is directly related to the printed circuit board construction and the
amount of additional copper area connected to the DAP. The DAP (exposed pad) on the bottom of the WSON
package is connected to the die substrate with a conductive die attach adhesive. The DAP has no direct
electrical (wire) connection to any of the pins. There is a parasitic PN junction between the die substrate and the
device ground. As such, it is strongly recommend that the DAP be connected directly to the ground at device pin
2 (GND). Alternatively, but not recommended, the DAP may be left floating (no electrical connection). The DAP
must not be connected to any potential other than ground.
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11 器件和文档支持
11.1 文档支持
11.1.1 相关文档ꢀ
相关文档如下：
•
•
•
•
《无引线框架封装 (LLP)》（文献编号：SNOA401）
《半导体和 IC 封装热指标》(SPRA953)
《使用新的热指标》（文献编号：SBVA025）
《采用 JEDEC PCB 设计的线性和逻辑封装散热特性》(SZZA017)
11.2 相关链接
表 2 列出了快速访问链接。范围包括技术文档、支持和社区资源、工具和软件，以及样片或购买的快速访问。
表 2. 相关链接
器件
产品文件夹
请单击此处
请单击此处
请单击此处
请单击此处
样片与购买
请单击此处
请单击此处
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
请单击此处
请单击此处
工具与软件
请单击此处
请单击此处
请单击此处
请单击此处
支持与社区
请单击此处
请单击此处
请单击此处
请单击此处
LP38691-ADJ
LP38693-ADJ
LP38691-ADJ-Q1
LP38693-ADJ-Q1
11.3 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
20
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PACKAGE OPTION ADDENDUM
www.ti.com
23-Jun-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LP38691QSD-ADJ/NOPB
LP38691QSDX-ADJ/NOPB
LP38691SD-ADJ
ACTIVE
ACTIVE
NRND
WSON
WSON
WSON
NGG
NGG
NGG
6
6
6
1000 RoHS & Green
4500 RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
L251B
Samples
Samples
SN
L251B
L117B
1000
Non-RoHS
& Green
Call TI
LP38691SD-ADJ/NOPB
LP38691SDX-ADJ/NOPB
LP38693MP-ADJ/NOPB
LP38693MPX-ADJ/NOPB
LP38693QSD-ADJ/NOPB
LP38693QSDX-ADJ/NOPB
LP38693SD-ADJ/NOPB
LP38693SDX-ADJ/NOPB
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
WSON
WSON
SOT-223
SOT-223
WSON
WSON
WSON
WSON
NGG
NGG
NDC
NDC
NGG
NGG
NGG
NGG
6
6
5
5
6
6
6
6
1000 RoHS & Green
4500 RoHS & Green
1000 RoHS & Green
2000 RoHS & Green
1000 RoHS & Green
4500 RoHS & Green
1000 RoHS & Green
4500 RoHS & Green
NIPDAU | SN
NIPDAU | SN
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
L117B
L117B
LJUB
LJUB
LLRB
LLRB
L127B
L127B
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
SN
SN
SN
NIPDAU | SN
NIPDAU | SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
23-Jun-2023
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF LP38691-ADJ, LP38691-ADJ-Q1, LP38693-ADJ, LP38693-ADJ-Q1 :
Catalog : LP38691-ADJ, LP38693-ADJ
•
Automotive : LP38691-ADJ-Q1, LP38691-Q1, LP38691-Q1, LP38693-ADJ-Q1, LP38693-Q1, LP38693-Q1
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Feb-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LP38691QSD-ADJ/NOPB WSON
NGG
NGG
6
6
1000
4500
178.0
330.0
12.4
12.4
3.3
3.3
3.3
3.3
1.0
1.0
8.0
8.0
12.0
12.0
Q1
Q1
LP38691QSDX-
ADJ/NOPB
WSON
LP38691SD-ADJ
WSON
NGG
NGG
NGG
6
6
6
5
5
6
6
1000
1000
4500
1000
2000
1000
4500
178.0
178.0
330.0
330.0
330.0
178.0
330.0
12.4
12.4
12.4
16.4
16.4
12.4
12.4
3.3
3.3
3.3
7.0
7.0
3.3
3.3
3.3
3.3
3.3
7.5
7.5
3.3
3.3
1.0
1.0
1.0
2.2
2.2
1.0
1.0
8.0
8.0
12.0
12.0
12.0
16.0
16.0
12.0
12.0
Q1
Q1
Q1
Q3
Q3
Q1
Q1
LP38691SD-ADJ/NOPB WSON
LP38691SDX-ADJ/NOPB WSON
8.0
LP38693MP-ADJ/NOPB SOT-223 NDC
LP38693MPX-ADJ/NOPB SOT-223 NDC
12.0
12.0
8.0
LP38693QSD-ADJ/NOPB WSON
NGG
NGG
LP38693QSDX-
ADJ/NOPB
WSON
8.0
LP38693SD-ADJ/NOPB WSON
LP38693SDX-ADJ/NOPB WSON
NGG
NGG
6
6
1000
4500
178.0
330.0
12.4
12.4
3.3
3.3
3.3
3.3
1.0
1.0
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Feb-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LP38691QSD-ADJ/NOPB
LP38691QSDX-ADJ/NOPB
LP38691SD-ADJ
WSON
WSON
WSON
WSON
WSON
SOT-223
SOT-223
WSON
WSON
WSON
WSON
NGG
NGG
NGG
NGG
NGG
NDC
NDC
NGG
NGG
NGG
NGG
6
6
6
6
6
5
5
6
6
6
6
1000
4500
1000
1000
4500
1000
2000
1000
4500
1000
4500
208.0
367.0
208.0
208.0
367.0
367.0
367.0
208.0
367.0
208.0
367.0
191.0
367.0
191.0
191.0
367.0
367.0
367.0
191.0
367.0
191.0
367.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
LP38691SD-ADJ/NOPB
LP38691SDX-ADJ/NOPB
LP38693MP-ADJ/NOPB
LP38693MPX-ADJ/NOPB
LP38693QSD-ADJ/NOPB
LP38693QSDX-ADJ/NOPB
LP38693SD-ADJ/NOPB
LP38693SDX-ADJ/NOPB
Pack Materials-Page 2
MECHANICAL DATA
NDC0005A
www.ti.com
MECHANICAL DATA
NGG0006A
SDE06A (Rev A)
www.ti.com
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