LP3875ES-2.5/NOPB [TI]
LP3872/LP3875 1.5A Fast Ultra Low Dropout Linear Regulators; LP3872 / LP3875 1.5A快速超低压降线性稳压器
| 型号： | LP3875ES-2.5/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LP3872/LP3875 1.5A Fast Ultra Low Dropout Linear Regulators |
| 文件： | 总25页 (文件大小：2750K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LP3872, LP3875
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SNVS227F –FEBRUARY 2003–REVISED APRIL 2013
LP3872/LP3875 1.5A Fast Ultra Low Dropout Linear Regulators
Check for Samples: LP3872, LP3875
1
FEATURES
DESCRIPTION
The LP3872/LP3875 series of fast ultra low-dropout
linear regulators operate from a +2.5V to +7.0V input
supply. Wide range of preset output voltage options
are available. These ultra low dropout linear
regulators respond very quickly to step changes in
load, which makes them suitable for low voltage
microprocessor applications. The LP3872/LP3875 are
developed on a CMOS process which allows low
quiescent current operation independent of output
load current. This CMOS process also allows the
LP3872/LP3875 to operate under extremely low
dropout conditions.
2
•
•
•
•
•
•
Ultra Low Dropout Voltage
Low Ground Pin Current
Load Regulation of 0.06%
10nA Quiescent Current in Shutdown Mode
Ensured Output Current of 1.5A DC
Available in DDPAK/TO-263, TO-220 and
SOT-223 Packages
•
•
•
•
•
•
Output Voltage Accuracy ± 1.5%
Error Flag Indicates Output Status
Sense Option Improves Load Regulation
Minimum Output Capacitor Requirements
Overtemperature/Overcurrent Protection
−40°C to +125°C Junction Temperature Range
Dropout Voltage: Ultra low dropout voltage; typically
38mV at 150mA load current and 380mV at 1.5A load
current.
Ground Pin Current: Typically 6mA at 1.5A load
current.
APPLICATIONS
Shutdown Mode: Typically 10nA quiescent current
when the shutdown pin is pulled low.
•
•
•
•
•
•
•
•
Microprocessor Power Supplies
GTL, GTL+, BTL, and SSTL Bus Terminators
Power Supplies for DSPs
SCSI Terminator
Error Flag: Error flag goes low when the output
voltage drops 10% below nominal value.
SENSE: Sense pin improves regulation at remote
loads.
Post Regulators
High Efficiency Linear Regulators
Battery Chargers
Precision Output Voltage: Multiple output voltage
options are available ranging from 1.8V to 5.0V with a
specified accuracy of ±1.5% at room temperature,
and ±3.0% over all conditions (varying line, load, and
temperature).
Other Battery Powered Applications
TYPICAL APPLICATION CIRCUITS
*SD and ERROR pins must be pulled high through a 10kΩ pull-up resistor. Connect the ERROR pin to ground if this
function is not used. See application hints for more information.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
*SD must be pulled high through a 10kΩ pull-up resistor. See application hints for more information.
CONNECTION DIAGRAM
Figure 1. 5-Pin TO-220 (Top View)
See NDH0005D Package
Figure 2. 5-+Pin DDPAK/TO-263 (Top View)
See KTT Package
GND
5
1
2
3
4
ERROR
/SENSE
VIN VOUT
SD
Figure 3. 5-Pin SOT-223 (Top View)
See NDC0005A Package
Table 1. Pin Descriptions for TO-220 and DDPAK/TO-263 Packages
LP3872
LP3875
Pin #
Name
SD
Function
Shutdown
Name
SD
Function
1
2
3
4
5
Shutdown
VIN
Input Supply
Ground
VIN
Input Supply
Ground
GND
VOUT
ERROR
GND
VOUT
SENSE
Output Voltage
ERROR Flag
Output Voltage
Remote Sense Pin
Table 2. Pin Descriptions for SOT-223 Package
LP3872
LP3875
Pin #
Name
SD
Function
Name
SD
Function
1
2
3
4
Shutdown
Shutdown
VIN
Input Supply
Output Voltage
ERROR Flag
VIN
Input Supply
Output Voltage
Remote Sense Pin
VOUT
ERROR
VOUT
SENSE
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Table 2. Pin Descriptions for SOT-223 Package (continued)
LP3872
LP3875
Pin #
Name
Function
Name
Function
5
GND
Ground
GND
Ground
BLOCK DIAGRAM
Figure 4. LP3872
Figure 5. LP3875
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(1)
ABSOLUTE MAXIMUM RATINGS
If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/Distributors for
availability and specifications.
VALUE / UNITS
Storage Temperature Range
−65°C to +150°C
260°C
Lead Temperature (Soldering, 5 sec.)
(2)
ESD Rating
2 kV
(3)
Power Dissipation
Internally Limited
−0.3V to +7.5V
−0.3V to +7.5V
−0.3V to +6.0V
Short Circuit Protected
VIN
Input Supply Voltage (Survival)
Shutdown Input Voltage (Survival)
(4) (5)
Output Voltage (Survival),
IOUT (Survival)
,
Maximum Voltage for ERROR Pin
Maximum Voltage for SENSE Pin
VOUT
(1) Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating ratings indicate conditions for which
the device is intended to be functional, but does not ensure specific performance limits. For specifications and test conditions, see
Electrical Characteristics. The specifications apply only for the test conditions listed. Some performance characteristics may degrade
when the device is not operated under the listed test conditions.
(2) The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin.
(3) At elevated temperatures, devices must be derated based on package thermal resistance. The devices in TO-220 package must be
derated at θjA = 50°C/W (with 0.5in2, 1oz. copper area), junction-to-ambient (with no heat sink). The devices in the DDPAK/TO-263
surface-mount package must be derated at θjA = 60°C/W (with 0.5in2, 1oz. copper area), junction-to-ambient. The SOT-223 package
must be derated at θjA = 90°C/W (with 0.5in2, 1oz. copper area), junction-to-ambient.
(4) If used in a dual-supply system where the regulator load is returned to a negative supply, the output must be diode-clamped to ground.
(5) The output PMOS structure contains a diode between the VIN and VOUT terminals. This diode is normally reverse biased. This diode will
get forward biased if the voltage at the output terminal is forced to be higher than the voltage at the input terminal. This diode can
typically withstand 200mA of DC current and 1Amp of peak current.
RECOMMENDED OPERATING CONDITIONS
VALUE / UNITS
(1)
Input Supply Voltage
2.5V to 7.0V
−0.3V to 7.0V
1.5A
Shutdown Input Voltage
Maximum Operating Current (DC)
Junction Temperature
−40°C to +125°C
(1) The minimum operating value for VIN is equal to either [VOUT(NOM) + VDROPOUT] or 2.5V, whichever is greater.
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ELECTRICAL CHARACTERISTICS – LP3872/LP3875
Limits in standard typeface are for TJ = 25°C, and limits in boldface type apply over the full operating temperature range.
Unless otherwise specified: VIN = VO(NOM) + 1V, IL = 10 mA, COUT = 10µF, VSD = 2V.
(1)
(2)
Typ
LP3872/5
Symbol
VO
Parameter
Conditions
Units
Min
Max
(3)
Output Voltage Tolerance
-1.5
-3.0
+1.5
+3.0
VOUT +1V ≤ VIN ≤ 7.0V, 10 mA ≤ IL ≤ 1.5A
VOUT + 1V ≤ VIN ≤ 7.0V
10 mA ≤ IL ≤ 1.5A
IL = 150 mA
0
%
%
%
(3)
Output Voltage Line Regulation
Output Voltage Load Regulation
0.02
0.06
ΔV OL
(3)
ΔVO/
ΔIOUT
0.06
0.12
50
60
38
380
5
VIN
-
(4)
Dropout Voltage
mV
mA
VOUT
450
550
IL = 1.5A
9
10
IL = 150 mA
Ground Pin Current In Normal
Operation Mode
IGND
14
15
IL = 1.5A
6
Ground Pin Current In Shutdown
Mode
V
SD ≤ 0.3V
-40°C ≤ TJ ≤ 85°C
O ≥ VO(NOM) - 4%
0.01
10
µA
A
IGND
50
IO(PK)
Peak Output Current
V
1.8
3.2
Short Circuit Protection
ISC
Short Circuit Current
A
Shutdown Input
Output = High
Output = Low
IL = 1.5A
VIN
0
2
VSDT
Shutdown Threshold
V
0.3
TdOFF
TdON
ISD
Turn-off delay
Turn-on delay
SD Input Current
20
25
1
µs
µs
nA
IL = 1.5A
VSD = VIN
Error Flag
VT
(5)
Threshold
See
10
5
5
2
16
8
%
%
(5)
VTH
Threshold Hysteresis
Error Flag Saturation
Flag Reset Delay
See
VEF(Sat)
Td
Isink = 100µA
0.02
1
0.1
V
µs
nA
mA
Ilk
Error Flag Pin Leakage Current
Error Flag Pin Sink Current
1
Imax
VError = 0.5V
1
AC Parameters
VIN = VOUT + 1V, COUT = 10µF
VOUT = 3.3V, f = 120Hz
73
57
PSRR
Ripple Rejection
dB
µV
VIN = VOUT + 0.5V, COUT = 10µF
VOUT = 3.3V, f = 120Hz
ρn(l/f)
Output Noise Density
Output Noise Voltage
f = 120Hz
0.8
150
100
BW = 10Hz – 100kHz, VOUT = 2.5V
BW = 300Hz – 300kH, VOUT = 2.5V
µV
(rms)
en
(1) Typical numbers are at 25°C and represent the most likely parametric norm.
(2) Limits are specified by testing, design, or statistical correlation.
(3) Output voltage line regulation is defined as the change in output voltage from the nominal value due to change in the input line voltage.
Output voltage load regulation is defined as the change in output voltage from the nominal value due to change in load current. The line
and load regulation specification contains only the typical number. However, the limits for line and load regulation are included in the
output voltage tolerance specification.
(4) Dropout voltage is defined as the minimum input to output differential voltage at which the output drops 2% below the nominal value.
Dropout voltage specification applies only to output voltages of 2.5V and above. For output voltages below 2.5V, the drop-out voltage is
nothing but the input to output differential, since the minimum input voltage is 2.5V.
(5) Error Flag threshold and hysteresis are specified as percentage of regulated output voltage. See Application Hints.
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TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise specified: TJ = 25°C, COUT = 10µF, CIN = 10µF, S/D pin is tied to VIN, VOUT = 2.5V, VIN = VO(NOM) + 1V,
IL = 10mA
Ground Current vs Output Voltage
Dropout Voltage vs Output Load Current
IL = 1.5A
6
5
4
3
2
1
0
600
500
400
300
200
100
0
0
0.5
1
1.5
1.8
2.3
2.8
3.3
3.8
4.3
5.0
OUTPUT LOAD CURRENT (A)
OUTPUT VOLTAGE (V)
Figure 6.
Figure 7.
Shutdown IQ vs Junction Temperature
Errorflag Threshold vs Junction Temperature
14
10
12
10
8
1
0.1
6
4
0.01
2
0
0.001
-40 -20
0
20 40 60 80 100 125
-40 -20
0
20 40 60 80 100 125
TEMPERATURE (oC)
Figure 8.
JUNCTION TEMPERATURE (oC)
Figure 9.
DC Load Reg. vs Junction Temperature
3
DC Line Regulation vs Temperature
3
2.5
2
2.5
2
1.5
1
1.5
1
0.5
0
0.5
0
-40 -20
0
20 40 60 80 100 125
-40 -20
0
20 40 60 80 100 125
JUNCTION TEMPERATURE (oC)
JUNCTION TEMPERATURE (oC)
Figure 10.
Figure 11.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise specified: TJ = 25°C, COUT = 10µF, CIN = 10µF, S/D pin is tied to VIN, VOUT = 2.5V, VIN = VO(NOM) + 1V,
IL = 10mA
Load Transient Response
CIN = COUT = 10µF, OSCON
Noise vs Frequency
3.000
2.500
2.000
1.500
1.000
0.500
0.000
VOUT
100mV/DIV
IL = 100mA
CIN = COUT = 10mF
ILOAD
1A/DIV
100
1k
10k
100k
TIME (50ms/DIV)
FREQUENCY (Hz)
Figure 12.
Figure 13.
Load Transient Response
CIN =COUT = 100µF, OSCON
Load Transient Response
CIN =COUT = 100µF, POSCAP
VOUT
100mV/DIV
VOUT
100mV/DIV
ILOAD
1A/DIV
ILOAD
1A/DIV
TIME (50ms/DIV)
TIME (50ms/DIV)
Figure 14.
Figure 15.
Load Transient Response
CIN =COUT = 10µF, TANTALUM
Load Transient Response
CIN =COUT = 100µF, TANTALUM
VOUT
100mV/DIV
VOUT
100mV/DIV
ILOAD
1A/DIV
ILOAD
1A/DIV
TIME (50ms/DIV)
TIME (50ms/DIV)
Figure 16.
Figure 17.
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Application Hints
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EXTERNAL CAPACITORS
Like any low-dropout regulator, external capacitors are required to assure stability. These capacitors must be
correctly selected for proper performance.
INPUT CAPACITOR: An input capacitor of at least 10µF is required. Ceramic, Tantalum, or Electrolytic
capacitors may be used, and capacitance may be increased without limit
OUTPUT CAPACITOR: An output capacitor is required for loop stability. It must be located less than 1 cm from
the device and connected directly to the output and ground pins using traces which have no other currents
flowing through them (see PCB Layout section).
The minimum value of output capacitance that can be used for stable full-load operation is 10µF, but it may be
increased without limit. The output capacitor must have an ESR value as shown in the stable region of the curve
below. Tantalum capacitors are recommended for the output capacitor.
10
COUT > 10 mF
STABLE REGION
1.0
0.1
.01
.001
0
1
2
LOAD CURRENT (A)
Figure 18. ESR Curve
SELECTING A CAPACITOR
It is important to note that capacitance tolerance and variation with temperature must be taken into consideration
when selecting a capacitor so that the minimum required amount of capacitance is provided over the full
operating temperature range. In general, a good Tantalum capacitor will show very little capacitance variation
with temperature, but a ceramic may not be as good (depending on dielectric type). Aluminum electrolytics also
typically have large temperature variation of capacitance value.
Equally important to consider is a capacitor's ESR change with temperature: this is not an issue with ceramics,
as their ESR is extremely low. However, it is very important in Tantalum and aluminum electrolytic capacitors.
Both show increasing ESR at colder temperatures, but the increase in aluminum electrolytic capacitors is so
severe they may not be feasible for some applications (see Capacitor Characteristics Section).
CAPACITOR CHARACTERISTICS
CERAMIC: For values of capacitance in the 10 to 100 µF range, ceramics are usually larger and more costly
than tantalums but give superior AC performance for bypassing high frequency noise because of very low ESR
(typically less than 10 mΩ). However, some dielectric types do not have good capacitance characteristics as a
function of voltage and temperature.
Z5U and Y5V dielectric ceramics have capacitance that drops severely with applied voltage. A typical Z5U or
Y5V capacitor can lose 60% of its rated capacitance with half of the rated voltage applied to it. The Z5U and Y5V
also exhibit a severe temperature effect, losing more than 50% of nominal capacitance at high and low limits of
the temperature range.
X7R and X5R dielectric ceramic capacitors are strongly recommended if ceramics are used, as they typically
maintain a capacitance range within ±20% of nominal over full operating ratings of temperature and voltage. Of
course, they are typically larger and more costly than Z5U/Y5U types for a given voltage and capacitance.
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TANTALUM: Solid Tantalum capacitors are recommended for use on the output because their typical ESR is
very close to the ideal value required for loop compensation. They also work well as input capacitors if selected
to meet the ESR requirements previously listed.
Tantalums also have good temperature stability: a good quality Tantalum will typically show a capacitance value
that varies less than 10-15% across the full temperature range of 125°C to −40°C. ESR will vary only about 2X
going from the high to low temperature limits.
The increasing ESR at lower temperatures can cause oscillations when marginal quality capacitors are used (if
the ESR of the capacitor is near the upper limit of the stability range at room temperature).
ALUMINUM: This capacitor type offers the most capacitance for the money. The disadvantages are that they are
larger in physical size, not widely available in surface mount, and have poor AC performance (especially at
higher frequencies) due to higher ESR and ESL.
Compared by size, the ESR of an aluminum electrolytic is higher than either Tantalum or ceramic, and it also
varies greatly with temperature. A typical aluminum electrolytic can exhibit an ESR increase of as much as 50X
when going from 25°C down to −40°C.
It should also be noted that many aluminum electrolytics only specify impedance at a frequency of 120 Hz, which
indicates they have poor high frequency performance. Only aluminum electrolytics that have an impedance
specified at a higher frequency (between 20 kHz and 100 kHz) should be used for the LP387X. Derating must be
applied to the manufacturer's ESR specification, since it is typically only valid at room temperature.
Any applications using aluminum electrolytics should be thoroughly tested at the lowest ambient operating
temperature where ESR is maximum.
TURN-ON CHARACTERISTICS FOR OUTPUT VOLTAGES PROGRAMMED TO 2.0V OR BELOW
As Vin increases during start-up, the regulator output will track the input until Vin reaches the minimum operating
voltage (typically about 2.2V). For output voltages programmed to 2.0V or below, the regulator output may
momentarily exceed its programmed output voltage during start up. Outputs programmed to voltages above 2.0V
are not affected by this behavior.
PCB LAYOUT
Good PC layout practices must be used or instability can be induced because of ground loops and voltage drops.
The input and output capacitors must be directly connected to the input, output, and ground pins of the regulator
using traces which do not have other currents flowing in them (Kelvin connect).
The best way to do this is to lay out CIN and COUT near the device with short traces to the VIN, VOUT, and ground
pins. The regulator ground pin should be connected to the external circuit ground so that the regulator and its
capacitors have a "single point ground".
It should be noted that stability problems have been seen in applications where "vias" to an internal ground plane
were used at the ground points of the IC and the input and output capacitors. This was caused by varying ground
potentials at these nodes resulting from current flowing through the ground plane. Using a single point ground
technique for the regulator and it's capacitors fixed the problem.
Since high current flows through the traces going into VIN and coming from VOUT, Kelvin connect the capacitor
leads to these pins so there is no voltage drop in series with the input and output capacitors.
RFI/EMI SUSCEPTIBILITY
RFI (radio frequency interference) and EMI (electromagnetic interference) can degrade any integrated circuit's
performance because of the small dimensions of the geometries inside the device. In applications where circuit
sources are present which generate signals with significant high frequency energy content (> 1 MHz), care must
be taken to ensure that this does not affect the IC regulator.
If RFI/EMI noise is present on the input side of the regulator (such as applications where the input source comes
from the output of a switching regulator), good ceramic bypass capacitors must be used at the input pin of the IC.
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If a load is connected to the IC output which switches at high speed (such as a clock), the high-frequency current
pulses required by the load must be supplied by the capacitors on the IC output. Since the bandwidth of the
regulator loop is less than 100 kHz, the control circuitry cannot respond to load changes above that frequency.
This means the effective output impedance of the IC at frequencies above 100 kHz is determined only by the
output capacitor(s).
In applications where the load is switching at high speed, the output of the IC may need RF isolation from the
load. It is recommended that some inductance be placed between the output capacitor and the load, and good
RF bypass capacitors be placed directly across the load.
PCB layout is also critical in high noise environments, since RFI/EMI is easily radiated directly into PC traces.
Noisy circuitry should be isolated from "clean" circuits where possible, and grounded through a separate path. At
MHz frequencies, ground planes begin to look inductive and RFI/EMI can cause ground bounce across the
ground plane.
In multi-layer PCB applications, care should be taken in layout so that noisy power and ground planes do not
radiate directly into adjacent layers which carry analog power and ground.
OUTPUT NOISE
Noise is specified in two ways-
Spot Noise or Output noise density is the RMS sum of all noise sources, measured at the regulator output, at
a specific frequency (measured with a 1Hz bandwidth). This type of noise is usually plotted on a curve as a
function of frequency.
Total output Noise or Broad-band noise is the RMS sum of spot noise over a specified bandwidth, usually
several decades of frequencies.
Attention should be paid to the units of measurement. Spot noise is measured in units µV/√Hz or nV/√Hz and
total output noise is measured in µV(rms).
The primary source of noise in low-dropout regulators is the internal reference. In CMOS regulators, noise has a
low frequency component and a high frequency component, which depend strongly on the silicon area and
quiescent current. Noise can be reduced in two ways: by increasing the transistor area or by increasing the
current drawn by the internal reference. Increasing the area will decrease the chance of fitting the die into a
smaller package. Increasing the current drawn by the internal reference increases the total supply current
(ground pin current). Using an optimized trade-off of ground pin current and die size, LP3872/LP3875 achieves
low noise performance and low quiescent current operation.
The total output noise specification for LP3872/LP3875 is presented in the Electrical Characteristics table. The
Output noise density at different frequencies is represented by a curve under typical performance characteristics.
SHORT-CIRCUIT PROTECTION
The LP3872 and LP3875 are short circuit protected and in the event of a peak over-current condition, the short-
circuit control loop will rapidly drive the output PMOS pass element off. Once the power pass element shuts
down, the control loop will rapidly cycle the output on and off until the average power dissipation causes the
thermal shutdown circuit to respond to servo the on/off cycling to a lower frequency. Please refer to the section
on thermal information for power dissipation calculations.
ERROR FLAG OPERATION
The LP3872/LP3875 produces a logic low signal at the Error Flag pin when the output drops out of regulation
due to low input voltage, current limiting, or thermal limiting. This flag has a built in hysteresis. The timing
diagram in Figure 19 shows the relationship between the ERROR flag and the output voltage. In this example,
the input voltage is changed to demonstrate the functionality of the Error Flag.
The internal Error flag comparator has an open drain output stage. Hence, the ERROR pin should be pulled high
through a pull up resistor. Although the ERROR flag pin can sink current of 1mA, this current is energy drain
from the input supply. Hence, the value of the pull up resistor should be in the range of 10kΩ to 1MΩ. The
ERROR pin must be connected to ground if this function is not used. It should also be noted that when the
shutdown pin is pulled low, the ERROR pin is forced to be invalid for reasons of saving power in shutdown
mode.
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Figure 19. Error Flag Operation
SENSE PIN
In applications where the regulator output is not very close to the load, LP3875 can provide better remote load
regulation using the SENSE pin. Figure 20 depicts the advantage of the SENSE option. LP3872 regulates the
voltage at the output pin. Hence, the voltage at the remote load will be the regulator output voltage minus the
drop across the trace resistance. For example, in the case of a 3.3V output, if the trace resistance is 100mΩ, the
voltage at the remote load will be 3.15V with 1.5A of load current, ILOAD. The LP3875 regulates the voltage at the
sense pin. Connecting the sense pin to the remote load will provide regulation at the remote load, as shown in
Figure 20. If the sense option pin is not required, the sense pin must be connected to the VOUT pin.
Figure 20. Improving Remote Load Regulation Using LP3875
SHUTDOWN OPERATION
A CMOS Logic level signal at the shutdown ( SD) pin will turn-off the regulator. Pin SD must be actively
terminated through a 10kΩ pull-up resistor for a proper operation. If this pin is driven from a source that actively
pulls high and low (such as a CMOS rail to rail comparator), the pull-up resistor is not required. This pin must be
tied to Vin if not used.
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www.ti.com
DROPOUT VOLTAGE
The dropout voltage of a regulator is defined as the minimum input-to-output differential required to stay within
2% of the nominal output voltage. For CMOS LDOs, the dropout voltage is the product of the load current and
the Rds(on) of the internal MOSFET.
REVERSE CURRENT PATH
The internal MOSFET in LP3872 and LP3875 has an inherent parasitic diode. During normal operation, the input
voltage is higher than the output voltage and the parasitic diode is reverse biased. However, if the output is
pulled above the input in an application, then current flows from the output to the input as the parasitic diode gets
forward biased. The output can be pulled above the input as long as the current in the parasitic diode is limited to
200mA continuous and 1A peak.
POWER DISSIPATION/HEATSINKING
LP3872 and LP3875 can deliver a continuous current of 1.5A over the full operating temperature range. A
heatsink may be required depending on the maximum power dissipation and maximum ambient temperature of
the application. Under all possible conditions, the junction temperature must be within the range specified under
operating conditions. The total power dissipation of the device is given by:
PD = (VIN−VOUT)IOUT+ (VIN)IGND
where IGND is the operating ground current of the device (specified under Electrical Characteristics).
The maximum allowable temperature rise (TRmax) depends on the maximum ambient temperature (TAmax) of the
application, and the maximum allowable junction temperature (TJmax): TRmax = TJmax− TAmax
The maximum allowable value for junction to ambient Thermal Resistance, θJA, can be calculated using the
formula:
θJA = TRmax / PD
LP3872 and LP3875 are available in TO-220 and DDPAK/TO-263 packages. The thermal resistance depends on
amount of copper area or heat sink, and on air flow. If the maximum allowable value of θJA calculated above is ≥
60 °C/W for TO-220 package and ≥ 60 °C/W for DDPAK/TO-263 package no heatsink is needed since the
package can dissipate enough heat to satisfy these requirements. If the value for allowable θJA falls below these
limits, a heat sink is required.
HEATSINKING TO-220 PACKAGE
The thermal resistance of a TO-220 package can be reduced by attaching it to a heat sink or a copper plane on
a PC board. If a copper plane is to be used, the values of θJA will be same as shown in next section for
DDPAK/TO-263 package.
The heatsink to be used in the application should have a heatsink to ambient thermal resistance,θHA≤ θJA − θCH
θJC.
−
In this equation, θCH is the thermal resistance from the case to the surface of the heat sink and θJC is the thermal
resistance from the junction to the surface of the case. θJC is about 3°C/W for a TO-220 package. The value for
θCH depends on method of attachment, insulator, etc. θCH varies between 1.5°C/W to 2.5°C/W. If the exact value
is unknown, 2°C/W can be assumed.
HEATSINKING DDPAK/TO-263 PACKAGE
The DDPAK/TO-263 package uses the copper plane on the PCB as a heatsink. The tab of these packages are
soldered to the copper plane for heat sinking. Figure 21 shows a curve for the θJA of DDPAK/TO-263 package for
different copper area sizes, using a typical PCB with 1 ounce copper and no solder mask over the copper area
for heat sinking.
12
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Copyright © 2003–2013, Texas Instruments Incorporated
Product Folder Links: LP3872 LP3875
LP3872, LP3875
www.ti.com
SNVS227F –FEBRUARY 2003–REVISED APRIL 2013
Figure 21. θJA vs Copper (1 Ounce) Area for DDPAK/TO-263 package
As shown in the figure, increasing the copper area beyond 1 square inch produces very little improvement. The
minimum value for θJA for the DDPAK/TO-263 package mounted to a PCB is 32°C/W.
Figure 22 shows the maximum allowable power dissipation for DDPAK/TO-263 packages for different ambient
temperatures, assuming θJA is 35°C/W and the maximum junction temperature is 125°C.
Figure 22. Maximum power dissipation vs ambient temperature for DDPAK/TO-263 package
HEATSINKING SOT-223 PACKAGE
Figure 23 shows a curve for the θJA of SOT-223 package for different copper area sizes, using a typical PCB with
1 ounce copper and no solder mask over the copper area for heat sinking.
Figure 23. θJA vs Copper(1 Ounce) Area for SOT-223 package
The following figures show different layout scenarios for SOT-223 package.
Copyright © 2003–2013, Texas Instruments Incorporated
Submit Documentation Feedback
13
Product Folder Links: LP3872 LP3875
LP3872, LP3875
SNVS227F –FEBRUARY 2003–REVISED APRIL 2013
www.ti.com
Figure 24. SCENARIO A, θJA = 148°C/W
Figure 25. SCENARIO B, θJA = 125°C/W
14
Submit Documentation Feedback
Copyright © 2003–2013, Texas Instruments Incorporated
Product Folder Links: LP3872 LP3875
LP3872, LP3875
www.ti.com
SNVS227F –FEBRUARY 2003–REVISED APRIL 2013
REVISION HISTORY
Changes from Revision E (April 2013) to Revision F
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 13
Copyright © 2003–2013, Texas Instruments Incorporated
Submit Documentation Feedback
15
Product Folder Links: LP3872 LP3875
PACKAGE OPTION ADDENDUM
www.ti.com
1-Nov-2013
PACKAGING INFORMATION
Orderable Device
LP3872EMP-1.8/NOPB
LP3872EMP-2.5/NOPB
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
SOT-223
SOT-223
NDC
5
5
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
LHAB
LHBB
ACTIVE
NDC
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LP3872EMP-3.3
NRND
SOT-223
SOT-223
NDC
NDC
5
5
1000
1000
TBD
Call TI
CU SN
Call TI
-40 to 125
-40 to 125
LHCB
LHCB
LP3872EMP-3.3/NOPB
ACTIVE
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
LP3872EMP-5.0
NRND
SOT-223
SOT-223
NDC
NDC
5
5
1000
1000
TBD
Call TI
CU SN
Call TI
-40 to 125
-40 to 125
LHDB
LHDB
LP3872EMP-5.0/NOPB
ACTIVE
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
LP3872EMPX-2.5/NOPB
LP3872EMPX-3.3/NOPB
LP3872ES-1.8
ACTIVE
ACTIVE
NRND
SOT-223
SOT-223
NDC
NDC
KTT
KTT
KTT
KTT
KTT
KTT
KTT
KTT
KTT
KTT
5
5
5
5
5
5
5
5
5
5
5
5
2000
2000
45
Green (RoHS
& no Sb/Br)
CU SN
CU SN
Call TI
CU SN
Call TI
CU SN
Call TI
CU SN
Call TI
CU SN
CU SN
CU SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Call TI
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
LHBB
LHCB
Green (RoHS
& no Sb/Br)
DDPAK/
TO-263
TBD
LP3872ES
-1.8
LP3872ES-1.8/NOPB
LP3872ES-2.5
ACTIVE
NRND
DDPAK/
TO-263
45
Pb-Free (RoHS
Exempt)
Level-3-245C-168 HR
Call TI
LP3872ES
-1.8
DDPAK/
TO-263
45
TBD
LP3872ES
-2.5
LP3872ES-2.5/NOPB
LP3872ES-3.3
ACTIVE
NRND
DDPAK/
TO-263
45
Pb-Free (RoHS
Exempt)
Level-3-245C-168 HR
Call TI
LP3872ES
-2.5
DDPAK/
TO-263
45
TBD
LP3872ES
-3.3
LP3872ES-3.3/NOPB
LP3872ES-5.0
ACTIVE
NRND
DDPAK/
TO-263
45
Pb-Free (RoHS
Exempt)
Level-3-245C-168 HR
Call TI
LP3872ES
-3.3
DDPAK/
TO-263
45
TBD
LP3872ES
-5.0
LP3872ES-5.0/NOPB
LP3872ESX-1.8/NOPB
LP3872ESX-2.5/NOPB
ACTIVE
ACTIVE
ACTIVE
DDPAK/
TO-263
45
Pb-Free (RoHS
Exempt)
Level-3-245C-168 HR
Level-3-245C-168 HR
Level-3-245C-168 HR
LP3872ES
-5.0
DDPAK/
TO-263
500
500
Pb-Free (RoHS
Exempt)
LP3872ES
-1.8
DDPAK/
TO-263
Pb-Free (RoHS
Exempt)
LP3872ES
-2.5
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
1-Nov-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
LP3872ESX-3.3/NOPB
LP3872ESX-5.0/NOPB
LP3875EMP-1.8/NOPB
LP3875EMP-2.5/NOPB
LP3875EMP-3.3/NOPB
ACTIVE
DDPAK/
TO-263
KTT
5
5
5
5
5
500
Pb-Free (RoHS
Exempt)
CU SN
CU SN
CU SN
CU SN
CU SN
Level-3-245C-168 HR
Level-3-245C-168 HR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
LP3872ES
-3.3
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DDPAK/
TO-263
KTT
NDC
NDC
NDC
500
Pb-Free (RoHS
Exempt)
LP3872ES
-5.0
SOT-223
SOT-223
SOT-223
1000
1000
1000
Green (RoHS
& no Sb/Br)
LHLB
LHNB
LHPB
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
LP3875EMP-5.0
NRND
SOT-223
SOT-223
NDC
NDC
5
5
1000
1000
TBD
Call TI
CU SN
Call TI
-40 to 125
-40 to 125
LHRB
LHRB
LP3875EMP-5.0/NOPB
ACTIVE
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
LP3875ES-1.8/NOPB
LP3875ES-2.5
ACTIVE
NRND
DDPAK/
TO-263
KTT
KTT
KTT
KTT
KTT
KTT
KTT
KTT
NDH
5
5
5
5
5
5
5
5
5
45
45
Pb-Free (RoHS
Exempt)
CU SN
Call TI
CU SN
Call TI
CU SN
CU SN
CU SN
CU SN
CU SN
Level-3-245C-168 HR
Call TI
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
LP3875ES
-1.8
DDPAK/
TO-263
TBD
LP3875ES
-2.5
LP3875ES-2.5/NOPB
LP3875ES-3.3
ACTIVE
NRND
DDPAK/
TO-263
45
Pb-Free (RoHS
Exempt)
Level-3-245C-168 HR
Call TI
LP3875ES
-2.5
DDPAK/
TO-263
45
TBD
LP3875ES
-3.3
LP3875ES-3.3/NOPB
LP3875ESX-1.8/NOPB
LP3875ESX-2.5/NOPB
LP3875ESX-3.3/NOPB
LP3875ET-3.3/NOPB
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DDPAK/
TO-263
45
Pb-Free (RoHS
Exempt)
Level-3-245C-168 HR
Level-3-245C-168 HR
Level-3-245C-168 HR
Level-3-245C-168 HR
Level-1-NA-UNLIM
LP3875ES
-3.3
DDPAK/
TO-263
500
500
500
45
Pb-Free (RoHS
Exempt)
LP3875ES
-1.8
DDPAK/
TO-263
Pb-Free (RoHS
Exempt)
LP3875ES
-2.5
DDPAK/
TO-263
Pb-Free (RoHS
Exempt)
LP3875ES
-3.3
TO-220
Green (RoHS
& no Sb/Br)
LP3875ET
-3.3
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
1-Nov-2013
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Sep-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LP3872EMP-1.8/NOPB SOT-223 NDC
LP3872EMP-2.5/NOPB SOT-223 NDC
5
5
5
5
5
5
5
5
5
1000
1000
1000
1000
1000
1000
2000
2000
500
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
24.4
7.0
7.0
7.0
7.0
7.0
7.0
7.0
7.0
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
5.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
24.0
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q2
LP3872EMP-3.3
LP3872EMP-3.3/NOPB SOT-223 NDC
LP3872EMP-5.0 SOT-223 NDC
SOT-223 NDC
LP3872EMP-5.0/NOPB SOT-223 NDC
LP3872EMPX-2.5/NOPB SOT-223 NDC
LP3872EMPX-3.3/NOPB SOT-223 NDC
LP3872ESX-1.8/NOPB DDPAK/
TO-263
KTT
KTT
KTT
KTT
10.75 14.85
10.75 14.85
10.75 14.85
10.75 14.85
LP3872ESX-2.5/NOPB DDPAK/
TO-263
5
5
5
500
500
500
330.0
330.0
330.0
24.4
24.4
24.4
5.0
5.0
5.0
16.0
16.0
16.0
24.0
24.0
24.0
Q2
Q2
Q2
LP3872ESX-3.3/NOPB DDPAK/
TO-263
LP3872ESX-5.0/NOPB DDPAK/
TO-263
LP3875EMP-1.8/NOPB SOT-223 NDC
LP3875EMP-2.5/NOPB SOT-223 NDC
LP3875EMP-3.3/NOPB SOT-223 NDC
5
5
5
1000
1000
1000
330.0
330.0
330.0
16.4
16.4
16.4
7.0
7.0
7.0
7.5
7.5
7.5
2.2
2.2
2.2
12.0
12.0
12.0
16.0
16.0
16.0
Q3
Q3
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Sep-2013
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LP3875EMP-5.0
SOT-223 NDC
5
5
5
1000
1000
500
330.0
330.0
330.0
16.4
16.4
24.4
7.0
7.0
7.5
7.5
2.2
2.2
5.0
12.0
12.0
16.0
16.0
16.0
24.0
Q3
Q3
Q2
LP3875EMP-5.0/NOPB SOT-223 NDC
LP3875ESX-1.8/NOPB DDPAK/
TO-263
KTT
KTT
KTT
10.75 14.85
10.75 14.85
10.75 14.85
LP3875ESX-2.5/NOPB DDPAK/
TO-263
5
5
500
500
330.0
330.0
24.4
24.4
5.0
5.0
16.0
16.0
24.0
24.0
Q2
Q2
LP3875ESX-3.3/NOPB DDPAK/
TO-263
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LP3872EMP-1.8/NOPB
LP3872EMP-2.5/NOPB
LP3872EMP-3.3
SOT-223
SOT-223
NDC
NDC
NDC
NDC
NDC
NDC
NDC
NDC
KTT
5
5
5
5
5
5
5
5
5
5
1000
1000
1000
1000
1000
1000
2000
2000
500
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
45.0
45.0
SOT-223
LP3872EMP-3.3/NOPB
LP3872EMP-5.0
SOT-223
SOT-223
LP3872EMP-5.0/NOPB
LP3872EMPX-2.5/NOPB
LP3872EMPX-3.3/NOPB
LP3872ESX-1.8/NOPB
LP3872ESX-2.5/NOPB
SOT-223
SOT-223
SOT-223
DDPAK/TO-263
DDPAK/TO-263
KTT
500
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Sep-2013
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LP3872ESX-3.3/NOPB
LP3872ESX-5.0/NOPB
LP3875EMP-1.8/NOPB
LP3875EMP-2.5/NOPB
LP3875EMP-3.3/NOPB
LP3875EMP-5.0
DDPAK/TO-263
DDPAK/TO-263
SOT-223
KTT
KTT
NDC
NDC
NDC
NDC
NDC
KTT
KTT
KTT
5
5
5
5
5
5
5
5
5
5
500
500
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
45.0
45.0
35.0
35.0
35.0
35.0
35.0
45.0
45.0
45.0
1000
1000
1000
1000
1000
500
SOT-223
SOT-223
SOT-223
LP3875EMP-5.0/NOPB
LP3875ESX-1.8/NOPB
LP3875ESX-2.5/NOPB
LP3875ESX-3.3/NOPB
SOT-223
DDPAK/TO-263
DDPAK/TO-263
DDPAK/TO-263
500
500
Pack Materials-Page 3
MECHANICAL DATA
NDH0005D
www.ti.com
MECHANICAL DATA
NDC0005A
www.ti.com
MECHANICAL DATA
KTT0005B
TS5B (Rev D)
BOTTOM SIDE OF PACKAGE
www.ti.com
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
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