LP3881ES-1.2/NOPB [TI]
具有使能功能的 800mA、低输入电压 (1.291V)、超低压降稳压器 | KTT | 5 | -40 to 125;型号: | LP3881ES-1.2/NOPB |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有使能功能的 800mA、低输入电压 (1.291V)、超低压降稳压器 | KTT | 5 | -40 to 125 输出元件 稳压器 调节器 |
文件: | 总19页 (文件大小:648K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LP3881
www.ti.com
SNVS224F –MARCH 2003–REVISED APRIL 2013
LP3881 0.8A Fast-Response Ultra Low Dropout Linear Regulators
Check for Samples: LP3881
1
FEATURES
DESCRIPTION
The LP3881 is a high current, fast response regulator
which can maintain output voltage regulation with
minimum input to output voltage drop. Fabricated on
a CMOS process, the device operates from two input
voltages: Vbias provides voltage to drive the gate of
the N-MOS power transistor, while Vin is the input
voltage which supplies power to the load. The use of
an external bias rail allows the part to operate from
ultra low Vin voltages. Unlike bipolar regulators, the
CMOS architecture consumes extremely low
quiescent current at any output load current. The use
of an N-MOS power transistor results in wide
bandwidth, yet minimum external capacitance is
required to maintain loop stability.
2
•
•
•
•
•
•
•
•
Ultra Low Dropout Voltage (75 mV @ 0.8A Typ)
Low Ground Pin Current
Load Regulation of 0.04%/A
60 nA Typical Quiescent Current in Shutdown
1.5% Output Accuracy (25°C)
TO-220, TO-263 and SOIC-8 Packages
Over Temperature/Over Current Protection
−40°C to +125°C Junction Temperature Range
APPLICATIONS
•
•
•
•
•
•
•
DSP Power Supplies
Server Core and I/O Supplies
PC Add-in-Cards
The fast transient response of these devices makes
them suitable for use in powering DSP,
Microcontroller Core voltages and Switch Mode
Power Supply post regulators. The parts are available
in TO-220, TO-263 and SOIC-8 packages.
Local Regulators in Set-Top Boxes
Microcontroller Power Supplies
High Efficiency Power Supplies
SMPS Post-Regulators
Dropout Voltage: 75 mV (typ) @ 0.8A load current.
Ground Pin Current: 3 mA (typ) at full load.
Shutdown Current: 60 nA (typ) when S/D pin is low.
Precision Output Voltage: 1.5% room temperature
accuracy.
TYPICAL APPLICATION CIRCUIT
At least 4.7 µF of input and output capacitance is required for stability.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2013, Texas Instruments Incorporated
LP3881
SNVS224F –MARCH 2003–REVISED APRIL 2013
www.ti.com
Connection Diagrams
Figure 1. TO-220, Top View
Figure 2. TO-263, Top View
V
V
V
1
2
3
4
8 N/C
OUT
V
7
6
5
OUT
IN
GND
S/D
GND
BIAS
GND
Figure 3. SOIC-8, Top View
.
.
Block Diagram
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
2
Submit Documentation Feedback
Copyright © 2003–2013, Texas Instruments Incorporated
Product Folder Links: LP3881
LP3881
www.ti.com
SNVS224F –MARCH 2003–REVISED APRIL 2013
(1)
ABSOLUTE MAXIMUM RATINGS
Storage Temperature Range
−65°C to +150°C
260°C
Lead Temp. (Soldering, 5 seconds)
Human Body Model(2)
Machine Model(3)
2 kV
ESD Rating
200V
Power Dissipation(4)
Internally Limited
−0.3V to +6V
−0.3V to +7V
−0.3V to +7V
Internally Limited
−0.3V to +6V
−40°C to +150°C
VIN Supply Voltage (Survival)
VBIAS Supply Voltage (Survival)
Shutdown Input Voltage (Survival)
IOUT (Survival)
Output Voltage (Survival)
Junction Temperature
(1) Absolute maximum ratings indicate limits beyond which damage to the component may occur. Operating ratings indicate conditions for
which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications, see Electrical
Characteristics. Specifications do not apply when operating the device outside of its rated operating conditions.
(2) The human body model is a 100 pF capacitor discharged through a 1.5k resistor into each pin.
(3) The machine model is a 220 pF capacitor discharged directly into each pin. The machine model ESD rating of pin 5 is 100V.
(4) At elevated temperatures, device power dissipation must be derated based on package thermal resistance and heatsink thermal values.
θJ-A for TO-220 devices is 65°C/W if no heatsink is used. If the TO-220 device is attached to a heatsink, a θJ-S value of 4°C/W can be
assumed. θJ-A for TO-263 devices is approximately 40°C/W if soldered down to a copper plane which is at least 1.5 square inches in
area. θJ-A value for typical SOIC-8 PC board mounting is 166°C/W. If power dissipation causes the junction temperature to exceed
specified limits, the device will go into thermal shutdown.
OPERATING RATINGS
VIN Supply Voltage
(VOUT + VDO) to 5.5V
0 to +6V
Shutdown Input Voltage
IOUT
0.8A
Operating Junction Temperature Range
VBIAS Supply Voltage
−40°C to +125°C
4.5V to 6V
Copyright © 2003–2013, Texas Instruments Incorporated
Submit Documentation Feedback
3
Product Folder Links: LP3881
LP3881
SNVS224F –MARCH 2003–REVISED APRIL 2013
www.ti.com
ELECTRICAL CHARACTERISTICS
Limits in standard typeface are for TJ = 25°C, and limits in boldface type apply over the full operating temperature range.
Unless otherwise specified: VIN = VO(NOM) + 1V, VBIAS = 4.5V, IL = 10 mA, CIN = COUT = 4.7 µF, VS/D = VBIAS
.
Symbol
Parameter
Conditions
Min(1)
Typical(2)
Max(1)
Units
VO
Output Voltage Tolerance
10 mA < IL < 0.8A
1.198
1.234
VO(NOM) + 1V ≤ VIN ≤ 5.5V
4.5V ≤ VBIAS ≤ 6V
1.216
1.186
1.246
1.478
1.522
1.5
V
1.455
1.545
1.773
1.827
1.8
1.746
1.854
ΔVO/ΔVIN
ΔVO/ΔIL
Output Voltage Line Regulation(3)
Output Voltage Load Regulation(4) 10 mA < IL < 0.8A
VO(NOM) + 1V ≤ VIN ≤ 5.5V
0.01
%/V
%/A
0.04
0.06
VDO
Dropout Voltage(5)
IL = 0.8A
(TO220 and TO263 only)
120
160
75
80
3
mV
IL = 0.8A
(SOIC only)
140
190
IQ(VIN
)
Quiescent Current Drawn from VIN 10 mA < IL < 0.8A
Supply
7
8
mA
µA
V
S/D ≤ 0.3V
10 mA < IL < 0.8A
S/D ≤ 0.3V
1
30
0.03
1
IQ(VBIAS
)
Quiescent Current Drawn from
VBIAS Supply
2
3
mA
V
1
30
0.03
2.5
µA
A
ISC
Short-Circuit Current
VOUT = 0V
Shutdown Input
VSDT
Output Turn-off Threshold
Output = ON
1.3
0.7
0.7
20
15
1
V
Output = OFF
0.3
Td (OFF)
Td (ON)
IS/D
Turn-OFF Delay
Turn-ON Delay
S/D Input Current
RLOAD X COUT << Td (OFF)
RLOAD X COUT << Td (ON)
VS/D =1.3V
µs
µA
VS/D ≤ 0.3V
−1
AC Parameters
PSRR (VIN
)
Ripple Rejection for VIN Input
Voltage
VIN = VOUT +1V, f = 120 Hz
80
VIN = VOUT + 1V, f = 1 kHz
VBIAS = VOUT + 3V, f = 120 Hz
VBIAS = VOUT + 3V, f = 1 kHz
f = 120 Hz
65
70
65
dB
PSRR (VBIAS
)
Ripple Rejection for VBIAS Voltage
Output Noise Density
µV/root−H
1
z
en
Output Noise Voltage
VOUT = 1.8V
BW = 10 Hz − 100 kHz
BW = 300 Hz − 300 kHz
150
90
µV (rms)
(1) Limits are specified through testing, statistical correlation, or design.
(2) Typical numbers represent the most likely parametric norm for 25°C operation.
(3) Output voltage line regulation is defined as the change in output voltage from nominal value resulting from a change in input voltage.
(4) Output voltage load regulation is defined as the change in output voltage from nominal value as the load current increases from no load
to full load.
(5) Dropout voltage is defined as the minimum input to output differential required to maintain the output with 2% of nominal value. The
SOIC-8 package devices have a slightly higher dropout voltage due to increased band wire resistance.
4
Submit Documentation Feedback
Copyright © 2003–2013, Texas Instruments Incorporated
Product Folder Links: LP3881
LP3881
www.ti.com
SNVS224F –MARCH 2003–REVISED APRIL 2013
TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise specified: TA = 25°C, COUT = 4.7µF, Cin = 4.7µF, S/D pin is tied to VBIAS, VIN = 2.2V, VOUT = 1.8V
Dropout
IGND
vs
VSD
vs
IL
0.12
0.10
125oC
VBIAS = 5V
25oC
0.08
0.06
0.04
-40oC
0.02
0
0
0.2
0.4
0.6
0.8
ILOAD (A)
Figure 4.
Figure 5.
VOUT
vs
Temperature
DC Load Regulation
Figure 6.
Figure 7.
Line Regulation
Line Regulation
vs
vs
VIN
VBIAS
Figure 8.
Figure 9.
Copyright © 2003–2013, Texas Instruments Incorporated
Submit Documentation Feedback
5
Product Folder Links: LP3881
LP3881
SNVS224F –MARCH 2003–REVISED APRIL 2013
www.ti.com
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise specified: TA = 25°C, COUT = 4.7µF, Cin = 4.7µF, S/D pin is tied to VBIAS, VIN = 2.2V, VOUT = 1.8V
IBIAS
IGND
vs
vs
IL
VSD
1.20
125oC
25oC
1.10
_
VBIAS = 5V
VIN = 2.3V
1.00
-40oC
0.90
_
0.80
0
0.2
_
0.4
_
0.6
_
0.8
ILOAD (A)
Figure 10.
Noise Measurement
Figure 11.
VOUTStartup Waveform
Figure 12.
Figure 13.
Line Regulation
Line Regulation
vs
vs
VBIAS
VBIAS
Figure 14.
Figure 15.
6
Submit Documentation Feedback
Copyright © 2003–2013, Texas Instruments Incorporated
Product Folder Links: LP3881
LP3881
www.ti.com
SNVS224F –MARCH 2003–REVISED APRIL 2013
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise specified: TA = 25°C, COUT = 4.7µF, Cin = 4.7µF, S/D pin is tied to VBIAS, VIN = 2.2V, VOUT = 1.8V
VIN PSRR
VIN PSRR
Figure 16.
Figure 17.
VBIAS PSRR
Figure 18.
Copyright © 2003–2013, Texas Instruments Incorporated
Submit Documentation Feedback
7
Product Folder Links: LP3881
LP3881
SNVS224F –MARCH 2003–REVISED APRIL 2013
www.ti.com
APPLICATION INFORMATION
Application Hints
EXTERNAL CAPACITORS
To assure regulator stability, input and output capacitors are required as shown in the Typical Application Circuit.
OUTPUT CAPACITOR
At least 4.7µF of output capacitance is required for stability (the amount of capacitance can be increased without
limit). The output capacitor must be located less than 1 cm from the output pin of the IC and returned to a clean
analog ground. The ESR (equivalent series resistance) of the output capacitor must be within the "stable" range
as shown in the graph below over the full operating temperature range for stable operation.
10
1.0
COUT > 4.7 mF
STABLE REGION
0.1
.01
.001
0
0.2
0.4
0.6
0.8
LOAD CURRENT (A)
Figure 19. Minimum ESR vs Output Load Current
Tantalum capacitors are recommended for the output as their ESR is ideally suited to the part's requirements
and the ESR is very stable over temperature. Aluminum electrolytics are not recommended because their ESR
increases very rapidly at temperatures below 10C. Aluminum caps can only be used in applications where lower
temperature operation is not required.
A second problem with Al caps is that many have ESR's which are only specified at low frequencies. The typical
loop bandwidth of a linear regulator is a few hundred kHz to several MHz. If an Al cap is used for the output cap,
it must be one whose ESR is specified at a frequency of 100 kHz or more.
Because the ESR of ceramic capacitors is only a few milli Ohms, they are not suitable for use as output
capacitors on LP388X devices. The regulator output can tolerate ceramic capacitance totaling up to 15% of the
amount of Tantalum capacitance connected from the output to ground.
OUTPUT "BYPASS" CAPACITORS
Many designers place small value "bypass" capacitors at various circuit points to reduce noise. Ceramic
capacitors in the value range of about 1000pF to 0.1µF placed directly on the output of a PNP or P-FET LDO
regulator can cause a loss of phase margin which can result in oscillations, even when a Tantalum output
capacitor is in parallel with it. This is not unique to Texas Instruments LDO regulators, it is true of any P-type
LDO regulator.
The reason for this is that PNP or P-FET regulators have a higher output impedance (compared to an NPN
regulator), which results in a pole-zero pair being formed by every different capacitor connected to the output.
The zero frequency is approximately:
Fz = 1 / (2 X π X ESR X C)
where
•
ESR is the equivalent series resistance of the capacitor
8
Submit Documentation Feedback
Copyright © 2003–2013, Texas Instruments Incorporated
Product Folder Links: LP3881
LP3881
www.ti.com
SNVS224F –MARCH 2003–REVISED APRIL 2013
•
C is the value of capacitance
(1)
The pole frequency is:
Fp = 1 / (2 X π X RL X C)
where
•
RL is the load resistance connected to the regulator output
(2)
To understand why a small capacitor can reduce phase margin: assume a typical LDO with a bandwidth of
1MHz, which is delivering 0.5A of current from a 2.5V output (which means RL is 5 Ohms). We then place a .047
µF capacitor on the output. This creates a pole whose frequency is:
Fp = 1 / (2 X π X 5 X .047 X 10E-6) = 677 kHz
(3)
This pole would add close to 60 degrees of phase lag at the crossover (unity gain) frequency of 1 MHz, which
would almost certainly make this regulator oscillate. Depending on the load current, output voltage, and
bandwidth, there are usually values of small capacitors which can seriously reduce phase margin. If the
capacitors are ceramic, they tend to oscillate more easily because they have very little internal inductance to
damp it out. If bypass capacitors are used, it is best to place them near the load and use trace inductance to
"decouple" them from the regulator output.
INPUT CAPACITOR
The input capacitor must be at least 4.7 µF, but can be increased without limit. It's purpose is to provide a low
source impedance for the regulator input. Ceramic capacitors work best for this, but Tantalums are also very
good. There is no ESR limitation on the input capacitor (the lower, the better). Aluminum electrolytics can be
used, but their ESR increase very quickly at cold temperatures. They are not recommended for any application
where temperatures go below about 10°C.
BIAS CAPACITOR
The 0.1µF capacitor on the bias line can be any good quality capacitor (ceramic is recommended).
BIAS VOLTAGE
The bias voltage is an external voltage rail required to get gate drive for the N-FET pass transistor. Bias voltage
must be in the range of 4.5 - 6V to assure proper operation of the part.
UNDER VOLTAGE LOCKOUT
The bias voltage is monitored by a circuit which prevents the regulator output from turning on if the bias voltage
is below approximately 4V.
SHUTDOWN OPERATION
Pulling down the shutdown (S/D) pin will turn-off the regulator. Pin S/D must be actively terminated through a
pull-up resistor (10 kΩ to 100 kΩ) for a proper operation. If this pin is driven from a source that actively pulls high
and low (such as a CMOS rail to rail comparator), the pull-up resistor is not required. This pin must be tied to Vin
if not used.
POWER DISSIPATION/HEATSINKING
A heatsink may be required depending on the maximum power dissipation and maximum ambient temperature of
the application. Under all possible conditions, the junction temperature must be within the range specified under
operating conditions. The total power dissipation of the device is given by:
PD = (VIN−VOUT)IOUT+ (VIN)IGND
where
•
IGND is the operating ground current of the device
(4)
The maximum allowable temperature rise (TRmax) depends on the maximum ambient temperature (TAmax) of the
application, and the maximum allowable junction temperature (TJmax):
TRmax = TJmax− TAmax
Copyright © 2003–2013, Texas Instruments Incorporated
Submit Documentation Feedback
9
Product Folder Links: LP3881
LP3881
SNVS224F –MARCH 2003–REVISED APRIL 2013
www.ti.com
The maximum allowable value for junction to ambient Thermal Resistance, θJA, can be calculated using the
formula:
θJA = TRmax / PD
These parts are available in TO-220 and TO-263 packages. The thermal resistance depends on amount of
copper area or heat sink, and on air flow. If the maximum allowable value of θJA calculated above is ≥ 60 °C/W
for TO-220 package and ≥ 60 °C/W for TO-263 package no heatsink is needed since the package can dissipate
enough heat to satisfy these requirements. If the value for allowable θJA falls below these limits, a heat sink is
required.
HEATSINKING TO-220 PACKAGE
The thermal resistance of a TO220 package can be reduced by attaching it to a heat sink or a copper plane on a
PC board. If a copper plane is to be used, the values of θJA will be same as shown in next section for TO263
package.
The heatsink to be used in the application should have a heatsink to ambient thermal resistance,
θHA≤ θJA − θCH − θJC.
In this equation, θCH is the thermal resistance from the case to the surface of the heat sink and θJC is the thermal
resistance from the junction to the surface of the case. θJC is about 3°C/W for a TO220 package. The value for
θCH depends on method of attachment, insulator, etc. θCH varies between 1.5°C/W to 2.5°C/W. If the exact value
is unknown, 2°C/W can be assumed.
HEATSINKING TO-263 PACKAGE
The TO-263 package uses the copper plane on the PCB as a heatsink. The tab of these packages are soldered
to the copper plane for heat sinking. The graph below shows a curve for the θJA of TO-263 package for different
copper area sizes, using a typical PCB with 1 ounce copper and no solder mask over the copper area for heat
sinking.
Figure 20. θJA vs Copper (1 Ounce) Area for TO-263 package
As shown in the graph below, increasing the copper area beyond 1 square inch produces very little improvement.
The minimum value for θJA for the TO-263 package mounted to a PCB is 32°C/W.
Figure 21 shows the maximum allowable power dissipation for TO-263 packages for different ambient
temperatures, assuming θJA is 35°C/W and the maximum junction temperature is 125°C.
10
Submit Documentation Feedback
Copyright © 2003–2013, Texas Instruments Incorporated
Product Folder Links: LP3881
LP3881
www.ti.com
SNVS224F –MARCH 2003–REVISED APRIL 2013
Figure 21. Maximum power dissipation vs ambient temperature for TO-263 package
HEATSINKING SOIC PACKAGE
Heatsinking for the SOIC-8 package is accomplished by allowing heat to flow through the ground slug on the
bottom of the package into the copper on the PC board. The heat slug must be soldered down to a copper plane
to get good heat transfer. It can also be connected through vias to internal copper planes. Since the heat slug is
at ground potential, traces must not be routed under it which are not at ground potential. Under all possible
conditions, the junction temperature must be within the range specified under operating conditions.
Figure 22 shows a curve for the θJA of the SOIC package for different copper area sizes using a typical PCB with
one ounce copper in still air.
180
130
80
30
0
0.5
COPPER AREA (sq. in.)
1.5
1
Figure 22. θJA vs. Copper (1 ounce) Area for SOIC Package
Copyright © 2003–2013, Texas Instruments Incorporated
Submit Documentation Feedback
11
Product Folder Links: LP3881
LP3881
SNVS224F –MARCH 2003–REVISED APRIL 2013
www.ti.com
REVISION HISTORY
Changes from Revision E (April 2013) to Revision F
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 11
12
Submit Documentation Feedback
Copyright © 2003–2013, Texas Instruments Incorporated
Product Folder Links: LP3881
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LP3881ES-1.2/NOPB
LP3881ES-1.5/NOPB
LP3881ES-1.8/NOPB
LP3881ESX-1.2/NOPB
LP3881ESX-1.8/NOPB
ACTIVE
DDPAK/
TO-263
KTT
5
5
5
5
5
45
RoHS-Exempt
& Green
SN
Level-3-245C-168 HR
Level-3-245C-168 HR
Level-3-245C-168 HR
Level-3-245C-168 HR
Level-3-245C-168 HR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
LP3881ES
-1.2
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DDPAK/
TO-263
KTT
45
RoHS-Exempt
& Green
SN
SN
SN
SN
LP3881ES
-1.5
DDPAK/
TO-263
KTT
45
RoHS-Exempt
& Green
LP3881ES
-1.8
DDPAK/
TO-263
KTT
500
500
RoHS-Exempt
& Green
LP3881ES
-1.2
DDPAK/
TO-263
KTT
RoHS-Exempt
& Green
LP3881ES
-1.8
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LP3881ESX-1.2/NOPB DDPAK/
TO-263
KTT
KTT
5
5
500
500
330.0
24.4
10.75 14.85
5.0
16.0
24.0
Q2
LP3881ESX-1.8/NOPB DDPAK/
TO-263
330.0
24.4
10.75 14.85
5.0
16.0
24.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LP3881ESX-1.2/NOPB
LP3881ESX-1.8/NOPB
DDPAK/TO-263
DDPAK/TO-263
KTT
KTT
5
5
500
500
367.0
367.0
367.0
367.0
45.0
45.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
LP3881ES-1.2/NOPB
LP3881ES-1.5/NOPB
LP3881ES-1.8/NOPB
KTT
KTT
KTT
TO-263
TO-263
TO-263
5
5
5
45
45
45
502
502
502
25
25
25
8204.2
8204.2
8204.2
9.19
9.19
9.19
Pack Materials-Page 3
MECHANICAL DATA
KTT0005B
TS5B (Rev D)
BOTTOM SIDE OF PACKAGE
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022, Texas Instruments Incorporated
相关型号:
LP3881ES-1.5/NOPB
IC VREG 1.5 V FIXED POSITIVE LDO REGULATOR, 0.16 V DROPOUT, PSSO5, MOLDED, TO-263, 5 PIN, Fixed Positive Single Output LDO Regulator
NSC
LP3881ES-1.8/NOPB
IC VREG 1.8 V FIXED POSITIVE LDO REGULATOR, 0.16 V DROPOUT, PSSO5, MOLDED, TO-263, 5 PIN, Fixed Positive Single Output LDO Regulator
NSC
LP3881ESX-1.2/NOPB
IC VREG 1.216 V FIXED POSITIVE LDO REGULATOR, 0.16 V DROPOUT, PSSO5, MOLDED, TO-263, 5 PIN, Fixed Positive Single Output LDO Regulator
NSC
©2020 ICPDF网 联系我们和版权申明