LP38853T-ADJ [TI]
LP38853 3A Fast-Response High-Accuracy Adjustable LDO Linear Regulator with Enable and Soft-Start; LP38853 3A快速响应高精度可调LDO线性稳压器与启用和软启动
| 型号： | LP38853T-ADJ |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LP38853 3A Fast-Response High-Accuracy Adjustable LDO Linear Regulator with Enable and Soft-Start |
| 文件： | 总28页 (文件大小：1685K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LP38853
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SNVS335D –DECEMBER 2006–REVISED APRIL 2013
LP38853 3A Fast-Response High-Accuracy Adjustable LDO Linear Regulator with Enable
and Soft-Start
Check for Samples: LP38853
1
FEATURES
DESCRIPTION
The LP38853-ADJ is a high current, fast response
regulator which can maintain output voltage
regulation with extremely low input to output voltage
drop. Fabricated on a CMOS process, the device
operates from two input voltages: VBIAS provides
voltage to drive the gate of the N-MOS power
transistor, while VIN is the input voltage which
supplies power to the load. The use of an external
bias rail allows the part to operate from ultra low VIN
voltages. Unlike bipolar regulators, the CMOS
architecture consumes extremely low quiescent
current at any output load current. The use of an N-
MOS power transistor results in wide bandwidth, yet
minimum external capacitance is required to maintain
loop stability.
2
•
Adjustable VOUT Range of 0.80V to 1.8V
•
Wide VBIAS Supply Operating Range of 3.0V to
5.5V
•
•
Stable with 10µF Ceramic Capacitors
Dropout Voltage of 240 mV (typical) at 3A Load
Current
•
Precision VADJ Across All Line and Load
Conditions:
–
–
–
±1.5% VADJ for TJ = 25°C
±2.0% VADJ for 0°C ≤ TJ ≤ +125°C
±3.0% VADJ for -40°C ≤ TJ ≤ +125°C
•
•
•
Over-Temperature and Over-Current
Protection
The fast transient response of this device makes it
suitable for use in powering DSP, Microcontroller
Core voltages and Switch Mode Power Supply post
regulators. The part is available in SO PowerPAD
8–pin, PFM 7–pin, and DDPAK 7-pin packages.
Available in 8 Lead SO PowerPAD, 7 Lead PFM
and 7 Lead DDPAK Packages
−40°C to +125°C Operating Junction
Temperature Range
Dropout Voltage: 240 mV (typical) at 3A load
current.
APPLICATIONS
•
ASIC Power Supplies in:
Low Ground Pin Current: 10 mA (typical) at 3A load
current.
–
Desktops, Notebooks, and Graphics Cards,
Servers
Soft-Start: Programmable Soft-Start time.
–
Gaming Set Top Boxes, Printers and
Copiers
Precision ADJ Voltage: ±1.5% for TJ = 25°C, and
±2.0% for 0°C ≤ TJ ≤ +125°C, across all line and load
conditions
•
•
•
Server Core and I/O Supplies
DSP and FPGA Power Supplies
SMPS Post-Regulator
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2013, Texas Instruments Incorporated
LP38853
SNVS335D –DECEMBER 2006–REVISED APRIL 2013
www.ti.com
Typical Application Circuit
LP38853-ADJ
V
IN
V
OUT
IN
OUT
C
IN
C
FF
R1
R2
10 mF Ceramic
V
BIAS
BIAS
C
BIAS
C
OUT
10 mF
Ceramic
1 mF
ADJ
V
EN
EN
SS
GND
C
SS
GND
GND
Connection Diagram
TAB
IS
GND
TAB
IS
GND
SS
EN
1
2
3
4
5
6
7
SS
EN
IN
GND
ADJ
1
2
3
4
5
6
7
IN
GND
ADJ
OUT
BIAS
OUT
BIAS
Figure 1. DDPAK-7 – Top View
See Package Number KTW0007B
Figure 2. PFM – Top View
See Package Number NDZ0007B
ADJ
OUT
BIAS
GND
1
8
7
6
5
N/C
IN
2
3
4
EN
SS
DAP
Connect to GND
Figure 3. SO PowerPAD-8 – Top View
See Package Number DDA0008A
PIN DESCRIPTIONS
SO PowerPAD-
PFM-7
Pin #
DDPAK-7
Pin #
Pin
Symbol
8
Pin Description
Pin #
Soft-Start capacitor connection. Used to control the rise time of
VOUT at turn-on.
1
1
5
SS
2
3
4
5
6
7
-
2
3
4
5
6
7
-
6
7
4
1
2
3
8
EN
IN
Device Enable, High = On, Low = Off.
The unregulated voltage input
GND
ADJ
OUT
BIAS
N/C
Ground
The feedback connection to set the output voltage
The regulated output voltage
The supply for the internal control and reference circuitry.
No internal connection
The PFM and DDPAK TAB is a thermal and electrical connection
that is physically attached to the backside of the die, and used as a
thermal heat-sink connection. See the Application Information
section for details.
TAB
TAB
-
TAB
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PIN DESCRIPTIONS (continued)
SO PowerPAD-
PFM-7
Pin #
DDPAK-7
Pin #
Pin
Symbol
8
Pin Description
Pin #
The SO PowerPAD DAP is a thermal connection only that is
physically attached to the backside of the die, and used as a
thermal heat-sink connection. See the Application Information
section for details.
-
-
DAP
DAP
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)(2)
Storage Temperature Range
Lead Temperature Soldering, 5 seconds
ESD Rating
−65°C to +150°C
260°C
Human Body Model(3)
±2 kV
Power Dissipation(4)
Internally Limited
−0.3V to +6.0V
−0.3V to +6.0V
−0.3V to +6.0V
−0.3V to +6.0V
Internally Limited
−40°C to +150°C
VIN Supply Voltage (Survival)
VBIAS Supply Voltage (Survival)
VSS SoftStart Voltage (Survival)
VOUT Voltage (Survival)
IOUT Current (Survival)
Junction Temperature
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but does not ensure specific performance limits. For ensured specifications and conditions,
see the Electrical Characteristics.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
(3) The human body model is a 100 pF capacitor discharged through a 1.5k resistor into each pin. Test method is per JESD22-A114.
(4) Device power dissipation must be de-rated based on device power dissipation (PD), ambient temperature (TA), and package junction to
ambient thermal resistance (θJA). Additional heat-sinking may be required to ensure that the device junction temperature (TJ) does not
exceed the maximum operating rating. See the Application Information section for details.
Operating Ratings(1)
VIN Supply Voltage
(VOUT + VDO) to VBIAS
3.0V to 5.5V
VBIAS Supply Voltage
0.8V ≤ VOUT ≤ 1.2V
1.2V < VOUT ≤ 1.8V
4.5V to 5.5V
VEN Voltage
0.0V to VBIAS
IOUT
0 mA to 3.0A
Junction Temperature Range(2)
−40°C to +125°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but does not ensure specific performance limits. For ensured specifications and conditions,
see the Electrical Characteristics.
(2) Device power dissipation must be de-rated based on device power dissipation (PD), ambient temperature (TA), and package junction to
ambient thermal resistance (θJA). Additional heat-sinking may be required to ensure that the device junction temperature (TJ) does not
exceed the maximum operating rating. See the Application Information section for details.
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Electrical Characteristics
Unless otherwise specified: VOUT = 0.80V, VIN = VOUT(NOM) + 1V, VBIAS = 3.0V, VEN = VBIAS, IOUT = 10 mA, CIN = COUT = 10 µF,
CBIAS = 1 µF, CSS = open. Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction
temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are specified through test, design, or statistical
correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes
only.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
VOUT(NOM)+1V ≤ VIN ≤ VBIAS ≤ 4.5V,(1)
3.0V ≤ VBIAS ≤ 5.5V,
10 mA ≤ IOUT ≤ 3A
492.5
485.0
507.5
515.0
500.
VOUT(NOM)+1V ≤ VIN ≤ VBIAS ≤ 4.5V,(1)
3.0V ≤ VBIAS ≤ 5.5V,
10 mA ≤ IOUT ≤ 3.0A,
VADJ
VADJ Accuracy
mV
490.0
500.
510.0
0°C ≤ TJ ≤ +125°C
3.0V ≤ VBIAS ≤ 5.5V
4.5V ≤ VBIAS ≤ 5.5V
VOUT(NOM)+1V ≤ VIN ≤ VBIAS
3.0V ≤ VBIAS ≤ 5.5V
10 mA ≤ IOUT ≤ 3.0A
0.80
1.20
VOUT
VOUT Range
V
0.80
1.80
(2)
ΔVOUT/ΔVIN Line Regulation, VIN
ΔVOUT/ΔVBIAS Line Regulation, VBIAS
ΔVOUT/ΔIOUT Output Voltage Load Regulation(3)
-
-
-
0.04
0.10
0.2
-
-
-
%/V
%/V
%/A
(2)
300
450
VDO
Dropout Voltage(4)
IOUT = 3.0A
-
240
mV
VOUT = 0.80V
VBIAS = 3.0V
10 mA ≤ IOUT ≤ 3.0A
8.5
9.0
-
7.0
mA
Quiescent Current Drawn from VIN
Supply
IGND(IN)
10
300
V
EN ≤ 0.5V
10 mA ≤ IOUT ≤ 3.0A
EN ≤ 0.5V
1
μA
mA
μA
V
3.8
4.5
-
3.0
Quiescent Current Drawn from
VBIAS Supply
IGND(BIAS)
170
200
V
100
2.45
150
2.20
2.00
2.70
2.90
UVLO
Under-Voltage Lock-Out Threshold VBIAS rising until device is functional
VBIAS falling from UVLO threshold until
Under-Voltage Lock-Out Hysteresis
60
50
300
350
UVLO(HYS)
mV
device is non-functional
VIN = VOUT(NOM) + 1V,
Output Short-Circuit Current
ISC
-
5.8
-
A
VBIAS = 3.0V, VOUT = 0.0V
Soft-Start
rSS
Soft-Start internal resistance
11.0
-
13.5
675
16.0
-
kΩ
μs
Soft-Start time
CSS = 10 nF
tSS
tSS = CSS × rSS × 5
Enable
VEN = VBIAS
-
0.01
-30
-
IEN
ENABLE pin Current
μA
-19
-13
-40
-51
VEN = 0.0V, VBIAS = 5.5V
1.00
0.90
1.50
1.55
VEN(ON)
Enable Voltage Threshold
Enable Voltage Hysteresis
VEN rising until Output = ON
1.25
100
V
VEN falling from VEN(ON) until Output =
OFF
50
30
150
200
VEN(HYS)
mV
tOFF
tON
Turn-OFF Delay Time
Turn-ON Delay Time
RLOAD x COUT << tOFF
RLOAD x COUT << tON
-
-
20
15
-
-
µs
(1) VIN cannot exceed either VBIAS or 4.5V, whichever value is lower.
(2) Output voltage line regulation is defined as the change in output voltage from nominal value resulting from a change in input voltage.
(3) Output voltage load regulation is defined as the change in output voltage from nominal value as the load current increases from no load
to full load.
(4) Dropout voltage is defined as the input to output voltage differential (VIN - VOUT) where the input voltage is low enough to cause the
output voltage to drop 2% from the nominal value.
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Electrical Characteristics (continued)
Unless otherwise specified: VOUT = 0.80V, VIN = VOUT(NOM) + 1V, VBIAS = 3.0V, VEN = VBIAS, IOUT = 10 mA, CIN = COUT = 10 µF,
CBIAS = 1 µF, CSS = open. Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction
temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are specified through test, design, or statistical
correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes
only.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
AC Parameters
VIN = VOUT(NOM) + 1V,
f = 120 Hz
-
-
-
-
80
70
58
58
-
-
-
-
PSRR
Ripple Rejection for VIN Input
Voltage
(VIN
)
VIN = VOUT(NOM) + 1V,
f = 1 kHz
dB
VBIAS = VOUT(NOM) + 3V,
f = 120 Hz
PSRR
(VBIAS
Ripple Rejection for VBIAS Voltage
)
VBIAS = VOUT(NOM) + 3V,
f = 1 kHz
Output Noise Density
Output Noise Voltage
f = 120 Hz
-
-
-
1
-
-
-
µV/√Hz
en
BW = 10 Hz − 100 kHz
BW = 300 Hz − 300 kHz
150
90
µVRMS
Thermal Parameters
Thermal Shutdown Junction
Temperature
TSD
-
160
-
°C
TSD(HYS)
Thermal Shutdown Hysteresis
-
-
-
-
-
-
-
10
60
60
168
3
-
-
-
-
-
-
-
PFM
Thermal Resistance, Junction to
Ambient(5)
θJ-A
DDPAK-7
SO PowerPAD-8
PFM-7
°C/W
Thermal Resistance, Junction to
Case(5) (6)
θJ-C
DDPAK-7
3
SO PowerPAD-8
11
(5) Device power dissipation must be de-rated based on device power dissipation (PD), ambient temperature (TA), and package junction to
ambient thermal resistance (θJA). Additional heat-sinking may be required to ensure that the device junction temperature (TJ) does not
exceed the maximum operating rating. See the Application Information section for details.
(6) For PFM and DDPAK: θJ-C refers to the BOTTOM surface of the package, under the epoxy body, as the 'CASE'. For SO PowerPAD-8:
θJ-C refers to the DAP (aka: Exposed Pad) on BOTTOM surface of the package as the 'CASE'.
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Typical Performance Characteristics
Refer to the Typical Application Circuit. Unless otherwise specified: TJ = 25°C, R1 = 1.40 kΩ, R2 = 1.00 kΩ, CFF= 0.01 µF, VIN
= VOUT(NOM) + 1V, VBIAS = 3.0V, IOUT = 10 mA, CIN = 10 µF Ceramic, COUT = 10 µF Ceramic, CBIAS = 1 µF Ceramic, , CSS
Open.
=
VBIAS Ground Pin Current (IGND(BIAS)) vs VBIAS
VBIAS Ground Pin Current (IGND(BIAS)) vs Temperature
Figure 4.
Figure 5.
VIN Ground Pin Current vs Temperature
Load Regulation vs Temperature
Figure 6.
Figure 7.
Dropout Voltage (VDO) vs Temperature
Output Current Limit (ISC) vs Temperature
Figure 8.
Figure 9.
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Typical Performance Characteristics (continued)
Refer to the Typical Application Circuit. Unless otherwise specified: TJ = 25°C, R1 = 1.40 kΩ, R2 = 1.00 kΩ, CFF= 0.01 µF, VIN
= VOUT(NOM) + 1V, VBIAS = 3.0V, IOUT = 10 mA, CIN = 10 µF Ceramic, COUT = 10 µF Ceramic, CBIAS = 1 µF Ceramic, , CSS
Open.
=
VOUT vs Temperature
VOUT vs VIN
Figure 10.
Figure 11.
UVLO Thresholds vs Temperature
Soft-Start rSS Variation vs Temperature
Figure 12.
Figure 13.
VOUT vs CSS, 10 nF to 47 nF
Enable Thresholds (VEN) vs Temperature
Figure 14.
Figure 15.
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Typical Performance Characteristics (continued)
Refer to the Typical Application Circuit. Unless otherwise specified: TJ = 25°C, R1 = 1.40 kΩ, R2 = 1.00 kΩ, CFF= 0.01 µF, VIN
= VOUT(NOM) + 1V, VBIAS = 3.0V, IOUT = 10 mA, CIN = 10 µF Ceramic, COUT = 10 µF Ceramic, CBIAS = 1 µF Ceramic, , CSS
Open.
=
Enable Pull-Down Current (IEN) vs Temperature
Enable Pull-Up Resistor (rEN) vs Temperature
Figure 16.
Figure 17.
VIN Line Transient Response
VIN Line Transient Response
Figure 18.
Figure 19.
VBIAS Line Transient Response
VBIAS Line Transient Response
Figure 20.
Figure 21.
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Typical Performance Characteristics (continued)
Refer to the Typical Application Circuit. Unless otherwise specified: TJ = 25°C, R1 = 1.40 kΩ, R2 = 1.00 kΩ, CFF= 0.01 µF, VIN
= VOUT(NOM) + 1V, VBIAS = 3.0V, IOUT = 10 mA, CIN = 10 µF Ceramic, COUT = 10 µF Ceramic, CBIAS = 1 µF Ceramic, , CSS
Open.
=
Load Transient Response, COUT = 10 µF Ceramic
Load Transient Response, COUT = 10 µF Ceramic
Figure 22.
Figure 23.
Load Transient Response, COUT = 100 µF Ceramic
Load Transient Response, COUT = 100 µF Ceramic
Figure 24.
Figure 25.
Load Transient Response, COUT = 100 µF Tantalum
Load Transient Response, COUT = 100 µF Tantalum
Figure 26.
Figure 27.
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Typical Performance Characteristics (continued)
Refer to the Typical Application Circuit. Unless otherwise specified: TJ = 25°C, R1 = 1.40 kΩ, R2 = 1.00 kΩ, CFF= 0.01 µF, VIN
= VOUT(NOM) + 1V, VBIAS = 3.0V, IOUT = 10 mA, CIN = 10 µF Ceramic, COUT = 10 µF Ceramic, CBIAS = 1 µF Ceramic, , CSS
Open.
=
VBIAS PSRR
VIN PSRR
Figure 28.
Figure 29.
Output Noise
Figure 30.
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Block Diagram
OUT
IN
LP38853-ADJ
BIAS
Under-Voltage
Lock-Out
Thermal
Shut Down
r
EN
ADJ
EN
Enable
1.2V
r
SS
V
REF
SS
I
LIMIT
GND
0.5V
APPLICATION INFORMATION
EXTERNAL CAPACITORS
To assure regulator stability, input and output capacitors are required as shown in the Typical Application Circuit.
Output Capacitor
A minimum output capacitance of 10 µF, ceramic, is required for stability. The amount of output capacitance can
be increased without limit. The output capacitor must be located less than 1 cm from the output pin of the IC and
returned to the device ground pin with a clean analog ground.
Only high quality ceramic types such as X5R or X7R should be used, as the Z5U and Y5F types do not provide
sufficient capacitance over temperature.
Tantalum capacitors will also provide stable operation across the entire operating temperature range. However,
the effects of ESR may provide variations in the output voltage during fast load transients. Using the minimum
recommended 10 µF ceramic capacitor at the output will allow unlimited capacitance, Tantalum and/or
Aluminum, to be added in parallel.
Input Capacitor
The input capacitor must be at least 10 µF, but can be increased without limit. It's purpose is to provide a low
source impedance for the regulator input. A ceramic capacitor, X5R or X7R, is recommended.
Tantalum capacitors may also be used at the input pin. There is no specific ESR limitation on the input capacitor
(the lower, the better).
Aluminum electrolytic capacitors can be used, but are not recommended as their ESR increases very quickly at
cold temperatures. They are not recommended for any application where the ambient temperature falls below
0°C.
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Bias Capacitor
The capacitor on the bias pin must be at least 1 µF, and can be any good quality capacitor (ceramic is
recommended).
Feed Forward Capacitor, CFF
(Refer to theTypical Application Circuit)
When using a ceramic capacitor for COUT, the typical ESR value will be too small to provide any meaningful
positive phase compensation, FZ, to offset the internal negative phase shifts in the gain loop.
FZ = (1 / (2 x π x COUT x ESR) )
(1)
A capacitor placed across the gain resistor R1 will provide additional phase margin to improve load transient
response of the device. This capacitor, CFF, in parallel with R1, will form a zero in the loop response given by the
formula:
FZ = (1 / (2 x π x CFF x R1) )
(2)
For optimum load transient response select CFF so the zero frequency, FZ, falls between 10 kHz and 15 kHz.
(CFF = (1 / (2 x π x R1 x FZ)
(3)
The phase lead provided by CFF diminishes as the DC gain approaches unity, or VOUT approaches VADJ. This is
because CFF also forms a pole with a frequency of:
FP = (1 / (2 x π x CFF x (R1 || R2) ) )
(4)
It's important to note that at higher output voltages, where R1 is much larger than R2, the pole and zero are far
apart in frequency. At lower output voltages the frequency of the pole and the zero mover closer together. The
phase lead provided from CFF diminishes quickly as the output voltage is reduced, and has no effect when VOUT
= VADJ. For this reason, relying on this compensation technique alone is adequate only for higher output
voltages. For the LP38853, the practical minimum VOUT is 0.8V when a ceramic capacitor is used for COUT
.
Figure 31. FZERO and FPOLE vs Gain
SETTING THE OUTPUT VOLTAGE
(Refer to theTypical Application Circuit)
The output voltage is set using the external resistive divider R1 and R2. The output voltage is given by the
formula:
≈
’
’
◊
◊
R1
R2
≈
∆
«
VOUT = VADJ x 1+
÷
∆
∆
«
(5)
The resistors used for R1 and R2 should be high quality, tight tolerance, and with matching temperature
coefficients. It is important to remember that, although the value of VADJ is specified, the use of low quality
resistors for R1 and R2 can easily produce a VOUT value that is unacceptable.
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It is recommended that the values selected for R1 and R2 are such that the parallel value is less than 10 kΩ.
This is to prevent internal parasitic capacitances on the ADJ pin from interfering with the FZ pole set by R1 and
CFF.
( (R1 x R2) / (R1 + R2) ) ≤ 10 kΩ
(6)
Table 1 lists some suggested, best fit, standard ±1% resistor values for R1 and R2, and a standard ±10%
capacitor values for CFF, for a range of VOUT values. Other values of R1, R2, and CFF are available that will give
similar results.
Table 1.
VOUT
0.8V
0.9V
1.0V
1.1V
1.2V
1.3V
1.4V
1.5V
1.6V
1.7V
1.8V
R1
R2
CFF
FZ
1.07 kΩ
1.50 kΩ
1.00 kΩ
1.65 kΩ
1.40 kΩ
1.15 kΩ
1.07 kΩ
2.00 kΩ
1.65 kΩ
2.55 kΩ
2.94 kΩ
1.78 kΩ
1.87 kΩ
1.00 kΩ
1.37 kΩ
1.00 kΩ
715 Ω
12 nF
8.2 nF
12 nF
8.2 nF
10 nF
12 nF
12 nF
6.8 nF
8.2 nF
5.6 nF
4.7 nF
12.4 kHz
12.9 kHz
13.3 kHz
11.8 kHz
11.4 kHz
11.5 kHz
12.4 kHz
11.7 kHz
11.8 kHz
11.1 kHz
11.5 kHz
590 Ω
1.00 kΩ
750 Ω
1.07 kΩ
1.13 kΩ
Please refer to the TI AN-1378 Application Report for additional information on how resistor tolerances affect the
calculated VOUT value.
INPUT VOLTAGE
The input voltage (VIN) is the high current external voltage rail that will be regulated down to a lower voltage,
which is applied to the load. The input voltage must be at least VOUT + VDO, and no higher than whatever value is
used for VBIAS
.
For applications where VBIAS is higher than 4.5V, VIN must be no greater than 4.5V, otherwise output voltage
accuracy may be affected.
BIAS VOLTAGE
The bias voltage (VBIAS) is a low current external voltage rail required to bias the control circuitry and provide
gate drive for the N-FET pass transistor. When VOUT is set to 1.20V, or less, VBIAS may be anywhere in the
operating range of 3.0V to 5.5V. If VOUT is set higher than 1.20V , VBIAS must be between 4.5V and 5.5V to
ensure proper operation of the device.
UNDER VOLTAGE LOCKOUT
The bias voltage is monitored by a circuit which prevents the device from functioning when the bias voltage is
below the Under-Voltage Lock-Out (UVLO) threshold of approximately 2.45V.
As the bias voltage rises above the UVLO threshold the device control circuitry becomes active. There is
approximately 150 mV of hysteresis built into the UVLO threshold to provide noise immunity.
When the bias voltage is between the UVLO threshold and the Minimum Operating Rating value of 3.0V the
device will be functional, but the operating parameters will not be within the specified limits.
SUPPLY SEQUENCING
There is no requirement for the order that VIN or VBIAS are applied or removed.
One practical limitation is that the Soft-Start circuit starts charging CSS when both VBIAS rises above the UVLO
threshold and the Enable pin is above the VEN(ON) threshold. If the application of VIN is delayed beyond this point
the benefits of Soft-Start will be compromised.
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In any case, the output voltage cannot be ensured until both VIN and VBIAS are within the range of specified
operating values.
If used in a dual-supply system where the regulator output load is returned to a negative supply, the output pin
must be diode clamped to ground. A Schottky diode is recommended for this diode clamp.
REVERSE VOLTAGE
A reverse voltage condition will exist when the voltage at the output pin is higher than the voltage at the input pin.
Typically this will happen when VIN is abruptly taken low and COUT continues to hold a sufficient charge such that
the input to output voltage becomes reversed.
The NMOS pass element, by design, contains no body diode. This means that, as long as the gate of the pass
element is not driven, there will not be any reverse current flow through the pass element during a reverse
voltage event. The gate of the pass element is not driven when VBIAS is below the UVLO threshold, or when the
Enable pin is held low.
When VBIAS is above the UVLO threshold, and the Enable pin is above the VEN(ON) threshold, the control circuitry
is active and will attempt to regulate the output voltage. Since the input voltage is less than the output voltage the
control circuit will drive the gate of the pass element to the full VBIAS potential when the output voltage begins to
fall. In this condition, reverse current will flow from the output pin to the input pin , limited only by the RDS(ON) of
the pass element and the output to input voltage differential. Discharging an output capacitor up 1000 µF in this
manner will not damage the device as the current will rapidly decay. However, continuous reverse current should
be avoided.
SOFT-START
The LP38853 incorporates a Soft-Start function that reduces the start-up current surge into the output capacitor
(COUT) by allowing VOUT to rise slowly to the final value. This is accomplished by controlling VREF at the SS pin.
The soft-start timing capacitor (CSS) is internally held to ground until both VBIAS rises above the Under-Voltage
Lock-Out threshold (ULVO) and the Enable pin is higher than the VEN(ON) threshold.
VREF will rise at an RC rate defined by the internal resistance of the SS pin (rSS), and the external capacitor
connected to the SS pin. This allows the output voltage to rise in a controlled manner until steady-state
regulation is achieved. Typically, five time constants are recommended to assure that the output voltage is
sufficiently close to the final steady-state value. During the soft-start time the output current can rise to the built-in
current limit.
Soft-Start Time = CSS × rSS × 5
(7)
Since the VOUT rise will be exponential, not linear, the in-rush current will peak during the first time constant (τ),
and VOUT will require four additional time constants (4τ) to reach the final value (5τ) .
After achieving normal operation, should either VBIAS fall below the ULVO threshold, or the Enable pin fall below
the VEN(OFF) threshold, the device output will be disabled and the Soft-Start capacitor (CSS) discharge circuit will
become active. The CSS discharge circuit will remain active until VBIAS falls to 500 mV (typical). When VBIAS falls
below 500 mV (typical), the CSS discharge circuit will cease to function due to a lack of sufficient biasing to the
control circuitry.
Since VREF appears on the SS pin, any leakage through CSS will cause VREF to fall, and thus affect VOUT. A
leakage of 50 nA (about 10 MΩ) through CSS will cause VOUT to be approximately 0.1% lower than nominal, while
a leakage of 500 nA (about 1 MΩ) will cause VOUT to be approximately 1% lower than nominal. Typical ceramic
capacitors will have a factor of 10X difference in leakage between 25°C and 85°C, so the maximum ambient
temperature must be included in the capacitor selection process.
Typical CSS values will be in the range of 1 nF to 100 nF, providing typical Soft-Start times in the range of 70 μs
to 7 ms (5τ). Values less than 1 nF can be used, but the Soft-Start effect will be minimal. Values larger than 100
nF will provide soft-start, but may not be fully discharged if VBIAS falls from the UVLVO threshold to less than 500
mV in less than 100 µs.
Figure 32 shows the relationship between the COUT value and a typical CSS value.
14
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Figure 32. Typical CSS vs COUT Values
The CSS capacitor must be connected to a clean ground path back to the device ground pin. No components,
other than CSS, should be connected to the SS pin, as there could be adverse effects to VOUT
.
If the Soft-Start function is not needed the SS pin should be left open, although some minimal capacitance value
is always recommended.
ENABLE OPERATION
The Enable pin (EN) provides a mechanism to enable, or disable, the regulator output stage. The Enable pin has
an internal pull-up, through a typical 180 kΩ resistor, to VBIAS
.
If the Enable pin is actively driven, pulling the Enable pin above the VEN threshold of 1.25V (typical) will turn the
regulator output on, while pulling the Enable pin below the VEN threshold will turn the regulator output off. There
is approximately 100 mV of hysteresis built into the Enable threshold provide noise immunity.
If the Enable function is not needed this pin should be left open, or connected directly to VBIAS. If the Enable pin
is left open, stray capacitance on this pin must be minimized, otherwise the output turn-on will be delayed while
the stray capacitance is charged through the internal resistance (rEN).
POWER DISSIPATION AND HEAT-SINKING
Additional copper area for heat-sinking may be required depending on the maximum device dissipation (PD) and
the maximum anticipated ambient temperature (TA) for the device. Under all possible conditions, the junction
temperature must be within the range specified under operating conditions.
The total power dissipation of the device is the sum of three different points of dissipation in the device.
The first part is the power that is dissipated in the NMOS pass element, and can be determined with the formula:
PD(PASS) = (VIN - VOUT) × IOUT
(8)
The second part is the power that is dissipated in the bias and control circuitry, and can be determined with the
formula:
PD(BIAS) = VBIAS × IGND(BIAS)
where
•
IGND(BIAS) is the portion of the operating ground current of the device that is related to VBIAS
.
(9)
The third part is the power that is dissipated in portions of the output stage circuitry, and can be determined with
the formula:
PD(IN) = VIN × IGND(IN)
where
•
IGND(IN) is the portion of the operating ground current of the device that is related to VIN.
(10)
15
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The total power dissipation is then:
PD = PD(PASS) + PD(BIAS) + PD(IN)
(11)
The maximum allowable junction temperature rise (ΔTJ) depends on the maximum anticipated ambient
temperature (TA) for the application, and the maximum allowable operating junction temperature (TJ(MAX)) .
DJ = TJ(MAX) - TA(MAX)
(12)
The maximum allowable value for junction to ambient Thermal Resistance, θJA, can be calculated using the
formula:
DTJ
PD
q
Ç
JA
(13)
Heat-Sinking The PFM Package
The PFM package has a θJA rating of 60°C/W and a θJC rating of 3°C/W. These ratings are for the package only,
no additional heat-sinking, and with no airflow. If the needed θJA, as calculated above, is greater than or equal to
60°C/W then no additional heat-sinking is required since the package can safely dissipate the heat and not
exceed the operating TJ(MAX). If the needed θJA is less than 60°C/W then additional heat-sinking is needed.
The thermal resistance of a PFM package can be reduced by attaching it to a heat sink or a copper plane on a
PC board. If a copper plane is to be used, the values of θJA will be same as shown in next section for DDPAK
package.
The heat-sink to be used in the application should have a heat-sink to ambient thermal resistance, θHA
:
q
£ q - q + q
(
)
HA
JA
CH
JC
where
•
•
•
θJA is the required total thermal resistance from the junction to the ambient air
θCH is the thermal resistance from the case to the surface of the heart-sink
θJC is the thermal resistance from the junction to the surface of the case.
(14)
For this equation, θJC is about 3°C/W for a PFM package. The value for θCH depends on method of attachment,
insulator, etc. θCH varies between 1.5°C/W to 2.5°C/W. Consult the heat-sink manufacturer datasheet for details
and recommendations.
Heat-Sinking The DDPAK Package
The DDPAK package has a θJA rating of 60°C/W, and a θJC rating of 3°C/W. These ratings are for the package
only, no additional heat-sinking, and with no airflow.
The DDPAK package uses the copper plane on the PCB as a heat-sink. The tab of this package is soldered to
the copper plane for heat sinking. Figure 33 shows a curve for the θJA of DDPAK package for different copper
area sizes, using a typical PCB with 1 ounce copper and no solder mask over the copper area for heat-sinking.
Figure 33 shows that increasing the copper area beyond 1 square inch produces very little improvement. The
minimum value for θJA for the DDPAK package mounted to a PCB is 32°C/W.
Figure 34 shows the maximum allowable power dissipation for DDPAK packages for different ambient
temperatures, assuming θJA is 35°C/W and the maximum junction temperature is 125°C.
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SNVS335D –DECEMBER 2006–REVISED APRIL 2013
5
4
3
2
1
0
PFM Package
1 Sq Inch of 1 oz. Copper
qJA = 35°C/W
TJ=125°C
TJ < 125°C
–50 –25
0
25
50
75 100 125
AMBIENT TEMPERATURE (°C)
Figure 33. θJA vs Copper (1 Ounce) Area for the
Figure 34. 101Maximum Power Dissipation vs
Ambient Temperature for the DDPAK Package
DDPAK package
Heat-Sinking The SO PowerPAD-8 Package
The LP38853MR package has a θJA rating of 168°C/W, and a θJC rating of 11°C/W. The θJA rating of 168°C/W
includes the device DAP soldered to an area of 0.008 square inches (0.09 in x 0.09 in) of 1 ounce copper, with
no airflow.
Increasing the copper area soldered to the DAP to 1 square inch of 1 ounce copper, using a dog-bone type
layout, will improve the θJA rating to 98°C/W. Figure 35 shows that increasing the copper area beyond 1 square
inch produces very little improvement.
Figure 36 shows the maximum allowable power dissipation for the SO PowerPAD-8 package for a range of
ambient temperatures, assuming θJA is 98°C/W and the maximum junction temperature is 125°C.
Figure 35. θJA vs Copper (1 Ounce) Area for the SO Figure 36. Maximum Power Dissipation vs Ambient
PowerPAD-8 Package
Temperature for the SO PowerPAD-8 Package
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REVISION HISTORY
Changes from Revision C (April 2013) to Revision D
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 17
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
LP38853MR-ADJ
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
ACTIVE SO PowerPAD
DDA
8
8
8
8
7
7
7
7
7
7
95
TBD
Call TI
CU SN
Call TI
CU SN
Call TI
CU SN
Call TI
CU SN
Call TI
CU SN
Call TI
Level-3-260C-168 HR
Call TI
L38853
MRADJ
LP38853MR-ADJ/NOPB
LP38853MRX-ADJ
LP38853MRX-ADJ/NOPB
LP38853S-ADJ
ACTIVE SO PowerPAD
ACTIVE SO PowerPAD
ACTIVE SO PowerPAD
DDA
DDA
DDA
KTW
KTW
KTW
KTW
NDZ
NDZ
95
2500
2500
45
Green (RoHS
& no Sb/Br)
L38853
MRADJ
TBD
L38853
MRADJ
Green (RoHS
& no Sb/Br)
Level-3-260C-168 HR
Call TI
L38853
MRADJ
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DDPAK/
TO-263
TBD
LP38853S
ADJ
LP38853S-ADJ/NOPB
LP38853SX-ADJ
DDPAK/
TO-263
45
Pb-Free (RoHS
Exempt)
Level-3-245C-168 HR
Call TI
LP38853S
ADJ
DDPAK/
TO-263
500
500
45
TBD
LP38853S
ADJ
LP38853SX-ADJ/NOPB
LP38853T-ADJ
DDPAK/
TO-263
Pb-Free (RoHS
Exempt)
Level-3-245C-168 HR
Call TI
LP38853S
ADJ
TO-220
TBD
LP38853T
ADJ
LP38853T-ADJ/NOPB
TO-220
45
Green (RoHS
& no Sb/Br)
Level-1-NA-UNLIM
LP38853T
ADJ
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
2500
2500
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LP38853MRX-ADJ
LP38853MRX-ADJ/NOPB
LP38853SX-ADJ
SO
Power
PAD
DDA
DDA
8
8
330.0
330.0
12.4
12.4
6.5
6.5
5.4
5.4
2.0
2.0
8.0
8.0
12.0
12.0
Q1
Q1
SO
Power
PAD
DDPAK/
TO-263
KTW
KTW
7
7
500
500
330.0
330.0
24.4
24.4
10.75 14.85
10.75 14.85
5.0
5.0
16.0
16.0
24.0
24.0
Q2
Q2
LP38853SX-ADJ/NOPB DDPAK/
TO-263
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LP38853MRX-ADJ
LP38853MRX-ADJ/NOPB
LP38853SX-ADJ
SO PowerPAD
SO PowerPAD
DDPAK/TO-263
DDPAK/TO-263
DDA
DDA
KTW
KTW
8
8
7
7
2500
2500
500
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
35.0
35.0
45.0
45.0
LP38853SX-ADJ/NOPB
500
Pack Materials-Page 2
MECHANICAL DATA
NDZ0007B
TA07B (Rev E)
www.ti.com
MECHANICAL DATA
DDA0008A
MRA08A (Rev D)
www.ti.com
MECHANICAL DATA
KTW0007B
TS7B (Rev E)
BOTTOM SIDE OF PACKAGE
www.ti.com
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