LP3907SQ-PXPP/NOPB_技术文档

LP3907

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SNVS511O –JUNE 2007–REVISED MAY 2013

Dual High-Current Step-Down DC/DC and Dual Linear Regulator with I²C-Compatible

Interface

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1

FEATURES

KEY SPECIFICATIONS

2

•

Compatible with Advanced Applications

Processors and FPGAs

•

Step-Down DC/DC Converter (Buck)

–

Programmable V_OUTfrom:

•

2 LDOs for Powering Internal Processor

Functions and I/Os

–

Buck1 : 0.8V - 2.0V @ 1A

Buck2 : 1.0V - 3.5V @ 600mA

High-Speed Serial Interface for Independent

Control of Device Functions and Settings

–

Up to 96% Efficiency

2.1MHz PWM Switching Frequency

•

Precision Internal Reference

Thermal Overload Protection

Current Overload Protection

PWM to PFM Automatic Mode Change

Under Low Loads

–

±3% Output Voltage Accuracy

Automatic Soft Start

24-Lead 4 × 4 × 0.8mm WQFN or

25-Bump 2.5 x 2.5mm DSBGA Package

•

Linear Regulators (LDO)

•

Software Programmable Regulators

–

Programmable VOUT of 1.0V to 3.5V

(except “JJ11” and “FX6W” options)

External Power-On-Reset Function for Buck1

and Buck2 (i.e., Power Good with Delay

Function)

–

±3% Output Voltage Accuracy

300mA Output Current

30mV (Typ) Dropout

•

Undervoltage Lock-Out Detector to Monitor

Input Supply Voltage

LP3907-Q1 is an Automotive-Grade Product

that is AECQ-100 Grade 1 Qualified

DESCRIPTION

The LP3907 is a multi-function, programmable Power

Management Unit, optimized for low power FPGAs,

microprocessors, and DSPs. This device integrates

two highly efficient 1A/600mA step-down DC/DC

converters with dynamic voltage management (DVM),

two 300mA linear regulators, and a 400kHz I²C \-

compatible interface to allow a host controller access

to the internal control registers of the LP3907. The

LP3907 additionally features programmable power-on

sequencing. Package options include a tiny 4 x 4 x

0.8mm WQFN 24-pin package and an even smaller

2.5 x 2.5mm DSBGA 25-bump package.

APPLICATIONS

•

FPGA, DSP Core Power

Applications Processors

Peripheral I/O Power

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

LP3907

SNVS511O –JUNE 2007–REVISED MAY 2013

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Typical Application Circuits

VINLDO12

EN_T

VDD

100k

1 PF

ENLDO1

ENLDO2

nPOR

VIN1

ENSW1

ENSW2

LDO1

10 PF

2.2 PH

SW1

FB1

10 PF

0.47 PF

VINLDO1

VINLDO2

LDO2

GND_SW1

1 PF

LP3907

VIN2

10 PF

2.2 PH

0.47 PF

SW2

FB2

SDA

SCL

10 PF

GND_SW2

AVDD

GND_L

GND_C

DAP

1 PF

Figure 1.

2

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SNVS511O –JUNE 2007–REVISED MAY 2013

DC SOURCE

4.5V - 5.5V

+

Li-ion/polymer cell 3.3V - 4.2V

Cvdd

4.7PF

LP3907 PMIC

1PF

1uF

PF

10 PF

10

1

19

13

24

10

6

ULVO

Lsw1 2.2 PH

1.2V

OSC

VBUCK1

5

SW1

10 PF

Vin OK

BUCK1

AVDD

VFB1

8

21

ENLDO1

22

7

2.2 PH

Lsw1

14

ENLDO2

ENSW 1

3.3V

VBUCK2

Power

ON-OFF

Logic

SW2

10 PF

BUCK2

AVDD

VFB2

11

12

2

ENSW 2

EN_T

VINLDO1

Thermal

Shutdown

3.3V

LDO1

20

Cldo1

0.47 PF

RESET

VinLDO12

17

16

VINLDO2

2

I C_SCL

BIAS

I²C

1.8V

LDO2

2

I C_SDA

LDO2

23

Cldo2

0.47 PF

RDY1 RDY2

VDD

Logic Control

and

Registers

100k

nPOR

Power On

Reset

3

4

15

9

18

GND_L

GND_SW1

GND_SW2

GND_C

Figure 2.

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SNVS511O –JUNE 2007–REVISED MAY 2013

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Connection Diagrams

18

17

16

15

14

13

1

2

3

4

5

6

24-Lead WQFN Package (top view)

25-Bump Thin DSBGA Package, Large Bump

Package Number YZR0025, Bottom View

Package Number YZR0025, Top View

VIN

LDO12

VIN

LDO12

VIN

LDO2

VIN

LDO2

GND_S

W1

GND_S

W1

5

4

3

SW1

VIN1

FB1

SW1

5

4

VIN

LDO12

VIN

LDO12

EN_S

W1

EN_S

W1

EN_T

LDO2

EN_T

FB1

AVDD

FB2

LDO2

EN_

LDO2

EN_

LDO1

EN_

LDO1

EN_

LDO2

GND_C

nPOR

SDA

AVDD

FB2

nPOR

SDA

GND_C

3

2

1

EN_

SW2

EN_

SW2

SCL

LDO1

2

1

VIN

LDO1

VIN

LDO1

GND_

SW2

GND_

L

GND_

SW2

GND_

L

SW2

D

VIN2

E

VIN2

E

SW2

D

A

B

C

B

A

Package Type

24-lead WQFN

25-bump DSBGA

Default I²C Address

60

61

4

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SNVS511O –JUNE 2007–REVISED MAY 2013

Table 1. Pin Descriptions⁽¹⁾

WQFN

Pin No.

DSBGA pin

no.

Name

I/O

Type

Description

1

2

B4, B5

C4

VINLDO12

EN_T

I

PWR

D

Analog Power for Internal Functions (VREF, BIAS, I²C, Logic)

Enable for preset power on sequence. (See Power-Up

Sequencing using the EN_T Function.)

3

C3

nPOR

O

D

nPOR Power on reset pin for both Buck1 and Buck 2. Open drain

logic output 100K pull-up resistor. nPOR is pulled to ground when

the voltages on these supplies are not good. See nPOR section

for more info.

4

C5

D5

E5

D4

E4

D3

E3

E2

D2

E1

D1

C1

C2

B2

B1

A1

GND_SW1

SW1

G

O

I

G

PWR

D

Buck1 NMOS Power Ground

5

Buck1 switcher output pin

6

VIN1

Power in from either DC source or Battery to Buck1

Enable Pin for Buck1 switcher, a logic HIGH enables Buck1

Buck1 input feedback terminal

7

ENSW1

FB1

I

8

I

A

9

GND_C

AVDD

FB2

G

I

G

Non switching core ground pin

Analog Power for Buck converters

Buck2 input feedback terminal

10

11

12

13

14

15

16

17

18

19

PWR

A

I

ENSW2

VIN2

I

D

Enable Pin for Buck2 switcher, a logic HIGH enables Buck2

Power in from either DC source or Battery to Buck2

Buck2 switcher output pin

I

PWR

G

SW2

O

G

I/O

I

GND_SW2

SDA

Buck2 NMOS Power ground

I²C Data (bidirectional)

I²C Clock

D

SCL

D

GND_L

VINLDO1

G

I

G

LDO ground

PWR

Power in from either DC source or battery to input terminal to

LDO1

20

21

22

23

24

A2

B3

A3

A4

A5

LDO1

ENLDO1

ENLDO2

LDO2

O

I

PWR

D

LDO1 Output

LDO1 enable pin, a logic HIGH enables the LDO1

LDO2 enable pin, a logic HIGH enables the LDO2

LDO2 Output

I

D

O

I

PWR

VINLDO2

Power in from either DC source or battery to input terminal to

LDO2.

DAP

GND

Connection isn't necessary for electrical performance, but it is

recommended for better thermal dissipation.

(1) A: Analog Pin

D: Digital Pin

G: Ground Pin

PWR: Power Pin

I: Input Pin

Note

I/O: Input/Output Pin

O: Output Pin.

Power Block Operation

Power Block Input

VINLDO12

AVDD

Enabled

VIN+⁽¹⁾

Disabled

VIN+

Always Powered

VIN+

VIN1

VIN+ or 0V

≤ VIN+

VIN2

VIN+

LDO 1

≤ VIN+

If Enabled, Min Vin is 1.74V

LDO 2

≤ VIN+

(1) VIN+ is the largest potential voltage on the device.

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SNVS511O –JUNE 2007–REVISED MAY 2013

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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Default Voltage Options⁽¹⁾⁽²⁾

Part Number

Buck1

1.5V

1.2V

1.0V

1.2V

1.0V

1.2V

1.8V

1.2V

1.8V

1.3V

Buck2

3.3V

3.4V

3.3V

3.4V

3.3V

1.8V

2.7V

1.8V

2.8V

1.8V

3.3V

2.2V

LDO1

2.5V

1.8V

2.6V

1.8V

2.65V⁽³⁾

2.6V

1.8V

3.3V

3.5V

2.85V⁽³⁾

3.3V

1.2V

2.8V

2.9V

LDO2

2.5V

3.3V

2.5V

3.3V

2.85V⁽³⁾

2.8V

2.5V

2.8V

2.4V

LP3907SQ-PXPP/NOPB

LP3907SQX-PXPP/NOPB

LP3907SQ-TJXIP/NOPB

LP3907SQX-TJXIP/NOPB

LP3907QSQ-JXIP/NOPB

LP3907QSQX-JXIP/NOPB

LP3907QSQ-JXI7/NOPB

LP3907QSQX-JXI7/NOPB

LP3907SQ-JXQX/NOPB

LP3907SQX-JXQX/NOPB

LP3907SQ-JYQX/NOPB

LP3907SQX-JYQX/NOPB

LP3907SQ-PJXIX/NOPB

LP3907SQX-PJXIX/NOPB

LP3907SQ-PFX6W/NOPB

LP3907SQX-PFX6W/NOPB

LP3907SQ-BJX6X/NOPB

LP3907SQX-BJX6X/NOPB

LP3907SQ-BJXQX/NOPB

LP3907SQX-BJXQX/NOPB

LP3907SQ-BJYQX/NOPB

LP3907SQX-BJYQX/NOPB

LP3907SQ-BJXIX/NOPB

LP3907SQX-BJXIX/NOPB

LP3907SQ-BFX6W/NOPB

LP3907SQX-BFX6W/NOPB

LP3907SQ-JJXP/NOPB

LP3907SQX-JJXP/NOPB

LP3907SQ-VRZX/NOPB

LP3907SQX-VRZX/NOPB

LP3907TL-JJ11/NOPB

LP3907TLX-JJ11/NOPB

LP3907TL-JSXS/NOPB

LP3907TLX-JSXS/NOPB

LP3907TL-JJCP/NOPB

LP3907TLX-JJCP/NOPB

LP390QTL-VXSS/NOPB

LP3907QTLX-VXSS/NOPB

LP3907TL-PLNTO/NOPB

LP3907TLX-PLNTO/NOPB

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

(3) Voltage is fixed and not programmable.

6

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SNVS511O –JUNE 2007–REVISED MAY 2013

ABSOLUTE MAXIMUM RATINGS⁽¹⁾⁽²⁾

V_IN, SDA, SCL

−0.3V to +6V

GND to GND SLUG

±0.3V

Power Dissipation (P_{D_MAX}

)

(T_A=85°C, T_MAX=125°C, )⁽³⁾

1.43W

150°C

Junction Temperature (T_J-MAX

Storage Temperature Range

Maximum Lead Temperature (Soldering)

ESD Ratings

)

−65°C to +150°C

260°C

Human Body Model

(4)

2kV

(1) Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under

which operation of the device is ensured. Operating Ratings do not imply ensured performance limits. For ensured performance limits

and associated test conditions, see the Electrical Characteristics.

(2) All voltages are with respect to the potential at the GND pin.

(3) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may

have to be derated. Maximum ambient temperature (T_A-MAX) is dependent on the maximum operating junction temperature (T_J-MAX-OP

=

125°C), the maximum power dissipation of the device in the application (P_D-MAX), and the junction-to-ambient thermal resistance of the

part/package in the application (θ_JA), as given by the following equation: T_A-MAX= T_J-MAX-OP− (θ_JA× P_D-MAX). See APPLICATION

DESCRIPTION.

(4) The Human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin. (MILSTD - 883 3015.7)

OPERATING RATINGS: BUCKS^(1)(2)(3)(4)

V_IN

2.8V to 5.5V

0 to (V_IN+ 0.3V)

−40°C to +125°C

−40°C to +85°C

V_EN

Junction Temperature (T_J) Range

Ambient Temperature (T_A) Range

(5)

(1) Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under

which operation of the device is ensured. Operating Ratings do not imply ensured performance limits. For ensured performance limits

and associated test conditions, see the Electrical Characteristics.

(2) All voltages are with respect to the potential at the GND pin.

(3) Min and Max limits are ensured by design, test, or statistical analysis. Typical numbers are not ensured, but do represent the most likely

norm.

(4) Buck V_IN≥ V_OUT+ 1V.

(5) Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power

dissipation exists, special care must be paid to thermal dissipation issues in board design.

THERMAL PROPERTIES^(1)(2)(3)

Junction-to-Ambient Thermal Resistance (θ_JA) RTW0024A

28°C/W

51°C/W

Junction-to-Ambient Thermal Resistance (θ_JA) YZR0025

(1) Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at T_J= 160°C (typ.) and

disengages at T_J= 140°C (typ.)

(2) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may

have to be derated. Maximum ambient temperature (T_A-MAX) is dependent on the maximum operating junction temperature (T_J-MAX-OP

=

125°C), the maximum power dissipation of the device in the application (P_D-MAX), and the junction-to-ambient thermal resistance of the

part/package in the application (θ_JA), as given by the following equation: T_A-MAX= T_J-MAX-OP− (θ_JA× P_D-MAX). See APPLICATION

DESCRIPTION.

(3) Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power

dissipation exists, special care must be paid to thermal dissipation issues in board design.

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GENERAL ELECTRICAL CHARACTERISTICS^{(1)(2)(3)(4)(5)}

Unless otherwise noted, V_IN= 3.6V. Typical values and limits appearing in normal type apply for T_J= 25°C. Limits appearing

in boldface type apply over the entire junction temperature range for operation, −40°C to +125°C.

Symbol

Parameter

Conditions

Min

Typ

3

Max

Units

µA

V

I_Q

VINLDO12 Shutdown Current

Power-On Reset Threshold

Thermal Shutdown Threshold

Themal Shutdown Hysteresis

Under Voltage Lock Out

V_IN= 3.6V

V_DDFalling Edge⁽⁵⁾

V_POR

T_SD

1.9

160

20

°C

T_SDH

UVLO

°C

Rising

Falling

2.9

2.7

V

(1) Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under

which operation of the device is ensured. Operating Ratings do not imply ensured performance limits. For ensured performance limits

and associated test conditions, see the Electrical Characteristics.

(2) All voltages are with respect to the potential at the GND pin.

(3) Min and Max limits are ensured by design, test, or statistical analysis. Typical numbers are not ensured, but do represent the most likely

norm.

(4) This specification is ensured by design.

(5) VPOR is voltage at which the EPROM resets. This is different from the UVLO on VINLDO12, which is the voltage at which the

regulators shut off; and is also different from the nPOR function, which signals if the regulators are in a specified range.

(1)

I²C-COMPATIBLE INTERFACE ELECTRICAL SPECIFICATIONS

Unless otherwise noted, V_IN= 3.6V. Typical values and limits appearing in normal type apply for T_J= 25°C. Limits appearing

in boldface type apply over the entire junction temperature range for operation, −40°C to +125°C

Symbol

F_CLK

Parameter

Clock Frequency

Conditions

Min

Typ

Max

Units

kHz

µs

400

(1)

t_BF

Bus-Free Time Between Start and Stop

Hold Time Repeated Start Condition

CLK Low Period

1.3

0.6

1.3

0.6

0

t_HOLD

t_CLKLP

t_CLKHP

t_SU

µs

CLK High Period

µs

Set Up Time Repeated Start Condition

Data Hold time

µs

t_DATAHLD

t_DATASU

T_SU

µs

Data Set Up Time

100

0.6

ns

Set Up Time for Start Condition

µs

T_TRANS

Maximum Pulse Width of Spikes that

Must be Suppressed by the Input Filter of

Both DATA & CLK Signals.

50

ns

(1) This specification is ensured by design.

LOW DROPOUT REGULATORS, LDO1 and LDO2

Unless otherwise noted, V_IN= 3.6V, C_IN= 1.0µF, C_OUT= 0.47µF. Typical values and limits appearing in normal type apply for

T_J= 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, −40°C to

(1)(2)(3)(4)(5)(6)(7)

+125°C.

Symbol

Parameter

Conditions

Min

Typ

Max

5.5

Units

V_IN

Operational Voltage Range

VINLDO1 and VINLDO2 PMOS

1.74

V

(8)

pins

(1) All voltages are with respect to the potential at the GND pin.

(2) Min and Max limits are ensured by design, test, or statistical analysis. Typical numbers are not ensured, but do represent the most likely

norm.

(3) C_IN, C_OUT: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics.

(4) The device maintains a stable, regulated output voltage without a load.

(5) Dropout voltage is the voltage difference between the input and the output at which the output voltage drops to 100mV below its nominal

value.

(6) Quiescent current is defined here as the difference in current between the input voltage source and the load at V_OUT

.

(7) V_INminimum for line regulation values is 1.8V.

(8) Pins 24, 19 can operate from V_INmin of 1.74 to a V_INmax of 5.5V. This rating is only for the series pass PMOS power FET. It allows the

system design to use a lower voltage rating if the input voltage comes from a buck output.

8

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LOW DROPOUT REGULATORS, LDO1 and LDO2 (continued)

Unless otherwise noted, V_IN= 3.6V, C_IN= 1.0µF, C_OUT= 0.47µF. Typical values and limits appearing in normal type apply for

T_J= 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, −40°C to

(1)(2)(3)(4)(5)(6)(7)

+125°C.

Symbol

V_OUTAccuracy

ΔV_OUT

Parameter

Output Voltage Accuracy (Default V_OUT

Line Regulation

Conditions

Min

Typ

Max

3

Units

)

Load current = 1 mA

−3

%

V_IN= (V_OUT+ 0.3V) to 5.0V,

⁽⁷⁾, Load Current = mA

0.15

%/V

Load Regulation

V_IN= 3.6V,

Load Current = 1mA to I_MAX

0.011

%/mA

mA

I_SC

Short Circuit Current Limit

Dropout Voltage

LDO1-2, V_OUT= 0V

500

30

V_IN– V_OUT

Load Current = 50mA

200

mV

(5)

PSRR

Power Supply Ripple Rejection

Supply Output Noise

Quiescent Current “On”

Quiescent Current “Off”

Turn On Time

F = 10kHz, Load Current = I_MAX

10Hz < F < 100KHz

I_OUT= 0mA

45

80

dB

µVrms

µA

θn

(6) (9)

I_Q

40

I_OUT= I_MAX

EN is de-asserted⁽¹⁰⁾

60

µA

0.03

300

µA

T_ON

Start up from shut-down

µs

C_OUT

Output Capacitor

Capacitance for stability 0°C ≤ T_J

≤ 125°C

0.33

0.47

1.0

µF

−40°C ≤ T_J≤ 125°C

0.68

5

µF

ESR

500

mΩ

(9) The I_Qcan be defined as the standing current of the LP3907 when the I²C bus is active and all other power blocks have been disabled

via the I²C bus, or it can be defined as the I²C bus active, and the other power blocks are active under no load condition. These two

values can be used by the system designer when the LP3907 is powered using a battery.

(10) The I_Qexhibits a higher current draw when the EN pin is de-asserted because the I²2 buffer pins draw an additional 2µA.

BUCK CONVERTERS SW1, SW2

Unless otherwise noted, V_IN= 3.6V, C_IN= 10µF, C_OUT= 10µF, L_OUT= 2.2µH ceramic. Typical values and limits appearing in

normal type apply for T_J= 25°C. Limits appearing in boldface type apply over the entire junction temperature range for

(1)(2)(3)(4)(5)(6)

operation, −40°C to +125°C.

Symbol

V_FB

Parameter

Feedback Voltage

Conditions

Min

Typ

Max

+3

Units

%

−3

V_OUT

Line Regulation

2.8< V_IN< 5.5

0.089

%/V

I_O=10mA

Load Regulation

100mA < I_O< I_MAX

Load Current = 250mA

EN is de-asserted

0.0013

96

%/mA

%

Eff

Efficiency

I_SHDN

f_OSC

I_PEAK

Shutdown Supply Current

Internal Oscillator Frequency

Buck1 Peak Switching Current Limit

Buck2 Peak Switching Current Limit

Quiescent Current “On”

Pin-Pin Resistance PFET

Pin-Pin Resistance NFET

0.01

2.1

µA

1.7

MHz

A

1.5

1.0

(7)

I_Q

No load PFM Mode

33

µA

mΩ

R_DSON(P)

R_DSON(N)

200

180

(1) All voltages are with respect to the potential at the GND pin.

(2) Min and Max limits are ensured by design, test, or statistical analysis. Typical numbers are not ensured, but do represent the most likely

norm.

(3) C_IN, C_OUT: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics.

(4) The device maintains a stable, regulated output voltage without a load.

(5) Quiescent current is defined here as the difference in current between the input voltage source and the load at V_OUT

.

(6) Buck V_IN≥ V_OUT+ 1V.

(7) The I_Qcan be defined as the standing current of the LP3907 when the I²C bus is active and all other power blocks have been disabled

via the I²C bus, or it can be defined as the I²C bus active, and the other power blocks are active under no load condition. These two

values can be used by the system designer when the LP3907 is powered using a battery.

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BUCK CONVERTERS SW1, SW2 (continued)

Unless otherwise noted, V_IN= 3.6V, C_IN= 10µF, C_OUT= 10µF, L_OUT= 2.2µH ceramic. Typical values and limits appearing in

normal type apply for T_J= 25°C. Limits appearing in boldface type apply over the entire junction temperature range for

(1)(2)(3)(4)(5)(6)

operation, −40°C to +125°C.

Symbol

T_ON

Parameter

Conditions

Start up from shut-down

Capacitance for stability

Min

Typ

Max

Units

µs

Turn On Time

Input Capacitor

500

C_IN

C_O

10

µF

Output Capacitor

µF

I/O ELECTRICAL CHARACTERISTICS

Unless otherwise noted: Typical values and limits appearing in normal type apply for T_J= 25°C. Limits appearing in boldface

(1)

type apply over the entire junction temperature range for operation, T_J= −40°C to +125°C.

Limit

Symbol

Parameter

Conditions

Units

Min

1.2

Max

0.4

V_IL

V_IH

Input Low Level

Input High Level

V

(1) This specification is ensured by design.

POWER-ON RESET THRESHOLD/FUNCTION (POR)

Symbol

Parameter

Conditions

Min

Typ

Max

Units

nPOR

nPOR = Power on reset forBuck1 and

Buck2

Default

50

ms

nPOR

threshold

Percentage of Target voltage Buck1 or

Buck2

V_BUCK1AND V_BUCK2rising

V_BUCK1OR V_BUCK2falling

Load = IoL = 500mA

94

85

%

V

VOL

Output Level Low

0.23

0.5

10

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TYPICAL PERFORMANCE CHARACTERISTICS — LDO

T_A= 25°C unless otherwise noted

Output Voltage Change

vs

Output Voltage Change

vs

Temperature (LDO2)

V_IN= 3.6V, V_OUT= 3.3V, 100mA load

Temperature (LDO1)

V_IN= 3.6V, V_OUT= 2.6V, 100mA load

2.00

1.50

1.00

0.50

0.00

-0.50

-1.00

-1.50

-2.00

2.00

1.50

1.00

0.50

0.00

-0.50

-1.00

-1.50

-2.00

-50 -35 -20 -5 10 25 40 55 70 85 100

TEMPERATURE (°C)

Figure 3.

Figure 4.

Load Transient (LDO1)

3.6 V_IN, 2.6V_OUT, 0 – 150mA load

Load Transient (LDO2)

3.6 V_IN, 3.3 V_OUT, 0 – 150mA load

Figure 5.

Figure 6.

Line Transient (LDO1)

3.6 - 4.2 V_IN, 2.6 V_OUT, 300mA load

Line Transient (LDO2)

3.6 – 4.2 V_IN, 3.3V_OUT, 300mA load

Figure 7.

Figure 8.

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TYPICAL PERFORMANCE CHARACTERISTICS — LDO (continued)

T_A= 25°C unless otherwise noted

Enable Start-up time (LDO1) )

0-3.6 V_IN, 2.6 V_OUT, 1mA load

Enable Start-up time (LDO2)

0 – 3.6 V_IN, 3.3 V_OUT, 1 mA load

Figure 9.

Figure 10.

LDO Maximum Load

V_IN= 1.74V

300

VIN = 1.74V

250

200

150

100

1.00 1.10 1.20 1.30 1.40 1.50 1.60

OUT(V)

V

Figure 11.

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TYPICAL PERFORMANCE CHARACTERISTICS — BUCKS

V_IN= 2.8V to 5.5V, T_A= 25°C

Output Voltage

vs.

Supply Voltage

(V_OUT= 1.0V)

Shutdown Current

vs.

Temp

0.15

0.12

0.09

0.06

0.03

0.00

1.05

1.03

1.01

0.99

0.97

0.95

I

= 20 mA

OUT

I

= 750 mA

OUT

VIN = 5.5V

VIN = 3.6V

I

= 1.0A

OUT

VIN = 2.7V

-40

-20

0

20

40

60

80

2.5

3.0

3.5

4.0

4.5

5.0

5.5

TEMPERATURE (°C)

SUPPLY VOLTAGE (V)

Figure 12.

Figure 13.

Output Voltage

vs.

Supply Voltage

(V_OUT= 1.8V)

Output Voltage

vs.

Supply Voltage

(V_OUT= 3.5V)

1.85

1.83

1.81

1.79

1.77

1.75

3.35

3.33

3.31

3.29

3.27

3.25

I

= 20 mA

OUT

I

= 20 mA

OUT

I

= 300 mA

OUT

I

= 750 mA

OUT

I

= 600 mA

OUT

I

= 1.0A

4.4

OUT

2.7

3.3

3.8

4.9

4.0

4.5

5.0

5.5

SUPPLY VOLTAGE (V)

Figure 14.

Figure 15.

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TYPICAL PERFORMANCE CHARACTERISTICS — BUCK1

V_IN= 2.8V to 5.5V, T_A= 25°C, V_OUT= 1.2V, 2.0V

Efficiency

vs

Efficiency

vs

Output Current

(V_OUT=1.2V, L= 2.2µH —(Forced PWM mode)

100

(V_OUT=2.0V, L= 2.2µH — Forced PWM mode)

100

90

80

90

80

70

60

50

40

30

20

10

= 2.8V

V

IN

= 2.8V

V_IN

70

60

50

40

30

20

10

= 3.6V

V_IN

V

= 3.6V

IN

= 5.5V

V_IN

V

= 5.5V

IN

0.1

1

10

100

1000

0.1

1

10

100

1000

OUTPUT CURRENT (mA)

Figure 16.

Figure 17.

Efficiency

vs

Efficiency

vs

Output Current

(V_OUT=1.2V, L= 2.2µH — PWM mode to PFM mode)

(V_OUT=2.0V, L= 2.2µH — PWM mode to PFM mode)

100

90

= 2.8V

V_IN

V

= 2.8V

IN

80

70

60

50

40

= 3.6V

V_IN

80

70

60

50

40

V

= 3.6V

IN

= 5.5V

V_IN

V

= 5.5V

IN

0.1

1

10

100

1000

0.1

1

10

100

1000

OUTPUT CURRENT (mA)

Figure 18.

Figure 19.

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TYPICAL PERFORMANCE CHARACTERISTICS — BUCK2

V_IN= 4.5V to 5.5V, T_A= 25°C, V_OUT= 1.8V, 3.3V

Efficiency

vs

Efficiency

vs

Output Current

(V_OUT=3.3V, L= 2.2µH — Forced PWM mode)

100

( V_OUT=1.8V, L= 2.2µH —Forced PWM mode)

100

90

80

70

90

80

= 4.5V

V_IN

70

60

50

40

30

20

10

= 4.5V

V_IN

60

50

40

30

20

10

= 5.5V

V_IN

= 5.5V

V_IN

0.1

1

10

100

1000

0.1

1

10

100

1000

OUTPUT CURRENT (mA)

Figure 20.

Figure 21.

TYPICAL PERFORMANCE CHARACTERISTICS — BUCK2

V_IN= 4.3V to 5.5V, T_A= 25°C, V_OUT= 1.8V, 3.3V

Efficiency

vs

Efficiency

vs

Output Current

(V_OUT=1.2V, L= 2.2µH — PWM mode to PFM mode)

100

(V_OUT=2.0V, L= 2.2µH — PWM mode to PFM mode)

100

90

= 4.5V

V_IN

= 5.5V

V_IN

= 4.5V

V_IN

80

70

60

50

40

80

70

60

50

40

= 5.5V

V_IN

0.1

1

10

100

1000

0.1

1

10

100

1000

OUTPUT CURRENT (mA)

Figure 22.

Figure 23.

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TYPICAL PERFORMANCE CHARACTERISTICS — BUCKS

V_IN= 3.6V, T_A= 25°C, V_OUT= 1.2V unless otherwise noted

Load Transient Response

V_OUT= 1.2V, I_LOAD= 300–500mA (PWM Mode)

Mode Change by Load Transient

V_OUT= 1.2V, I_LOAD= 50–150mA (PFM to PWM Mode)

Figure 24.

Figure 25.

Line Transient Response

V_IN= 3.6 – 4.2V, V_OUT= 1.2V, 250mA load

Line Transient Response

V_IN= 3.6 – 4.2V, V_OUT= 3.3V, 250 mA load

Figure 26.

Figure 27.

Start up into PWM Mode

V_OUT= 1.2V, 1.0A load

Start up into PWM Mode

V_OUT= 3.3 V, 600mA load

Figure 28.

Figure 29.

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TYPICAL PERFORMANCE CHARACTERISTICS — BUCKS (continued)

V_IN= 3.6V, T_A= 25°C, V_OUT= 1.2V unless otherwise noted

Start up into PFM Mode

V_OUT= 1.2V, 30mA load

Start up into PFM Mode

V_OUT= 3.3V, 30mA load

Figure 30.

Figure 31.

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DC/DC CONVERTERS

Overview

The LP3907 supplies the various power needs of the application by means of two Linear Low Drop Regulators

(LDO1 and LDO2) and two Buck converters (SW1 and SW2). The following table lists the output characteristics

of the various regulators.

Table 2. Supply Specification

Output

(1)

Supply

Load

I_MAX

V_OUTRange(V)

Resolution (mV)

Maximum Output Current (mA)

LDO1

LDO2

SW1

analog

digital

1.0 to 3.5

0.8 to 2.0

1.0 to 3.5

100

50

300

1000

600

SW2

100

(1) *For default values of the regulators, please consult Figure 2.

Linear Low Dropout Regulators (LDOS)

LDO1 and LDO2 are identical linear regulators targeting analog loads characterized by low noise requirements.

LDO1 and LDO2 are enabled through the ENLDO pin or through the corresponding LDO1 or LDO2 control

register. The output voltages of both LDOs are register programmable. The default output voltages are factory

programmed during Final Test, which can be tailored to the specific needs of the system designer.

VLDO

VIN

LDO

Register

controlled

+

-

ENLDO

Vref

GND

Figure 32.

No-Load Stability

The LDOs will remain stable and in regulation with no external load. This is an important consideration in some

circuits, for example, CMOS RAM keep-alive applications.

LDO1 and LDO2 Control Registers

LDO1 and LDO2 can be configured by means of the LDO1 and LDO2 control registers. The output voltage is

programmable in steps of 100mV from 1.0V to 3.5V by programming bits D4-0 in the LDO Control registers. Both

LDO1 and LDO2 are enabled by applying a logic 1 to the ENLDO1 and ENLDO2 pin. Enable/disable control is

also provided through enable bit of the LDO1 and LDO2 control registers. The value of the enable LDO bit in the

register is logic 1 by default. The output voltage can be altered while the LDO is enabled.

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SW1, SW2: Synchronous Step-Down Magnetic DC/DC Converters

Functional Description

The LP3907 incorporates two high-efficiency synchronous switching buck regulators, SW1 and SW2, that deliver

a constant voltage from a single Li-Ion battery to the portable system processors. Using a voltage mode

architecture with synchronous rectification, both bucks have the ability to deliver up to 1000mA and 600mA,

respectively, depending on the input voltage and output voltage (voltage head room), and the inductor chosen

(maximum current capability).

There are three modes of operation depending on the current required - PWM, PFM, and shutdown. PWM mode

handles current loads of approximately 70mA or higher, delivering voltage precision of ±3% with 90% efficiency

or better. Lighter output current loads cause the device to automatically switch into PFM for reduced current

consumption (I_Q= 15µA typ.) and a longer battery life. The Standby operating mode turns off the device, offering

the lowest current consumption. PWM or PFM mode is selected automatically or PWM mode can be forced

through the setting of the buck control register.

Both SW1 and SW2 can operate up to a 100% duty cycle (PMOS switch always on) for low drop out control of

the output voltage. In this way the output voltage will be controlled down to the lowest possible input voltage.

Additional features include soft-start, under-voltage lock-out, current overload protection, and thermal overload

protection.

Circuit Operation Description

A buck converter contains a control block, a switching PFET connected between input and output, a synchronous

rectifying NFET connected between the output and ground (BCKGND pin) and a feedback path. During the first

portion of each switching cycle, the control block turns on the internal PFET switch. This allows current to flow

from the input through the inductor to the output filter capacitor and load. The inductor limits the current to a

ramp with a slope of

V_IN- V_OUT

L

(1)

by storing energy in a magnetic field. During the second portion of each cycle, the control block turns the PFET

switch off, blocking current flow from the input, and then turns the NFET synchronous rectifier on. The inductor

draws current from ground through the NFET to the output filter capacitor and load, which ramps the inductor

current down with a slope of

-V_OUT

L

(2)

The output filter stores charge when the inductor current is high, and releases it when low, smoothing the voltage

across the load.

PWM Operation

During PWM operation the converter operates as a voltage-mode controller with input voltage feed forward. This

allows the converter to achieve excellent load and line regulation. The DC gain of the power stage is proportional

to the input voltage. To eliminate this dependence, feed forward voltage inversely proportional to the input

voltage is introduced.

Internal Synchronous Rectification

While in PWM mode, the buck uses an internal NFET as a synchronous rectifier to reduce rectifier forward

voltage drop and associated power loss. Synchronous rectification provides a significant improvement in

efficiency whenever the output voltage is relatively low compared to the voltage drop across an ordinary rectifier

diode.

Current Limiting

A current limit feature allows the converter to protect itself and external components during overload conditions.

PWM mode implements current limiting using an internal comparator that trips at 1.5A for Buck1 and at 1.0A for

Buck2 (typ). If the output is shorted to ground the device enters a timed current limit mode where the NFET is

turned on for a longer duration until the inductor current falls below a low threshold, ensuring inductor current has

more time to decay, thereby preventing runaway.

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PFM Operation

At very light loads, the converter enters PFM mode and operates with reduced switching frequency and supply

current to maintain high efficiency.

The part will automatically transition into PFM mode when either of two conditions occurs for a duration of 32 or

more clock cycles:

1. The inductor current becomes discontinuous

or

2. The peak PMOS switch current drops below the I_MODElevel

V_IN

(Typically I_MODE< 66 mA +

)

160:

(3)

During PFM operation, the converter positions the output voltage slightly higher than the nominal output voltage

during PWM operation, allowing additional headroom for voltage drop during a load transient from light to heavy

load. The PFM comparators sense the output voltage via the feedback pin and control the switching of the output

FETs such that the output voltage ramps between 0.8% and 1.6% (typical) above the nominal PWM output

voltage. If the output voltage is below the ‘low’ PFM comparator threshold, the PMOS power switch is turned on.

It remains on until the output voltage exceeds the ‘high’ PFM threshold or the peak current exceeds the I_PFMlevel

set for PFM mode. The typical peak current in PFM mode is:

V_IN

I_PFM= 66 mA +

80:

(4)

Once the PMOS power switch is turned off, the NMOS power switch is turned on until the inductor current ramps

to zero. When the NMOS zero-current condition is detected, the NMOS power switch is turned off. If the output

voltage is below the ‘high’ PFM comparator threshold (see Figure 33), the PMOS switch is again turned on and

the cycle is repeated until the output reaches the desired level. Once the output reaches the ‘high’ PFM

threshold, the NMOS switch is turned on briefly to ramp the inductor current to zero and then both output

switches are turned off and the part enters an extremely low power mode. Quiescent supply current during this

‘sleep’ mode is less than 30µA, which allows the part to achieve high efficiencies under extremely light load

conditions. When the output drops below the ‘low’ PFM threshold, the cycle repeats to restore the output voltage

to ~1.6% above the nominal PWM output voltage.

If the load current should increase during PFM mode (see Figure 33) causing the output voltage to fall below the

‘low2’ PFM threshold, the part will automatically transition into fixed-frequency PWM mode.

SW1, SW2 Operation

SW1 and SW2 have selectable output voltages ranging from 0.8V to 3.5V (typ.). Both SW1 and SW2 in the

LP3907 are I²C register controlled and are enabled by default through the internal state machine of the LP3907

following a Power-On event that moves the operating mode to the Active state. (See Flexible Power Sequencing

of Multiple Power Supplies.) The SW1 and SW2 output voltages revert to default values when the power on

sequence has been completed. The default output voltage for each buck converter is factory programmable.

(See APPLICATION DESCRIPTION).

SW1, SW2 Control Registers

SW1, SW2 can be enabled/disabled through the corresponding control register.

The Modulation mode PWM/PFM is by default automatic and depends on the load as described above in the

functional description. The modulation mode can be overridden by setting I²C bit to a logic 1 in the corresponding

buck control register, forcing the buck to operate in PWM mode regardless of the load condition.

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High PFM Threshold

PFM Mode at Light Load

~1.016 * Vout

Load current

increases

Low1 PFM Threshold

~1.008 * Vout

Current load

increases,

draws Vout

towards

Low2 PFM

Threshold

High PFM

Nfet on

Low PFM

Threshold,

turn on

Pfet on

until

Ipfm limit

reached

Voltage

drains

Threshold

inductor

reached,

current

PFET

go into

until

Low2 PFM Threshold

Vout

sleep mode

I inductor = 0

PWM Mode at

Moderate to Heavy

Loads

Low2 PFM Threshold,

switch back to PWMmode

Figure 33.

Shutdown Mode

During shutdown the PFET switch, reference, control and bias circuitry of the converters are turned off. The

NFET switch will be on in shutdown to discharge the output. When the converter is enabled, soft start is

activated. It is recommended to disable the converter during the system power up and under voltage conditions

when the supply is less than 2.8V.

Soft Start

The soft-start feature allows the power converter to gradually reach the initial steady state operating point, thus

reducing startup stresses and surges. The two LP3907 buck converters have a soft-start circuit that limits in-rush

current during startup. During startup the switch current limit is increased in steps. Soft start is activated only if

EN goes from logic low to logic high after V_INreaches 2.8V. Soft start is implemented by increasing switch

current limit in steps of 180mA, 300mA, and 720mA for Buck1; 161mA, 300mA and 536mA for Buck2 (typ.

Switch current limit). The start-up time thereby depends on the output capacitor and load current demanded at

start-up.

Low Dropout Operation

The LP3907 can operate at 100% duty cycle (no switching; PMOS switch completely on) for low dropout support

of the output voltage. In this way the output voltage will be controlled down to the lowest possible input voltage.

When the device operates near 100% duty cycle, output voltage ripple is approximately 25mV. The minimum

input voltage needed to support the output voltage is

V_{IN, MIN}= I_LOAD* (R_{DSON, PFET}+ R_INDUCTOR) + V_OUT

Load current

•

I_LOAD

Drain to source resistance of

PFET switch in the triode region

R_{DSON, PFET}

Inductor resistance

•

R_INDUCTOR

Flexible Power Sequencing of Multiple Power Supplies

The LP3907 provides several options for power on sequencing. The two bucks can be individually controlled with

ENSW1 and ENSW2. The two LDOs can also be individually controlled with ENLDO1 and ENLDO2.

If the user desires a set power on sequence, he can program the chip through I²C and raise EN_T from LOW to

HIGH to activate the power on sequencing.

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Power-Up Sequencing using the EN_T Function

EN_T assertion causes the LP3907 to emerge from Standby mode to Full Operation mode at a preset timing

sequence. By default, the enables for the LDOs and Bucks (ENLDO1, ENLDO2, EN_T, ENSW1, ENSW2) are

500K internally pulled down, which causes the part to stay OFF until enabled. If the user wishes to use the

preset timing sequence to power on the regulators, transition the EN_T pin from Low to High. Otherwise, simply

tie the enables of each specific regulator HIGH to turn on automatically.

EN_T is edge triggered with rising edge signaling the chip to power on. The EN_T input is deglitched and the

default is set at 1ms. As shown in the next 2 diagrams, a rising EN_T edge will start a power-on sequence, while

a falling EN_T edge will start a shutdown sequence. If EN_T is high, toggling the external enables of the

regulators will have no effect on the chip.

The regulators can also be programmed through I²C to turn on and off. By default, I²C enables for the regulators

on ON.

The regulators are on following the pattern below:

Regulators on = (I²C enable) AND (External pin enable OR EN_T high).

NOTE

The EN_T power-up sequencing may also be employed immediately after V_INis applied to

the device. However, V_INmust be stable for approximately 8ms minimum before EN_T be

asserted high to ensure internal bias, reference, and the Flexible POR timing are

stabilized. This initial EN_T delay is necessary only upon first time device power on for

power sequencing function to operate properly.

2

I C

Regulator ON

Ext_Enable

Pins

0

1

Start Programmed

Timing Sequence

EN_T

Figure 34.

EN_T

t

1

Vout Buck1

Vout Buck2

t

2

t

3

Vout LDO1

Vout LDO2

t

4

Figure 35. LP3907 Default Power-Up Sequence

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Table 3. Power-On Timing Specification

Symbol

Description

Min

Typ

1.5

2

Max

Units

ms

t₁

t₂

t₃

t₄

Programmable Delay from EN_T assertion to V_CC_Buck1 On

Programmable Delay from EN_T assertion to V_CC_Buck2 On

Programmable Delay from EN_T assertion to V_CC_LDO1 On

Programmable Delay from EN_T assertion to V_CC_LDO2 On

ms

3

ms

6

ms

NOTE

The LP3907 default Power on delays can be reprogrammed at final test or I²C to 1, 1.5, 2,

3, 6, or 11ms.

EN_T

Vout Buck1

t

1

Vout Buck2

Vout LDO1

t

2

t

3

Vout LDO2

t

4

Figure 36. LP3907 Default Power-Off Sequence

Symbol

Description

Min

Typ

1.5

2

Max

Units

ms

t₁

t₂

t₃

t₄

Programmable Delay from EN_T deassertion to V_CC_Buck1 Off

Programmable Delay from EN_T deassertion to V_CC_Buck2 Off

Programmable Delay from EN_T deassertion to V_CC_LDO1 Off

Programmable Delay from EN_T deassertion to V_CC_LDO2 Off

ms

3

ms

6

ms

NOTE

The LP3907 default Power on delays can be reprogrammed at final test to 0, .5, 1, 2, 5, or

10ms. Default setting is the same as the on sequence.

Flexible Power-On Reset (i.e., Power Good with delay)

The LP3907 is equipped with an internal Power-On-Reset (“POR”) circuit which monitors the output voltage

levels on bucks 1 and 2. The nPOR is an open drain logic output which is logic LOW when either of the buck

outputs are below 91% of the rising value , or when one or both outputs fall below 82% of the desired value. The

time delay between output voltage level and nPOR is enabled is (50µs, 50ms, 100ms, 200ms) 50ms by default.

The system designer can choose the external pull-up resistor (i.e. 100kΩ) for the nPOR pin.

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t2

t1

Case1

EN1

EN2

RDY1

RDY2

nPOR

0V

Counter

delay

t2

t1

Case2

EN1

EN2

RDY1

0V

RDY2

nPOR

Counter

delay

t2

t1

Case3

EN1

EN2

RDY1

RDY2

nPOR

Counter

delay

Figure 37. NPOR With Counter Delay

The above diagram shows the simplest application of the Power On Reset, where both switcher enables are tied

together. In Case 1, EN1 causes nPOR to transition LOW and triggers the nPOR delay counter. If the power

supply for Buck2 does not come on within that period, nPOR will stay LOW, indicating a power fail mode. Case 2

indicates the vice versa scenario if Buck1 supply did not come on. In both cases the nPOR remains LOW.

Case 3 shows a typical application of the Power On Reset, where both switcher enables are tied together. Even

if RDY1 ramps up slightly faster than RDY2 (or vice versa), then nPOR signal will trigger a programmable delay

before going HIGH, as explained below.

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t0 t1

t2

t3

t4

EN1

RDY1

Counter

delay

Counter

delay

nPOR

EN2

RDY2

Figure 38. Faults Occurring in Counter Delay After Startup

The above timing diagram details the Power good with delay with respect to the enable signals EN1, and EN2.

The RDY1, RDY2 are internal signals derived from the output of two comparators. Each comparator has been

trimmed as follows:

Comparator Level

Buck Supply Level

HIGH

LOW

Greater than 94%

Less than 85%

The circuits for EN1 and RDY1 is symmetrical to EN2 and RDY2, so each reference to EN1 and RDY1 will also

work for EN2 and RDY2 and vice versa.

If EN1 and RDY1 signals are High at time t1, then the RDY1 signal rising edge triggers the programmable delay

counter (50μs, 50ms, 100ms, 200ms). This delay forces nPOR LOW between time interval t1 and t2. nPOR is

then pulled high after the programmable delay is completed. Now if EN2 and RDY2 are initiated during this

interval the nPOR signal ignores this event.

If either RDY1or RDY2 were to go LOW at t3 then the programmable delay is triggered again.

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t0 t1

t2

t3

t4

EN1

RDY1

nPOR

Counter

delay

Case 1:

EN2

RDY2

Mask Time

nPOR

Mask

Window

Counter

delay

Case 2:

EN2

RDY2

0V

Mask

Window

Mask Time

Counter

delay

nPOR

Figure 39. NPOR Mask Window

If the EN1 and RDY1 are initiated in normal operation, then nPOR is asserted and deasserted as explained

above.

In Case 1, we see that case where EN2 and RDY2 are initiated after triggered programmable delay. To prevent

the nPOR being asserted again, a masked window ( 5ms ) counter delay is triggered off the EN2 rising edge.

nPOR is still held HIGH for the duration of the mask, whereupon the nPOR status afterwards will depend on the

status of both RDY1 and RDY2 lines.

In Case 2, we see the case where EN2 is initiated after the RDY1 triggered programmable delay, but RDY2

never goes HIGH (Buck2 never turns on). Normal operation operation of nPOR occurs wilth respect to EN1 and

RDY1, and the nPOR signal is held HIGH for the duration of the mask window. We see that nPOR goes LOW

after the masking window has timed out because it is now dependent on RDY1 and RDY2, where RDY2 is LOW.

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Delay Mask Counter

EN1

RDY1

S

R

Q

EN2

nPOR

RDY2

Delay

POR

Delay Mask Counter

Figure 40. Design Implementation of the Flexible Power-On Reset

An internal Power-on reset of the IC is used with EN1, and EN2 to produce a reset signal (LOW) to the delay

timer nPOR. EN1 and RDY1 or EN2 and RDY2 are used to generate the set signal (HIGH) to the delay timer.

S=R=1 never occurs. The mask timers are triggered off EN1 and EN2 which are gated with RDY1, and RDY2 to

generate outputs to the final AND gate to generate the nPOR.

Under-Voltage Lock-Out

The LP3907 features an under-voltage lock-out circuit. The function of this circuit is to continuously monitor the

raw input supply voltage (VINLDO12) and automatically disables the four voltage regulators whenever this supply

voltage is less than 2.8VDC.

The circuit incorporates a bandgap based circuit that establishes the reference used to determine the 2.8VDC

trip point for a V_INOK – Not OK detector. This V_INOK signal is then used to gate the enable signals to the four

regulators of the LP3907. When VINLDO12 is greater than 2.8VDC the four enables control the four regulators,

when VINLDO12 is less than 2.8VDC the four regulators are disabled by the V_INdetector being in the “Not OK”

state. The circuit has built in hysteresis to prevent chattering occurring.

I²C-Compatible Serial Interface

I²C SIGNALS

The LP3907 features an I²C-compatible serial interface, using two dedicated pins: SCL and SDA for I²C clock

and data respectively. Both signals need a pull-up resistor according to the I²C specification. The LP3907

interface is an I²C slave that is clocked by the incoming SCL clock.

Signal timing specifications are according to the I²C bus specification. The maximum bit rate is 400kbit/s. See I²C

specification from Philips for further details.

I²C DATA VALIDITY

The data on the SDA line must be stable during the HIGH period of the clock signal (SCL), e.g.- the state of the

data line can only be changed when CLK is LOW.

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2

I C_SCL

2

I C_SDA

data

change

allowed

data

valid

data

change

allowed

data

valid

data

change

allowed

Figure 41. I²C Signals: Data Validity

I²C Start and Stop Conditions

START and STOP bits classify the beginning and the end of the I²C session. START condition is defined as the

SDA signal transitioning from HIGH to LOW while the SCL line is HIGH. STOP condition is defined as the SDA

2

transitioning from LOW to HIGH while the SCL is HIGH. The C master always generates START and STOP

bits. The I2C bus is considered to be busy after START condition and free after STOP condition. During data

transmission, I²C master can generate repeated START conditions. First START and repeated START

conditions are equivalent, function-wise.

2

I C_SDA

2

I C_SCL

S

P

START condition

STOP condition

Figure 42. START and STOP Conditions

Transferring Data

Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first.

Each byte of data has to be followed by an acknowledge bit. The acknowledged related clock pulse is generated

by the master. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver

must pull down the SDA line during the 9th clock pulse, signifying acknowledgment. A receiver which has been

addressed must generate an acknowledgment (“ACK”) after each byte has been received.

After the START condition, the I²C master sends a chip address. This address is seven bits long followed by an

eighth bit which is a data direction bit (R/W).

NOTE

Please note that according to industry I²C standards for 7-bit addresses, the MSB of an 8-

bit address is removed, and communication actually starts with the 7th most significant bit.

For the eighth bit (LSB), a “0” indicates a WRITE and a “1” indicates a READ. The second

byte selects the register to which the data will be written. The third byte contains data to

write to the selected register.

The LP3907 has factory-programmed I²C addresses. The WQFN chip has a chip address of 60'h, while the

DSBGA chip has a chip address of 61'h.

MSB

LSB

ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0

R/W

bit0

bit7

bit6

bit5

bit4

bit3

bit2

bit1

1

0

I²C SLAVE address (chip address)

Figure 43. I²C Chip Address (see note above)

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ack from slave

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ack from slave

start msb Chip Address lsb

w

ack msb Register Add lsb ack msb

DATA

lsb ack stop

SCL

SDA

1

3 4 5 6

2

7

8

9

1 2 3 ...

start

id = K¶60

w

ack

addr = K¶02

ack

DGGUHVVꢀK¶$$ꢀGDWD

ack stop

w = write (SDA = “0”)

r = read (SDA = “1”)

ack = acknowledge (SDA pulled down by either master or slave)

rs = repeated start

id = LP3907 WQFN chip address: 0x60; DSBGA chip address: 0x61

Figure 44. I²C Write Cycle

When a READ function is to be accomplished, a WRITE function must precede the READ function, as shown in

the Read Cycle waveform.

ack from slave

ack from slave repeated start

ack from slave data from slave ack from master

start msb Chip Address lsb

w

ack msb Register Add lsb ack rs

msb Chip Address lsb

r

ack msb

DATA

lsb ack stop

.

SCL

SDA

start

id = K¶60

w

ack

register addr = K¶10

ack rs

id = K¶60

r

ack

GDWDꢀDGGUꢀK¶6A

ack stop

Figure 45. I²C Read Cycle

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LP3907 Control Registers

Register

Address

Register

Name

Read/Write

Register Description

0x02

0x07

0x10

0x11

0x20

0x23

0x24

0x25

0x29

0x2A

0x2B

0x38

0x39

0x3A

ICRA

SCR1

R

Interrupt Status Register A

System Control 1 Register

R/W

R

BKLDOEN

BKLDOSR

VCCR

Buck and LDO Output Voltage Enable Register

Buck and LDO Output Voltage Status Register

Voltage Change Control Register 1

Buck1 Target Voltage 1 Register

Buck1 Target Voltage 2 Register

Buck1 Ramp Control

R/W

B1TV1

B1TV2

B1RC

B2TV1

Buck2 Target Voltage 1 Register

Buck2 Target Voltage 2 Register

Buck2 Ramp Control

B2TV2

B2RC

BFCR

Buck Function Register

LDO1VCR

LDO2VCR

LDO1 Voltage control Registers

LDO2 Voltage control Registers

Interrupt Status Register (ISRA) 0X02

This register informs the System Engineer of the temperature status of the chip.

D7-2

D1

D0

Name

Access

Data

—

Temp 125°C

R

—

Reserved

0

Status bit for thermal warning

PMIC T>125°C

0 – PMIC Temp. < 125°C

1 – PMIC Temp. > 125°C

Reserved

0

Reset

0

Control 1 Register (SCR1) 0X07

This register allows the user to select the preset delay sequence for power-on timing, to switch between PFM

and PWM mode for the bucks, and also to select between an internal and external clock for the bucks.

D7

D6-4

D3

D2

D1

D0

Name

Access

Data

—

EN_DLY

R/W

—

FPWM2

R/W

FPWM1

R/W

ECEN

R/W

Reserved

Selects the preset

delay sequence from

EN_T assertion

Reserved

Buck2 PWM /PFM Mode Buck 1 PWM /PFM

select

0 – Auto Switch PFM -

PWM operation

1 – PWM Mode Only

Reserved

Mode select

0 – Auto Switch PFM -

PWM operation

(shown below)

1 – PWM Mode Only

Reset

0

Factory-Programmed

Default

1

Factory-Programmed

Default

Factory-Programmed

Default

0

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EN_DLY Preset Delay Sequence after EN_T Assertion

Delay (ms)

EN_DLY<2:0>

Buck1

1

Buck2

LDO1

LDO2

000

001

010

011

100

101

110

111

1

1.5

2

1

2

3

1

3

2

1

6

1

2

1

1.5

3

6

2

1

2

6

1.5

2

1.5

11

2

3

Buck and LDO Output Voltage Enable Register (BKLDOEN) – 0X10

This register controls the enables for the Bucks and LDOs.

D7

D6

LDO2EN

R/W

D5

D4

LDO1EN

R/W

D3

D2

D1

D0

BK1EN

R/W

Name

Access

Data

—

BK2EN

R/W

—

Reserved

0 – Disable

1 – Enable

Reserved

0 – Disable

1 – Enable

Reserved

0 – Disable

1 – Enable

Reserved

0 – Disable

1 – Enable

Reset

0

1

0

1

0

1

Buck AND LDO Status Register (BKLDOSR) – 0X11

This register monitors whether the Bucks and LDOs meet the voltage output specifications.

D7

BKS_OK

R

D6

LDOS_OK

R

D5

LDO2_OK

R

D4

LDO1_OK

R

D3

D2

BK2_OK

D1

D0

Name

Access

Data

—

BK1_OK

R

0 – Buck 1-2

Not Valid

0 – LDO 1-2

Not Valid

0 – LDO2 Not

Valid

0 – LDO1 Not

Valid

Reserve 0 – Buck2 Not

Reserve 0 – Buck1 Not

d

Valid

d

Valid

1 – Bucks Valid 1 – LDOs Valid 1 – LDO2 Valid 1 – LDO1 Valid

1 – Buck2 Valid

1 – Buck1 Valid

Reset

0

Buck Voltage Change Control Register 1 (VCCR) – 0X20

This register selects and controls the output target voltages for the buck regulators.

D7-6

D5

D4

D3-2

D1

D0

Name

Access

Data

—

B2VS

R/W

B2GO

R/W

—

B1VS

R/W

B1GO

R/W

Reserved

Buck2 Target Voltage

Select

Buck2 Voltage Ramp

CTRL

Reserved

Buck1 Target Voltage

Select

Buck1 Voltage Ramp

CTRL

0 – B2VT1

0 – Hold

0 – B1VT1

0 – Hold

1 – B2VT2

1 – Ramp to B2VS

selection

1 – B1VT2

1 – Ramp to B1VS

selection

Reset

00

0

00

0

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Buck1 Target Voltage 1 Register (B1TV1) – 0X23

This register allows the user to program the output target voltage of Buck1.

D7-5

D4-0

BK1_VOUT1

Name

Access

Data

—

R/W

Reserved

Buck1 Output Voltage (V)

5’h00

5’h01

5’h02

5’h03

5’h04

5’h05

5’h06

5’h07

5’h08

5’h09

5’h0A

5’h0B

5’h0C

5’h0D

5’h0E

5’h0F

5’h10

5’h11

5’h12

5’h13

5’h14

5’h15

5’h16

5’h17

5’h18

5’h19

5’h1A–5’h1F

Ext Ctrl

0.80

0.85

0.90

0.95

1.00

1.05

1.10

1.15

1.20

1.25

1.30

1.35

1.40

1.45

1.50

1.55

1.60

1.65

1.70

1.75

1.80

1.85

1.90

1.95

2.00

Reset

000

Factory-Programmed Default

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Buck1 Target Voltage 2 Register (B1TV2) – 0X24

This register allows the user to program the output target voltage of Buck1.

D7-5

D4-0

BK1_VOUT2

Name

Access

Data

—

R/W

Reserved

Buck1 Output Voltage (V)

(1)

5’h00

5’h01

5’h02

5’h03

5’h04

5’h05

5’h06

5’h07

5’h08

5’h09

5’h0A

5’h0B

5’h0C

5’h0D

5’h0E

5’h0F

5’h10

5’h11

5’h12

5’h13

5’h14

5’h15

5’h16

5’h17

5’h18

5’h19

5’h1A–5’h1F

Ext Ctrl

0.80

0.85

0.90

0.95

1.00

1.05

1.10

1.15

1.20

1.25

1.30

1.35

1.40

1.45

1.50

1.55

1.60

1.65

1.70

1.75

1.80

1.85

1.90

1.95

2.00

Reset

000

Factory-Programmed Default

(1) If using Ext Ctrl, contact TI Sales for support.

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Buck1 Ramp Control Register (B1RC) - 0x25

This register allows the user to program the rate of change between the target voltages of Buck1.

D7

- - - -

D6-4

- - - -

D3-0

B1RS

R/W

Name

Access

Data

- - - -

Reserved

Data Code

4h'0

Ramp Rate mV/us

Instant

4h'1

1

2

4h'2

4h'3

3

4h'4

4

4h'5

5

4h'6

6

4h'7

7

4h'8

8

4h'9

9

4h'A

10

4h'B - 4h'F

Reset

0

010

1000

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Buck2 Target Voltage 1 Register (B2TV1) – 0X29

This register allows the user to program the output target voltage of Buck2.

D7-5

D4-0

Name

Access

Data

—

BK2_VOUT1

R/W

Reserved

Buck2 Output Voltage (V)

5’h00

5’h01

5’h02

5’h03

5’h04

5’h05

5’h06

5’h07

5’h08

5’h09

5’h0A

5’h0B

5’h0C

5’h0D

5’h0E

5’h0F

5’h10

5’h11

5’h12

5’h13

5’h14

5’h15

5’h16

5’h17

5’h18

5’h19

5’h1A–5’h1F

Ext Ctrl

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

2.0

2.1

2.2

2.4

2.5

2.6

2.7

2.8

2.9

3.0

3.1

3.2

3.3

3.4

3.5

Reset

000

Factory-Programmed Default

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Buck2 Target Voltage 2 Register (B2TV2) – 0X2A

This register allows the user to program the output target voltage of Buck2.

D7-5

D4-0

BK2_VOUT2

Name

Access

Data

—

R/W

Reserved

Buck2 Output Voltage (V)

(1)

5’h00

5’h01

5’h02

5’h03

5’h04

5’h05

5’h06

5’h07

5’h08

5’h09

5’h0A

5’h0B

5’h0C

5’h0D

5’h0E

5’h0F

5’h10

5’h11

5’h12

5’h13

5’h14

5’h15

5’h16

5’h17

5’h18

5’h19

5’h1A–5’h1F

Ext Ctrl

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

2.0

2.1

2.2

2.4

2.5

2.6

2.7

2.8

2.9

3.0

3.1

3.2

3.3

3.4

3.5

Reset

000

Factory-Programmed Default

(1) If using Ext Ctrl, contact TI Sales for support.

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Buck2 Ramp Control Register (B2RC) - 0x2B

This register allows the user to program the rate of change between the target voltages of Buck2.

D7

- - - -

D6-4

- - - -

D3-0

B2RS

R/W

Name

Access

Data

- - - -

Reserved

Data Code

4h'0

Ramp Rate mV/us

Instant

4h'1

1

2

4h'2

4h'3

3

4h'4

4

4h'5

5

4h'6

6

4h'7

7

4h'8

8

4h'9

9

4h'A

10

4h'B - 4h'F

Reset

0

010

1000

Buck Runction Register (BFCR) – 0x38

This register allows the Buck switcher clock frequency to be spread across a wider range, allowing for less

Electro-magnetic Interference (EMI). The spread spectrum modulation frequency refers to the rate at which the

frequency ramps up and down, centered at 2MHz.

Spread Spectrum

frequency

Peak frequency deviation

2 kHz triangle

wave

10 kHz triangle

wave

2 MHz

Time

Figure 46.

This register also allows dynamic scaling of the nPOR Delay Timing. The LP3907 is equipped with an internal

Power-On-Reset (“POR”) circuit which monitors the output voltage levels on the buck regulators, allowing the

user to more actively monitor the power status of the chip.

The Under Voltage Lock-Out feature continuously monitor the raw input supply voltage (VINLDO12) and

automatically disables the four voltage regulators whenever this supply voltage is less than 2.8VDC. This

prevents the user from damaging the power source (i.e. battery), but can be disabled if the user wishes.

Note that if the supply to VDD_M is close to 2.8V with a heavy load current on the regulators, the chip is in

danger of powering down due to UVLO. If the user wishes to keep the chip active under those conditions, enable

the “Bypass UVLO” feature.

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D7-2

D4

BP_UVLO

D3

D1

BK_SLOMOD

D0

Name

Access

Data

—

TPOR

R/w

BK_SSEN

R/W

Reserved

Bypass UVLO

monitoring

nPOR Delay Timing

00 - 50µs

Buck Spread Spectrum

Modulation

Spread Spectrum

Function Output

0 - Allow UVLO

1 - Disable UVLO

01 - 50ms

10 - 100ms

11 - 200ms

0 – 10 kHz triangular wave 0 – Disabled

1 – 2 kHz triangular wave

1 – Enabled

Reset

000

Factory-Programmed

Default

01

1

0

LDO1 Control Register (LDO1VCR) – 0X39

This register allows the user to program the output target voltage of LDO 1.

For “JJ11” voltage options LDO1 has a fixed output voltage of 2.85V.

D7-5

D4-0

LDO1_OUT

R/W

Name

Access

Data

—

Reserved

LDO1 Output voltage (V)

5’h00

5’h01

5’h02

5’h03

5’h04

5’h05

5’h06

5’h07

5’h08

5’h09

5’h0A

5’h0B

5’h0C

5’h0D

5’h0E

5’h0F

5’h10

5’h11

5’h12

5’h13

5’h14

5’h15

5’h16

5’h17

5’h18

5’h19

5’h1A–5’h1F

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

2.0

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

3.0

3.1

3.2

3.3

3.4

3.5

Reset

000

Factory-Programmed Default

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LDO2 Control Register (LDO2VCR) – 0X3A

This register allows the user to program the output target voltage of LDO 2.

For “JJ11” voltage options LDO2 has a fixed output voltage of 2.85V.

D7-5

D4-0

Name

Access

Data

—

LDO2_OUT

R/W

Reserved

LDO2 Output voltage (V)

5’h00

5’h01

5’h02

5’h03

5’h04

5’h05

5’h06

5’h07

5’h08

5’h09

5’h0A

5’h0B

5’h0C

5’h0D

5’h0E

5’h0F

5’h10

5’h11

5’h12

5’h13

5’h14

5’h15

5’h16

5’h17

5’h18

5’h19

5’h1A–5’h1F

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

2.0

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

3.0

3.1

3.2

3.3

3.4

3.5

Reset

000

Factory-Programmed Default

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APPLICATION DESCRIPTION

Analog Power Signal Routing

All power inputs should be tied to the main VDD source (for example, battery), unless the user wishes to power it

from another source. (i.e. external LDO output).

The analog VDD inputs power the internal bias and error amplifiers, so they should be tied to the main VDD. The

analog VDD inputs must have an input voltage between 2.8 and 5.5V, as specified in the Electrical

Characteristics Section in the front of the datasheet.

The other V_INs (V_INLDO1, V_INLDO2, V_IN1, V_IN2) can actually have inputs lower than 2.8V, as long as it's higher

than the programmed output (+0.3V, to be safe).

The analog and digital grounds should be tied together outside of the chip to reduce noise coupling.

Component Selection

Inductors for SW1 and SW2

There are two main considerations when choosing an inductor; the inductor should not saturate and the inductor

current ripple is small enough to achieve the desired output voltage ripple. Care should be taken when reviewing

the different saturation current ratings that are specified by different manufacturers. Saturation current ratings are

typically specified at 25ºC, so ratings at maximum ambient temperature of the application should be requested

from the manufacturer.

There are two methods to choose the inductor saturation current rating:

Method 1:

The saturation current is greater than the sum of the maximum load current and the worst case average to peak

inductor current. This can be written as follows:

I_sat> I_outmax+ I_ripple

V_IN- V_OUT

2L

· _x§^V^OUT

·

¹

1

§ ·

§

©

x

where

I_ripple

⁼© _f¹

V

¹ ©

IN

(5)

I_RIPPLE: Average to peak inductor current

I_OUTMAX: Maximum load current

V_IN: Maximum input voltage to the buck

L:

f:

Min inductor value including worse case tolerances (30% drop can be considered for method 1)

Minimum switching frequency (1.6 MHz)

V_OUT: Buck Output voltage

Method 2:

A more conservative and recommended approach is to choose an inductor that has saturation current rating

greater than the maximum current limit of 1250mA for Buck1 and 1750mA for Buck2.

Given a peak-to-peak current ripple (I_PP) the inductor needs to be at least

V_IN- V_OUT

I_PP

· _x§^V^OUT

·

¹

§ ·

1

§

©

x

L t

V

¹ ©

IN

(6)

Inductor

Value

2.2

Unit

Description

Notes

L_SW1,2

µH

SW1,2 inductor

D.C.R. 70mΩ

40

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SNVS511O –JUNE 2007–REVISED MAY 2013

External Capacitors

The regulators on the LP3907 require external capacitors for regulator stability. These are specifically designed

for portable applications requiring minimum board space and smallest components. These capacitors must be

correctly selected for good performance.

LDO Capacitor Selection

Input Capacitor

An input capacitor is required for stability. It is recommended that a 1.0μF capacitor be connected between the

LDO input pin and ground (this capacitance value may be increased without limit).

This capacitor must be located a distance of not more than 1cm from the input pin and returned to a clean

analog ground. Any good quality ceramic, tantalum, or film capacitor may be used at the input.

Important: Tantalum capacitors can suffer catastrophic failures due to surge currents when connected to a low

impedance source of power (like a battery or a very large capacitor). If a tantalum capacitor is used at the input,

it must be ensured by the manufacturer to have a surge current rating sufficient for the application.

There are no requirements for the ESR (Equivalent Series Resistance) on the input capacitor, but tolerance and

temperature coefficient must be considered when selecting the capacitor to ensure the capacitance will remain

approximately 1.0μF over the entire operating temperature range.

Output Capacitor

The LDOs on the LP3907 are designed specifically to work with very small ceramic output capacitors. A 0.47µF

ceramic capacitor (temperature types Z5U, Y5V or X7R) with ESR between 5 mΩ to 500mΩ, is suitable in the

application circuit.

It is also possible to use tantalum or film capacitors at the device output, C_OUT(or V_OUT), but these are not as

attractive for reasons of size and cost.

The output capacitor must meet the requirement for the minimum value of capacitance and also have an ESR

value that is within the range 5 mΩ to 500 mΩ for stability.

Capacitor Characteristics

The LDOs are designed to work with ceramic capacitors on the output to take advantage of the benefits they

offer. For capacitance values in the range of 0.47µF to 4.7µF, ceramic capacitors are the smallest, least

expensive and have the lowest ESR values, thus making them best for eliminating high frequency noise. The

ESR of a typical 1.0µF ceramic capacitor is in the range of 20mΩ to 40mΩ, which easily meets the ESR

requirement for stability for the LDOs.

For both input and output capacitors, careful interpretation of the capacitor specification is required to ensure

correct device operation. The capacitor value can change greatly, depending on the operating conditions and

capacitor type.

In particular, the output capacitor selection should take account of all the capacitor parameters, to ensure that the

specification is met within the application. The capacitance can vary with DC bias conditions as well as

temperature and frequency of operation. Capacitor values will also show some decrease over time due to aging.

The capacitor parameters are also dependent on the particular case size, with smaller sizes giving poorer

performance figures in general. As an example, below is typical graph comparing different capacitor case sizes in

a Capacitance vs. DC Bias plot.

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0603, 10V, X5R

100%

80%

60%

40%

20%

0402, 6.3V, X5R

0

1.0

2.0

3.0

4.0

5.0

DC BIAS (V)

Figure 47. Graph Showing a Typical Variation in Capacitance vs. DC Bias

As shown in the graph, increasing the DC Bias condition can result in the capacitance value that falls below the

minimum value given in the recommended capacitor specifications table. Note that the graph shows the

capacitance out of spec for the 0402 case size capacitor at higher bias voltages. It is therefore recommended

that the capacitor manufacturers' specifications for the nominal value capacitor are consulted for all conditions,

as some capacitor sizes (e.g. 0402) may not be suitable in the actual application.

The ceramic capacitor’s capacitance can vary with temperature. The capacitor type X7R, which operates over a

temperature range of −55°C to +125°C, will only vary the capacitance to within ±15%. The capacitor type X5R

has a similar tolerance over a reduced temperature range of −55°C to +85°C. Many large value ceramic

capacitors, larger than 1µF are manufactured with Z5U or Y5V temperature characteristics. Their capacitance

can drop by more than 50% as the temperature varies from 25°C to 85°C. Therefore X7R is recommended over

Z5U and Y5V in applications where the ambient temperature will change significantly above or below 25°C.

Tantalum capacitors are less desirable than ceramic for use as output capacitors because they are more

expensive when comparing equivalent capacitance and voltage ratings in the 0.47µF to 4.7µF range.

Another important consideration is that tantalum capacitors have higher ESR values than equivalent size

ceramics. This means that while it may be possible to find a tantalum capacitor with an ESR value within the

stable range, it would have to be larger in capacitance (which means bigger and more costly) than a ceramic

capacitor with the same ESR value. It should also be noted that the ESR of a typical tantalum will increase about

2:1 as the temperature goes from 25°C down to −40°C, so some guard band must be allowed.

Input Capacitor Selection for SW1 and SW2

A ceramic input capacitor of 10µF, 6.3V is sufficient for the magnetic dc/dc converters. Place the input capacitor

as close as possible to the input of the device. A large value may be used for improved input voltage filtering.

The recommended capacitor types are X7R or X5R. Y5V type capacitors should not be used. DC bias

characteristics of ceramic capacitors must be considered when selecting case sizes like 0805 and 0603. The

input filter capacitor supplies current to the PFET switch of the dc/dc converter in the first half of each cycle and

reduces voltage ripple imposed on the input power source. A ceramic capacitor’s low ESR (Equivalent Series

Resistance) provides the best noise filtering of the input voltage spikes due to fast current transients. A capacitor

with sufficient ripple current rating should be selected. The Input current ripple can be calculated as:

r²

V_OUT

§

©

·

¹

(V_in± V_out) x V_out

I_rms= I_outmax

1 +

where

r =

V_IN

12

L x f x I_outmaxx V_in

(7)

The worse case is when V_IN= 2V_OUT

.

42

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Output Capacitor Selection for SW1, SW2

A 10μF, 6.3V ceramic capacitor should be used on the output of the sw1 and sw2 magnetic dc/dc converters.

The output capacitor needs to be mounted as close as possible to the output of the device. A large value may be

used for improved input voltage filtering. The recommended capacitor types are X7R or X5R. Y5V type

capacitors should not be used. DC bias characteristics of ceramic capacitors must be considered when selecting

case sizes like 0805 and 0603. DC bias characteristics vary from manufacturer to manufacturer and DC bias

curves should be requested from them and analyzed as part of the capacitor selection process.

The output filter capacitor of the magnetic dc/dc converter smooths out current flow from the inductor to the load,

helps maintain a steady output voltage during transient load changes and reduces output voltage ripple. These

capacitors must be selected with sufficient capacitance and sufficiently low ESD to perform these functions.

The output voltage ripple is caused by the charging and discharging of the output capacitor and also due to its

ESR and can be calculated as follows:

I_ripple

V_pp-c

=

4 x f x C

(8)

(9)

Voltage peak-to-peak ripple due to ESR can be expressed as follows:

V_PP–ESR= 2 × I_RIPPLE× R_ESR

Because the V_PP-Cand V_PP-ESRare out of phase, the rms value can be used to get an approximate value of the

peak-to-peak ripple:

V_pp-c²+ V_pp-esr

2

V_pp-rms

=

(10)

Note that the output voltage ripple is dependent on the inductor current ripple and the equivalent series

resistance of the output capacitor (R_ESR). The R_ESRis frequency dependent as well as temperature dependent.

The R_ESRshould be calculated with the applicable switching frequency and ambient temperature.

Capacitor

Min Value

0.47

Unit

µF

Description

LDO1 output capacitor

LDO2 output capacitor

SW1 output capacitor

SW2 output capacitor

Recommended Type

Ceramic, 6.3V, X5R

C_LDO1

C_LDO2

C_SW1

C_SW2

0.47

µF

Ceramic, 6.3V, X5R

10.0

µF

10.0

µF

I²C Pull-up Resistor

Both SDA and SCL terminals need to have pull-up resistors connected to VINLDO12 or to the power supply of

the I²C master. The values of the pull-up resistors (typ. ∼1.8kΩ) are determined by the capacitance of the bus.

Too large of a resistor combined with a given bus capacitance will result in a rise time that would violate the max.

rise time specification. A too small resistor will result in a contention with the pull-down transistor on either

slave(s) or master.

Operation without I²C Interface

Operation of the LP3907 without the I²C interface is possible if the system can operate with default values for the

LDO and Buck regulators. (Read below: Factory programmable options). The I²C-less system must rely on the

correct default output values of the LDO and Buck converters.

Factory Programmable Options

The following options are EPROM programmed during final test of the LP3907. The system designer that needs

specific options is advised to contact the TI sales office.

Factory programmable options

Enable delay for power on

Current value

code 010 (see Control 1 Register (SCR1) 0X07)

SW1 ramp speed

SW2 ramp speed

8 mV/µs

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The I²C Chip ID address is offered as a metal mask option. The current address for the WQFN chip equals 0x60,

while the address for the DSBGA chip is 0x61.

High V_INHigh-Load Operation

Additional information is provided when the IC is operated at extremes of V_INand regulator loads. These are

described in terms of the Junction temperature and, Buck output ripple management.

Junction Temperature

The maximum junction temperature T_J-MAX-OPof 125°C of the IC package.

The following equations demonstrate junction temperature determination, ambient temperature T_A-MAXand Total

chip power must be controlled to keep T_Jbelow this maximum:

T^J-MAX-OP= T_A-MAX+ (θ_JA) [°C/ Watt] * (P_D-MAX) [Watts]

Total IC power dissipation P_D-MAXis the sum of the individual power dissipation of the four regulators plus a minor

amount for chip overhead. Chip overhead is Bias, TSD & LDO analog.

P^D-MAX= P_LDO1+ P_LD02+ P_BUCK1+ P_BUCK2+ (0.0001A * V_IN) [Watts].

Power dissipation of LDO1

P_LDO1= (V_INLDO1- V_OUTLDO1) * Iout_LDO1[V*A]

Power dissipation of LDO2

P_LDO2= (V_INLDO2- Vout_LDO2) * Iout_LDO2[V*A]

Power dissipation of Buck1

P_Buck1= P_IN– P_OUT

=

Vout_Buck1* Iout_Buck1* (1 -η₁) / η₁[V*A]

η₁= efficiency of buck 1

Power dissipation of Buck2

P_Buck2= P_IN– P_OUT

=

Vout_Buck2* Iout_Buck2* (1 - η₂) / η₂[V*A]

η₂= efficiency of Buck2

Where η is the efficiency for the specific condition taken from efficiency graphs.

44

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SNVS511O –JUNE 2007–REVISED MAY 2013

Thermal Performance of the WQFN Package

The LP3907 is a monolithic device with integrated power FETs. For that reason, it is important to pay special

attention to the thermal impedance of the WQFN package and to the PCB layout rules in order to maximize

power dissipation of the WQFN package.

The WQFN package is designed for enhanced thermal performance and features an exposed die attach pad at

the bottom center of the package that creates a direct path to the PCB for maximum power dissipation.

Compared to the traditional leaded packages where the die attach pad is embedded inside the molding

compound, the WQFN reduces one layer in the thermal path.

The thermal advantage of the WQFN package is fully realized only when the exposed die attach pad is soldered

down to a thermal land on the PCB board with thermal vias planted underneath the thermal land. Based on

thermal analysis of the WQFN package, the junction-to-ambient thermal resistance (θ_JA) can be improved by a

factor of two when the die attach pad of the WQFN package is soldered directly onto the PCB with thermal land

and thermal vias, as opposed to an alternative with no direct soldering to a thermal land. Typical pitch and outer

diameter for thermal vias are 1.27mm and 0.33mm respectively. Typical copper via barrel plating is 1oz, although

thicker copper may be used to further improve thermal performance. The LP3907 die attach pad is connected to

the substrate of the IC, and therefore, the thermal land and vias on the PCB board need to be connected to

ground (GND pin).

For more information on board layout techniques, refer to Application Note AN–1187 “Leadless Lead Frame

Package (LLP)” SNOA401 on http://www.ti.com This application note also discusses package handling, solder

stencil and the assembly process.

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REVISION HISTORY

Changes from Revision N (May 2013) to Revision O

Page

•

Changed layout of National Data Sheet to TI format .......................................................................................................... 45

46

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PACKAGE MATERIALS INFORMATION

www.ti.com

11-Oct-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

LP3907QSQ-JJXP/NOPB WQFN

LP3907QSQ-JXI7/NOPB WQFN

LP3907QSQ-JXIP/NOPB WQFN

RTW

24

1000

4500

178.0

330.0

12.4

4.3

1.3

8.0

12.0

Q1

LP3907QSQX-JJXP/NOP WQFN

B

LP3907QSQX-JXI7/NOPB WQFN

LP3907QSQX-JXIP/NOPB WQFN

LP3907QTL-VXSS/NOPB DSBGA

RTW

YZR

24

25

4500

250

330.0

178.0

12.4

8.4

4.3

1.3

8.0

4.0

12.0

8.0

Q1

2.69

0.76

LP3907QTLX-VXSS/NOP DSBGA

B

3000

8.4

8.0

LP3907SQ-BFX6W/NOPB WQFN

LP3907SQ-BJX6X/NOPB WQFN

LP3907SQ-BJXIX/NOPB WQFN

LP3907SQ-BJXQX/NOPB WQFN

LP3907SQ-BJYQX/NOPB WQFN

LP3907SQ-JXQX/NOPB WQFN

LP3907SQ-PFX6W/NOPB WQFN

LP3907SQ-PJXIX/NOPB WQFN

LP3907SQ-PXPP/NOPB WQFN

RTW

24

1000

178.0

12.4

4.3

1.3

8.0

12.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

11-Oct-2013

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

LP3907SQ-VRZX/NOPB WQFN

RTW

24

1000

4500

178.0

330.0

12.4

4.3

1.3

8.0

12.0

Q1

LP3907SQX-BFX6W/NOP WQFN

B

LP3907SQX-BJX6X/NOP WQFN

B

RTW

24

4500

330.0

12.4

4.3

1.3

8.0

12.0

Q1

LP3907SQX-BJXIX/NOPB WQFN

RTW

24

4500

330.0

12.4

4.3

1.3

8.0

12.0

Q1

LP3907SQX-BJXQX/NOP WQFN

B

LP3907SQX-BJYQX/NOP WQFN

B

RTW

24

4500

330.0

12.4

4.3

1.3

8.0

12.0

Q1

LP3907SQX-JXQX/NOPB WQFN

RTW

24

4500

330.0

12.4

4.3

1.3

8.0

12.0

Q1

LP3907SQX-PFX6W/NOP WQFN

B

LP3907SQX-PJXIX/NOPB WQFN

LP3907SQX-PXPP/NOPB WQFN

LP3907SQX-VRZX/NOPB WQFN

LP3907TL-JJ11/NOPB DSBGA

LP3907TL-JJCP/NOPB DSBGA

LP3907TL-JSXS/NOPB DSBGA

LP3907TL-PLNTO/NOPB DSBGA

LP3907TLX-JJ11/NOPB DSBGA

LP3907TLX-JJCP/NOPB DSBGA

LP3907TLX-JSXS/NOPB DSBGA

RTW

YZR

24

25

4500

250

330.0

178.0

12.4

8.4

4.3

1.3

8.0

4.0

12.0

8.0

Q1

4.3

1.3

2.69

0.76

250

8.4

8.0

250

8.4

8.0

250

8.4

8.0

3000

8.4

8.0

8.4

8.0

8.4

8.0

LP3907TLX-PLNTO/NOP DSBGA

B

8.4

8.0

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

11-Oct-2013

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

LP3907QSQ-JJXP/NOPB

LP3907QSQ-JXI7/NOPB

LP3907QSQ-JXIP/NOPB

LP3907QSQX-JJXP/NOPB

LP3907QSQX-JXI7/NOPB

LP3907QSQX-JXIP/NOPB

LP3907QTL-VXSS/NOPB

LP3907QTLX-VXSS/NOPB

LP3907SQ-BFX6W/NOPB

LP3907SQ-BJX6X/NOPB

LP3907SQ-BJXIX/NOPB

LP3907SQ-BJXQX/NOPB

LP3907SQ-BJYQX/NOPB

LP3907SQ-JXQX/NOPB

LP3907SQ-PFX6W/NOPB

LP3907SQ-PJXIX/NOPB

LP3907SQ-PXPP/NOPB

LP3907SQ-VRZX/NOPB

WQFN

DSBGA

WQFN

RTW

YZR

24

25

24

1000

4500

250

210.0

367.0

210.0

367.0

185.0

367.0

185.0

367.0

35.0

YZR

3000

1000

4500

RTW

LP3907SQX-BFX6W/NOP

B

LP3907SQX-BJX6X/NOPB

WQFN

RTW

24

4500

367.0

35.0

Pack Materials-Page 3

PACKAGE MATERIALS INFORMATION

www.ti.com

11-Oct-2013

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

LP3907SQX-BJXIX/NOPB

WQFN

RTW

24

4500

367.0

35.0

LP3907SQX-BJXQX/NOP

B

LP3907SQX-BJYQX/NOP

B

WQFN

RTW

24

4500

367.0

35.0

LP3907SQX-JXQX/NOPB

WQFN

RTW

24

4500

367.0

35.0

LP3907SQX-PFX6W/NOP

B

LP3907SQX-PJXIX/NOPB

LP3907SQX-PXPP/NOPB

LP3907SQX-VRZX/NOPB

LP3907TL-JJ11/NOPB

WQFN

RTW

YZR

24

25

4500

250

367.0

210.0

367.0

185.0

35.0

WQFN

DSBGA

LP3907TL-JJCP/NOPB

LP3907TL-JSXS/NOPB

LP3907TL-PLNTO/NOPB

LP3907TLX-JJ11/NOPB

LP3907TLX-JJCP/NOPB

LP3907TLX-JSXS/NOPB

LP3907TLX-PLNTO/NOPB

250

3000

Pack Materials-Page 4

MECHANICAL DATA

RTW0024A

SQA24A (Rev B)

www.ti.com

MECHANICAL DATA

YZR0025xxx

0.600±0.075

D

E

TLA25XXX (Rev D)

D: Max = 2.521 mm, Min = 2.46 mm

E: Max = 2.521 mm, Min = 2.46 mm

4215055/A

12/12

A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.

B. This drawing is subject to change without notice.

NOTES:

www.ti.com

IMPORTANT NOTICE

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Products

Applications

Audio

www.ti.com/audio

amplifier.ti.com

dataconverter.ti.com

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Communications and Telecom www.ti.com/communications

Amplifiers

Data Converters

DLP® Products

DSP

Computers and Peripherals

Consumer Electronics

Energy and Lighting

Industrial

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Interface

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interface.ti.com

logic.ti.com

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www.ti.com/medical

Medical

Logic

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Power Mgmt

Microcontrollers

RFID

power.ti.com

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Video and Imaging

www.ti.com/space-avionics-defense

www.ti.com/video

microcontroller.ti.com

www.ti-rfid.com

www.ti.com/omap

OMAP Applications Processors

Wireless Connectivity

TI E2E Community

e2e.ti.com

www.ti.com/wirelessconnectivity

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	LP3907SQ-PXPP/NOPB
厂家：	TEXAS INSTRUMENTS
描述：	Dual High-Current Step-Down DC/DC and Dual Linear Regulator with I2C-Compatible Interface 24-WQFN -40 to 85 开关
文件：	总57页 (文件大小：3508K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LP3907SQ-PXPP/NOPB [TI]

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