LP3950 [TI]
具有音频同步器的彩色 LED 驱动器;
| 型号： | LP3950 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有音频同步器的彩色 LED 驱动器 驱动 驱动器 |
| 文件： | 总38页 (文件大小：1909K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LP3950
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SNVS331C –NOVEMBER 2004–REVISED APRIL 2013
LP3950 Color LED Driver with Audio Synchronizer
Check for Samples: LP3950
1
FEATURES
DESCRIPTION
The LP3950 is a color LED driver with a built-in audio
synchronization feature for any analog audio input
such as polyphonic ring tones and MP3 music. LEDs
can be synchronized to an audio signal with two
methods - amplitude and frequency. Also several fine
tuning options are available for differentiation
purposes. The chip also has an unique AGC
(Automatic Gain Control) feature which tracks the
input signal level and automatically adjusts the gain
to an optimal value.
2
•
•
•
•
•
Audio Synchronization for Color LEDs with
Two Modes: Amplitude and Frequency
Programmable Frequency and Amplitude
Response with Tracking Speed Control
Automatic Gain Control or Selectable Gain for
Input Signal Optimization
RGB Pattern Generator Similar to
LP3933/LP3936
Magnetic DC-DC Boost Converter with
Programmable Boost Output Voltage
Selectable SPI or I2C Compatible Interface
The LP3950 has a high efficiency magnetic DC/DC
converter with programmable output voltage and
switching frequency. The converter has high output
current capability so it is also able to drive flash LEDs
in camera phone applications.
•
•
One Pin Default Enable for Non-Serial Interface
Users. One Pin Selector for Synchronization
Mode
The LP3950 is similar to LP3933 and LP3936 in that
the color LEDs (or RGB LEDs) can also be
•
Space Efficient 32-Pin TLGA Package
programmed
to
generate
light
patterns
(programmable color, intensity, on/off timing, slope
and blinking cycle).
APPLICATIONS
•
•
•
Cellular Phones
MP3/CD/Minidisc Players
Toys
All functions are software controllable through a SPI
or I2C compatible interface but the device also
supports one pin control for enabling predefined
(default) audio synchronization mode.
Typical Application
2.8V
V
IN
L
1
D
1
C
IN
10 mF
C
C
C
VDD1
100 nF
VDD2
100 nF
VDDA
100 nF
4.7 mH
V
DD1
V
DD2
V
DDA
C
1
ASE
SW
SINGLE-ENDED
10 nF
AUDIO SIGNAL
FB
R1
G1
B1
R2
G2
B2
RT
C
OUT
10 mF
R
R1
C
2
AD1
R
G1
10 nF
DIFFERENTIAL
AUDIO SIGNAL
C
3
R
B1
R2
G2
AD2
R
10 nF
LP3950
4
SERIAL
R
INTERFACE
R
B2
NRST
R
T
MICROCONTROLLER
PWM_LED
IF_SEL
82k
VREF
GNDs
V
C
DD_IO
VREF
100 nF
DME
AMODE
C
VDD_IO
100 nF
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2013, Texas Instruments Incorporated
LP3950
SNVS331C –NOVEMBER 2004–REVISED APRIL 2013
www.ti.com
Connection Diagrams
Top View
Bottom View
Figure 1. 32-Lead TLGA Package
4.5 x 5.5 x 0.8 mm, 0.5 mm Pitch, See Package Number NPC0032A
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SNVS331C –NOVEMBER 2004–REVISED APRIL 2013
PIN DESCRIPTIONS
Pin #
1
Name
FB
Type
Input
Description
Boost converter feedback.
Power switch ground.
2
GND_BOOST
SW
Ground
Output
3
Open drain, boost converter power switch.
Supply voltage for internal digital circuits.
Ground return for VDD2 (internal digital).
Default mode enable (internal pull down 1 MΩ).
Audio mode selection (internal pull down 1 MΩ).
Supply voltage for audio circuits.
Analog audio input, single-ended.
Analog audio input, differential.
Analog audio input, differential.
Ground for analog audio inputs.
Oscillator resistor.
4
VDD2
Power
5
GND2
DME
Ground
Logic Input
Logic Input
Power
6
7
AMODE
VDDA
8
9
ASE
Input
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
AD1
Input
AD2
Input
GNDA
RT
Ground
Input
VDD1
Power
Supply voltage for internal analog circuits.
Ground.
GND1
VREF
Ground
Output
Internal reference bypass capacitor.
Ground.
GND3
NRST
SS/SDA
SO
Ground
Logic Input
Logic I/O
Logic Output
Logic Input
Logic Input
Logic Input
Power
Low active reset input.
SPI slave select/ I2C data line.
SPI serial data output.
SI
SPI serial data input.
SPI/ I2C clock.
SCK/SCL
PWM_LED
VDDIO
IF_SEL
B2
Direct PWM control for LEDs.
Supply voltage for logic IO signals.
SPI/I2C select (IF_SEL = 1 in SPI mode).
Open drain output, blue LED2.
Open drain output, green LED2.
Open drain output, red LED2.
RGB driver ground.
Logic Input
Output
G2
Output
R2
Output
GND_RGB
R1
Ground
Output
Open drain output, red LED1.
Open drain output, green LED1.
Open drain output, blue LED1.
G1
Output
B1
Output
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)(2)(3)
(4) (5)
V (SW, FB, R1–2, G1–2, B1–2)
VDD1, VDD2, VDDIO, VDDA
Voltage on ASE, AD1, AD2
Voltage on Logic Pins
−0.3V to +7.2V
−0.3V to +6.0V
−0.3V to VDD1 +0.3V with 6.0V max
−0.3V to VDD_IO+0.3V with 6.0V max
(6)
I (R1, G1, B1, R2, G2, B2)
150 mA
10 µA
I (VREF
)
(7)
Continuous Power Dissipation
Internally Limited
125°C
Junction Temperature (TJ-MAX
Storage Temperature Range
Maximum Lead Temperature
)
−65°C to +150°C
260°C
(8)
(Reflow soldering, 3 times)
(9)
ESD Rating
Human Body Model:
Machine Model:
2 kV
200V
(1) All voltages are with respect to the potential at the GND pins (GND1–3, GND_BOOST, GND_RGB, GNDA).
(2) Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under
which operation of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed
performance limits and associated test conditions, see the Electrical Characteristics tables.
(3) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
(4) Battery/Charger voltage should be above 6.0V no more than 10% of the operational lifetime.
(5) Voltage tolerance of LP3950 above 6.0V relies on fact that VDD1, VDD2 and VDDA (2.8V) are available (ON) at all conditions. If VDD1
VDD2 and VDDA are not available (ON) at all conditions, Texas Instruments does not guarantee any parameters or reliability for this
device. Also, VDD1, VDD2 and VDDA must be at the same electric potential.
,
(6) The total load current of the boost converter should be limited to 300 mA.
(7) Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 160°C (typ.) and
disengages at TJ = 140°C (typ.).
(8) For detailed package and soldering specifications and information, please refer to Texas Instruments Application Note 1125 (SNAA002):
Laminate CSP/FBGA.
(9) The Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. The machine model is a 200 pF
capacitor discharged directly into each pin. MIL-STD-883 3015.7
Operating Ratings(1)(2)
V (SW, FB, R1–2, G1–2, B1–2)
0V to 6.0V
(3)
VDD1, VDD2, VDDA
2.7V to 2.9V
VDDIO
1.65V to VDD1,2 V
Voltage on ASE, AD1, AD2
Recommended Load Current
Junction Temperature (TJ) Range
Ambient Temperature (TA) Range
0.1V to VDD1 - 0.1V
0 mA to 300 mA
−40°C to +125°C
−40°C to +85°C
(4)
(1) Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under
which operation of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed
performance limits and associated test conditions, see the Electrical Characteristics tables.
(2) All voltages are with respect to the potential at the GND pins (GND1–3, GND_BOOST, GND_RGB, GNDA).
(3) Voltage tolerance of LP3950 above 6.0V relies on fact that VDD1, VDD2 and VDDA (2.8V) are available (ON) at all conditions. If VDD1
VDD2 and VDDA are not available (ON) at all conditions, Texas Instruments does not guarantee any parameters or reliability for this
device. Also, VDD1, VDD2 and VDDA must be at the same electric potential.
,
(4) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP
=
125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the
part/package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP − (θJA x PD-MAX).
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SNVS331C –NOVEMBER 2004–REVISED APRIL 2013
Thermal Properties
Junction-to-Ambient Thermal Resistance
72°C/W
(1)
(θJA), NPC0032A Package
(1) Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power
dissipation exists, special care must be paid to thermal dissipation issues in board design.
(1)(2)
Electrical Characteristics
Limits in standard typeface are for TJ = +25°C. Limits in boldface type apply over the operating ambient temperature range
(−40°C ≤ TA ≤ +85°C). Unless otherwise noted, specifications apply to Figure 2 with: VDD1 = VDD2 = VDDA = 2.8V, CVDD1
=
(3)
CVDD2 = CVDDA = CVDDIO = 100 nF, COUT = CIN = 10 µF, CVREF = 100 nF, L1 = 4.7 µH and fBOOST = 2.0 MHz
.
Symbol
IVDD
Parameter
Condition
Min
Typ
Max
5
Units
Standby Supply Current
NSTBY = L (register)
1
µA
(VDD1 + VDD2 + VDDA current)
SCK, SS, SI, NRST = H
No-Load Supply Current
(VDD1 + VDD2 + VDDA current, boost off)
NSTBY = H (reg.)
EN_BOOST = L (reg.)
SCK, SS, SI, NRST = H
300
850
400
µA
µA
Full Load Supply Current
NSTBY = H (reg.)
(VDD1 + VDD2 + VDDA current, boost on)(4) EN_BOOST = H (reg.)
SCK, SS, SI, NRST = H
All Outputs Active
IVDDIO
VDDIO Supply Current
1.0 MHz SCK Frequency
CL = 50 pF at SO Pin
20
µA
IVDDA
VREF
Audio Circuitry Supply Current(5)
Reference Voltage(6)
INPUT_SEL = [10] (register)
550
µA
V
IREF ≤ 1.0 nA Only for Test Purpose
1.230
(1) All voltages are with respect to the potential at the GND pins (GND1–3, GND_BOOST, GND_RGB, GNDA).
(2) Min and Max limits are guaranteed by design, test, or statistical analysis. Typical numbers are not guaranteed, but do represent the
most likely norm.
(3) Low-ESR Surface-Mount Ceramic Capacitors are used in setting electrical characteristics.
(4) Audio block inactive.
(5) In single-ended and in differential mode one audio buffer only is active and IVDDA will be reduced by 90 µA (typ).
(6) VREF pin (Bandgap reference output) is for internal use only. A capacitor should always be placed between VREF and GND1.
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Block Diagram
I
= 300 mA
MAX
BATTERY
LDO
2.8V
V
= 4.1V TO 5.3V
OUT
C
IN
10 mF
C
C
VDD2
VDDA
C
VDD1
L
1
100 nF
100 nF
100 nF
4.7 mH
V
DDA
V
V
DD2
DD1
D1
SW
FB
GND_BOOST
V
REF
C
C
OUT
10 mF
VREF
OSC
THSD
100 nF
RT
LP3950
EN
V
REF
BOOST
SINGLE ENDED
AUDIO SIGNAL
RT
82k
10 nF
ASE
R
R1
R1
FREQ
10 nF
10 nF
ADC
AGC
PWM
AD1
AD2
R
G1
G1
B1
AMPL
R
B1
GNDA
DIFFERENTIAL
AUDIO SIGNAL
R
R
R2
SPI
R2
G2
B2
RGB PATTERN
GENERATOR
CTRL
2
I C
G2
R
B2
LEVEL SHIFTER
GND_RGB
C
MICROCONTROLLER
VDDIO
100 nF
Figure 2. LP3950 Block Diagram
Modes of Operation
RESET: In the RESET mode all the internal registers are reset to the default values. RESET is entered always if
input NRST is LOW or internal Power On Reset is active.
STANDBY: The STANDBY mode is entered if the register bit NSTBY is LOW and RESET is not active. This is
the low power consumption mode, when all the circuit functions are disabled. Registers can be written in
this mode and the control bits are effective immediately after start up.
STARTUP: INTERNAL STARTUP SEQUENCE powers up all the needed internal blocks (VREF, oscillator, etc.).
To ensure the correct oscillator initialization, a 10 ms delay is generated by the internal state-machine.
Thermal shutdown (THSD) disables the chip operation and Startup mode is entered until no thermal
shutdown event is present.
BOOST STARTUP:Soft start for boost output is generated in the BOOST STARTUP mode. In this mode the
boost output is raised in PFM mode during the 10 ms delay generated by the state-machine. All RGB
outputs are off during the 10 ms delay to ensure smooth startup. The Boost startup is entered from
Internal Startup Sequence if EN_BOOST is HIGH or from Normal mode when EN_BOOST is written
HIGH.
NORMAL: During the NORMAL mode the user controls the chip using the control registers. Registers can be
written in any sequence and any number of bits can be altered in a register within one write cycle . If the
default mode is selected, default control register values are used.
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RESET
NRST=L
or
NSTBY= L and
DME = L and
NRST = H
POR = H
STANDBY
(NSTBY = H or DME = H)
NSTBY=L
and
DME=L
and
(NSTBY= H or DME = H)
and
and
NRST = H
NRST = H
NRST=H
INTERNAL
STARTUP
SEQUENCE
1
V
= 95% OK
THSD = H
REF
~10 ms DELAY
DME = H or
EN_BOOST = H
DME = L and
EN_BOOST = L
1
1
BOOST STARTUP
~10 ms DELAY
EN_BOOST
1
RISING EDGE
NORMAL MODE
1)
THSD = L
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Units
Logic Interface Characteristics(1)
Symbol
Parameter
Conditions
Min
Typ
Max
0.5
LOGIC INPUTS SS, SI, SCK/SCL, PWM_LED, IF_SEL
VIL
VIH
II
Input Low Level
Input High Level
Logic Input Current
Clock Frequency
V
V
VDDIO − 0.5
−1.0
1.0
400
8
µA
fSCL
I2C Mode
SPI Mode
kHz
MHz
LOGIC OUTPUT SO
VOL
Output Low Level
ISO = 3.0 mA
ISO = −3.0 mA
VSO = 2.8V
0.3
0.5
1.0
0.5
0.5
6.0
V
V
VOH
Output High Level
VDDIO − 0.5
VDDIO − 0.3
IL
Output Leakage Current
µA
LOGIC I/O SDA
VOL
Output Low Level
ISDA = 3.0 mA
0.3
V
LOGIC INPUTS DME, AMODE (Internal pull down 1 MΩ)
VIL
VIH
II
Input Low Level
Input High Level
Logic Input Current
V
V
VDDIO − 0.5
−1.0
µA
(1) (1.80V ≤ VDDIO ≤ VDD1,2V). Limits in standard typeface are for TJ = +25°C. Limits in boldface type apply over the operating ambient
temperature range (−40°C ≤ TA ≤ +85°C).
Logic Interface Characteristics, Low I/O Voltage(1)
Symbol
Parameter
Conditions
Min
Typ
Max
0.35
Units
LOGIC INPUTS SCL, PWM_LED, IF_SEL
VIL
Input Low Level
Input High Level
Logic Input Current
Clock Frequency
V
V
VIH
VDDIO − 0.35
−1.0
II
1.0
µA
kHz
fSCL
I2C Mode
200
LOGIC I/O SDA
VOL
Output Low Level
ISDA = 3.0 mA
0.3
0.5
0.35
6.0
V
LOGIC INPUTS DME, AMODE (Internal pull down 1 MΩ)
VIL
VIH
II
Input Low Level
Input High Level
Logic Input Current
V
V
VDDIO − 0.35
−1.0
µA
(1) (1.65V ≤ VDDIO < 1.80V) . I2C compatible interface only.
Logic Input NRST Characteristics(1)
Symbol
Parameter
Conditions
Min
Typ
Max
0.5
Units
V
VIL
Input Low Level
VIH
II
Input High Level
1.3
V
Logic Input Current
Reset Pulse Width
−1.0
1.0
µA
tNRST
Note: Guaranteed by
design
10
µs
(1) (1.65V ≤ VDDIO ≤ VDD1,2V).
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Control Interface
The LP3950 supports three different interface modes:
1. SPI interface (4 wire, serial)
2. I2C compatible interface (2 wire, serial)
3. Direct enable (2 wire, enable lines)
User can define the serial interface by the IF_SEL pin. The following table shows the pin configuration for both
interface modes. Note that the pin configurations will be based on the status of the IF_SEL pin.
IF_SEL
Interface
Pin Configuration
Comment
HIGH
SPI
SCK
SI
(clock)
(data in)
SO
SS
(data out)
(chip select)
LOW
I2C Compatible
SCL
SDA
SI
(clock)
Use pull up resistor for SCL.
Use pull up resistor for SDA.
SI HIGH → address is 51'h;
SI LOW → address is 50'h;
(data in/out)
(I2 address)
(NC)
SO
Unused pin SO can be left unconnected.
SPI Interface
The transmission consists of 16-bit write and read cycles. One cycle consists of seven address bits, one
read/write (R/W) bit and eight data bits. R/W bit high state defines a write cycle and low defines a read cycle. SO
output is normally in high-impedance state and it is active only during when data is sent out during a read cycle.
A pull-up or pull-down resistor may be needed for SO line if a floating logic signal can cause unintended current
consumption in the circuitry.
The address and data are transmitted Most Significant Byte (MSB) first. The Slave Select signal (SS) must be
low during the cycle transmission. SS resets the interface when high and it has to be taken high between
successive cycles. Data is clocked in on the rising edge of the SCK clock signal, while data is clocked out on the
falling edge of SCK.
SS
SCK
1
R/W
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
SI
SO
Figure 3. SPI Write Cycle
SS
SCK
SI
R/W
0
A6
A5
A4
A3
A2
A1
A0
Don't Care
D4 D3
SO
D7
D6
D5
D2
D1
D0
Figure 4. SPI Read Cycle
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SS
5
3
12
2
1
4
SCK
SI
7
6
MSB IN BIT 14
BIT 9
BIT 8
R/W
BIT 7
BIT 1
LSB IN
11
8
9
10
MSBOUT
BIT 1
LSB OUT
SO
Address
Data
Figure 5. SPI Timing Diagram
Table 1. SPI Timing Parameters(1)
Limit
Symbol
Parameter
Units
Min
80
40
40
40
40
0
Max
1
2
Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Enable Lead Time
Enable Lag Time
Clock Low Time
3
4
5
Clock High Time
Data Setup Time
Data Hold Time
6
7
20
8
Data Access Time
Output Disable Time
Output Data Valid
Output Data Hold Time
SS Inactive Time
27
27
37
9
10
11
12
0
15
(1) Data guaranteed by design.
I2C Compatible Interface
I2C SIGNALS
In I2C compatible mode, the LP3950 pin SCL is used for the I2C clock and the SDA pin is used for the I2C data.
Both these signals need a pull-up resistor according to I2C specification. The values of the pull-up resistors are
determined by the capacitance of the bus (typ. 1.8k). Signal timing specifications are shown in Table 2. Unused
pin SO can be left unconnected and pin SI must be connected to VDDIO or GND (address selector). Maximum bit
rate is 400 kbit/s (VDDIO 1.80V to VDD1,2V). I2C compatible interface can be used down to 1.65 VDDIO with
maximum bit rate of 200 kbit/s.
I2C DATA VALIDITY
The data on the SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state
of the data line can only be changed when CLK is LOW.
SCL
SDA
data
change
allowed
data
change
allowed
data
valid
data
change
allowed
data
valid
Figure 6. I2C Signals: Data Validity
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I2C START AND STOP CONDITIONS
START and STOP bits classify the beginning and the end of the I2C session. START condition is defined as SDA
signal transition from HIGH to LOW while SCL line is HIGH. STOP condition is defined as the SDA transition
from LOW to HIGH while SCL is HIGH. The I2C master always generates START and STOP bits. The I2C bus is
considered to be busy after START condition and free after STOP condition. During data transmission, the I2C
master can generate repeated START conditions. First START and repeated START conditions are equivalent,
function-wise.
SDA
SCL
S
P
START condition
STOP condition
Figure 7. Start and Stop Conditions
TRANSFERRING DATA
Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first.
Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated
by the master. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver
must pull down the SDA line during the 9th clock pulse, signifying an acknowledge. A receiver which has been
addressed must generate an acknowledge after each byte has been received.
After the START condition, the I2C master sends a chip address. This address is seven bits long followed by an
eighth bit which is a data direction bit (R/W). The LP3950 address is 50'h or 51'h. The selection of the address is
done by connecting SI pin to VDDIO (51 hex) or GND (50 hex). For the eighth bit, a “0” indicates a WRITE and a
“1” indicates a READ. The second byte selects the register to which the data will be written. The third byte
contains data to write to the selected register.
MSB
LSB
ADR5
bit6
ADR6
bit7
ADR4
bit5
ADR3
bit4
ADR2
bit3
ADR1
bit2
ADR0
bit1
R/W
bit0
0
1
1
0
1
1
0
2
I C SLAVE address (chip address)
Figure 8. I2C Chip Address
ack from slave
ack from slave
ack from slave
ack stop
start
msb Chip Address lsb
w
ack
msb Register Add lsb
ack
msb DATA lsb
SCL
SDA
start
Id = 36h
w
ack
addr = 02h
ack
address h‘02 data
ack stop
w = write (SDA = “0”)
r = read (SDA = “1”)
ack = acknowledge (SDA pulled down by either master or slave)
rs = repeated start
id = chip address, 50'h or 51'h for LP3950.
Figure 9. I2C Write Cycle
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When a READ function is to be accomplished, a WRITE function must precede the READ function, as shown in
Figure 10 .
ack from slave
ack from slave repeated start
ack from slave data from slave ack from master
start msb Chip Address lsb
w
msb Register Add lsb
rs
msb Chip Address lsb
r
msb DATA lsb
stop
SCL
SDA
start
Id = 36h
w
ack
addr = h‘00
ack rs
Id = 36h
r
ack
Address h‘00 data
ack stop
Figure 10. I2C Read Cycle
SDA
10
7
8
7
6
1
8
2
SCL
5
1
4
9
3
Figure 11. I2C Timing Diagram
Table 2. I2C Timing Parameters(1)
Symbol
Parameter
Limit
Units
Min
0.6
3.2
1.3
Max
1
2
Hold Time (repeated) START Condition
Clock Low Time (1.65V ≤ VDDIO < 1.80V)
Clock Low Time (1.80V ≤ VDDIO ≤ VDD1,2V)
Clock High Time (1.65V ≤ VDDIO < 1.80V)
Clock High Time (1.80V ≤ VDDIO ≤ VDD1,2V)
Setup Time for a Repeated START Condition
Data Hold Time (data output, delay generated by LP3950)
Data Hold Time (data input)
µs
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
2
3
1200
600
3
4
600
5
300
900
900
5
0
6
Data Setup Time
100
7
Rise Time of SDA and SCL
20+0.1Cb
15+0.1Cb
600
300
300
8
Fall Time of SDA and SCL
9
Set-up Time for STOP condition
10
Cb
Bus Free Time between a STOP and a START Condition
1.3
Capacitive Load Parameter for Each Bus Line.
10
200
Load of One Picofarad Corresponds to One Nanosecond.
(1) Data guaranteed by design
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Magnetic Boost DC/DC Converter
The boost DC/DC converter generates a 4.1V–5.3V output voltage to drive LEDs from a single Li-Ion battery
(3.0V to 4.5V). The output voltage is controlled with an eight-bit register in nine steps. The converter is a
magnetic switching PWM mode DC/DC converter with a current limit. The converter has three options for
switching frequency, 1.0 MHz, 1.67 MHz and 2.0 MHz (default), when the timing resistor RT is 82 kΩ.
The LP3950 boost converter uses an unique pulse-skipping elimination method to stabilize the noise spectrum.
Even with light load or no load a minimum length current pulse is fed to the inductor. An internal active load is
used to remove the excess charge from the output capacitor when needed (see NOTE below). The boost
converter should be disabled when there is no load to avoid idle current consumption.
The topology of the magnetic boost converter is called CPM control, current programmed mode, where the
inductor current is measured and controlled with the feedback. The output voltage control changes the resistor
divider in the feedback loop.
Figure 12 shows the boost topology with the protection circuitry. Four different protection schemes are
implemented:
1. Over voltage protection, limits the maximum output voltage
–
–
Keeps the output below breakdown voltage
Prevents boost operation if the battery voltage is much higher than desired output
2. Over current protection, limits the maximum inductor current
Voltage over switching NMOS is monitored; too high voltages turn the switch off
–
3. Feedback (FB) protection for no connection
4. Duty cycle limit function, done with digital control
NOTE
When the battery voltage is close to the output voltage, the output voltage may rise slightly
over programmed value if the load on output is small and pulse-skipping elimination is
active.
V
V
OUT
2 MHz clock
Duty control
IN
SW
FBNCCOMP
FB
+
-
R
S
R
R
OVPCOMP
SWITCH
+
-
RESETCOMP
+
-
-
+
R
ERRORAMP
ACTIVE
LOAD
+
-
R
+
-
LOOPC
SLOPER
OLPCOMP
Figure 12. Boost Converter Functional Block Diagram
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Magnetic Boost DC/DC Converter Electrical Characteristics(1)(2)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
ILOAD
Load Current
3.0V ≤ VIN ≤ 4.5V
VOUT = 5.0V
0
300
mA
VOUT
Output Voltage Accuracy
(FB Pin)
1.0 mA ≤ ILOAD ≤ 300 mA
3.0V ≤ VIN ≤ 4.5V
−5
+5
%
V
VOUT = 5.0V (target value), autoload OFF
Output Voltage
(FB Pin)
1.0 mA ≤ ILOAD ≤ 300 mA
3.0V < VIN < 5.0V + V(SCHOTTKY),
autoload OFF
5.0
1.0 mA ≤ ILOAD ≤ 300 mA
VIN > 5V + V(SCHOTTKY)
VIN–V(SCHOTTKY)
V
Ω
RDSON
fPWF
Switch ON Resistance
VDD1,2 = 2.8V, ISW = 0.5A
0.4
2.0
±3
0.7
PWM Mode Switching
Frequency
RT = 82 kΩ
freq_sel[2:0] = 1XX
MHz
Frequency Accuracy
2.7 ≤ VDD1,2 ≤ 2.9
RT = 82 kΩ
−6
−9
+6
%
+9
tPULSE
Switch Pulse Minimum
Width
No Load
25
ns
tSTARTUP Startup Time
ICL_OUT SW Pin Current Limit
15
ms
700
800
900
mA
500
1000
(1) Limits in standard typeface are for TJ = +25°C. Limits in boldface type apply over the operating ambient temperature range (−40°C ≤ TA
≤ +85°C). Unless otherwise noted, specifications apply to Figure 2 with: VDD1 = VDD2 = VDDA = 2.8V, CVDD1 = CVDD2 = CVDDA = CVDDIO
100 nF, COUT = CIN = 10 µF, CVREF = 100 nF, L1 = 4.7 µH and fBOOST = 2.0 MHz.
=
(2) Low-ESR Surface-Mount Ceramic Capacitors are used in setting electrical characteristics.
Boost Standby Mode
User can set the boost converter to STANDBY mode by writing the register bit EN_BOOST low when there is no
load to avoid idle current consumption. When EN_BOOST is written high, the converter starts in PFM (Pulse
Frequency Modulation) mode for 10 ms and then goes to PWM (Pulse Width Modulation ) mode. All RGB
outputs are off during the 10 ms delay.
Boost Output Voltage Control
User can control the boost output voltage by eight-bit boost output voltage register according to the following
table.
BOOST[7:0]
Register 0D'h
BOOST Output Voltage
(typical)
Binary
Hex
00
01
03
07
0F
1F
3F
7F
FF
0000 0000
0000 0001
0000 0011
0000 0111
0000 1111
0001 1111
0011 1111
0111 1111
1111 1111
4.10
4.25
4.40
4.55
4.70
4.85
5.00 Default
5.15
5.30
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Boost Frequency Control
The register ‘boost frequency’ has address 0C’h. The default value after reset is 07’h. ‘x’ means don’t care.
FREQ_SEL[2:0]
Frequency
2.00 MHz
1.67 MHz
1.00 MHz
1xx
01x
001
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Boost Converter Typical Performance Characteristics
VIN = 3.6V, VOUT = 5.0V if not otherwise stated.
Boost Frequency
vs
Boost Converter Efficiency
RT Resistor
Figure 13.
Figure 14.
Battery Current
vs
Battery Current
vs
Voltage
Voltage
Figure 15.
Figure 16.
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Boost Converter Typical Performance Characteristics (continued)
VIN = 3.6V, VOUT = 5.0V if not otherwise stated.
Boost Typical Waveforms at 100 mA Load
Boost Startup with No Load
TIME (200 ns/DIV)
Figure 17.
Figure 18.
Boost Line Regulation
Boost Load Transient Response, 50 mA to 100 mA
Figure 19.
Figure 20.
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RGB LED Pattern Generator
The LP3950 RGB outputs can be controlled either with audio synchronization or with RGB pattern generator.
The pattern generator of LP3950 drives three independently controlled LED outputs (for example, R1, G1 and
B1). The functionality is similar compared to RGB functionality of LP3936 and LP3933.
The output of RGB pattern generator can be selected to drive RGB1 (R1-G1-B1), RGB2 (R2-G2-B2) or RGB1
and RGB2 (R1&R2 – G1&G2 – B1&B2) outputs.
Programmable Pattern Mode
User has control over the following parameters separately for each LED:
ON and OFF(start and stop time in blinking cycle)
DUTY (PWM brightness control)
SLOPE (dimming slope)
ENABLE (output enable control)
The main blinking cycle is controlled with three-bit CYCLE control (0.25 / 0.5 / 1.0 / 2.0 / 4.0s).
ON[3:0]
LED
brightness
OFF[3:0]
DUTY[3:0] SLOPE[3:0]
Duty increases Duty constant Duty decreases
SLOPE[3:0]
PWM
current
pulses
Blinking period
Figure 21. RGB PWM Operating Principle
RGB_START is the master control for the whole RGB function. The internal PWM and blinking control can be
disabled by setting the RGB_PWM control LOW. In this case the individual enable controls can be used to switch
outputs on and off. PWM_EN input can be used for external hardware PWM control.
In the normal PWM mode the R, G and B switches are controlled in 3 phases (one phase per driver). During
each phase the peak current set by an external ballast resistor is driven through the LED for the time defined by
DUTY setting (0 µs to 50 µs). As a time averaged current this means 0% to 33% of the peak current. The PWM
period is 150 µs and the pulse frequency is 6.67 kHz in normal mode.
R1
1111
G1
0110
B1
1100
3
1
2
3
1
2
150 ms/6.7 kHz
Combined PWM cycle
Figure 22. Normal Mode PWM Waveforms at Different Duty Settings
In the FLASH mode all the outputs are controlled in one phase and the PWM period is 50 µs. The time averaged
FLASH mode current is three times the normal mode current at the same DUTY value.
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ON <OFF
ON OFF
R1
G1
ON
OFF
OFF<ON
OFF
ON
OFF
ON
B1
ON = OFF = 0
First cycle
Next cycles
Figure 23. Example Blinking Waveforms
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RGB Driver Characteristics
(R1, G1, B1, R2, G2, B2 outputs). Limits in standard typeface are for TJ = +25°C. Limits in boldface type apply over the
operating ambient temperature range (−40°C ≤ TA ≤ +85°C).
Symbol
RDS-ON
ILEAKAGE
tSMAX
Parameter
ON Resistance
Conditions
Min
Typ
3.5
Max
6.0
Units
Ω
Off State Leakage Current
Maximum Slope Period
Minimum Slope Period
Slope Resolution
VFB = 5.0V, LED driver off
At Maximum Duty Setting
At Maximum Duty Setting
At Maximum Duty Setting
Cycle 1.0s
0.03
0.93
31
1.0
µA
s
tSMIN
ms
ms
s
tSRES
62
tSTART/STOP
Duty
Start/Stop Resolution
Duty Step Size
1/16
1/16
±3
tBLINK
DCYCF
DCYC
Blinking Cycle Accuracy
Duty Cycle Range
Duty Cycle Range
Duty Resolution
−6
0
+6
%
%
EN_FLASH = 1
99.6
33.2
EN_FLASH = 0
0
%
DRESF
DRES
EN_FLASH = 1 (4-bit)
EN_FLASH = 0 (4-bit)
EN_FLASH = 1
6.64
2.21
20
%
Duty Resolution
%
fPWMF
fPWM
PWM Frequency
kHz
kHz
PWM Frequency
EN_FLASH = 0
6.67
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(1)
Table 3. RGB LED PWM Control
RDUTY[3:0]
GDUTY[3:0]
BDUTY[3:0]
DUTY sets the brightness of the LED by adjusting the duty cycle of the PWM driver. The minimum DUTY cycle is 0%
[0000] and the maximum in the flash mode is 100% [1111]. The peak pulse current is determined by the external
resistor, LED forward voltage drop and the boost voltage. In the normal mode the maximum duty cycle is 33%.
RSLOPE[3:0]
GSLOPE[3:0]
BSLOPE[3:0]
SLOPE sets the turn-on and turn-off slopes. Fastest slope is set by [0000] and slowest by [1111]. SLOPE changes the
duty cycle at constant, programmable rate. For each slope setting the maximum slope time appears at maximum
DUTY setting. When DUTY is reduced, the slope time decreases proportionally. For example, in case of maximum
DUTY, the sloping time can be adjusted from 31 ms [0000] to 930 ms [1111]. For DUTY [0111] the sloping time is 14
ms [0000] to 434 ms [1111]. The blinking cycle has no effect on SLOPE.
RON[3:0]
GON[3:0]
BON[3:0]
ON sets the beginning time of the turn-on slope. The on-time is relative to the selected blinking cycle length. On-
setting N (N = 0–15) sets the on-time to N/16 * cycle length.
ROFF[3:0]
GOFF[3:0]
BOFF[3:0]
ROFF[3:0]
GOFF[3:0]
BOFF[3:0]
OFF sets the beginning time of the turn-off slope. Off-time is relative to blinking cycle length in the same way as on-
time.
If ON = 0, OFF = 0 and RGB_PWM = 1, then RGB outputs are continuously on (no blinking), the DUTY setting
controls the brightness and the SLOPE control is ignored.
If ON and OFF are the same, but not 0, RGB outputs are turned off.
CYCLE[2:0]
CYCLE sets the blinking cycle: [000] for 0.25s, [001] for 0.5s, [010] for 1.0s, [011] for 2.0s. and [1XX] for 4.0s CYCLE
effects to all RGB LEDs.
RSW1
GSW1
BSW1
RSW2
GSW2
BSW2
Enable for R1 switch
Enable for G1 switch
Enable for B1 switch
Enable for R2 switch
Enable for G2 switch
Enable for B2 switch
RGB_START
Master Switch for both RGB drivers:
RGB_START = 0 → RGB OFF
RGB_START = 1 → RGB ON, starts the new cycle from t = 0
RGB_PWM
EN_FLASH
RGB_PWM = 0 → RSW, GWS and BSW control directly the RGB outputs (on/off control only)
RGB_PWM = 1 → Normal PWM RGB functionality (duty, slope, on/off times, cycle)
Flash mode enable control for RGB1 and RGB2. In the flash mode (EN_FLASH = 1) RGB outputs are PWM controlled
simultaneously, not in 3-phase system as in the normal mode.
R1_PWM
G1_PWM
B1_PWM
R2_PWM
G2_PWM
B2_PWM
xx_PWM = 0 → External PWM control from PWM_LED pin is disabled
xx_PWM = 1 → External PWM control from PWM_LED pin is enabled
Internal PWM control (DUTY) can be used independently of external PWM control. External PWM has the same effect
on all enabled outputs.
(1) The LP3933 shares the same pattern generator. Application Note AN-1291 (SNVA069), “Driving RGB LEDs Using LP3933 Lighting
Management System” contains a thorough description of the RGB driver functionality including programming examples.
PWM_LED input can be used as a direct on/off or PWM brightness control for selected RGB outputs. For
example it can trigger the flash using a flash signal from the camera. If PWM_LED input is not used, it must be
tied to VDDIO
.
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AUDIO SYNCHRONIZATION
The LEDs connected to the RGB outputs can be synchronized to incoming audio signal with Audio
Synchronization feature. Audio Synchronization has two modes. Amplitude mode synchronizes LEDs based on
the peak amplitude of the input signal. In the amplitude mode the user can select one of three amplitude
mapping options. The frequency mode synchronizes the LEDs based on bass, middle and treble amplitudes (=
low pass, band pass and high pass filters). The user can select between two different responses of frequency for
best audio-visual user experience. Both of the modes provide a control for speed of the mapping with four
different speed configurations. Programmable gain and AGC (Automatic Gain Control) function are also available
for adjustment of the optimum audio signal mapping. The Audio Synchronization functionality is described more
closely below.
INPUT SIGNAL TYPE
The LP3950 support four types of analog audio input signals for audio synchronization
1. Single ended audio
2. Differential audio
3. Stereo
4. Single ended and differential audio.
Figure 24 shows how to wire the LP3950 audio inputs case by case (NC = Not Connected).
USING A DIGITAL PWM AUDIO SIGNAL AS AN AUDIO SYNCHRONIZATION SOURCE
If the input signal is a PWM signal, use a first or second order low pass filter to convert the digital PWM audio
signal into an analog waveform. There are two parameters that need to be known to get the filter to work
successfully: frequency of the PWM signal and the voltage level of the PWM signal. Suggested cut-off frequency
(-3dB) should be around 2 kHz to 4 kHz and the stop-band attenuation at sampling frequency should be around -
48dB or better. Use a resistor divider to reduce the digital signal amplitude to meet the specification of the analog
audio input. Because a low-order low-pass filter attenuates the high-frequency components from audio signal,
MODE_CONTROL=[01] selection is recommended when frequency synchronization mode is enabled. Figure 33
shows an example of a second order RC-filter for 29 kHz PWM signal with 3.3V amplitude. Active filters, such as
a Sallen-Key filter, may also be applied. An active filter gives better stop-band attenuation and cut-off frequency
can be higher than for a RC-filter.
To make sure that the filter rolls off sufficiently quickly, connect your filter circuit to the audio input(s), turn on the
audio synchronization feature, set manual gain to maximum, apply the PWM signal to the filter input and keep an
eye on LEDs. If they are blinking without an audio signal (modulation), a sharper roll-off after the cut-off
frequency, more stop-band attenuation, or smaller amplitude of the PWM signal is required.
BUFFERS
BUFFERS
SEL
SEL
10 nF
10 nF
10 nF
ASE
AD1
AD2
ASE
AD1
AD2
MIX/
MUX
MIX/
MUX
NC
NC
10 nF
SINGLE-ENDED
STEREO
BUFFERS
BUFFERS
SEL
SEL
10 nF
ASE
NC
ASE
AD1
AD2
10 nF
AD1
10 nF
MIX/
MUX
MIX/
MUX
AD2
10 nF
10 nF
SINGLE ENDED AND DIFFERENTIAL
DIFFERENTIAL
Figure 24. Wiring Diagram for LP3950 Audio Inputs
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INPUT BUFFERING
Figure 25 describes the LP3950 audio input buffering structure in high level. The electric parameters of the
buffers are described in Table 4. Operational amplifiers for both buffers are rail-to-rail input opamps. The single
ended buffer is simply a voltage follower. DC level of the input signal is generated by a resistor divider. The
differential amplifier is a basic differential-to-single-ended converter.
V
DDA
1.0 MW
10 nF
-
+
ASE
1.0 MW
500 kW
500 kW
10 nF
10 nF
AD1
AD2
-
+
V
DDA
500 kW
1.0 MW
1.0 MW
Figure 25. Audio Input Buffer Structure
AUDIO SYNCHRONIZATION SIGNAL PATH
LP3950 audio synchronization is mainly done digitally and it consists of the following signal path blocks (see
Figure 26):
•
•
•
•
•
•
•
•
•
•
•
Input buffers
Multiplexer
AD converter
DC remover
Automatic gain control (AGC) / programmable gain
3 band digital filter
Peak detector
Look-up tables (LUT)
Mode selector
Integrators
PWM generator
Functional Block Diagram
FILTER CONTROL
FILTERS
MODE
BUFFERS
GAIN
EN
SEL
ASE
LUT
LUT
R
G
AD1
MIX/
SYNC
MODE
SEL
DC
REMOVER
GAIN
CONTROL
PWM
ADC
INT
FETS
MUX
B
AD2
PEAK
DETECTOR
Figure 26. Signal Path Block Diagram
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The digitized input signal has a DC component that is removed by the digital DC REMOVER (-3 dB @ 400 Hz).
The automatic GAIN CONTROL adjusts the input signal to suitable range automatically. User can disable AGC
and the gain can be set manually with PROGRAMMABLE GAIN. The LP3950 has two audio synchronization
modes: amplitude and frequency. For amplitude based synchronization the PEAK DETECTION method is used.
For frequency based synchronization the three-way crossover FILTER separates high pass, low pass and band
pass signals. For both modes, a predefined lookup table (LUT) is used to match the audio visual effect. The
MODE SELECTOR selects the synchronization mode. Reaction speed can be selected using INTEGRATOR
speed variables. Finally PWM GENERATOR sets the driver FETs duty cycles.
Table 4. Audio Synchronization Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Zin
Input Impedance of AD1, AD2, ASE pins
200
500
kΩ
AIN_SINGLE
AIN_DIFF
f3 dB
Audio Input Level Range (peak-to-peak),
Single Ended Audio
0.1
0.1
V
DDA −0.1
DDA −0.1
V
V
Audio Input Level Range (peak-to-peak),
Differential Audio
V
Crossover Frequencies (−3 dB)
Narrow Frequency Response
Low Pass
Band Pass
High Pass
0.5
1.0 and 1.5
2.0
kHz
Wide Frequency Response
Low Pass
Band Pass
High Pass
1.0
2.0 and 3.0
4.0
CONTROL OF AUDIO SYNCHRONIZATION
The following table describes the controls required for audio synchronization. Note that these controls are
functional when using serial interface (I2C or SPI) for device control. Also LP3950 audio synchronization
functionality is illustrated in Figure 27.
Table 5. Audio Synchronization Control
EN_SYNC
Audio synchronization enabled. Set EN_SYNC = 1 to enable audio synchronization or 0 to disable.
SYNC_MODE
Synchronization mode selector. Set SYNC_MODE = 0 for amplitude synchronization. Set SYNC_MODE
= 1 for frequency synchronization.
MODE_CTRL[1:0]
EN_AGC
See below: Mode control
Automatic gain control. Set EN_AGC = 1 to enable automatic control or 0 to disable. When EN_AGC is
disabled, the audio input signal gain value is defined by GAIN_SEL.
GAIN_SEL[2:0]
Input signal gain control. Gain has a range from 0 dB to 21 dB with 3 dB steps:
[000] ... 0 dB
[001] ... 3 dB
[010] ... 6 dB
[011] ... 9 dB
[100] ... 12 dB
[101] ... 15 dB
[110] ... 18 dB
[111] ... 21 dB
INPUT_SEL[1:0]
[00] ... Single ended input signal, ASE.
[01] ... Differential input signal, AD1 and AD2.
[10] ... Stereo input or single ended and differential input signal.
Note: Sum of input signals divided by 2.
[11] ... No input
Please see Figure 24 for wiring.
SPEED_CTRL[1:0]
Control for speed of the mapping. Sets the reaction speed (or "sampling rate") for the audio input signal:
[00] ... FASTEST
[11] ... SLOW
[01] ... FAST
[10] ... MEDIUM
In the amplitude mode fMAX = 3.8 Hz, in the frequency mode fMAX = 7.6 Hz.
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LP3950 AUDIO SYNCHRONIZATION
SYNC_MODE = 0
SYNC_MODE = 1
AMPLITUDE
SYNC.
FREQUENCY
SYNC.
MODE0
MODE0
MODE1
MODE2
MODE1
FASTEST
FAST
FASTEST
FAST
FASTEST
FAST
FASTEST
FAST
FASTEST
FAST
MEDIUM
SLOW
MEDIUM
SLOW
MEDIUM
SLOW
MEDIUM
SLOW
MEDIUM
SLOW
Figure 27. LP3950 Audio Synchronization Functionality
MODE CONTROL IN THE FREQUENCY MODE
During the frequency mode (SYNC_MODE = 1) the user can select between two filter options by
MODE_CTRL[1:0] as shown below (Figure 29). User can select the filters based on the music type and light
effect requirements. Filter options: Left figure, wide frequency response; MODE_CTRL[1:0] is set to [00], [10] or
[11]. Right figure, narrow frequency response: MODE_CTRL[1:0] set to [01]. Signal passed through the lowpass
filter is used to control the duty cycle of red LEDs (R1 and/or R2 PWM outputs), the signal passed through the
bandpass filter is used to control green LEDs (G1 and/or G2 PWM outputs) and high pass signal controls blue
LEDs (B1 and/or B2 PWM outputs). Finally, the user can select the desired mapping speed by
SPEED_CTRL[1:0]. Of course, the user can connect any color LED to any output in his/her own application (i.e.
the red output does not need to drive a red LED). Maximum duty cycle is 100% as in the Flash mode (not 33%
as in the normal mode of the pattern generator, which is described in Table 3).
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
BANDPASS
LOWPASS
HIPASS
BANDPASS
LOWPASS
HIPASS
1.0 2.0 3.0 4.0 5.0 6.0 7.0
kHz
0.5 1.0 1.5 2.0 2.5 3.0 3.5
kHz
0
8.0
0
4.0
Figure 28. Cross-over Frequency
Left: Wide Frequency Response
Figure 29. Cross-over Frequency
Right: Narrow Frequency Response
MODE CONTROL IN THE AMPLITUDE MODE
During the amplitude synchronization mode (SYNC_MODE = 0) the user can select between three different
amplitude mappings by using MODE_CTRL[1:0] select. These three mapping options give different light
responses as shown in Figure 30. Again, the user can select the desired mapping speed by SPEED_CTRL[1:0].
Maximum duty cycle is 100%. If MODE_CTRL[1:0] = 11 and SYNC_MODE = 0, audio synchronization is
inactive.
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MODE_CTRL[1:0] = [00] = MODE0
MODE_CTRL[1:0] = [01] = MODE1
MODE_CTRL[1:0] = [10] = MODE2
This figure is for illustrating purpose only and does not necessarily represent the accurate function of the circuit.
Figure 30. Amplitude Synchronization Mapping Options
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MODE CONTROL IN THE DEFAULT MODE
One of the main benefits of LP3950 is the default mode, which enables user to build applications without I2C or
SPI control. The LP3950 is set to the default mode when DME pin is high. DME pin high –state forces registers
NSTBY and EN_SYNC to the high [1] state so that the start-up sequence get started (see start-up sequence on
Modes of Operation). Function of LP3950 in the default mode of operation is controlled by AMODE pin. If
AMODE is pulled low the LP3950 is in the amplitude synchronization mode. If the AMODE pin is pulled high the
LP3950 is in the frequency synchronization mode. In the default mode default control register values are used,
see Table 8. Please refer to Figure 32 in Typical Applications for wiring.
RGB OUTPUT SELECTOR
The usage of RGB outputs (RGB1 and RGB2) can be selected with RGB_SEL[1:0] control bits. Audio
synchronization and RGB pattern generator output can be connected to RGB ports as shown in the following
table.
Table 6. RGB Output Control
RGB_SEL[0]
RGB_SEL[1]
RGB1 Output Control
Pattern Generator
Audio Sync
RGB2 Output Control
Pattern Generator
Pattern Generator
Audio Sync
0
1
0
1
0
0
1
1
Pattern Generator
Audio Sync
Audio Sync
Recommended External Components
OUTPUT CAPACITOR, COUT
The output capacitor COUT directly affects the magnitude of the output ripple voltage. In general, the higher the
value of COUT, the lower the output ripple magnitude. Multilayer ceramic capacitors with low ESR (Equivalent
Series Resistance) are the best choice. At the lighter loads, the low ESR ceramics offer a much lower VOUT ripple
than the higher ESR tantalums of the same value. At the higher loads, the ceramics offer a slightly lower VOUT
ripple magnitude than the tantalums of the same value. However, the dv/dt of the VOUT ripple with the ceramics is
much lower that the tantalums under all load conditions. Capacitor voltage rating must be sufficient, 10V is
recommended.
Some ceramic capacitors, especially those in small packages, exhibit a strong capacitance reduction
with the increased applied voltage. The capacitance value can fall to below half of the nominal
capacitance. Too low output capacitance can make the boost converter unstable.
INPUT CAPACITOR, CIN
The input capacitor CIN directly affects the magnitude of the input ripple voltage and to a lesser degree the VOUT
ripple. A higher value CIN will give a lower VIN ripple. Capacitor voltage rating must be sufficient, 10V is
recommended.
OUTPUT DIODE, D1
A Schottky diode should be used for the output diode. To maintain high efficiency the average current rating of
the schottky diode should be larger than the peak inductor current (1.0A). Schottky diodes with a low forward
drop and fast switching speeds are ideal for increasing efficiency in portable applications. Choose a reverse
breakdown of the schottky diode larger than the output voltage. Do not use ordinary rectifier diodes, since slow
switching speeds and long recovery times cause the efficiency and the load regulation to suffer.
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INDUCTOR, L1
LP3950's high switching frequency enables the use of a small surface mount inductor. A 4.7 µH shielded inductor
is suggested for 2.0 MHz switching frequency. Values below 2.2 µH should not be used at 2.0 MHz. At lower
switching frequencies 4.7 µH inductors should always be used. The inductor should have a saturation current
rating higher than the peak current it will experience during circuit operation (1.0A). Less than 300 mΩ ESR is
suggested for high efficiency. Open core inductors cause flux linkage with circuit components and, thus, may
interfere with the normal operation of the circuit. This should be avoided. For high efficiency, choose an inductor
with a high frequency core material such as ferrite to reduce the core losses. To minimize radiated noise, use a
toroid, pot core or shielded core inductor. The inductor should be connected to the SW pin as close to the IC as
possible. Examples of suitable inductors are TDK type VLF4012AT- 4R7M1R1 and Coilcraft type MSS4020-
472MLD.
Table 7. List of Recommended External Components
Symbol
CVDD1
CVDD2
COUT
CIN
Symbol Explanation
VDD1 Bypass Capacitor
Value
100
Unit
nF
nF
µF
µF
nF
nF
nF
kΩ
kΩ
nF
Type
Ceramic, X5R
VDD2 Bypass Capacitor
100
Ceramic, X5R
Ceramic, X5R
Ceramic, X5R
Ceramic, X5R
Ceramic, X5R
Ceramic, X5R
Output Capacitor from FB to GND
Input Capacitor from Battery Voltage to GND
VDD_IO Bypass Capacitor
10 ± 10%
10 ± 10%
100
CVDDIO
CVDDA
C1,2,3
RT
VDDA Bypass Capacitor
100
Audio Input Capacitors
10
(1)
Oscillator Frequency Bias Resistor
SO Output Pull-up Resistor
82
1%
RSO
100
CVREF
Reference Voltage Capacitor, between VREF and
GND
100
Ceramic, X5R
L1
Boost Converter Inductor
4.7
0.3
µH
V
Shielded, Low ESR,
ISAT1.0A
D1
Rectifying Diode, VF @ Maxload
RGB LED
Schottky Diode
Red, Green, Blue or White LEDs
Current Limit Resistors
User Defined
RRX, RGX, RBX
(1) Resistor RT tolerance change will change the timing accuracy of RGB block. Also the boost converter switching frequency will be
affected.
PCB Design Guidelines
Printed circuit board layout is critical to low noise operation and good performance of the LP3950. Bypass
capacitors should be close to the VDD pins of the integrated circuit. Special attention must be given to the routing
of the switching loops. Lengths of these loops should be minimized. It is essential to place the input capacitor,
the output capacitor, the inductor and the schottky diode very close to the integrated circuit and use wide
routings for those components. Sensitive components should be placed far from those components with high
pulsating current. A ground plane is recommended.
The power switch loop (the switch is on) has the greatest affect on noise generation. The loop is formed by the
input capacitor, the inductor, the SW pin, the GND_BOOST pin and the ground plane, as shown by the dashed
line in Figure 31. The other switching loop, the rectifier loop, is formed by the input capacitor, the inductor, the
diode, the output capacitor and the ground plane, as shown by the dotted line. Arrange the components so that
the switching current loops curl in the same direction (see arrows in Figure 31). See also Application Note AN
1149, Layout Guidelines for Switching Mode Power Supplies.
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L
1
SW
D
1
C
IN
C
OUT
GND_BOOST
Figure 31. The Current Loops
Typical Applications
V
DD
= 2.7V TO 2.9V
C
C
C
VDD2
VDDA
100 nF
VDD1
100 nF
100 nF
V
IN
= 3.0V TO 4.5V
V
V
V
DD2
V
DDA
C
IN
10 mF
L
1
4.7 mH
DD1
C
VDD_IO
D
1
DD_IO
100 nF
SW
FB
C
OUT
10 mF
DME
RED
LEDS
R
R1
NRST
R
R2
R3
PWM_LED
R1
G1
B1
R
NOT CONNECTED
SO
ASE
LEFT CHANNEL
AUDIO SIGNAL
C
10 nF
1
GREEN
LEDS
R
G1
G2
G3
AD1
R
R
C
2
RIGHT CHANNEL
AUDIO SIGNAL
C
3
LP3950
10 nF
10 nF
AD2
RT
R
T
82k
BLUE
LEDS
R
B1
B2
B3
C
VREF
100 nF
R
R
V
REF
SDA
SI
HIGH
IF_SEL
SCL
CURRENT
RGB LED
R
R4
R2
G2
B2
AMODE
R
G4
R
B4
GND_RGB
GND_BOOST
GNDA GND1 GND2 GND3
Figure 32. The LP3950 Set to the Default Mode
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V
DD
= 2.7V TO 2.9V
C
C
VDDA
C
VDD2
100 nF
VDD1
100 nF
100 nF
V
IN
= 3.0V TO 4.5V
L
1
V
V
V
DD2
V
DDA
DD1
C
IN
10 mF
C
D
1
VDD_IO
4.7 mH
V
DDIO
DD_IO
100 nF
SW
FB
C
OUT
IF_SEL
SO
RED
LEDS
R
R1
10 mF
R
SO
100 kW
R
R2
R3
R1
G1
B1
R
PWM_LED
SCK
GREEN
LEDS
MICROCONTROLLER
R
G1
SI
SS
R
G2
G3
NRST
LP3950
R
R
1
R
10 kW
2
10 kW
10nF
C
1
ASE
AD1
AD2
SINGLE
ENDED
PWM
C
2
10 nF
C
10 nF
3
BLUE
LEDS
NC
NC
R
B1
SIGNAL
R
B2
R
T
82k
RT
R
R
B3
C
VREF
100 nF
HIGH
CURRENT
RGB LED
V
REF
R4
G4
DME
R2
G2
B2
AMODE
R
GND_RGB
R
B4
GND_BOOST
GNDA GND1 GND2 GND3
NC = Not Connected
Figure 33. Typical Application of LP3950 When the SPI Interface Is Used
Here, a second order RC-filter is used on the ASE input to convert a PWM signal to an analog waveform.
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V
DD
= 2.7V TO 2.9V
C
C
VDDA
C
VDD2
100 nF
VDD1
100 nF
100 nF
V
IN
= 3.0V TO 4.5V
L
1
V
V
V
DD2
V
DDA
DD1
C
IN
10 mF
C
D
1
VDD_IO
4.7 mH
V
DDIO
DD_IO
100 nF
SW
FB
C
OUT
IF_SEL
SO
10 mF
R
SO
100 kW
BACKLIGHT LEDS
R
R1
R
R2
PWM_LED
SCK
R
R
R1
R3
MICROCONTROLLER
SI
R4
SS
NRST
KEYPAD LEDS
V
= 2.7V TO 2.9V
DD
R
G1
G2
G3
R
R
R
3
G1
B1
LP3950
100 kW
R4
100 kW
R
B1
LMV321
C 10nF
1
+
-
ASE
R
B2
R
2
R
B3
C
R
4
1
100 kW
100 nF 10 kW
NC
NC
AD1
AD2
SINGE ENDED
AUDIO SIGNAL
AUDIO SYNC. FUNLIGHT
R5
R
82k
T
R
R
RT
C
VREF
R2
G2
B2
R6
G4
G5
100 nF
V
REF
R
R
DME
AMODE
R
B4
GND_RGB
GND_BOOST
R
B5
GNDA GND1 GND2 GND3
Figure 34. Backlight and Keypad LEDs Controlled by the Pattern Generator
Funlight LEDs Controlled by Audio Synchronization
There may be cases where the audio input signal going into the LP3950 is too weak for audio synchronization.
This figure presents a single-supply inverting amplifier connected to the ASE input for audio signal amplification.
The amplification is +20 dB, which is well enough for 20 mVp-p audio signal. Because the amplifier (LMV321) is
operating in single supply voltage, a voltage divider using R3 and R4 is implemented to bias the amplifier so the
input signal is within the input common-mode voltage range of the amplifier. The capacitor C4 is placed between
the inverting input and resistor R1 to block the DC signal going into the audio signal source. The values of R1 and
C4 affect the cutoff frequency, fc = 1/(2*Pi*R1*C4), in this case it is around 160 Hz. As a result, the LMV321
output signal is centered around mid-supply, that is VDD/2. The output can swing to both rails, maximizing the
signal-to-noise ratio in a low voltage system
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D0
Table 8. LP3950 Control Register Names and Default Values
ADDR
(HEX)
SETUP
D7
D6
D5
D4
D3
D2
D1
00
RGB
CONTROL
RGB PWM
RGB
START
0
RSW1
0
GSW1
0
BSW1
0
RSW2
0
GSW2
0
BSW2
0
0
01
02
03
04
RED
ON/OFF
RON[3]
RON[2]
RON[1]
RON[0]
ROFF[3]
ROFF[2]
ROFF[1]
ROFF[0]
0
0
0
0
0
0
0
0
GREEN
ON/OFF
GON[3]
GON[2]
GON[1]
GON[0]
GOFF[3]
GOFF[2]
GOFF[1]
GOFF[0]
0
0
0
0
0
0
0
0
BLUE
ON/OFF
BON[3]
BON[2]
BON[1]
BON[0]
BOFF[3]
BOFF[2]
BOFF[1]
BOFF[0]
0
0
0
0
0
0
0
0
RED
SLOPE &
DUTY
RSLOPE[3]
RSLOPE[2] RSLOPE[1] RSLOPE[0] RDUTY[3]
RDUTY[2]
RDUTY[1]
RDUTY[0]
0
0
0
0
0
0
0
0
CYCLE
05
06
GREEN
SLOPE &
DUTY
GSLOPE[3]
GSLOPE[2] GSLOPE[1] GSLOPE[0] GDUTY[3]
GDUTY[2]
GDUTY[1]
GDUTY[0]
0
0
0
0
0
0
0
0
CYCLE
BLUE
SLOPE &
DUTY
BSLOPE[3]
BSLOPE[2] BSLOPE[1] BSLOPE[0] BDUTY[3]
BDUTY[2]
BDUTY[1]
BDUTY[0]
0
0
0
0
0
0
0
0
CYCLE
07
CYCLE
PWM
CYCLE[1]
CYCLE[0]
R1_PWM
G1_PWM
B1_PWM
R2_PWM
G2_PWM
B2_PWM
0
0
0
0
0
0
0
0
0B
ENABLES
CYCLE[2]
NSTBY
EN_BOOST EN_FLASH
AUTOLOAD RGB_SEL[1 RGB_SEL[0
0
0
0
0
_EN
]
]
1
1
1
0C
0D
2A
BOOST
FREQUEN
CY
FREQ_SEL[ FREQ_SEL[ FREQ_SEL[
2]
1]
0]
1
1
1
BOOST
OUTPUT
VOLTAGE
BOOST[7]
BOOST[6]
BOOST[5]
BOOST[4]
BOOST[3]
BOOST[2]
BOOST[1]
BOOST[0]
0
0
1
1
1
1
1
1
AUDIO
SYNC
GAIN_SEL[2] GAIN_SEL[ GAIN_SEL[ SYNC_MO
EN_AGC
EN_SYNC INPUT_SEL INPUT_SEL
1
1]
0]
DE
1
0
[0]
[0]
CONTROL
1
0
1
0
1
0
2B
AUDIO
SYNC
MODE_CT MODE_CT SPEED_CT SPEED_CT
RL[1]
RL[0]
RL[1]
RL[0]
CONTROL
2
0
1
0
1
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REVISION HISTORY
Changes from Revision B (April 2013) to Revision C
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 32
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LP3950SL/NOPB
ACTIVE
TLGA
NPC
32
1000 RoHS & Green
NIAU
Level-3-260C-168 HR
-40 to 85
LP3950SL
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Oct-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LP3950SL/NOPB
TLGA
NPC
32
1000
178.0
12.4
4.8
5.8
1.3
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Oct-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
TLGA NPC 32
SPQ
Length (mm) Width (mm) Height (mm)
208.0 191.0 35.0
LP3950SL/NOPB
1000
Pack Materials-Page 2
MECHANICAL DATA
NPC0032A
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