LP3958 [TI]
具有高压升压转换器的照明管理单元;
| 型号： | LP3958 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有高压升压转换器的照明管理单元 升压转换器 高压 |
| 文件： | 总35页 (文件大小：606K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LP3958
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SNVS423C –JANUARY 2006–REVISED MARCH 2013
Lighting Management Unit with High Voltage Boost Converter
Check for Samples: LP3958
1
FEATURES
DESCRIPTION
LP3958 is a Lighting Management Unit for portable
applications. It is used to drive display backlight and
keypad LEDs. The device can drive 5 separately
connected strings of LEDs with high voltage boost
converter.
2
•
High-Efficiency Boost Converter With
Programmable Output Voltage
•
Two Individual Drivers for Serial Display
Backlight LEDs
•
•
•
•
•
Three Drivers for Serial Keypad LEDs
Automatic Dimming Controller
The keypad LED driver allows driving LEDs from high
voltage boost converter or separate supply
voltage.The MAIN and SUB outputs are high
resolution current mode drivers. Keypad LED outputs
can be used in switch mode and current mode.
External PWM control can be used for any selected
outputs.
Stand Alone Serial Leypad LEDs Controller
Three General-Purpose IO Pins
25-Bump DSBGA Package: 2.54mm x 2.54mm
x 0.6mm
The device is controlled through 2-wire low voltage
I2C compatible interface that reduces the number of
required connections.
APPLICATIONS
•
•
•
Cellular Phones and PDAs
MP3 Players
LP3958 is offered in
package.
a tiny 25-bump DSBGA
Digital Cameras
Typical Application
= 70 mA
I
MAX
Li-Ion Battery
or Charger
L1
= 8...18 V
V
OUT
D1
10 mH
C
OUT
2 x 4.7 éF
C
IN
C
VDD
SW
FB
10mF
100 nF
VDD1
MAIN
BACKLIGHT
0...25 mA/LED
VDD2
VDDA
VREF
MAIN
SUB
1 mF
C
VDDA
100 nF
SUB
BACKLIGHT
0...25 mA/LED
C
VREF
R
KEY
IKEY
IRT
KEY1
KEY2
KEY3
R
3 STRINGS
OF 4 LEDS
FOR
RT
LP3958
V
DDIO
KEYPAD
R
SDA
SDA
SCL
GPIO[2]
GPIO[1]
MCU
NRST
GPIO[0]/PWM
VDDIO
C
VDDIO
GND 1-5
100 nF
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2013, Texas Instruments Incorporated
LP3958
SNVS423C –JANUARY 2006–REVISED MARCH 2013
www.ti.com
CONNECTION DIAGRAMS
25-Bump Thin DSBGA Package, Large Bump, Package Number YZR0025
5
4
3
2
1
KEY2
IKEY
FB
SW
SW
FB
NRST
VDDIO
GNDT
SUB
KEY1
SCL
KEY2
IKEY
KEY3
KEY3
KEY1
SCL
5
4
3
2
1
GND_
KEY
GND
_SW
GND
_SW
GND_
KEY
NRST
VDDIO
GNDT
SUB
GPIO
[2]
GPIO
[2]
GPIO
[0]
GPIO
[0]
SDA
SDA
VDD2
VDD2
GPIO
[1]
GND_
WLED
GND_
WLED
GPIO
[1]
VREF
GND
B
VDD1
VDDA
C
VREF
GND
B
VDD1
VDDA
C
IRT
MAIN
MAIN
IRT
A
D
E
E
D
A
Figure 1. Top View
Figure 2. Bottom View
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Table 1. PIN DESCRIPTIONS
Pin No.
5E
5D
5C
5B
5A
4E
4D
4C
4B
4A
3E
3D
3C
3B
3A
2E
2D
2C
2B
2A
1E
1D
1C
1B
1A
Name
SW
Type
Output
Description
Boost Converter Power Switch
Boost Converter Feedback
FB
Input
KEY1
Output
Keypad LED Output 1 (Current Sink)
Keypad LED Output 2 (Current Sink)
Keypad LED Output 3 (Current Sink)
Power Switch Ground
KEY2
Output
KEY3
Output
GND_SW
NRST
Ground
Input
External Reset, Active Low
SCL
Logic Input
Input
Clock Input for I2C Compatible Interface
External Keypad LED Maximum Current Set Resistor
Ground for KEY LED Currents
IKEY
GND_KEY
VDD2
Ground
Power
Supply Voltage 3.0...5.5 V
VDDIO
SDA
Power
Supply Voltage for Digital Input/Output Buffers and Drivers
Data Input/Output for I2C Compatible Interface
General Purpose Logic Input/Output
General Purpose Logic Input/Output / External PWM Input
Ground for White LED Currents (MAIN and SUB Outputs)
Ground
Logic Input/Output
Logic Input/Output
Logic Input/Output
Ground
GPIO[2]
GPIO[0] / PWM
GND_WLED
GNDT
VDD1
Ground
Power
Supply Voltage 3.0...5.5 V
VREF
Output
Reference Voltage (1.23V)
GPIO[1]
MAIN
Logic Input/Output
Output
General Purpose Logic Input/Output
MAIN Display White LED Current Output (Current Sink)
SUB Display White LED Current Output (Current Sink)
Internal LDO Output (2.80V)
SUB
Output
VDDA
GND
Output
Ground
Ground for Core Circuitry
IRT
Input
Oscillator Frequency Set Resistor
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
(1) (2)(3)
Absolute Maximum Ratings
V (SW, FB, MAIN, SUB, KEY1, KEY2, KEY3)
-0.3V to +20V
VDD1, VDD2, VDDIO, VDDA
-0.3V to +6.0V
Voltage on IKEY, IRT, VREF
-0.3V to VDD1+0.3V with 6.0V max
Voltage on Logic Pins
-0.3V to VDDIO +0.3V with 6.0V max
I (VREF
)
10µA
100mA
I(KEY1, KEY2, KEY3)
(4)
Continuous Power Dissipation
Internally Limited
125ºC
Junction Temperature (TJ-MAX
Storage Temperature Range
)
-65ºC to +150ºC
260ºC
(5)
Maximum Lead Temperature (Soldering)
(6)
ESD Rating
Human Body Model
Machine Model
2kV
200V
(1) Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under
which operation of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed
performance limits and associated test conditions, see the Electrical Characteristics tables.
(2) All voltages are with respect to the potential at the GND pins.
(3) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
(4) Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ=150ºC (typ.) and
disengages at TJ=130ºC (typ.).
(5) For detailed soldering specifications and information, please refer to Application Note AN1112: DSBGA Wafer Level Chip Scale
Package
(6) The Human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin. The machine model is a 200pF
capacitor discharged directly into each pin. MIL-STD-883 3015.7
(1) (2)
Operating Ratings
V (SW, FB, MAIN, SUB)
0 to +19V
3.0 to 5.5V
VDD1,2
VDDIO
1.65V to VDD1
Recommended Load Current (KEY1, KEY2, KEY3) CC Mode
Recommended Total Boost Converter Load Current
Junction Temperature (TJ)
0mA to 15mA/driver
0mA to 70mA
-30ºC to +125ºC
-30ºC to +85ºC
Ambient Temperature (TA)(3)
(1) Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under
which operation of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed
performance limits and associated test conditions, see the Electrical Characteristics tables.
(2) All voltages are with respect to the potential at the GND pins.
(3) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP
125ºC), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the
part/package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX).
=
Thermal Properties
Junction-to-Ambient Thermal Resistance(θJA
(1)
)
60 - 100ºC/W
(1) Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power
dissipation exists, special care must be paid to thermal dissipation issues in board design.
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(1) (2)
Electrical Characteristics
Limits in standard typeface are for TJ = 25º C. Limits in boldface type apply over the operating ambient temperature range (-
30ºC < TA < +85ºC). Unless otherwise noted, specifications apply to the LP3958 Block Diagram with: VDD1,2 = 3.0 ... 5.5V,
CVDD = CVDDIO = 100nF, COUT = 2 x 4.7µF, CIN = 10µF, CVDDA = 1µF, CVREF = 100nF, L1 = 10µH, RKEY = 8.2kΩ and RRT
=
(3)
82kΩ
.
Symbol
Parameter
Standby supply current
(VDD1, VDD2
No-boost supply current
(VDD1, VDD2
No-load supply current
(VDD1, VDD2
Test Conditions
NSTBY = L
Register 0DH=08H
Min
Typ
Max
7
Unit
IVDD
1.7
µA
(4)
)
NSTBY = H,
EN_BOOST = L
300
750
800
µA
uA
)
NSTBY = H,
EN_BOOST = H
Autoload OFF
1300
)
VDDA
Output voltage of internal LDO
IVDDA = 1mA
2.80
1.23
V
%
V
-3
+3
(5)
VREF
Reference voltage
(1) All voltages are with respect to the potential at the GND pins.
(2) Min and Max limits are guaranteed by design, test, or statistical analysis. Typical numbers are not guaranteed, but do represent the
most likely norm.
(3) Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics.
(4) Boost output voltage set to 8V (08H in register 0DH) to prevent any unneccessary current consumption.
(5) No external loading allowed for VREF pin.
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BLOCK DIAGRAM
Optional EMI FILTER,
close to SW pin
C
SW
R
SW
= 70 mA
I
MAX
390W
100 pF
= 8...18 V
V
L1
OUT
10 mH
C
D1
SW
FB
OUT
C
IN
C
VDD
2 x 4.7 éF
100 nF VDD2
VDD1
10 éF
Logic supply
BG
Li-Ion
Battery
or
PWM
1 mF
LDO
REF
POR
VDDA
GND_SW
MAIN
Charger
C
VDDA
VREF
100 nF
BOOST
BACKLIGHT
0...25 mA/LED
THSD
C
VREF
MAIN
8-Bit
IDAC
R
KEY
IKEY
IRT
GND_WLED
BIAS
OSC
D
A
SUB
BACKLIGHT
R
0...25 mA/LED
RT
SUB
V
DDIO
8-Bit
IDAC
R
SDA
CONTROL
D
A
SDA
SCL
3 STRINGS
OF 4 LEDS
MCU
NRST
VDDIO
FOR KEYPAD
I2C
CVDDIO
100 nF
GPIO[2]
GPIO[1]
GPIO[0]/PWM
KEY1
KEY2
KEY3
BRIGHTNESS
CONTROL
GND_KEY
GND
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APPLICATION INFORMATION
Modes of Operation
RESET: In the RESET mode all the internal registers are reset to the default values. Reset is entered always if
input NRST is LOW or internal Power On Reset is active. Power On Reset (POR) will activate during the
chip startup or when the supply voltages VDD1 and VDD2 fall below 1.5V. Once VDD1 and VDD2 rises above
1.5V, POR will inactivate and the chip will continue to the STANDBY mode. NSTBY control bit is low after
POR by default.
STANDBY: The STANDBY mode is entered if the register bit NSTBY is LOW and Reset is not active. This is the
low power consumption mode, when all circuit functions are disabled. Registers can be written in this
mode and the control bits are effective immediately after start up.
STARTUP: When NSTBY bit is written high, the INTERNAL STARTUP SEQUENCE powers up all the needed
internal blocks (VREF, Bias, Oscillator etc.). To ensure the correct oscillator initialization, a 10ms delay is
generated by the internal state-machine. If the chip temperature rises too high, the Thermal Shutdown
(THSD) disables the chip operation and STARTUP mode is entered until no thermal shutdown event is
present.
BOOST STARTUP:Soft start for boost output is generated in the BOOST STARTUP mode. The boost output is
raised in low current PWM mode during the 20ms delay generated by the state-machine. All LED outputs
are off during the 20ms delay to ensure smooth startup. The Boost startup is entered from Internal Startup
Sequence if EN_BOOST is HIGH or from Normal mode when EN_BOOST is written HIGH.
NORMAL: During NORMAL mode the user controls the chip using the Control Registers. The registers can be
written in any sequence and any number of bits can be altered in a register in one write.
RESET
NRST = L
NSTBY = L
or POR = H
and NRST = H
STANDBY
NSTBY = L and
NSTBY = H and
NRST = H
NRST = H
INTERNAL
STARTUP
SEQUENCE
V
REF
= 95% OK*
THSD = H
~10 ms Delay
EN_BOOST = H*
EN_BOOST = L*
BOOST STARTUP
~20 ms Delay
EN_BOOST
rising edge*
NORMAL MODE
* THSD = L
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Power-Up Sequence
When powering up the device, VDD1 and VDD2 should be greater than VDDIO to prevent any damage to the device.
VDD
VDD1,2
0V
VDDIO
VDDIO
0V
Magnetic Boost DC/DC Converter
The LP3958 Boost DC/DC Converter generates an 8…18V supply voltage for the LEDs from single Li-Ion battery
(3V…4.5V). The output voltage is controlled with an 8-bit register in 10 steps. The converter is a magnetic
switching PWM mode DC/DC converter with a current limit. Switching frequency is 1MHz, when timing resistor
RT is 82kΩ. Timing resistor defines the internal oscillator frequency and thus directly affects boost frequency and
KEY timings.
EMI filter (RSW and CSW) on the SW pin can be used to suppress EMI caused by fast switching. These
components should be as near as possible to the SW pin to ensure reliable operation. The LP3958 Boost
Converter uses pulse-skipping elimination to stabilize the noise spectrum. Even with light load or no load a
minimum length current pulse is fed to the inductor. An active load is used to remove the excess charge from the
output capacitor at very light loads. Active load can be disabled with the EN_AUTOLOAD bit. Disabling active
load will increase slightly the efficiency at light loads, but the downside is that pulse skipping will occur. The
Boost Converter should be stopped when there is no load to minimise the current consumption.
The topology of the magnetic boost converter is called CPM control, current programmed mode, where the
inductor current is measured and controlled with the feedback. The user can program the output voltage of the
boost converter. The output voltage control changes the resistor divider in the feedback loop. Figure 3 shows the
boost topology with the protection circuitry. Four different protection schemes are implemented:
1. Over voltage protection, limits the maximum output voltage
–
–
Keeps the output below breakdown voltage.
Prevents boost operation if battery voltage is much higher than desired output.
2. Over current protection, limits the maximum inductor current
Voltage over switching NMOS is monitored; too high voltages turn the switch off.
–
3. Feedback break protection. Prevents uncontrolled operation if FB pin gets disconnected.
4. Duty cycle limiting, done with digital control.
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V
V
1 MHz clock
Duty control
IN
OUT
SW
FB
UVCOMP
R
S
-
+
2V
OVPCOMP
R
R
SWITCH
+
-
RESETCOMP
+
-
R
-
+
ERRORAMP
ACTIVE
LOAD
+
-
R
R
+
SLOPER
OLPCOMP
LOOPC
-
OCPCOMP
IMAX
+
-
Figure 3. Boost Converter Topology
MAGNETIC BOOST DC/DC CONVERTER ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
ILOAD
Maximum Continuous Load
Current
3.0V = VIN
VOUT = 18V
70
mA
VOUT
Output Voltage Accuracy
(FB Pin)
3.0V ≤ VIN ≤ 5.5V
VOUT = 18V
−3.5
+3.5
0.3
%
Ω
RDSON
fPWM
Switch ON Resistance
ISW = 0.5A
0.15
1.0
PWM Mode Switching
Frequency
RT = 82 kΩ
MHz
Frequency Accuracy
RT = 82 kΩ
−7
−9
+7
%
+9
tPULSE
Switch Pulse Minimum
Width
no load
45
ns
tSTARTUP Startup Time
Boost startup from STANDBY to VOUT = 18V,
no load
15
ms
IMAX
SW Pin Current Limit
800
1150
mA
BOOST STANDBY MODE
User can set the Boost Converter to STANDBY mode by writing the register bit EN_BOOST low. When
EN_BOOST is written high, the converter starts for 20ms in low current PWM mode and then goes to normal
PWM mode. All LED outputs are off during the 20ms delay to ensure smooth startup.
BOOST OUTPUT VOLTAGE CONTROL
User can control the boost output voltage by Boost Output 8-bit register.
Boost Output [7:0]
Boost Output
Register 0DH
Voltage (typical)
Bin
Dec
8
0000 1000
0000 1001
0000 1010
0000 1011
8.0V
9.0V
9
10
11
10.0V
11.0V
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0000 1100
0000 1101
0000 1110
0000 1111
0001 0000
0001 0001
0001 0010
12
13
14
15
16
17
18
12.0V
13.0V
14.0V
15.0V
16.0V
17.0V
18.0V
If register value is lower than 8, then value of 8 is used internally.
If register value is higher than 18, then value of 18 is used internally.
Boost Output Voltage Control
VIN = 3.6 V
Control 8 V...18 V
Figure 4.
Boost Converter Typical Performance Characteristics
Vin = 3.6V, Vout = 18.0V if not otherwise stated
Boost Converter Efficiency
Boost Typical Waveforms at 70mA Load
92
91
90
89
88
87
I
= 70 mA
50 mA
LOAD
25 mA
L = Coilcraft LPS4018-103ML
3.0
3.5
4.0
4.5
5.0
5.5
INPUT VOLTAGE (V)
Figure 5.
Figure 6.
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Vin = 3.6V, Vout = 18.0V if not otherwise stated
Battery Current vs Voltage
Boost Output Voltage vs. Current
19
18
17
16
15
14
13
ILOAD = 70 mA
VOUT = 18 V
VOUT = 8 V
V
= 3.0V
IN
L = Coilcraft LPS4018-103ML
0
20 40 60 80
100
120
OUTPUT CURRENT (mA)
Figure 7.
Figure 8.
Boost Line Regulation 3.0V - 3.6V, no load
Boost Turn On Time with No Load
20
18
16
14
12
10
8
6
V
TARGET VALUE = 18V
OUT
3
4
2
0
1
2
4
5
6
7
8
TIME (ms)
Figure 9.
Figure 10.
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Vin = 3.6V, Vout = 18.0V if not otherwise stated
Boost Load Transient Response 25mA – 70mA
Autoload Effect on Input Current, No Load
AUTOLOAD ON
AUTOLOAD OFF
Figure 11.
Figure 12.
Boost Maximum Current vs. Output Voltage
500
400
300
200
100
V
= 5.5V
IN
V
= 3.6V
IN
V
IN
= 3.0V
10
8
12
14
16
18
OUTPUT VOLTAGE (V)
Figure 13.
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Vin = 3.6V, Vout = 18.0V if not otherwise stated
Functionality of Keypad LED Outputs (KEY1, KEY2, KEY3)
LP3958 has three individual keypad LED output pins. Output pins can be used in switch mode or constant
current mode. Output mode can be selected with the control register (address 00H) bit CC_SW. If the bit is set
high, then keypad LED outputs are in switch mode, otherwise in constant current mode. These modes are
described later in separate chapters.
Keypad LED output control can be done in three ways:
1. Defining the expected balance and brightness in Keypad register (address 01H)
2. Direct setting each LED ON/OFF via Keypad control register (address 00H)
3. External PWM control
BRIGHTNESS CONTROL WITH KEYPAD REGISTER
If the keypad LED output is used by defining the balance and brightness in the Keypad register, then one needs
to set EN_KEYP bit high and KEYP_PWM bit high in the Control register (address 00H). K1SW, K2SW and
K3SW are used to enable each LED output, enabled when written high. CC_SW defines the LED output mode. A
single register is used for defining the balance and brightness for keypad LED output:
KEYPAD REGISTER (01H)
Name
BALANCE[2:0]
BRIGHT[2:0]
OVL
Bit
6:4
3:1
0
Description
Balance of KEY1, KEY2 and KEY3 outputs
Brightness control
Overlapping mode selection:
0 = non-overlapping mode
1 = overlapping mode
Brightness control is logarithmic and is programmed as follows:
Table 2.
Bright[2:0]
Brightness [%]
Ratio to max
brightness
000
001
010
011
100
101
110
111
0
0
1.56
3.12
6.25
12.5
25
1/64
1/32
1/16
1/8
1/4
50
1/2
100
1/1
The LED balance can be selected as follows. This is valid only in non-overlapping mode.
Table 3.
Balance
[2:0]
KEY1
active [%]
KEY2
active [%]
KEY3
active [%]
000
001
010
011
100
101
110
111
100
0
0
100
0
0
0
0
100
0
50
0
50
50
0
50
50
33
25
50
33
50
33
25
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OVERLAPPING MODE
The brightness is controlled using PWM duty cycle based control method as Figure 14 shows.
50 ms / 20 kHz
FRAME
KEY1
KEY2
KEY3
ON
ON
ON
Figure 14. Overlapping Mode
Since KEY outputs are on simuneltaneously, the maximum load peak current is:
IMAX = I(KEY1)MAX + I(KEY2)MAX + I(KEY3)MAX
(1)
NON-OVERLAPPING MODE
The timing diagram shows the splitted KEY1, KEY2 and KEY3 and brightness control effect to splitted parts. Full
brightness is used in the diagram. If for example ½ brightness is used, the frame is still 50µs, but all LED outputs’
ON time is 50% shorter and at the last 25µs all LED outputs are OFF.
50 ms / 20 kHz
FRAME
ON
KEY1
KEY2
KEY3
SUM
ON
ON
KEY1
33%
KEY2
33%
KEY3
33%
Figure 15. Non-overlapping Mode
The non-overlapping mode has 8-programmed balance ratios. Since the KEY1, KEY2 and KEY3 are split in to
non-overlapping slots the output current through the keypad LED can be calculated by following equation:
IAVG=(CKEY1×IKEY1+CKEY2×IKEY2+CKEY3×IKEY3)×B
where
•
•
C = Balance [%] (see Table 3)
B = Brightness [%] (see Table 2)
(2)
LED ON/OFF CONTROL WITH KEYPAD CONTROL REGISTER
Each LED output can be set ON by writing the corresponding bit high in the control register. K1SW controls
KEY1, K2SW controls KEY2 and K3SW controls KEY3 output. Note that EN_KEYP bit must be high and
KEYP_PWM bit low. In this mode, the KEYPAD register does not have any effect. CC_SW bit in control register
defines the LED output mode.
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Switch Mode / Constant Current Mode
Each keypad LED output can be set to act as a switch or a constant current sink. Selection of mode is done with
the CC_SW bit in the Control Register. If bit is set high, then the switch mode is selected. Default is switch mode.
1. SWITCH MODE
In switch mode, the keypad LED outputs are low ohmic switches to ground. Resistance is typically 3.5Ω.
External ballast resistors must be used to limit the current through the LED.
2. CONSTANT CURRENT MODE
In constant current mode, the maximum output current is defined with a single external resistor (RKEY) and the
maximum current control register (address 02H).
KEYPAD MAX CURRENT REGISTER (02H)
Name
IK1[1:0]
IK2[1:0]
IK3[1:0]
Bit
5:4
3:2
1:0
Description
KEY1 maximum current
KEY2 maximum current
KEY3 maximum current
Maximum current for each LED output is adjusted with the Keypad max current register in following way:
IK1[1:0], IK2[1:0], IK3[1:0]
Maximum current / output
0.25 x IMAX
00
01
10
11
0.50 x IMAX
0.75 x IMAX
1.00 x IMAX
External ballast resistors are not needed in this mode. The maximum current for all keypad LED drivers is set
with RKEY. The equation for calculating the maximum current is:
IMAX = 100 × 1.23V / (RKEY + 50 Ω)
where
•
•
•
•
•
IMAX = maximum KEY current in any KEY output (during constant current mode)
1.23V = reference voltage
100 = internal current mirror multiplier
RKEY = resistor value in Ohms
50 Ω = Internal resistor in the IKEY input
(3)
Table with example resistance values and corresponding output currents:
Maximum current / output IMAX
KEY resistor RKEY (kΩ)
(mA)
14.9
13.4
12.2
10.2
8.2
8.2
9.1
10
12
15
18
24
6.8
5.1
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Note that the LED output requires a minimum saturation voltage in order to act as a true constant current sink.
The saturation voltage minimum is typically 100mV. If the LED output voltage drops below 100mV, then the
current will decrease significantly.
External PWM Control
The GPIO[0]/PWM pin can be used to control the KEY output. PWM function for the pin is selected by writing
EN_PWM_PIN high in GPIO control register (address 06H). Note, that EN_KEYP bit must be set high. Each LED
output can be enabled with K1SW, K2SW and K3SW bits. EN_EXT_K1_PWM, EN_EXT_K2_PWM and
EN_EXT_K3_PWM bits are used to select, which LED outputs are controlled with the external PWM input. Note
that polarity of external PWM control is active high i.e. when high, then LED output is enabled. If KEYP_PWM is
set low, then each selected LED output is controlled directly with external PWM input. If KEYP_PWM is set high,
then internal PWM control is modulated by the external PWM input. In latter case, internal PWM control is
passed to LED when external PWM input is high.
Keypad LEDs Driver Performance Characteristics
Symbol
ILEAKAGE
Parameter
Test Conditions
Min
Typ
Max
1
Unit
µA
KEY1, KEY2, KEY3 pin leakage current
Maximum recommended sink current(1) CC mode
SW mode
IMAX(KEY)
15
60
mA
mA
%
Accuracy at 15mA
CC mode
CC mode
5
1:100
3
Current mirror ratio
KEY current matching error
Switch resistance
IKEY set to 15mA, CC mode
SW mode
%
Ω
RSW
ƒKEY
3.5
20
KEY internal PMW switching frequency Accuracy same as internal clock
frequency accuracy
kHz
VSAT
Saturation voltage (current drop 10%)
IKEY set to 15mA
100
500
mV
(1) KEY current should be limited as follows:
constant current mode – limited by external RKEY resistor
switch mode – limited by external ballast resistors
Backlight Drivers
LP3958 has 2 independent backlight drivers. Both drivers are regulated constant current sinks. LED current for
both LED strings are controlled by the 8-bit current mode DACs with 0.1 mA step. MAIN and SUB LEDs can be
also controlled with one DAC (MAIN) for better matching allowing the use of larger displays having up to 8 white
LEDs by setting DISPL bit to 1.
VBOOST
External PWM
&
en_main_pwm
8-Bit IDAC
main[7:0]
MAIN
en_main
Figure 16. MAIN output for 4 LEDs (DISPL = 0)
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VBOOST
External PWM
en_sub_pwm
&
8-Bit IDAC
SUB
sub[7:0]
en_sub
Figure 17. SUB output for 2 LEDs (DISPL = 0)
VBOOST
VBOOST
External PWM
en_main_pwm
&
8-Bit IDAC
MAIN
main[7:0]
en_main
Figure 18. MAIN and SUB outputs for 8 LEDs (DISPL = 1)
PWM CONTROL
External PWM control is enabled by writing 1 to EN_MAIN_PWM and/or EN_SUB_PWM bits in register address
2BH. GPIO[0] pin is used as external PWM input when EN_PWM_PIN is set high. PWM input is active high, i.e.
LED is activated when in high state.
FADE IN / FADE OUT
LP3958 has an automatic fade in and out for main and sub backlight. The fade function is enabled with
EN_FADE bit. The slope of the fade curve is set by the SLOPE bit. Fade control for main and sub display is set
by FADE_SEL bit.
Recommended fading sequence:
1. ASSUMPTION: Current WLED value in register
2. Set SLOPE
3. Set FADE_SEL
4. Set EN_FADE = 1
5. Set target WLED value
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6. Fading will be done either within 0.65s or 1.3s based on SLOPE selection
Fading times apply to full scale change i.e. from 0 to 100% or vice versa. If the current change does not
correspond to full scale change, the time will be respectively shorter. See WLED Dimming diagrams for typical
fade times.
WLED CONTROL REGISTER (03H)
Name
Bit
Description(1)
SLOPE
5
FADE execution time:
0 = 1.3s (full scale)
1 = 0.65s (full scale)
FADE_SEL
EN_FADE
DISPL
4
3
2
1
0
FADE selection:
0 = FADE controls MAIN
1 = FADE controls SUB
FADE enable
0 = FADE disabled
1 = FADE enabled
Display mode:
0 = MAIN and SUB individual control
1 = MAIN and SUB controlled with MAIN DAC
EN_MAIN
EN_SUB
MAIN enable:
0 = disable
1 = enable
SUB enable:
0 = disable
1 = enable
(1) If DISPL=1 and FADE_SEL=0 then FADE effects MAIN and SUB
Adjustment is made with 04H (main current) and with 05H (sub current) registers:
MAIN CURRENT [7:0]
SUB CURRENT [7:0]
Driver current,
mA (typical)
0000 0000
0000 0001
0000 0010
0000 0011
…
0
0.1
0.2
0.3
…
…
…
1111 1101
1111 1110
1111 1111
25.3
25.4
25.5
Backlight Driver Electrical Characteristics
Symbol
IMAX
Parameter
Maximum Sink Current
Leakage Current
Test Conditions
Min
Typ
25.5
0.03
12.8
Max
30
Unit
mA
µA
ILEAKAGE
VSUB, MAIN =18V
1
IMAIN
ISUB
MAIN Current tolerance
SUB Current tolerance
IMAIN and ISUB set to 12.8mA (80H)
ISINK=12.8mA, DISPL=1
ISINK=12.8mA, DISPL=0
ISINK=25mA
11.1
14.1
mA
MatchMAIN-
SUB
Sink Current Matching Error(1)
Sink Current Matching Error
95% Saturation Voltage
0.2
5
%
%
MatchMAIN-
SUB
VSAT
400
600
mV
800
(1) Matching is the maximum difference from the average.
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WLED Dimming, SLOPE=0
WLED Dimming, SLOPE=1
100
80
60
40
20
0
100
80
60
40
20
0
FADE OUT
FADE IN
FADE OUT
FADE IN
0
0.1
0.5 0.6 0.7
0
0.2
0.1 1.2 1.4
0.2 0.3 0.4
TIME (s)
0.4 0.6 0.8
TIME (s)
Figure 19.
Figure 20.
WLED Output Current vs. Voltage
+25°C
-40°C
+85°C
Figure 21.
General Purpose I/O Functionality
LP3958 has three general purpose I/O pins: GPIO[0]/PWM, GPIO[1] and GPIO[2]. GPIO[0]/PWM can also be
used as a PWM input for the external LED PWM controlling. GPIO bi-directional drivers are operating from the
VDDIO supply domain.
Registers for GPIO are as follows:
GPIO CONTROL (06H)
Name
Bit
Description
Enable PWM pin
EN_PWM_PIN
4
0 = disable
1 = enable
OEN[2:0]
2:0
GPIO pin direction
0 = input
1 = output
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GPIO DATA (07H)
Name
Bit
Description
Data bits
DATA[2:0]
2:0
GPIO control register is used to set the direction of each GPIO pin. For example, by setting OEN0 bit high the
GPIO[0]/PWM pin acts as a logic output pin with data defined DATA0 in GPIO data register. Note, that the
EN_PWM_PIN bit overrides OEN0 state by forcing GPIO[0]/PWM to act as PWM input. GPIO[1] and GPIO[2]
pins can be selected to be inputs or outputs, defined by OEN1 and OEN2 bit status. PWM functionality is valid
only for GPIO[0]/PWM pin. GPIO data register contains the data of GPIO pins. When output direction is selected
to GPIO pin, then GPIO data register defines the output pin state. When GPIO data register is read, it contains
the state of the pin despite of the pin direction.
Table 4. Logic Interface Characteristics(VDDIO = 1.65V...VDD1,2 unless otherwise noted)
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
LOGIC INPUT SCL, SDA, GPIO[0:2]
VIL
VIH
II
Input Low Level
Input High Level
Logic Input Current
Clock Frequency
0.2×VDDIO
V
V
0.8×VDDIO
−1.0
1.0
µA
kHz
fSCL
400
LOGIC INPUT NRST
VIL
VIH
II
Input Low Level
0.5
1.0
V
V
Input High Level
Input Current
1.2
-1.0
10
µA
µs
tNRST
Reset Pulse Width
LOGIC OUTPUT SDA
VOL
VOH
IL
Output Low Level
ISDA = 3mA
0.3
0.5
1.0
0.5
1.0
V
Output High Level
ISDA = -3mA
VSDA = 2.8V
VDDIO − 0.5
VDDIO − 0.3
Output Leakage Current
µA
LOGIC OUTPUT GPIO[0:2]
VOL
VOH
IL
Output Low Level
IGPIO = 3 mA
IGPIO = −3 mA
VGPIO = 2.8V
0.3
V
V
Output High Level
VDDIO − 0.5
VDDIO − 0.3
Output Leakage Current
µA
I2C Compatible Interface
I2C SIGNALS
The SCL pin is used for the I2C clock and the SDA pin is used for bidirectional data transfer. Both these signals
need a pull-up resistor according to I2C specification.
I2C DATA VALIDITY
The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state of
the data line can only be changed when CLK is LOW.
SCL
SDA
data
change
allowed
data
change
allowed
data
change
allowed
data
valid
data
valid
Figure 22. I2C Signals: Data Validity
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I2C START AND STOP CONDITIONS
START and STOP bits classify the beginning and the end of the I2C session. START condition is defined as SDA
signal transitioning from HIGH to LOW while SCL line is HIGH. STOP condition is defined as the SDA
transitioning from LOW to HIGH while SCL is HIGH. The I2C master always generates START and STOP bits.
The I2C bus is considered to be busy after START condition and free after STOP condition. During data
transmission, I2C master can generate repeated START conditions. First START and repeated START
conditions are equivalent, function-wise.
SDA
SCL
S
P
STOP condition
START condition
Figure 23. I2C Start and Stop Conditions
TRANSFERRING DATA
Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first.
Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated
by the master. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver
must pull down the SDA line during the 9th clock pulse, signifying an acknowledge. A receiver which has been
addressed must generate an acknowledge after each byte has been received.
After the START condition, the I2C master sends a chip address. This address is seven bits long followed by an
eighth bit which is a data direction bit (R/W). The LP3958 address is 59H (101 1001b). For the eighth bit, a “0”
indicates a WRITE and a “1” indicates a READ. This means that the first byte is B2H for WRITE and B3H for
READ. The second byte selects the register to which the data will be written. The third byte contains data to write
to the selected register.
MSB
LSB
ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 R/W
Bit7
bit6
2
bit5
bit4
bit3
bit2
bit1
bit0
I C SLAVE address (chip address)
Figure 24. I2C Chip Address
Register changes take an effect at the SCL rising edge during the last ACK from slave.
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ack from slave
ack from slave
ack stop
ack from slave
start msb Chip Address lsb
w
ack
msb Register Add lsb
ack
msb DATA lsb
SCL
SDA
start
id = 59H = 101 1001b
w
ack
addr = 02H
ack
address 02H data
ack stop
w = write (SDA = “0”)
r = read (SDA = “1”)
ack = acknowledge (SDA pulled down by either master or slave)
rs = repeated start
id = 7-bit chip address, 59H (101 1001b) for LP3958.
Figure 25. I2C Write Cycle
When a READ function is to be accomplished, a WRITE function must precede the READ function, as shown in
the Read Cycle waveform.
ack from slave
ack from slave repeated start
ack from slave data from slave ack from master
start msb Chip Address lsb
w
msb Register Add lsb
rs
msb Chip Address lsb
r
msb DATA lsb
stop
SCL
SDA
start
id = 59H = 101 1001b
w
ack
addr = 00H
ack rs
id = 59H = 101 1001b
r
ack
address 00H data
ack stop
Figure 26. I2C Read Cycle
SDA
10
7
8
7
6
1
8
2
SCL
5
1
4
9
3
Figure 27. I2C Timing Diagram
I2C TIMING PARAMETERS (VDD1,2 = 3.0 to 4.5V, VDDIO = 1.8V to VDD1,2
)
Limit(1)
Symbol
Parameter
Hold Time (repeated) START Condition
Unit
Min
0.6
Max
1
µs
(1) Data guaranteed by design
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Symbol
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Limit(1)
Parameter
Unit
Min
1.3
Max
2
3
Clock Low Time
Clock High Time
µs
ns
ns
ns
ns
ns
ns
ns
ns
µs
pF
600
4
Setup Time for a Repeated START Condition
Data Hold Time (Output direction, delay generated by LP3958)
Data Hold Time (Input direction, delay generated by Master)
Data Setup Time
600
5
300
900
900
5
0
6
100
7
Rise Time of SDA and SCL
20+0.1Cb
15+0.1Cb
600
300
300
8
Fall Time of SDA and SCL
9
Set-up Time for STOP condition
10
Cb
Bus Free Time between a STOP and a START Condition
Capacitive Load for Each Bus Line
1.3
10
200
Recommended External Components
OUTPUT CAPACITOR, COUT
The output capacitor COUT directly affects the magnitude of the output ripple voltage. In general, the higher the
value of COUT, the lower the output ripple magnitude. Multilayer ceramic capacitors with low ESR are the best
choice. At the lighter loads, the low ESR ceramics offer a much lower VOUT ripple that the higher ESR tantalums
of the same value. At the higher loads, the ceramics offer a slightly lower VOUT ripple magnitude than the
tantalums of the same value. However, the dv/dt of the VOUT ripple with the ceramics is much lower that the
tantalums under all load conditions. Capacitor voltage rating must be sufficient, 25V or greater is recommended.
Examples of suitable capacitors are: TDK C3216X5R1E475K, Panasonic ECJ3YB1E475K, ECJMFB1E475K and
ECJ4YB1E475K.
Some ceramic capacitors, especially those in small packages, exhibit a strong capacitance reduction
with the increased applied voltage (DC bias effect). The capacitance value can fall below half of the
nominal capacitance. Too low output capacitance can make the boost converter unstable. Output
capacitors DC bias effect should be better than –50% at 18V.
INPUT CAPACITOR, CIN
The input capacitor CIN directly affects the magnitude of the input ripple voltage and to a lesser degree the VOUT
ripple. A higher value CIN will give a lower VIN ripple. Capacitor voltage rating must be sufficient, 10V or greater is
recommended.
OUTPUT DIODE, D1
A schottky diode should be used for the output diode. Peak repetitive current should be greater than inductor
peak current (800mA) to ensure reliable operation. Schottky diodes with a low forward drop and fast switching
speeds are ideal for increasing efficiency in portable applications. Choose a reverse breakdown voltage of the
schottky diode significantly larger (~30V) than the output voltage. Do not use ordinary rectifier diodes, since slow
switching speeds and long recovery times cause the efficiency and the load regulation to suffer. Example of
suitable diode is: Central Semiconductor CMMSH1-40.
EMI FILTER COMPONENTS CSW, RSW
EMI filter (RSW and CSW) on the SW pin can be used to suppress EMI caused by fast switching. These
components should be as near as possible to the SW pin to ensure reliable operation. 50V or greater voltage
rating is recommended for capacitor.
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INDUCTOR, L1
A 10uH shielded inductor is suggested for LP3958 boost converter. The inductor should have a saturation
current rating higher than the rms current it will experience during circuit operation (600mA). Less than 300mΩ
ESR is suggested for high efficiency and sufficient output current. Open core inductors cause flux linkage with
circuit components and interfere with the normal operation of the circuit. This should be avoided. For high
efficiency, choose an inductor with a high frequency core material such as ferrite to reduce the core losses. To
minimize radiated noise, use a toroid, pot core or shielded core inductor. The inductor should be connected to
the SW pin as close to the IC as possible. Examples of suitable inductors are: TDK VLF4012AT-100MR79,
VLF4018BT-100MR90, VLF5014AT-100MR92, Coilcraft LPS4018-103ML.
LIST OF RECOMMENDED EXTERNAL COMPONENTS
Symbol
CVDD
Symbol Explanation
Value
100
100
1
Unit
nF
Type
Ceramic, X7R / X5R
Ceramic, X7R / X5R
Ceramic, X7R / X5R
C between VDD1,2 and GND
C between VDDIO and GND
C between VDDA and GND
C between FB and GND
CVDDIO
CVDDA
nF
µF
2 x 4.7 or 1 x
10
µF
Ceramic, X7R / X5R, tolerance
±10%
COUT
Maximum DC bias effect @ 18V
C between battery voltage and GND
L between SW and VBAT
Saturation current
-50
10
%
µF
µH
mA
nF
kΩ
kΩ
V
CIN
L1
Ceramic, X7R / X5R
10
Shielded inductor, low ESR
600
100
8.2
CVREF
RKEY
RRT
C between VREF and GND
R between IKEY and GND
R between IRT and GND
Rectifying diode (Vf @ maxload)
Reverse voltage
Ceramic, X7R / X5R
±1%
±1%
82
0.3-0.5
30
D1
V
Schottky diode
Repetitive peak current
C in EMI filter
800
100
390
mA
pF
Ω
CSW
RSW
Ceramic, X7R / X5R, 50V
±1%
R in EMI filter
LEDs
User Defined
Note: See Application Note AN-1436 "Design and Programming Examples for Lighting Management Unit
LP3958" for more information on how to design with LP3958
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Table 5. LP3958 Control Register Names and Default Values
ADDR
(HEX)
REGISTER
D7
D6
D5
D4
D3
D2
D1
D0
00
01
02
03
04
05
06
07
0B
Control Register
KEYP_PWM
EN_KEYP
CC_SW
K1SW
K2SW
K3SW
0
0
1
0
0
0
Keypad
Keypad Max Current
WLED Control
MAIN Current
SUB Current
GPIO Control
GPIO Data
BALANCE[2:0]
BRIGHT[2:0]
OVL
0
0
0
0
0
0
0
IK1[1:0]
IK2[1:0]
IK3[1:0]
0
SLOPE
0
0
0
EN_FADE
0
0
DISPL
0
0
EN_MAIN
0
0
EN_SUB
0
FADE_SEL
0
MAIN[7:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SUB[7:0]
0
0
0
EN_PWM_PIN
OEN[2:0]
0
0
DATA[2:0]
0
Enables
NSTBY
EN_BOOST
EN_AUTOLOA
D
0
0
1
0D
2B
Boost Output
PWM Enable
BOOST[7:0]
0
0
0
0
1
0
0
0
EN_EXT_K1_P EN_EXT_K2_P EN_EXT_K3_P EN_MAIN_PW EN_SUB_PWM
WM
WM
WM
M
0
0
0
0
0
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LP3958 Register Bit Explanations
Each register is shown with a key indicating the accessibility of the each individual bit, and the initial condition:
Table 6. Register Bit Accessibility and Initial Condition
Key
RW
R
Bit Accessibility
Read/write
Read only
–0,–1
Condition after POR
CONTROL REGISTER (00H) – KEYPAD LEDS CONTROL REGISTER
D7
D6
D5
D4
D3
D2
D1
D0
KEYP_PWM
RW - 0
EN_KEYP
RW - 0
CC_SW
RW - 1
K1SW
RW - 0
K2SW
RW - 0
K3SW
RW - 0
R - 0
R - 0
0 - Internal KEYPAD PWM control disabled
1 - Internal KEYPAD PWM control enabled
KEYP_PWM
EN_KEYP
CC_SW
K1SW
Bit 7
Bit 6
Bit 5
0 – KEYPAD outputs disabled
1 – KEYPAD outputs enabled
0 – Constant current sink mode
1 – Switch mode
0 – KEYPAD1 disabled
1 – KEYPAD1 enabled
Bit 3
Bit 2
0 – KEYPAD2 disabled
1 – KEYPAD2 enabled
K2SW
0 – KEYPAD3 disabled
1 – KEYPAD3 enabled
K3SW
Bit 1
KEYPAD (01H) – KEYPAD BALANCE AND BRIGHTNESS CONTROL REGISTER
D7
D6
D5
D4
D3
D2
D1
D0
BALANCE[2:0]
RW - 0
BRIGHT[2:0]
RW - 0
OVL
R - 0
RW - 0
RW - 0
RW - 0
RW - 0
RW - 0
BALANCE[2:0]
BRIGHT[2:0]
Bits 6-4
PWM balance for KEYPAD outputs
Bits 3-1
PWM brightness control for KEYPAD outputs
0 – Overlapping mode disabled
1 – Overlapping mode enabled
OVL
Bit 0
KEYPAD MAX CURRENT (02H) – MAXIMUM KEYPAD CURRENT CONTROL REGISTER
D7
D6
D5
D4
D3
D2
D1
D0
IK1[1:0]
IK2[1:0]
IK3[1:0]
R - 0
R - 0
RW - 0
RW - 0
RW - 0
RW - 0
RW - 0
RW - 0
Maximum current for KEY1,2,3 driver
IK1,2,3[1:0]
Maximum output current
0.25 × IMAX
00
01
10
11
0.50 × IMAX
0.75 × IMAX
1.00 × IMAX
26
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LP3958
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SNVS423C –JANUARY 2006–REVISED MARCH 2013
WLED CONTROL (03H) – WLED CONTROL REGISTER
D7
D6
D5
D4
D3
D2
D1
D0
SLOPE
RW - 0
FADE_SEL
RW - 0
EN_FADE
RW - 0
DISPL
RW - 0
EN_MAIN
RW - 0
EN_SUB
RW - 0
R - 0
R - 0
0 – fade execution time 0.65 sec (full scale)
1 – fade execution time 1.3 sec (full scale)
SLOPE
Bit 5
0 – fade control for MAIN
1 – fade control for SUB
FADE_SEL
EN_FADE
DISPL
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0 – automatic fade disabled
1 – automatic fade enabled
0 - MAIN and SUB individual control
1 - MAIN and SUB controlled with MAIN DAC
0 – MAIN output disabled
1 – MAIN output enabled
EN_MAIN
EN_SUB
0 – SUB output disabled
1 – SUB output enabled
MAIN CURRENT (04H) – MAIN CURRENT CONTROL REGISTER
D7
D6
D5
D4
D3
D2
D1
D0
MAIN[7:0]
RW - 0
RW - 0
RW - 0
RW - 0
RW - 0
RW - 0
RW - 0
RW - 0
SUB CURRENT (05H) – SUB CURRENT CONTROL REGISTER
D7
D6
D5
D4
D3
D2
D1
D0
SUB[7:0]
RW - 0
RW - 0
RW - 0
RW - 0
RW - 0
RW - 0
RW - 0
RW - 0
MAIN, SUB current adjustment
Typical driver current (mA)
MAIN[7:0], SUB[7:0]
0000 0000
0000 0001
0000 0010
0000 0011
0000 0100
…
0
0.1
0.2
0.3
0.4
…
1111 1101
1111 1110
1111 1111
25.3
25.4
25.5
GPIO CONTROL (06H) – GPIO CONTROL REGISTER
D7
D6
D5
D4
D3
D2
D1
D0
EN_PWM_PIN
RW - 0
OEN[2:0]
RW - 0
R - 0
R - 0
R - 0
R - 0
RW - 0
RW - 0
0 – External PWM pin disabled
1 – External PWM pin enabled
EN_PWM_PIN
OEN[2:0]
Bit 4
0 – GPIO pin set as a input
1 – GPIO pin set as a output
Bits 2-0
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GPIO DATA (07H) – GPIO DATA REGISTER
D7
D6
D5
D4
D3
D2
D1
D0
DATA[2:0]
RW - 0
R - 0
R - 0
R - 0
R - 0
R - 0
RW - 0
RW - 0
DATA[2:0]
Bits 2-0
GPIO data register bits
ENABLES (0BH) – ENABLES REGISTER
D7
D6
D5
D4
D3
D2
D1
D0
NSTBY
EN_BOOST
EN_AUTOLOA
D
R - 0
RW - 0
RW - 0
R - 0
R - 0
RW - 1
R - 0
R - 0
0 – LP3958 standby mode
1 – LP3958 active mode
NSTBY
Bit 6
Bit 5
Bit 2
0 – Boost converter disabled
1 – Boost converter enabled
EN_BOOST
0 – Boost active load disabled
1 – Boost active load enabled
EN_AUTOLOAD
BOOST OUTPUT (0DH) – BOOST OUTPUT VOLTAGE CONTROL REGISTER
D7
D6
D5
D4
D3
D2
D1
D0
BOOST[7:0]
RW - 0
RW - 0
RW - 0
RW - 0
RW - 1
RW - 0
RW - 0
RW - 0
BOOST output voltage adjustment
BOOST[7:0]
0000 1000
0000 1001
0000 1010
0000 1011
0000 1100
0000 1101
0000 1110
0000 1111
0001 0000
0001 0001
0001 0010
Typical boost output voltage (V)
8.00
9.00
10.00
11.00
12.00
13.00
14.00
15.00
16.00
17.00
18.00
PWM ENABLE (2BH) – EXTERNAL PWM CONTROL REGISTER
D7
D6
D5
D4
D3
D2
D1
D0
EN_EXT_K1_P EN_EXT_K2_P EN_EXT_K3_P EN_MAIN_PW EN_SUB_PWM
WM
WM
WM
M
R - 0
R - 0
R - 0
RW - 0
RW - 0
RW - 0
RW - 0
RW - 0
0 – External PWM control for KEY1 disabled
1 – External PWM control for KEY1 enabled
EN_EXT_K1_PWM
EN_EXT_K2_PWM
EN_EXT_K3_PWM
Bit 4
Bit 3
Bit 2
0 – External PWM control for KEY2 disabled
1 – External PWM control for KEY2 enabled
0 – External PWM control for KEY3 disabled
1 – External PWM control for KEY3 enabled
28
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SNVS423C –JANUARY 2006–REVISED MARCH 2013
0 – External PWM control for MAIN disabled
1 – External PWM control for MAIN enabled
EN_EXT_MAIN_PWM
EN_EXT_SUB_PWM
Bit 1
Bit 0
0 – External PWM control for SUB disabled
1 – External PWM control for SUB enabled
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REVISION HISTORY
Changes from Revision B (March 2013) to Revision C
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 28
30
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LP3958TL/NOPB
ACTIVE
DSBGA
YZR
25
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-30 to 85
SJHB
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LP3958TL/NOPB
DSBGA
YZR
25
250
178.0
8.4
2.69
2.69
0.76
4.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
DSBGA YZR 25
SPQ
Length (mm) Width (mm) Height (mm)
208.0 191.0 35.0
LP3958TL/NOPB
250
Pack Materials-Page 2
MECHANICAL DATA
YZR0025xxx
0.600±0.075
D
E
TLA25XXX (Rev D)
D: Max = 2.562 mm, Min =2.502 mm
E: Max = 2.562 mm, Min =2.502 mm
4215055/A
12/12
A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.
B. This drawing is subject to change without notice.
NOTES:
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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