LP3964ESX-3.3 [TI]

3.3V FIXED POSITIVE LDO REGULATOR, 0.35V DROPOUT, PSSO5, TO-263, 5 PIN;


型号：	LP3964ESX-3.3
厂家：	TEXAS INSTRUMENTS
描述：	3.3V FIXED POSITIVE LDO REGULATOR, 0.35V DROPOUT, PSSO5, TO-263, 5 PIN 输出元件调节器
文件：	总32页 (文件大小：2981K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LP3961, LP3964

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SNVS056H –MAY 2000–REVISED APRIL 2013

LP3961/LP3964 800mA Fast Ultra Low Dropout Linear Regulators

Check for Samples: LP3961, LP3964

FEATURES

DESCRIPTION

The LP3961/LP3964 series of fast ultra low-dropout

linear regulators operate from a +2.5V to +7.0V input

supply. Wide range of preset output voltage options

are available. These ultra low dropout linear

regulators respond very fast to step changes in load

which makes them suitable for low voltage

microprocessor applications. The LP3961/LP3964 are

developed on a CMOS process which allows low

quiescent current operation independent of output

load current. This CMOS process also allows the

LP3961/LP3964 to operate under extremely low

dropout conditions.

•

Ultra Low Dropout Voltage

Low Ground Pin Current

Load Regulation of 0.02%

15µA Quiescent Current in Shutdown Mode

Specified Output Current of 0.8A DC

Available in SOT-223, SFM/TO-263 and TO-220

Packages

•

Output Voltage Accuracy ± 1.5%

Error Flag Indicates Output Status (LP3961)

Sense Option Improves Better Load

Regulation (LP3964)

Dropout Voltage: Ultra low dropout voltage; typically

24mV at 80mA load current and 240mV at 800mA

load current.

•

Extremely Low Output Capacitor

Requirements

Ground Pin Current: Typically 4mA at 800mA load

current.

•

Overtemperature/Overcurrent Protection

−40°C to +125°C Junction Temperature Range

Shutdown Mode: Typically 15µA quiescent current

when the shutdown pin is pulled low.

APPLICATIONS

Error Flag:Error flag goes low when the output

voltage drops 10% below nominal value (for LP3961).

•

Microprocessor Power Supplies

GTL, GTL+, BTL, and SSTL Bus Terminators

Power Supplies for DSPs

SCSI Terminator

SENSE: Sense pin improves regulation at remote

loads. (For LP3964)

Precision Output Voltage: Multiple output voltage

options are available ranging from 1.2V to 5.0V and

adjustable (LP3964), with a specified accuracy of

±1.5% at room temperature, and ±3.0% over all

conditions (varying line, load, and temperature).

Post Regulators

High Efficiency Linear Regulators

Battery Chargers

Other Battery Powered Applications

Typical Application Circuits

A. SD and ERROR pins must be pulled high through a 10kΩ pull-up resistor. Connect the ERROR pin to ground if this

function is not used. See Application Hints for more information.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

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*SD and ERROR pins must be pulled high through a 10kΩ pull-up resistor. Connect the ERROR pin to ground if this

function is not used. See Application Hints for more information.

Block Diagram LP3961

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Block Diagram LP3964

Block Diagram LP3964-ADJ

Connection Diagram

Figure 1. Top View

SOT-223-5 Package

Figure 2. Top View

TO-220-5 Package

Bent, Staggered Leads

Figure 3. Top View

SFM/TO-263-5 Package

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Pin Descriptions for SOT-223-5 Package

LP3961

LP3964

Pin #

Name

Function

Name

Function

V_IN

Shutdown

Input Supply

Output Voltage

ERROR Flag

V_IN

Input Supply

V_OUT

ERROR

V_OUT

Output Voltage

SENSE/ADJ

Remote Sense Pin or output

Adjust Pin

GND

Ground

GND

Ground

Pin Descriptions for TO-220-5 and SFM/TO-263-5 Packages

LP3961

LP3964

Pin #

Name

Function

Name

Function

Shutdown

V_IN

Input Supply

Ground

V_IN

Input Supply

Ground

GND

V_OUT

ERROR

GND

Output Voltage

ERROR Flag

V_OUT

Output Voltage

SENSE/ADJ

Remote Sense Pin or output

Adjust Pin

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

(1)(2)

Absolute Maximum Ratings

Storage Temperature Range

−65°C to +150°C

260°C

Lead Temperature (Soldering, 5 sec.)

(3)

ESD Rating

2 kV

(4)

Power Dissipation

Internally Limited

−0.3V to +7.5V

−0.3V to V_IN+0.3V

−0.3V to +7.5V

Short Circuit Protected

V_IN+0.3V

Input Supply Voltage (Survival)

Shutdown Input Voltage (Survival)

(5) (6)

Output Voltage (Survival),

I_OUT(Survival)

Maximum Voltage for ERROR Pin

Maximum Voltage for SENSE Pin

V_OUT+0.3V

(1) Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating ratings indicate conditions for which

the device is intended to be functional, but does not ensure specific performance limits. For ensured specifications and test conditions,

see Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may

degrade when the device is not operated under the listed test conditions.

(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.

(3) The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin.

(4) At elevated temperatures, devices must be derated based on package thermal resistance. The devices in TO-220 package must be

derated at θ_jA= 50°C/W (with 0.5in², 1oz. copper area), junction-to-ambient (with no heat sink). The devices in the SFM/TO-263

surface-mount package must be derated at θ_jA= 60°C/W (with 0.5in², 1oz. copper area), junction-to-ambient. The devices in SOT-223

package must be derated at θ_jA= 90°C/W (with 0.5in², 1oz. copper area), junction-to-ambient.

(5) If used in a dual-supply system where the regulator load is returned to a negative supply, the LP396X output must be diode-clamped to

ground.

(6) The output PMOS structure contains a diode between the V_INand V_OUTterminals. This diode is normally reverse biased. This diode will

get forward biased if the voltage at the output terminal is forced to be higher than the voltage at the input terminal. This diode can

typically withstand 200mA of DC current and 1Amp of peak current.

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Operating Ratings

Input Supply Voltage (Operating),

(1)

2.5V to 7.0V

−0.3V to V_IN+0.3V

0.8A

Shutdown Input Voltage (Operating)

Maximum Operating Current (DC)

Operating Junction Temp. Range

−40°C to +125°C

(1) The minimum operating value for V_INis equal to either [V_OUT(NOM)+ V_DROPOUT] or 2.5V, whichever is greater.

Electrical Characteristics

LP3961/LP3964

Limits in standard typeface are for T_J= 25°C, and limits in boldface type apply over the full operating temperature range.

Unless otherwise specified: V_IN= V_O(NOM)+ 1V, I_L= 10 mA, C_OUT= 33µF, V_SD= V_IN-0.3V.

(1)

(2)

Symbol

Parameter

Conditions

Typ

LP3961/4

Min

Units

Max

V_O

Output Voltage Tolerance⁽³⁾

10 mA ≤ I_L≤ 800mA

V_OUT+1 ≤ V_IN≤ 7.0V

-1.5

-3.0

+1.5

+3.0

V_ADJ

Adjust Pin Voltage (ADJ version) 10 mA ≤ I_L≤ 800mA

V_OUT+1.5V ≤ V_IN≤ 7.0V

1.198

1.180

1.234

1.253

1.216

ΔV _OL

Output Voltage Line Regulation

V_OUT+1V<V_IN<7.0V

0.02

0.06

(3)

ΔV_O/ ΔI_OUT

V_IN- V_OUT

Output Voltage Load Regulation 10 mA < I_L< 800 mA

0.02

0.08

(3)

I_L= 80 mA

240

Dropout Voltage⁽⁴⁾

I_L= 800 mA

300

350

I_L= 80 mA

Ground Pin Current In Normal

Operation Mode

I_GND

I_L= 800 mA

I_GND

Ground Pin Current In Shutdown

Mode⁽⁵⁾

_SD≤ 0.2V

1.5

µA

(6)

I_O(PK)

Peak Output Current

See

1.2

1.1

SHORT CIRCUIT PROTECTION

I_SCShort Circuit Current

OVER TEMPERATURE PROTECTION

2.8

Tsh(t)

Shutdown Threshold

165

°C

Tsh(h)

Thermal Shutdown Hysteresis

SHUTDOWN INPUT

Output = High

Output = Low

I_L= 800 mA

V_IN

V_IN–0.3

V_SDT

Shutdown Threshold

Turn-off delay

0.2

T_dOFF

µs

(1) Typical numbers are at 25°C and represent the most likely parametric norm.

(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation using

Statistical Quality Control (SQC) methods. The limits are used to calculate TI's Average Outgoing Quality Level (AOQL).

(3) Output voltage line regulation is defined as the change in output voltage from the nominal value due to change in the input line voltage.

Output voltage load regulation is defined as the change in output voltage from the nominal value due to change in load current. The line

and load regulation specification contains only the typical number. However, the limits for line and load regulation are included in the

output voltage tolerance specification.

(4) Dropout voltage is defined as the minimum input to output differential voltage at which the output drops 2% below the nominal value.

Dropout voltage specification applies only to output voltages of 2.5V and above. For output voltages below 2.5V, the drop-out voltage is

nothing but the input to output differential, since the minimum input voltage is 2.5V.

(5) This specification has been tested for −40°C ≤ T_J≤ 85°C since the temperature rise of the device is negligible under shutdown

conditions.

(6) At elevated temperatures, devices must be derated based on package thermal resistance. The devices in TO-220 package must be

derated at θ_jA= 50°C/W (with 0.5in², 1oz. copper area), junction-to-ambient (with no heat sink). The devices in the SFM/TO-263

surface-mount package must be derated at θ_jA= 60°C/W (with 0.5in², 1oz. copper area), junction-to-ambient. The devices in SOT-223

package must be derated at θ_jA= 90°C/W (with 0.5in², 1oz. copper area), junction-to-ambient.

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Electrical Characteristics

LP3961/LP3964 (continued)

Limits in standard typeface are for T_J= 25°C, and limits in boldface type apply over the full operating temperature range.

Unless otherwise specified: V_IN= V_O(NOM)+ 1V, I_L= 10 mA, C_OUT= 33µF, V_SD= V_IN-0.3V.

(1)

(2)

Symbol

Parameter

Conditions

Typ

LP3961/4

Min

Units

Max

T_dON

I_SD

ERROR FLAG COMPARATOR

Turn-on delay

I_L= 800 mA

V_SD= V_IN

µs

SD Input Current

(7)

V_T

V_TH

V_EF(Sat)

Threshold

See

(7)

Threshold Hysteresis

Error Flag Saturation

Flag Reset Delay

See

I_sink= 100µA

0.02

0.1

µs

I_lk

Error Flag Pin Leakage Current

Error Flag Pin Sink Current

I_max

V_Error= 0.5V (over temp.)

AC PARAMETERS

V_IN= V_OUT+ 1.5V

C_OUT= 100uF

V_OUT= 3.3V

PSRR

Ripple Rejection

V_IN= V_OUT+ 0.3V

C_OUT= 100uF

V_OUT= 3.3V

ρ_n(l/f

Output Noise Density

f = 120Hz

0.8

150

100

µV

BW = 10Hz – 100kHz

BW = 300Hz – 300kHz

e_n

Output Noise Voltage (rms)

µV (rms)

(7) Error Flag threshold and hysteresis are specified as percentage of regulated output voltage.

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Typical Performance Characteristics

Unless otherwise specified, V_IN=V_O(NOM)+ 1V, V_OUT= 2.5V, C_OUT= 33µF, I_OUT= 10mA, C_IN= 68µF, V_SD= V_IN, and T_A= 25°C.

Drop-Out Voltage

Temperature for Different Load Currents

Temperature for Different Output Voltages (I_OUT= 800mA)

Figure 4.

Figure 5.

Ground Pin Current

Input Voltage (V_SD=V_IN

Ground Pin Current

Input Voltage (V_SD=100mV)

)

Figure 6.

Figure 7.

Ground Current

Temperature (V_SD=V_IN

Ground Current

Temperature (V_SD=0V

)

Figure 8.

Figure 9.

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Typical Performance Characteristics (continued)

Unless otherwise specified, V_IN=V_O(NOM)+ 1V, V_OUT= 2.5V, C_OUT= 33µF, I_OUT= 10mA, C_IN= 68µF, V_SD= V_IN, and T_A= 25°C.

Ground Pin Current

Input Voltage

Shutdown Pin Voltage

Output Voltage

Figure 10.

Figure 11.

Output Noise Density, V_OUT= 2.5V

Output Noise Density, V_OUT= 5V

Figure 12.

Figure 13.

Ripple Rejection

Load Transient Response

Frequency

Figure 14.

Figure 15.

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Typical Performance Characteristics (continued)

Unless otherwise specified, V_IN=V_O(NOM)+ 1V, V_OUT= 2.5V, C_OUT= 33µF, I_OUT= 10mA, C_IN= 68µF, V_SD= V_IN, and T_A= 25°C.

δV_OUT

Temperature

Noise Density V_IN= 3.5V, V_OUT= 2.5V, I_L= 10 mA

Figure 16.

Figure 17.

Line Transient Response

Figure 18.

Figure 19.

Line Transient Response (I_OUT= 800mA)

Figure 20.

Figure 21.

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APPLICATION HINTS

EXTERNAL CAPACITORS

Like any low-dropout regulator, external capacitors are required to assure stability. these capacitors must be

correctly selected for proper performance.

INPUT CAPACITOR: The LP3961/4 requires a low source impedance to maintain regulator stability because the

internal bias circuitry is connected directly to V_IN. The input capacitor must be located less than 1 cm from the

LP3961/4 device and connected directly to the input and ground pins using traces which have no other currents

flowing through them (see PCB Layout).

The minimum allowable input capacitance for a given application depends on the type of the capacitor and ESR

(equivalent series resistance). A lower ESR capacitor allows the use of less capacitance, while higher ESR types

(like aluminum electrolytics) require more capacitance.

The lowest value of input capacitance that can be used for stable full-load operation is 68 µF (assuming it is a

ceramic or low-ESR Tantalum with ESR less than 100 mΩ).

To determine the minimum input capacitance amount and ESR value, an approximation which should be used is:

C_INESR (mΩ) / C_IN(µF) ≤ 1.5

This shows that input capacitors with higher ESR values can be used if sufficient total capacitance is provided.

Capacitor types (aluminum, ceramic, and tantalum) can be mixed in parallel, but the total equivalent input

capacitance/ESR must be defined as above to assure stable operation.

IMPORTANT: The input capacitor must maintain its ESR and capacitance in the "stable range" over the entire

temperature range of the application to assure stability (see Capacitor Characteristics).

OUTPUT CAPACITOR: An output capacitor is also required for loop stability. It must be located less than 1 cm

from the LP3961/4 device and connected directly to the output and ground pins using traces which have no other

currents flowing through them (see PCB Layout).

The minimum value of the output capacitance that can be used for stable full-load operation is 33 µF, but it may

be increased without limit. The output capacitor's ESR is critical because it forms a zero to provide phase lead

which is required for loop stability. The ESR must fall within the specified range:

0.2Ω ≤ C_OUTESR ≤ 5Ω

The lower limit of 200 mΩ means that ceramic capacitors are not suitable for use as LP3961/4 output capacitors

(but can be used on the input). Some ceramic capacitance can be used on the output if the total equivalent ESR

is in the stable range: when using a 100 µF Tantalum as the output capacitor, approximately 3 µF of ceramic

capacitance can be applied before stability becomes marginal.

IMPORTANT: The output capacitor must meet the requirements for minimum amount of capacitance and also

have an appropriate ESR value over the full temperature range of the application to assure stability (see

Capacitor Characteristics).

SELECTING A CAPACITOR

It is important to note that capacitance tolerance and variation with temperature must be taken into consideration

when selecting a capacitor so that the minimum required amount of capacitance is provided over the full

operating temperature range. In general, a good Tantalum capacitor will show very little capacitance variation

with temperature, but a ceramic may not be as good (depending on dielectric type). Aluminum electrolytics also

typically have large temperature variation of capacitance value.

Equally important to consider is a capacitor's ESR change with temperature: this is not an issue with ceramics,

as their ESR is extremely low. However, it is very important in Tantalum and aluminum electrolytic capacitors.

Both show increasing ESR at colder temperatures, but the increase in aluminum electrolytic capacitors is so

severe they may not be feasible for some applications (see Capacitor Characteristics).

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CAPACITOR CHARACTERISTICS

CERAMIC: For values of capacitance in the 10 to 100 µF range, ceramics are usually larger and more costly

than tantalums but give superior AC performance for bypassing high frequency noise because of very low ESR

(typically less than 10 mΩ). However, some dielectric types do not have good capacitance characteristics as a

function of voltage and temperature.

Z5U and Y5V dielectric ceramics have capacitance that drops severely with applied voltage. A typical Z5U or

Y5V capacitor can lose 60% of its rated capacitance with half of the rated voltage applied to it. The Z5U and Y5V

also exhibit a severe temperature effect, losing more than 50% of nominal capacitance at high and low limits of

the temperature range.

X7R and X5R dielectric ceramic capacitors are strongly recommended if ceramics are used, as they typically

maintain a capacitance range within ±20% of nominal over full operating ratings of temperature and voltage. Of

course, they are typically larger and more costly than Z5U/Y5U types for a given voltage and capacitance.

TANTALUM: Solid Tantalum capacitors are recommended for use on the output because their typical ESR is

very close to the ideal value required for loop compensation. They also work well as input capacitors if selected

to meet the ESR requirements previously listed.

Tantalums also have good temperature stability: a good quality Tantalum will typically show a capacitance value

that varies less than 10-15% across the full temperature range of 125°C to −40°C. ESR will vary only about 2X

going from the high to low temperature limits.

The increasing ESR at lower temperatures can cause oscillations when marginal quality capacitors are used (if

the ESR of the capacitor is near the upper limit of the stability range at room temperature).

ALUMINUM: This capacitor type offers the most capacitance for the money. The disadvantages are that they are

larger in physical size, not widely available in surface mount, and have poor AC performance (especially at

higher frequencies) due to higher ESR and ESL.

Compared by size, the ESR of an aluminum electrolytic is higher than either Tantalum or ceramic, and it also

varies greatly with temperature. A typical aluminum electrolytic can exhibit an ESR increase of as much as 50X

when going from 25°C down to −40°C.

It should also be noted that many aluminum electrolytics only specify impedance at a frequency of 120 Hz, which

indicates they have poor high frequency performance. Only aluminum electrolytics that have an impedance

specified at a higher frequency (between 20 kHz and 100 kHz) should be used for the LP396X. Derating must be

applied to the manufacturer's ESR specification, since it is typically only valid at room temperature.

Any applications using aluminum electrolytics should be thoroughly tested at the lowest ambient operating

temperature where ESR is maximum.

PCB LAYOUT

Good PC layout practices must be used or instability can be induced because of ground loops and voltage drops.

The input and output capacitors must be directly connected to the input, output, and ground pins of the LP3961/4

using traces which do not have other currents flowing in them Kelvin connect).

The best way to do this is to lay out C_INand C_OUTnear the device with short traces to the V_IN, V_OUT, and ground

pins. The regulator ground pin should be connected to the external circuit ground so that the regulator and its

capacitors have a "single point ground".

It should be noted that stability problems have been seen in applications where "vias" to an internal ground plane

were used at the ground points of the LP3961/4 IC and the input and output capacitors. This was caused by

varying ground potentials at these nodes resulting from current flowing through the ground plane. Using a single

point ground technique for the regulator and its capacitors fixed the problem.

Since high current flows through the traces going into V_INand coming from V_OUT, Kelvin connect the capacitor

leads to these pins so there is no voltage drop in series with the input and output capacitors.

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RFI/EMI SUSCEPTIBILITY

RFI (radio frequency interference) and EMI (electromagnetic interference) can degrade any integrated circuit's

performance because of the small dimensions of the geometries inside the device. In applications where circuit

sources are present which generate signals with significant high frequency energy content (> 1 MHz), care must

be taken to ensure that this does not affect the IC regulator.

If RFI/EMI noise is present on the input side of the LP396X regulator (such as applications where the input

source comes from the output of a switching regulator), good ceramic bypass capacitors must be used at the

input pin of the LP396X.

If a load is connected to the LP396X output which switches at high speed (such as a clock), the high-frequency

current pulses required by the load must be supplied by the capacitors on the LP396X output. Since the

bandwidth of the regulator loop is less than 100 kHz, the control circuitry cannot respond to load changes above

that frequency. The means the effective output impedance of the LP396X at frequencies above 100 kHz is

determined only by the output capacitor(s).

In applications where the load is switching at high speed, the output of the LP396X may need RF isolation from

the load. It is recommended that some inductance be placed between the LP396X output capacitor and the load,

and good RF bypass capacitors be placed directly across the load.

PCB layout is also critical in high noise environments, since RFI/EMI is easily radiated directly into PC traces.

Noisy circuitry should be isolated from "clean" circuits where possible, and grounded through a separate path. At

MHz frequencies, ground planes begin to look inductive and RFI/EMI can cause ground bounce across the

ground plane.

In multi-layer PCB applications, care should be taken in layout so that noisy power and ground planes do not

radiate directly into adjacent layers which carry analog power and ground.

OUTPUT ADJUSTMENT

An adjustable output device has output voltage range of 1.216V to 5.1V. To obtain a desired output voltage, the

following equation can be used with R1 always a 10kΩ resistor.

For output stability, C_Fmust be between 68pF and 100pF.

TURN-ON CHARACTERISTICS FOR OUTPUT VOLTAGES PROGRAMMED TO 2.0V OR BELOW

As Vin increases during start-up, the regulator output will track the input until Vin reaches the minimum operating

voltage (typically about 2.2V). For output voltages programmed to 2.0V or below, the regulator output may

momentarily exceed its programmed output voltage during start up. Outputs programmed to voltages above 2.0V

are not affected by this behavior.

OUTPUT NOISE

Noise is specified in two ways-

Spot Noise or Output noise density is the RMS sum of all noise sources, measured at the regulator output, at

a specific frequency (measured with a 1Hz bandwidth). This type of noise is usually plotted on a curve as a

function of frequency.

Total output Noise or Broad-band noise is the RMS sum of spot noise over a specified bandwidth, usually

several decades of frequencies.

Attention should be paid to the units of measurement. Spot noise is measured in units µV/√Hz or nV/√Hz and

total output noise is measured in µV(rms).

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The primary source of noise in low-dropout regulators is the internal reference. In CMOS regulators, noise has a

low frequency component and a high frequency component, which depend strongly on the silicon area and

quiescent current. Noise can be reduced in two ways: by increasing the transistor area or by increasing the

current drawn by the internal reference. Increasing the area will decrease the chance of fitting the die into a

smaller package. Increasing the current drawn by the internal reference increases the total supply current

(ground pin current). Using an optimized trade-off of ground pin current and die size, LP3961/LP3964 achieves

low noise performance and low quiescent current operation.

The total output noise specification for LP3961/LP3964 is presented in the Electrical Characteristics table. The

Output noise density at different frequencies is represented by a curve under typical performance characteristics.

SHORT-CIRCUIT PROTECTION

The LP3961and LP3964 is short circuit protected and in the event of a peak over-current condition, the short-

circuit control loop will rapidly drive the output PMOS pass element off. Once the power pass element shuts

down, the control loop will rapidly cycle the output on and off until the average power dissipation causes the

thermal shutdown circuit to respond to servo the on/off cycling to a lower frequency. Please refer to the section

on thermal information for power dissipation calculations.

ERROR FLAG OPERATION

The LP3961/LP3964 produces a logic low signal at the Error Flag pin when the output drops out of regulation

due to low input voltage, current limiting, or thermal limiting. This flag has a built in hysteresis. The timing

diagram in Figure 22 shows the relationship between the ERROR and the output voltage. In this example, the

input voltage is changed to demonstrate the functionality of the Error Flag.

The internal Error flag comparator has an open drain output stage. Hence, the ERROR pin should be pulled high

through a pull up resistor. Although the ERROR pin can sink current of 1mA, this current is energy drain from the

input supply. Hence, the value of the pull up resistor should be in the range of 100kΩ to 1MΩ. The ERROR pin

must be connected to ground if this function is not used. It should also be noted that when the shutdown pin

is pulled low, the ERROR pin is forced to be invalid for reasons of saving power in shutdown mode.

Figure 22. Error Flag Operation

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SNVS056H –MAY 2000–REVISED APRIL 2013

www.ti.com

SENSE PIN

In applications where the regulator output is not very close to the load, LP3964 can provide better remote load

regulation using the SENSE pin. Figure 23 depicts the advantage of the SENSE option. LP3961 regulates the

voltage at the output pin. Hence, the voltage at the remote load will be the regulator output voltage minus the

drop across the trace resistance. For example, in the case of a 3.3V output, if the trace resistance is 100mΩ, the

voltage at the remote load will be 3.22V with 800mAmps of load current, I_LOAD. The LP3964 regulates the voltage

at the sense pin. Connecting the sense pin to the remote load will provide regulation at the remote load, as

shown in Figure 23. If the sense option pin is not required, the sense pin must be connected to the V_OUTpin.

Figure 23. Improving remote load regulation using LP3964

SHUTDOWN OPERATION

A CMOS Logic level signal at the shutdown ( SD) pin will turn-off the regulator. Pin SD must be actively

terminated through a 10kΩ pull-up resistor for a proper operation. If this pin is driven from a source that actively

pulls high and low (such as a CMOS rail to rail comparator), the pull-up resistor is not required. This pin must be

tied to Vin if not used.

DROPOUT VOLTAGE

The dropout voltage of a regulator is defined as the minimum input-to-output differential required to stay within

2% of the output voltage. The LP3961/LP3964 use an internal MOSFET with an Rds(on) of 240mΩ (typically).

For CMOS LDOs, the dropout voltage is the product of the load current and the Rds(on) of the internal MOSFET.

REVERSE CURRENT PATH

The internal MOSFET in LP3961and LP3964 has an inherent parasitic diode. During normal operation, the input

voltage is higher than the output voltage and the parasitic diode is reverse biased. However, if the output is

pulled above the input in an application, then current flows from the output to the input as the parasitic diode gets

forward biased. The output can be pulled above the input as long as the current in the parasitic diode is limited to

200mA continuous and 1A peak.

MAXIMUM OUTPUT CURRENT CAPABILITY

LP3961 and LP3964 can deliver a continuous current of 800mA over the full operating temperature range. A

heatsink may be required depending on the maximum power dissipation and maximum ambient temperature of

the application. Under all possible conditions, the junction temperature must be within the range specified under

operating conditions. The total power dissipation of the device is given by:

P_D= (V_IN−V_OUT)I_OUT+ (V_IN)I_GND

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LP3961, LP3964

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SNVS056H –MAY 2000–REVISED APRIL 2013

where I_GNDis the operating ground current of the device (specified under Electrical Characteristics).

The maximum allowable temperature rise (T_Rmax) depends on the maximum ambient temperature (T_Amax) of the

application, and the maximum allowable junction temperature(T_Jmax):

T_Rmax= T_Jmax− T_Amax

The maximum allowable value for junction to ambient Thermal Resistance, θ_JA, can be calculated using the

formula:

θ_JA= T_Rmax/ P_D

LP3961 and LP3964 are available in TO-220, SFM/TO-263, and SOT-223 packages. The thermal resistance

depends on amount of copper area or heat sink, and on air flow. If the maximum allowable value of θ_JA

calculated above is ≥ 60 °C/W for TO-220 package, ≥60 °C/W for SFM/TO-263 package, and ≥ 140 °C/W for

SOT-223 package, no heatsink is needed since the package can dissipate enough heat to satisfy these

requirements. If the value for allowable θ_JAfalls below these limits, a heat sink is required.

HEATSINKING TO-220 PACKAGES

The thermal resistance of a TO-220 package can be reduced by attaching it to a heat sink or a copper plane on

a PC board. If a copper plane is to be used, the values of θ_JAwill be same as shown in next section for SFM/TO-

263 package.

The heatsink to be used in the application should have a heatsink to ambient thermal resistance,

θ_HA≤ θ_JA− θ_CH− θ_JC.

In this equation, θ_CHis the thermal resistance from the junction to the surface of the heat sink and θ_JCis the

thermal resistance from the junction to the surface of the case. θ_JCis about 3°C/W for a TO-220 package. The

value for θ_CHdepends on method of attachment, insulator, etc. θ_CHvaries between 1.5°C/W to 2.5°C/W. If the

exact value is unknown, 2°C/W can be assumed.

HEATSINKING SFM/TO-263 AND SOT-223 PACKAGES

The SFM/TO-263 and SOT-223 packages use the copper plane on the PCB as a heatsink. The tab of these

packages are soldered to the copper plane for heat sinking. Figure 24 shows a curve for the θ_JAof SFM/TO-263

package for different copper area sizes, using a typical PCB with 1 ounce copper and no solder mask over the

copper area for heat sinking.

Figure 24. θ_JAvs Copper(1 Ounce) Area for SFM/TO-263 package

As shown in Figure 24, increasing the copper area beyond 1 square inch produces very little improvement. The

minimum value for θ_JAfor the SFM/TO-263 packag mounted to a PCB is 32°C/W.

Figure 25 shows the maximum allowable power dissipation for SFM/TO-263 packages for different ambient

temperatures, assuming θ_JAis 35°C/W and the maximum junction temperature is 125°C.

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LP3961, LP3964

SNVS056H –MAY 2000–REVISED APRIL 2013

www.ti.com

Figure 25. Maximum power dissipation vs ambient temperature for SFM/TO-263 package

Figure 26 shows a curve for the θ_JAof SOT-223 package for different copper area sizes, using a typical PCB with

1 ounce copper and no solder mask over the copper area for heat sinking.

Figure 26. θ_JAvs Copper(1 Ounce) Area for SOT-223 package

The following figures show different layout scenarios for SOT-223 package.

Figure 27. SCENARIO A, θ_JA= 148°C/W

Figure 28. SCENARIO B, θ_JA= 125°C/W

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SNVS056H –MAY 2000–REVISED APRIL 2013

Figure 29. SCENARIO C, θ_JA= 92°C/W

Figure 30. SCENARIO D, θ_JA= 83°C/W

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LP3961, LP3964

SNVS056H –MAY 2000–REVISED APRIL 2013

www.ti.com

Figure 31. SCENARIO E, θ_JA= 77°C/W

Figure 32. SCENARIO F, θ_JA= 75°C/W

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LP3961, LP3964

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SNVS056H –MAY 2000–REVISED APRIL 2013

Figure 33. SCENARIO G, θ_JA= 113°C/W

Figure 34. SCENARIO H, θ_JA= 79°C/W

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LP3961, LP3964

SNVS056H –MAY 2000–REVISED APRIL 2013

www.ti.com

Figure 35. SCENARIO I, θ_JA= 78.5°C/W

Submit Documentation Feedback

Product Folder Links: LP3961 LP3964

LP3961, LP3964

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SNVS056H –MAY 2000–REVISED APRIL 2013

REVISION HISTORY

Changes from Revision G (April 2013) to Revision H

Page

•

Changed layout of National Data Sheet to TI format .......................................................................................................... 20

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Product Folder Links: LP3961 LP3964

PACKAGE OPTION ADDENDUM

www.ti.com

1-Nov-2013

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(6)

(3)

(4/5)

LP3961EMP-1.8/NOPB

ACTIVE

SOT-223

NDC

1000

Green (RoHS

& no Sb/Br)

CU SN

Level-1-260C-UNLIM

-40 to 125

LBAB

LP3961EMP-2.5

NRND

SOT-223

NDC

1000

TBD

Call TI

CU SN

Call TI

-40 to 125

LBBB

LP3961EMP-2.5/NOPB

ACTIVE

Green (RoHS

& no Sb/Br)

Level-1-260C-UNLIM

LP3961EMP-3.3

NRND

SOT-223

NDC

1000

TBD

Call TI

CU SN

Call TI

-40 to 125

LAZB

LP3961EMP-3.3/NOPB

ACTIVE

Green (RoHS

& no Sb/Br)

Level-1-260C-UNLIM

LP3961EMP-5.0

NRND

SOT-223

NDC

1000

TBD

Call TI

CU SN

Call TI

-40 to 125

LBSB

LP3961EMP-5.0/NOPB

ACTIVE

Green (RoHS

& no Sb/Br)

Level-1-260C-UNLIM

LP3961EMPX-1.8/NOPB

ACTIVE

SOT-223

NDC

2000

Green (RoHS

& no Sb/Br)

CU SN

Level-1-260C-UNLIM

-40 to 125

LBAB

LP3961EMPX-2.5

NRND

SOT-223

NDC

2000

TBD

Call TI

CU SN

Call TI

-40 to 125

LBBB

LP3961EMPX-2.5/NOPB

ACTIVE

Green (RoHS

& no Sb/Br)

Level-1-260C-UNLIM

LP3961EMPX-3.3

NRND

SOT-223

NDC

2000

TBD

Call TI

CU SN

Call TI

-40 to 125

LAZB

LP3961EMPX-3.3/NOPB

ACTIVE

Green (RoHS

& no Sb/Br)

Level-1-260C-UNLIM

LP3961ES-1.8

LP3961ES-1.8/NOPB

LP3961ES-2.5

NRND

ACTIVE

NRND

DDPAK/

TO-263

KTT

TBD

Call TI

CU SN

Call TI

CU SN

Call TI

CU SN

Call TI

-40 to 125

LP3961ES

-1.8

DDPAK/

TO-263

Pb-Free (RoHS

Exempt)

Level-3-245C-168 HR

Call TI

LP3961ES

-1.8

DDPAK/

TO-263

TBD

LP3961ES

-2.5

LP3961ES-2.5/NOPB

LP3961ES-3.3

ACTIVE

NRND

DDPAK/

TO-263

Pb-Free (RoHS

Exempt)

Level-3-245C-168 HR

Call TI

LP3961ES

-2.5

DDPAK/

TO-263

TBD

LP3961ES

-3.3

LP3961ES-3.3/NOPB

LP3961ESX-2.5/NOPB

ACTIVE

DDPAK/

TO-263

Pb-Free (RoHS

Exempt)

Level-3-245C-168 HR

LP3961ES

-3.3

DDPAK/

TO-263

500

Pb-Free (RoHS

Exempt)

LP3961ES

-2.5

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

1-Nov-2013

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(6)

(3)

(4/5)

LP3961ESX-3.3/NOPB

ACTIVE

DDPAK/

TO-263

KTT

500

Pb-Free (RoHS

Exempt)

CU SN

Level-3-245C-168 HR

-40 to 125

LP3961ES

-3.3

LP3964EMP-1.8

NRND

SOT-223

NDC

1000

TBD

Call TI

CU SN

Call TI

-40 to 125

LBFB

LP3964EMP-1.8/NOPB

ACTIVE

Green (RoHS

& no Sb/Br)

Level-1-260C-UNLIM

LP3964EMP-2.5

NRND

SOT-223

NDC

1000

TBD

Call TI

CU SN

Call TI

-40 to 125

LBHB

LP3964EMP-2.5/NOPB

ACTIVE

Green (RoHS

& no Sb/Br)

Level-1-260C-UNLIM

LP3964EMP-3.3

NRND

SOT-223

NDC

1000

TBD

Call TI

CU SN

Call TI

-40 to 125

LBJB

LP3964EMP-3.3/NOPB

ACTIVE

Green (RoHS

& no Sb/Br)

Level-1-260C-UNLIM

LP3964EMP-ADJ

NRND

SOT-223

NDC

1000

TBD

Call TI

CU SN

Call TI

-40 to 125

LBPB

LP3964EMP-ADJ/NOPB

ACTIVE

Green (RoHS

& no Sb/Br)

Level-1-260C-UNLIM

LP3964EMPX-2.5/NOPB

ACTIVE

SOT-223

NDC

2000

Green (RoHS

& no Sb/Br)

CU SN

Level-1-260C-UNLIM

-40 to 125

LBHB

LP3964EMPX-ADJ

NRND

SOT-223

NDC

2000

TBD

Call TI

CU SN

Call TI

-40 to 125

LBPB

LP3964EMPX-ADJ/NOPB

ACTIVE

Green (RoHS

& no Sb/Br)

Level-1-260C-UNLIM

LP3964ES-1.8

LP3964ES-1.8/NOPB

LP3964ES-2.5

NRND

ACTIVE

NRND

DDPAK/

TO-263

KTT

TBD

Call TI

CU SN

Call TI

CU SN

Call TI

CU SN

Call TI

CU SN

Call TI

Level-3-245C-168 HR

Call TI

-40 to 125

LP3964ES

-1.8

DDPAK/

TO-263

Pb-Free (RoHS

Exempt)

LP3964ES

-1.8

DDPAK/

TO-263

TBD

LP3964ES

-2.5

LP3964ES-2.5/NOPB

LP3964ES-3.3

ACTIVE

NRND

DDPAK/

TO-263

Pb-Free (RoHS

Exempt)

Level-3-245C-168 HR

Call TI

LP3964ES

-2.5

DDPAK/

TO-263

TBD

LP3964ES

-3.3

LP3964ES-3.3/NOPB

LP3964ES-ADJ

ACTIVE

NRND

DDPAK/

TO-263

Pb-Free (RoHS

Exempt)

Level-3-245C-168 HR

Call TI

LP3964ES

-3.3

DDPAK/

TO-263

TBD

LP3964ES

-ADJ

LP3964ES-ADJ/NOPB

ACTIVE

DDPAK/

TO-263

Pb-Free (RoHS

Exempt)

Level-3-245C-168 HR

LP3964ES

-ADJ

Addendum-Page 2

PACKAGE OPTION ADDENDUM

www.ti.com

1-Nov-2013

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

-40 to 125

Device Marking

Samples

Drawing

Qty

(1)

(2)

(6)

(3)

(4/5)

LP3964ESX-2.5/NOPB

LP3964ESX-3.3

ACTIVE

DDPAK/

TO-263

KTT

500

Pb-Free (RoHS

Exempt)

CU SN

Call TI

CU SN

Level-3-245C-168 HR

LP3964ES

-2.5

NRND

ACTIVE

DDPAK/

TO-263

KTT

NDH

500

TBD

Call TI

LP3964ES

-3.3

LP3964ESX-3.3/NOPB

LP3964ESX-ADJ/NOPB

LP3964ET-ADJ/NOPB

DDPAK/

TO-263

Pb-Free (RoHS

Exempt)

Level-3-245C-168 HR

Level-1-NA-UNLIM

LP3964ES

-3.3

DDPAK/

TO-263

Pb-Free (RoHS

Exempt)

LP3964ES

-ADJ

TO-220

Green (RoHS

& no Sb/Br)

LP3964ET

-ADJ

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

⁽⁶⁾Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Addendum-Page 3

PACKAGE OPTION ADDENDUM

www.ti.com

1-Nov-2013

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 4

PACKAGE MATERIALS INFORMATION

www.ti.com

23-Sep-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

LP3961EMP-1.8/NOPB SOT-223 NDC

LP3961EMP-2.5 SOT-223 NDC

LP3961EMP-2.5/NOPB SOT-223 NDC

LP3961EMP-3.3 SOT-223 NDC

LP3961EMP-3.3/NOPB SOT-223 NDC

LP3961EMP-5.0 SOT-223 NDC

1000

2000

500

330.0

16.4

24.4

7.0

7.5

2.2

5.0

12.0

16.0

24.0

LP3961EMP-5.0/NOPB SOT-223 NDC

LP3961EMPX-1.8/NOPB SOT-223 NDC

LP3961EMPX-2.5

LP3961EMPX-2.5/NOPB SOT-223 NDC

LP3961EMPX-3.3 SOT-223 NDC

LP3961EMPX-3.3/NOPB SOT-223 NDC

SOT-223 NDC

LP3961ESX-2.5/NOPB DDPAK/

TO-263

KTT

10.75 14.85

LP3961ESX-3.3/NOPB DDPAK/

TO-263

KTT

500

330.0

24.4

10.75 14.85

5.0

16.0

24.0

LP3964EMP-1.8

LP3964EMP-1.8/NOPB SOT-223 NDC

LP3964EMP-2.5 SOT-223 NDC

SOT-223 NDC

1000

330.0

16.4

7.0

7.5

2.2

12.0

16.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

23-Sep-2013

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

LP3964EMP-2.5/NOPB SOT-223 NDC

LP3964EMP-3.3 SOT-223 NDC

LP3964EMP-3.3/NOPB SOT-223 NDC

LP3964EMP-ADJ SOT-223 NDC

1000

2000

500

330.0

16.4

24.4

7.0

7.5

2.2

5.0

12.0

16.0

24.0

LP3964EMP-ADJ/NOPB SOT-223 NDC

LP3964EMPX-2.5/NOPB SOT-223 NDC

LP3964EMPX-ADJ

SOT-223 NDC

LP3964EMPX-ADJ/NOPB SOT-223 NDC

LP3964ESX-2.5/NOPB DDPAK/

TO-263

KTT

10.75 14.85

LP3964ESX-3.3

DDPAK/

TO-263

500

330.0

24.4

5.0

16.0

24.0

LP3964ESX-3.3/NOPB DDPAK/

TO-263

LP3964ESX-ADJ/NOPB DDPAK/

TO-263

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

LP3961EMP-1.8/NOPB

LP3961EMP-2.5

SOT-223

NDC

1000

367.0

35.0

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

23-Sep-2013

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

LP3961EMP-2.5/NOPB

LP3961EMP-3.3

SOT-223

NDC

KTT

1000

2000

500

367.0

35.0

45.0

35.0

45.0

LP3961EMP-3.3/NOPB

LP3961EMP-5.0

SOT-223

LP3961EMP-5.0/NOPB

LP3961EMPX-1.8/NOPB

LP3961EMPX-2.5

SOT-223

LP3961EMPX-2.5/NOPB

LP3961EMPX-3.3

SOT-223

LP3961EMPX-3.3/NOPB

LP3961ESX-2.5/NOPB

LP3961ESX-3.3/NOPB

LP3964EMP-1.8

SOT-223

DDPAK/TO-263

SOT-223

KTT

500

NDC

KTT

1000

2000

500

LP3964EMP-1.8/NOPB

LP3964EMP-2.5

SOT-223

LP3964EMP-2.5/NOPB

LP3964EMP-3.3

SOT-223

LP3964EMP-3.3/NOPB

LP3964EMP-ADJ

SOT-223

LP3964EMP-ADJ/NOPB

LP3964EMPX-2.5/NOPB

LP3964EMPX-ADJ

SOT-223

LP3964EMPX-ADJ/NOPB

LP3964ESX-2.5/NOPB

LP3964ESX-3.3

SOT-223

DDPAK/TO-263

KTT

500

LP3964ESX-3.3/NOPB

LP3964ESX-ADJ/NOPB

KTT

500

KTT

500

Pack Materials-Page 3

MECHANICAL DATA

NDH0005D

www.ti.com

MECHANICAL DATA

NDC0005A

www.ti.com

MECHANICAL DATA

KTT0005B

TS5B (Rev D)

BOTTOM SIDE OF PACKAGE

www.ti.com

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Products

Applications

Audio

www.ti.com/audio

amplifier.ti.com

dataconverter.ti.com

www.dlp.com

Automotive and Transportation www.ti.com/automotive

Communications and Telecom www.ti.com/communications

Amplifiers

Data Converters

DLP® Products

DSP

Computers and Peripherals

Consumer Electronics

Energy and Lighting

Industrial

www.ti.com/computers

www.ti.com/consumer-apps

www.ti.com/energy

dsp.ti.com

Clocks and Timers

Interface

www.ti.com/clocks

interface.ti.com

logic.ti.com

www.ti.com/industrial

www.ti.com/medical

Medical

Logic

Security

www.ti.com/security

Power Mgmt

Microcontrollers

RFID

power.ti.com

Space, Avionics and Defense

Video and Imaging

www.ti.com/space-avionics-defense

www.ti.com/video

microcontroller.ti.com

www.ti-rfid.com

www.ti.com/omap

OMAP Applications Processors

Wireless Connectivity

TI E2E Community

e2e.ti.com

www.ti.com/wirelessconnectivity

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

LP3964ESX-3.3 [TI]

相关型号：

LP3964ESX-3.3/NOPB

LP3964ESX-3.3/NOPB

LP3964ESX-3.3/NOPB

LP3964ESX-5.0

LP3964ESX-5.0/NOPB

LP3964ESX-ADJ

LP3964ESX-ADJ/NOPB

LP3964ESX-ADJ/NOPB

LP3964ET-1.8

LP3964ET-1.8/NOPB

LP3964ET-2.5

LP3964ET-2.5