LP3972SQX-E514 [TI]
1-CHANNEL POWER SUPPLY SUPPORT CKT, QCC40, 5 X 5 MM, LLP-40;
| 型号： | LP3972SQX-E514 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, QCC40, 5 X 5 MM, LLP-40 |
| 文件： | 总56页 (文件大小：1439K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LP3972
www.ti.com
SNVS468K –SEPTEMBER 2006–REVISED MAY 2013
Power Management Unit for Advanced Application Processors
Check for Samples: LP3972
1
FEATURES
APPLICATIONS
2
•
Compatible With Advanced Applications
Processors Requiring DVM (Dynamic Voltage
Management)
•
•
•
•
•
PDA Phones
Smart Phones
Personal Media Players
Digital Cameras
•
•
•
Three Buck Regulators for Powering High-
Current Processor Functions or I/Os
Application Processors
Six LDOs for Powering RTC, Peripherals, and
I/Os
–
–
–
Marvell PXA
Freescale
Samsung
Backup Battery Charger With Automatic
Switch for Lithium-Manganese Coin Cell
Batteries and Super Capacitors
I2C Compatible High-Speed Serial Interface
DESCRIPTION
•
•
The LP3972 is a multi-function programmable Power
Management Unit designed especially for advanced
application processors. The LP3972 is optimized for
low-power handheld applications and provides six
low-dropout low-noise linear regulators, three DC/DC
magnetic buck regulators, a back-up battery charger,
and two GPIOs. A high-speed serial interface is
included to program individual regulator output
voltages as well as on and off control.
Software Control of Regulator Functions and
Settings
•
•
•
•
Precision Internal Reference
Thermal Overload Protection
Current Overload Protection
Tiny 40-Pin 5x5 mm WQFN Package
KEY SPECIFICATIONS
•
Buck Regulators
–
–
–
–
Programmable VOUT from 0.725 to 3.3V
Up to 95% efficiency
Up to 1.6A output current
±3% output voltage accuracy
•
LDOs
–
–
–
Programmable VOUT of 1.0V–3.3V
±3% output voltage accuracy
150/300/400 mA output currents
–
–
–
–
–
–
LDO_RTC 30 mA
LDO1 300 mA
LDO2 150 mA
LDO3 150 mA
LDO4 150 mA
LDO5 400 mA
–
100 mV (typ) dropout
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2013, Texas Instruments Incorporated
LP3972
SNVS468K –SEPTEMBER 2006–REVISED MAY 2013
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Application Circuits
V
IN
Back-up
Battery
+
-
LDO1
BUCK1
BUCK2
BUCK3
LDO2
LDO3
LP3972
LDO4
LDO5
RTC
Figure 1. Simplified Application Circuit
2
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SNVS468K –SEPTEMBER 2006–REVISED MAY 2013
Li-ion/polymer cell
+
See notes
Cvdd
4.7 mF
LP3972 PMIC
SYNC
35
VIN VDDA
APPLICATION
PROCESSOR
DC SOURCE
4.5 œ 5.5V
27
20
6
40
26 14
31
Cchg_det
4.7 mF
Clock
divider
37
PWR_EN
Lsw1 2.2 mH
COMP
39
CPU
SW1
CORE
BUCK1
BUCK2
EOC
10 mF
VBUCK2
10 mF
VFB1
5
VinBUBATT
15
Lsw2 2.2 mH
19
VoutLDO_RTC
Vout
Switch
SW2
VFB2
USB
23
32
Lsw3 2.2 mH
PWR_ON
1
UART
SW3
BUCK3
VFB3
10 mF
28
OSC
SYS_EN
36
VoutLDO1
BG
MVT
VIN
GPIO1/nCHG_EN
29
LDO1
Wake up
7
Cldo2
0.47 mF
2
30
3
nTEST_JIG
GPIO2
AP_IO
Power
ON-OFF
Logic
VoutLDO3
LDO3
LDO4
12
Cldo3
0.47 mF
SPARE
nRSTI
VoutLDO4
VinLDO4
VinLDO5
PLL
9
13
Cldo4
0.47 mF
RESET
PWR_EN
Logic Control
and registers
Internal HW reset for
test purposes
VoutLDO5
SRAM
RTC
LDO5
25
Cldo5
0.47 mF
SYS_EN
VIN
VoutLDO_RTC
16
LDORTC
CldoRTC
VoutLDO2
8
1.0 mF
See notes
LDO2
CODEC
Cldo1
1.0 mF
Power On
Reset
3.3V
Vout Switch
VDDA
10k
I2C_SCL
22
21
I2C
Thermal
Shutdown
10k
I2C_SDA
BIAS
vref
24
nRSTO
4
EXT_WAKEUP
nBATT_FLT
17
11
18
33
34
38
10
VREF
Cvrefh
10 nF
PGND1 PGND2 PGND3
BGND1,2,3 GND1
•
•
The I2C lines are pulled up via a I/O source
VINLDOs 4, 5 can either be powered from main battery source, or by a buck regulator or VIN
.
Figure 2. Application Circuit
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Connection Diagram
30 29 28 27 26 25 24 23 22 21
21 22 23 24 25 26 27 28 29 30
31
32
20
19
18
20
19
18
31
32
33
34
33
34
17
16
15
14
17
16
15
14
35
36
37
35
36
37
13
12
11
13
12
11
38
39
40
38
39
40
1
2
3
4
5
6
7
8
9
10
10
9
8
7
6
5
4
3
2
1
Top View
Bottom View
Note: Circle marks pin 1 position.
40-Pin WQFN, Package Number RSB0040A
PIN DESCRIPTIONS
Pin No.
Name
I/O
Type(1)
Description
1
PWR_ON
I
D
This is an active HI push button input which can be used to signal PWR_ON
and PWR_OFF events to the CPU by controlling the ext_wakeup [pin4] and
select contents of register 8H'88
2
3
nTEST_JIG
SPARE
I
I
D
D
This is an active LOW input signal used for detecting an external HW event. The
response is seen in the ext_wakeup [pin4] and select contents of register 8H'88
This is an input signal used for detecting a external HW event. The response is
seen in the ext_wakeup [pin4] and select contents of register 8H'88. The polarity
on this pin is assignable
4
EXT_WAKEUP
O
D
This pin generates a single 10 ms pulse output to CPU in response to input
from pins 1, 2, and 3. Flags CPU to interrogate register 8H'88
5
6
7
8
9
FB1
VIN
I
I
A
Buck1 input feedback terminal
Battery Input (Internal circuitry and LDO1-3 power input)
LDO1 output
PWR
PWR
PWR
D
VOUT LDO1
VOUT LDO2
nRSTI
O
O
I
LDO2 output
Active low Reset pin. Signal used to reset the IC (by default is pulled high
internally). Typically a push button reset.
10
11
12
13
14
GND1
VREF
G
O
O
O
I
G
Ground
A
Bypass Cap. for the high internal impedance reference.
VOUT LDO3
VOUT LDO4
VIN LDO4
PWR
PWR
PWR
LDO3 output
LDO4 output
Power input to LDO4, this can be connected to either from a 1.8V supply to
main Battery supply.
15
16
17
VIN BUBATT
VOUT LDO_RTC
nBATT_FLT
I
PWR
PWR
D
Back Up Battery input supply.
O
O
LDO_RTC output supply to the RTC of the application processor.
Main Battery fault output, indicates the main battery is low
(discharged) or the dc source has been removed from the system. This gives
the processor an indicator that the power will shut down. During this time the
processor will operate from the back up coin cell.
18
19
PGND2
SW2
G
O
G
Buck2 NMOS Power Ground
Buck2 switcher output
PWR
(1) A: Analog Pin D: Digital Pin G: Ground Pin P: Power Pin I: Input Pin I/O: Input/Output Pin O: Output Pin
Note: In this document, active-low logic items are prefixed with a lowercase "n".
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SNVS468K –SEPTEMBER 2006–REVISED MAY 2013
PIN DESCRIPTIONS (continued)
Pin No.
20
Name
VIN Buck2
SDA
I/O
Type(1)
Description
I
I/O
I
PWR
D
Battery input power to Buck2
I2C Data (Bidirectional)
I2C Clock
21
22
SCL
D
23
FB2
I
A
Buck2 input feedback terminal
24
nRSTO
VOUT LDO5
VIN LDO5
VDDA
O
O
I
D
Reset output from the PMIC to the processor
25
PWR
PWR
PWR
A
LDO5 output
26
Power input to LDO5, this can be connected to VIN or to a separate 1.8V supply.
Analog Power for VREF, BIAS
27
I
28
FB3
I
Buck3 Feedback
29
GPIO1 /
nCHG_EN
I/O
D
General Purpose I/O / Ext. backup battery charger enable pin. This pin enables
the main battery / DC source power to charge the backup battery. This pin
toggled via the application processor. By grounding this pin the DC source
continuously charges the backup battery
30
31
32
33
34
35
GPIO2
VIN Buck3
SW3
I/O
I
D
PWR
PWR
G
General Purpose I/O
Battery input power to Buck3
Buck3 switcher output
O
G
G
I
PGND3
BGND1,2,3
SYNC
Buck3 NMOS Power Ground
Bucks 1, 2 and 3 analog Ground
G
D
Frequency Synchronization: Connection to an external clock signal PLL to
synchronize the PMIC internal oscillator.
Input Digital enable pin for the high voltage power domain supplies. Output from
the Monahans processor.
36
SYS_EN
I
D
Digital enable pin for the Low Voltage domain supplies. Output signal from the
Monahans processor
37
38
39
40
PWR_EN
PGND1
SW1
I
D
G
O
I
G
Buck1 NMOS Power Ground
Buck1 Switcher output
PWR
PWR
VIN Buck1
Battery input power to Buck1
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)(2)
All Inputs
−0.3V to +6.5V
±0.3V
GND to GND SLUG
Junction Temperature (TJ-MAX
Storage Temperature
)
150°C
−65°C to +150°C
3.2W
Power Dissipation (TA = 70°C)(3)
(3)
Junction-to-Ambient Thermal Resistance θJA
Maximum Lead Temp (Soldering)
25°C/W
260°C
Human Body Model
Machine Model
2 kV
ESD Rating(4)
200V
(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is specified. Operating Ratings do not imply ensured performance limits. For specified performance limits and
associated test conditions, see the Electrical Characteristics tables.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
(3) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-
OP = 125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance
of the part/package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (θJA x PD-MAX).
(4) The Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. (MIL-STD-883 3015.7) The machine
model is a 200 pF capacitor discharged directly into each pin. (EAIJ).
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Operating Ratings
VIN
2.7V to 5.5V
1.74 to VIN
VINLDO4, 5
Junction Temperature (TJ)
Operating Temperature (TA)
Maximum Power Dissipation (TA = 70°C)(1)(2)
−40°C to +125°C
−40°C to +85°C
2.2W
(1) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-
OP = 125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance
of the part/package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (θJA x PD-MAX).
(2) Junction-to-ambient thermal resistance (θJA) is taken from a thermal modeling result, performed under the conditions and guidelines set
forth in the JEDEC standard JESD51–7. The test board is a 4-layer FR-4 board measuring 102 mm x 76 mm x 1.6 mm with a 2x1 array
of thermal vias. The ground plane on the board is 50 mm x 50 mm. Thickness of copper layers are 36 µm/1.8 µm/18 µm/36 µm (1.5 oz/1
oz/1 oz/1.5 oz). Ambient temperature in simulation is 22°C, still air. Power dissipation is 1W. Junction-to-ambient thermal resistance is
highly application and board-layout dependent. In applications where high maximum power dissipation exists, special care must be paid
to thermal dissipation issues in board design. The value of θJA of this product can vary significantly, depending on PCB material, layout,
and environmental conditions. In applications where high maximum power dissipation exists (high VIN, high IOUT), special care must be
paid to thermal dissipation issues. For more information on these topics, see Application Note AN-1187 Leadless Leadframe Package
(LLP)(SNOA401) and the Power Efficiency and Power Dissipation sections of this datasheet.
General Electrical Characteristics
Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the
entire junction temperature range for operation, −40°C to +125°C(1)(2)(3)
Symbol
VIN, VDDA, VIN Buck1, 2 and 3
VINLDO4, VINLDO5
TSD
Parameter
Battery Voltage
Test Conditions
Min
2.7
Typ
3.6
3.6
160
20
Max
5.5
Unit
V
Power Supply for LDO 4 and 5
Thermal Shutdown(4)
1.74
VIN
V
Temperature
Hysteresis
°C
(1) All voltages are with respect to the potential at the GND pin.
(2) All limits specified at room temperature (standard typeface) and at temperature extremes (bold typeface). All room temperature limits are
production tested, ensured through statistical analysis or ensured by design. All limits at temperature extremes are ensured via
correlation using standard Statistical Quality Control (SQC) methods. All limits are used to calculate Average Outgoing Quality Level
(AOQL).
(3) No input supply should be higher then VDDA
(4) This electrical specification is ensured by design.
Supply Specifications(1)(2)
VOUT (Volts)
IMAX: Maximum Current
Current (mA)
Supply
Range
(V)
Resolution
(mV)
N/A
LDO_RTC
LDO1 (VCC_MVT)
LDO2
2.8V
30 mA dc source 10 mA backup source
1.7 to 2.0
1.8 to 3.3
1.8 to 3.3
1.0 to 3.3
0.850 to 1.5
0.725 to 1.5
0.8 to 3.3
0.8 to 3.3
25
300
150
100
LDO3
100
150
LDO4
50-600
25
150
LDO5 (VCC_SRAM)
BUCK1 (VCC_APPS)
BUCK2
400
25
1600
1600
1600
50-600
50-600
BUCK3
(1) All voltages are with respect to the potential at the GND pin.
(2) The Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. (MIL-STD-883 3015.7) The machine
model is a 200 pF capacitor discharged directly into each pin. (EAIJ).
6
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SNVS468K –SEPTEMBER 2006–REVISED MAY 2013
Default Voltage Option(1)(2)(3)
Version
LP3972SQ-A514
LP3972SQ-A413
Enable
Version A
Version A
LDO_RTC
—
2.8
1.8
1.8D
3D
—
2.8
1.8
1.8D
3D
LDO1
SYS_EN
SYS_EN
SYS_EN
SYS_EN
PWR_EN
PWR_EN
SYS_EN
SYS_EN
SYS_EN
SYS_EN
SYS_EN
SYS_EN
PWR_EN
PWR_EN
SYS_EN
SYS_EN
LDO2
LDO3
LDO4
3D
2.8D
1.4
1.4
3
LDO5
1.4
1.4
3.3
1.8
BUCK1
BUCK2
BUCK3
Version
Enable
LDO_RTC
LDO1
1.8
LP3972SQ-E514
LP3972SQ-I514
Version E
Version I
—
2.8
1.8
1.8E
3D
—
2.8
1.8
1.8E
3E
SYS_EN
SYS_EN
SYS_EN
SYS_EN
PWR_EN
PWR_EN
SYS_EN
SYS_EN
SYS_EN
SYS_EN
SYS_EN
SYS_EN
PWR_EN
PWR_EN
SYS_EN
SYS_EN
LDO2
LDO3
LDO4
3D
3E
LDO5
1.4
1.4
3.3
1.8
1.4
1.4
3.3
1.8
BUCK1
BUCK2
BUCK3
Version
Enable
LDO_RTC
LDO1
LP3972SQ-I414
LP3972SQ-0514
Version I
Version 0
—
2.8
1.8
1.8E
3E
Tracking enabled
SYS_EN
3.3 w/ tracking
SYS_EN
SYS_EN
SYS_EN
SYS_EN
PWR_EN
PWR_EN
SYS_EN
SYS_EN
1.8
1.8E
3.3E
3E
LDO2
SYS_EN
LDO3
SYS_EN
LDO4
3E
SYS_EN
LDO5
1.4
1.4
3.0
1.8
PWR_EN
PWR_EN
SYS_EN
1.4
BUCK1
BUCK2
BUCK3
Version
Enable
LDO_RTC
LDO1
1.4
3.3
SYS_EN
1.8
LP3972SQ-5810
Version 5
2.8
1.8
SYS_EN
SYS_EN
SYS_EN
PWR_EN
PWR_EN
PWR_EN
SYS_EN
SYS_EN
LDO2
1.8E
2.5E
1.3E
1.1
LDO3
LDO4
LDO5
BUCK1
BUCK2
BUCK3
1.35
1.2
1.8
(1) All voltages are with respect to the potential at the GND pin.
(2) The Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. (MIL-STD-883 3015.7) The machine
model is a 200 pF capacitor discharged directly into each pin. (EAIJ).
(3) E = Regulator is ENABLED during startup. D = Regulator is DISABLED during startup.
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LDO RTC
Unless otherwise noted, VIN = 3.6V, CIN = 1.0 µF, COUT = 0.47 µF, COUT (VRTC) = 1.0 µF ceramic. Typical values and limits
appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature
range for operation, −40°C to +125°C(1)(2)(3)(4)
Symbol
Parameter
Test Conditions
Min
Typ
Max
2.968
0.15
Unit
V
VOUT Accuracy Output Voltage Accuracy
VIN Connected, Load Current = 1 mA
VIN = (VOUT nom + 1.0V) to 5.5V(5)
Load Current = 1 mA
2.632
2.8
ΔVOUT
Line Regulation
Load Regulation
%/V
From Main Battery
Load Current = 1 mA to 30 mA
0.05
0.5
%/mA
From Backup Battery, VIN = 3.0V
Load Current = 1 mA to 10 mA
ISC
Short Circuit Current Limit
From Main Battery
VIN = VOUT +0.3V to 5.5V
100
30
mA
From Backup Battery
Load Current = 10 mA
IOUT = 0 mA
VIN - VOUT
IQ_Max
TP1
Dropout Voltage
375
mV
µA
V
Maximum Quiescent Current
30
RTC LDO Input Switched from
Main Battery to Backup Battery
VIN Falling
2.9
TP2
CO
RTC LDO Input Switched from
Backup Battery to Main Battery
VIN Rising
3.0
1.0
V
Output Capacitor
Capacitance for Stability
ESR
0.7
5
µF
500
mΩ
(1) All voltages are with respect to the potential at the GND pin.
(2) All limits specified at room temperature (standard typeface) and at temperature extremes (bold typeface). All room temperature limits are
production tested, ensured through statistical analysis or ensured by design. All limits at temperature extremes are ensured via
correlation using standard Statistical Quality Control (SQC) methods. All limits are used to calculate Average Outgoing Quality Level
(AOQL).
(3) Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal value.
(4) LDO_RTC voltage can track LDO3 voltage. LP3972 has a tracking function (nIO_TRACK). When enabled, LDO_RTC voltage will track
LDO3 voltage within 200mV down to 2.8V when LDO3 is enabled
(5) VIN minimum for line regulation values is 2.7V for LDOs 1–3 and 1.8V for LDOs 4 and 5. Condition does not apply to input voltages
below the minimum input operating voltage.
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LDOs 1 to 5
Unless otherwise noted, VIN = 3.6V, CIN = 1.0 µF, COUT = 0.47 µF, COUT (VRTC) = 1.0 µF ceramic. Typical values and limits
appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature
range for operation, −40°C to +125°C(1)(2)(3)(4)(5)(6)(7)
Symbol
VOUT Accuracy Output Voltage Accuracy
(Default VOUT
Parameter
Test Conditions
Load Current = 1 mA
Min
Typ
Max
3
Unit
−3
%
)
ΔVOUT
Line Regulation
VIN =3.1V to 5.0V(5)
,
0.15
%/V
Load Current = 1 mA
Load Regulation
VIN = 3.6V,
0.011
%/mA
Load Current = 1 mA to IMAX
ISC
Short Circuit Current Limit
LDO1–4, VOUT = 0V
400
500
mA
LDO5, VOUT = 0V
VIN - VOUT
PSRR
IQ
Dropout Voltage
Load Current = 50 mA(3)
150
mV
dB
Power Supply Ripple Rejection f = 10 kHz, Load Current = IMAX
45
40
Quiescent Current "On"
Quiescent Current "On"
Quiescent Current "Off"
Turn On Time
IOUT = 0 mA
IOUT = IMAX
60
µA
EN is de-asserted
Start up from Shut-down
0.03
300
0.47
TON
µsec
µF
COUT
Output Capacitor
Capacitance for Stability
0°C ≤ TJ ≤ 125°C
0.33
−40°C ≤ TJ ≤ 125°C
0.68
5
1.0
ESR
500
mΩ
(1) All voltages are with respect to the potential at the GND pin.
(2) All limits specified at room temperature (standard typeface) and at temperature extremes (bold typeface). All room temperature limits are
production tested, ensured through statistical analysis or ensured by design. All limits at temperature extremes are ensured via
correlation using standard Statistical Quality Control (SQC) methods. All limits are used to calculate Average Outgoing Quality Level
(AOQL).
(3) Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal value.
(4) LDO_RTC voltage can track LDO3 voltage. LP3972 has a tracking function (nIO_TRACK). When enabled, LDO_RTC voltage will track
LDO3 voltage within 200mV down to 2.8V when LDO3 is enabled
(5) VIN minimum for line regulation values is 2.7V for LDOs 1–3 and 1.8V for LDOs 4 and 5. Condition does not apply to input voltages
below the minimum input operating voltage.
(6) An increase in the load current results in a slight decrease in the output voltage and vice versa.
(7) Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal value. This
specification does not apply for input voltages below 2.7V for LDOs 1–3 and 1.8V for LDOs 4 and 5.
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LDO Dropout Voltage vs. Load Current Collect Data For All LDOs
Dropout Voltage vs.
Load Current
Change in Output Voltage
vs. Load Current
300
250
200
150
100
50
200
150
100
50
REG1 3.3V OUTPUT
REG2 2.5V OUTPUT
REG3 1.3V OUTPUT
0
REG1 3.3V OUTPUT
-50
-100
V
= 3.6V
200
IN
0
0
200
400
600
800 1000 1200
0
400
600
800 1000 1200
LOAD CURRENT (mA)
LOAD CURRENT (mA)
Figure 3.
Figure 4.
LDO1 Line Regulation
VOUT = 1.8 volts VIN 3 to 4 volts Load = 100 mA
LDO1 Load Transient
VIN = 4.1 volts VOUT = 1.8 volts no-load-100 mA
4.03 ms
4.0 ms
Figure 5.
Figure 6.
Enable Start-up time (LDO1)
LDO1 Channel 2 LDO4 Channel 1 Sys_enable from 0 volts Load = 100 mA
4.03 ms
Figure 7.
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Buck Converters SW1, SW2, SW3
Unless otherwise noted, VIN = 3.6V, CIN = 10 µF, COUT = 10 µF, LOUT = 2.2 µH ceramic. Typical values and limits appearing in
normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for
operation, −40°C to +125°C(1)(2)(3)(4)
Symbol
VOUT
Parameter
Output Voltage Accuracy
Efficiency
Test Conditions
Min
Typ
Max
Unit
%
Default VOUT
−3
+3
Eff
Load Current = 500 mA
95
0.1
13
%
ISHDN
Shutdown Supply Current
Sync Mode Clock Frequency
Internal Oscillator Frequency
Peak Switching Current Limit
Quiescent Current "On"
EN is de-asserted
µA
Synchronized from 13 MHz System Clock
10.4
15.6
2.4
MHz
MHz
A
fOSC
IPEAK
IQ
2.0
2.1
21
No Load PFM Mode
No Load PWM Mode
µA
200
240
200
500
RDSON (P)
RDSON (N)
TON
Pin-Pin Resistance PFET
Pin-Pin Resistance NFET
Turn On Time
mΩ
mΩ
µsec
µF
Start up from Shut-down
Capacitance for Stability
Capacitance for Stability
CIN
Input Capacitor
8
8
CO
Output Capacitor
µF
(1) All voltages are with respect to the potential at the GND pin.
(2) All limits specified at room temperature (standard typeface) and at temperature extremes (bold typeface). All room temperature limits are
production tested, ensured through statistical analysis or ensured by design. All limits at temperature extremes are ensured via
correlation using standard Statistical Quality Control (SQC) methods. All limits are used to calculate Average Outgoing Quality Level
(AOQL).
(3) The input voltage range recommended for ideal applications performance for the specified output voltages is given below:VIN = 2.7V to
5.5V for 0.80V < VOUT < 1.8VVIN = (VOUT+ 1V) to 5.5V for 1.8V ≤ VOUT ≤ 3.3V
(4) Test condition: for VOUT less than 2.7V, VIN = 3.6V; for VOUT greater than or equal to 2.7V, VIN = VOUT+ 1V.
Buck1 Output Efficiency vs. Load Current Varied from 1mA to 1.5 Amps
VIN = 3, 3.5 volts VOUT = 1.4 volts Forced PWM
VIN = 4.0-4.5 volts VOUT = 1.4 volts Forced PWM
100.00
90.00
V
IN
= 3V
V
= 4V
IN
80.00
60.00
40.00
20.00
0.00
72.00
54.00
36.00
18.00
0.00
V
= 3.5V
IN
V
= 4.5V
IN
1
1e1
1e2
1e3
1e4
1
1e1
1e2
1e3
1e4
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
Figure 8.
Figure 9.
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Line Transient Response
VIN = 3 – 3.6 V, VOUT = 1.2 V, 250 mA load
VIN = 3, 3.5 volts VOUT = 1.4 volts Forced PWM
90.00
72.00
54.00
36.00
18.00
0.00
V
= 5.5V
IN
V
= 5V
IN
4.03 ms
1
1e1
1e2
1e3
1e4
OUTPUT CURRENT (mA)
Figure 10.
Figure 11.
Mode Change
Load transients 20 mA to 560 mA
VOUT = 1.4 volts [PFM to PWM] VIN = 4.1 volts
Load Transient
3.6 VIN, 3.3 VOUT, 0 – 100 mA load
4.03 ms
4.0 ms
Figure 12.
Figure 13.
Startup
Startup into PWM Mode 980 mA [channel 2]
VOUT = 1.4 volts VIN = 4.1 volts
4.03 ms
Figure 14.
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Back-Up Charger Electrical Characteristics
Unless otherwise noted, VIN = VBATT = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits
appearing in boldface type apply over the entire junction temperature range for operation, −40°C to +125°C(1)(2)(3)
Symbol
VIN
Parameter
Test Conditions
Min
3.3
Typ
Max
5.5
Unit
V
Operational Voltage Range
Voltage at VIN
IOUT
Backup Battery Charging Current VIN = 3.6V, Backup_Bat = 2.5V, Backup
Battery Charger Enabled(3)
190
3.1
9
µA
VOUT
Charger Termination Voltage
VIN = 5.0V Backup Battery Charger Enabled.
Programmable
2.91
V
Backup Battery Charger Short
Circuit Current
Backup_Bat = 0V, Backup Battery Charger
Enabled
mA
dB
PSRR
Power Supply Ripple Rejection
Ratio
I
OUT ≤ 50 µA, VOUT = 3.15V
15
VOUT + 0.4 ≤ VBATT = VIN ≤ 5.0V
f < 10 kHz
IQ
Quiescent Current
IOUT < 50 µA
25
µA
µF
COUT
Output Capacitance
Output Capacitor ESR
0 µA ≤ IOUT ≤ 100 µA
0.1
5
500
mΩ
(1) All voltages are with respect to the potential at the GND pin.
(2) All limits specified at room temperature (standard typeface) and at temperature extremes (bold typeface). All room temperature limits are
production tested, ensured through statistical analysis or ensured by design. All limits at temperature extremes are ensured via
correlation using standard Statistical Quality Control (SQC) methods. All limits are used to calculate Average Outgoing Quality Level
(AOQL).
(3) Back-up battery charge current is programmable via the I2C compatible interface. Refer to the Application Section for more information.
LP3972 Battery Switch Operation
The LP3972 has provisions for two battery connections, the main battery VBAT and Backup Battery.
The function of the battery switch is to connect power to the LDO_RTC from the appropriate battery, depending
on conditions described below:
•
•
•
If only the backup battery is applied, the switch will automatically connect the LDO_RTC power to this battery.
If only the main battery is applied, the switch will automatically connect the LDO_RTC power to this battery
If both batteries are applied, and the main battery is sufficiently charged (VBAT > 3.1V), the switch will
automatically connect the LDO_RTC power to the main battery.
•
As the main battery is discharged a separate circuit called nBATT_FLT will warn the system. Then if no action
is taken to restore the charge on the main battery, and discharging is continued the battery switch will
disconnect the input of the LDO_RTC from the main battery and connect to the backup battery.
•
•
•
The main battery voltage at which the LDO_RTC is switched over from main to backup battery is 2.8V
typically.
There is a hysteric voltage in this switch operation, thus the LDO_RTC will not be reconnected to main
battery until main battery voltage is greater than 3.1V typically.
The system designer may wish to disable the battery switch when only a main battery is used. This is
accomplished by setting the "no back up battery bit" in the control register 8h’0B bit 7 NBUB. With this bit set
to "1", the above described switching will not occur, that is the LDO_RTC will remain connected to the main
battery even as it is discharged below the 2.9V threshold. The Backup battery input should also be connected
to main battery.
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Logic Inputs and Outputs DC Operating Conditions(1)
Logic Inputs (SYS_EN, PWR_EN, SYNC, nRSTI, PWR_ON, nTEST_JIG, SPARE and GPI's)
Symbol
VIL
Parameter
Low Level Input Voltage
High Level Input Voltage
Input Leakage Current
Test Conditions
Min
Max
0.5
Unit
V
VIH
V
RTC − 0.5V
V
ILEAK
−1
+1
µA
(1) All voltages are with respect to the potential at the GND pin.
Logic Outputs (nRSTO, EXT_WAKEUP and GPO's)
Symbol
VOL
Parameter
Output Low Level
Test Conditions
Load = +0.2 mA = IOL Max
Load = −0.1 mA = IOL Max
VON = VIN
Min
Max
0.5
Unit
V
VOH
Output High Level
V
RTC − 0.5V
V
ILEAK
Output Leakage Current
+5
µA
Logic Output (nBATT_FLT)
Symbol
Parameter
Test Conditions
Min
2.4
Typ
2.8
Max
Unit
nBATT_FLT Threshold Voltage
Programmable via Serial Interface
Default = 2.8V
3.4
V
VOL
Output Low Level
Load = +0.4 mA = IOL Max
0.5
V
V
VOH
Output High Level
Input Leakage Current
Load = −0.2 mA = IOH Max
VRTC − 0.5V
ILEAK
+5
µA
I2C Compatible Serial Interface Electrical Specifications (SDA and SCL)
Unless otherwise noted, VIN = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing
in boldface type apply over the entire junction temperature range for operation, −40°C to +125°C(1)(2)(3)
Symbol
Parameter
Low Level Input Voltage
Test Conditions
See(4)
Min
−0.5
0.7 VRTC
0
Typ
Max
Unit
VIL
VIH
VOL
IOL
0.3 VRTC
VRTC
V
High Level Input Voltage
Low Level Output Voltage
Low Level Output Current
Clock Frequency
See(4)
See(4)
VOL = 0.4V(4)
See(4)
See(4)
See(4)
See(4)
See(4)
See(4)
See(4)
See(4)
See(4)
See(4)
0.2 VTRC
3.0
mA
kHz
µs
µs
µs
µs
µs
µs
ns
FCLK
400
tBF
Bus-Free Time Between Start and Stop
Hold Time Repeated Start Condition
CLK Low Period
1.3
0.6
1.3
0.6
0.6
0
tHOLD
tCLKLP
tCLKHP
tSU
CLK High Period
Set Up Time Repeated Start Condition
Data Hold Time
tDATAHLD
tCLKSU
TSU
Data Set Up Time
100
0.6
Set Up Time for Start Condition
µs
ns
TTRANS
Maximum pulse width of spikes that must be
suppressed by the input filter of both DATA and
CLK signals
50
(1) All voltages are with respect to the potential at the GND pin.
(2) All limits specified at room temperature (standard typeface) and at temperature extremes (bold typeface). All room temperature limits are
production tested, ensured through statistical analysis or ensured by design. All limits at temperature extremes are ensured via
correlation using standard Statistical Quality Control (SQC) methods. All limits are used to calculate Average Outgoing Quality Level
(AOQL).
(3) The I2C signals behave like open-drain outputs and require an external pull-up resistor on the system module in the 2 kΩ to 20 kΩ
range.
(4) This electrical specification is ensured by design.
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Detailed Description
Buck Converter Operation
DEVICE INFORMATION
The LP3972 includes three high efficiency step down DC-DC switching buck converters. Using a voltage mode
architecture with synchronous rectification, the buck converters have the ability to deliver up to 1600 mA
depending on the input voltage, output voltage, ambient temperature and the inductor chosen.
There are three modes of operation depending on the current required - PWM, PFM, and shutdown. The device
operates in PWM mode at load currents of approximately 100 mA or higher, having voltage tolerance of ±3%
with 95% efficiency or better. Lighter load currents cause the device to automatically switch into PFM for reduced
current consumption. Shutdown mode turns off the device, offering the lowest current consumption (IQ, SHUTDOWN
= 0.01 µA typ).
Additional features include soft-start, under voltage protection, current overload protection, and thermal shutdown
protection.
The part uses an internal reference voltage of 0.5V. It is recommended to keep the part in shutdown until the
input voltage is 2.7V or higher.
CIRCUIT OPERATION
The buck converter operates as follows. During the first portion of each switching cycle, the control block turns
on the internal PFET switch. This allows current to flow from the input through the inductor to the output filter
capacitor and load. The inductor limits the current to a ramp with a slope of (VIN–VOUT)/L, by storing energy in a
magnetic field.
During the second portion of each cycle, the controller turns the PFET switch off, blocking current flow from the
input, and then turns the NFET synchronous rectifier on. The inductor draws current from ground through the
NFET to the output filter capacitor and load, which ramps the inductor current down with a slope of –VOUT/L.
The output filter stores charge when the inductor current is high, and releases it when inductor current is low,
smoothing the voltage across the load.
The output voltage is regulated by modulating the PFET switch on time to control the average current sent to the
load. The effect is identical to sending a duty-cycle modulated rectangular wave formed by the switch and
synchronous rectifier at the SW pin to a low-pass filter formed by the inductor and output filter capacitor. The
output voltage is equal to the average voltage at the SW pin.
PWM OPERATION
During PWM operation the converter operates as a voltage mode controller with input voltage feed forward. This
allows the converter to achieve good load and line regulation. The DC gain of the power stage is proportional to
the input voltage. To eliminate this dependence, feed forward inversely proportional to the input voltage is
introduced.
While in PWM (Pulse Width Modulation) mode, the output voltage is regulated by switching at a constant
frequency and then modulating the energy per cycle to control power to the load. At the beginning of each clock
cycle the PFET switch is turned on and the inductor current ramps up until the comparator trips and the control
logic turns off the switch. The current limit comparator can also turn off the switch in case the current limit of the
PFET is exceeded. Then the NFET switch is turned on and the inductor current ramps down. The next cycle is
initiated by the clock turning off the NFET and turning on the PFET.
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V
SW
2V/DIV
I
L
200 mA/DIV
V
V
= 3.6V
IN
I
= 400 mA
OUT
= 1.5V
OUT
V
OUT
10 mV/DIV
AC Coupled
TIME (200 ns/DIV)
Figure 15. Typical PWM Operation
Internal Synchronous Rectification
While in PWM mode, the converters uses an internal NFET as a synchronous rectifier to reduce rectifier forward
voltage drop and associated power loss. Synchronous rectification provides a significant improvement in
efficiency whenever the output voltage is relatively low compared to the voltage drop across an ordinary rectifier
diode.
Current Limiting
A current limit feature allows the converters to protect itself and external components during overload conditions.
PWM mode implements current limiting using an internal comparator that trips at 2.0 A (typ). If the output is
shorted to ground the device enters a timed current limit mode where the NFET is turned on for a longer duration
until the inductor current falls below a low threshold, ensuring inductor current has more time to decay, thereby
preventing runaway.
PFM OPERATION
At very light loads, the converter enters PFM mode and operates with reduced switching frequency and supply
current to maintain high efficiency.
The part will automatically transition into PFM mode when either of two conditions occurs for a duration of 32 or
more clock cycles:
1. The inductor current becomes discontinuous.
2. The peak PMOS switch current drops below the IMODE level, (Typically IMODE < 30 mA + VIN/42Ω).
2V/DIV
V
SW
I
L
200 mA/DIV
VIN = 3.6V
I
= 20 mA
OUT
VOUT = 1.5V
V
OUT
20 mV/DIV
AC Coupled
TIME (4 ms/DIV)
Figure 16. Typical PFM Operation
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During PFM operation, the converter positions the output voltage slightly higher than the nominal output voltage
during PWM operation, allowing additional headroom for voltage drop during a load transient from light to heavy
load. The PFM comparators sense the output voltage via the feedback pin and control the switching of the output
FETs such that the output voltage ramps between <0.6% and <1.7% above the nominal PWM output voltage. If
the output voltage is below the "high" PFM comparator threshold, the PMOS power switch is turned on. It
remains on until the output voltage reaches the ‘high’ PFM threshold or the peak current exceeds the IPFM level
set for PFM mode. The typical peak current in PFM mode is: IPFM = 112 mA + VIN/27Ω. Once the PMOS power
switch is turned off, the NMOS power switch is turned on until the inductor current ramps to zero. When the
NMOS zero-current condition is detected, the NMOS power switch is turned off. If the output voltage is below the
‘high’ PFM comparator threshold (see Figure 17), the PMOS switch is again turned on and the cycle is repeated
until the output reaches the desired level. Once the output reaches the ‘high’ PFM threshold, the NMOS switch is
turned on briefly to ramp the inductor current to zero and then both output switches are turned off and the part
enters an extremely low power mode. Quiescent supply current during this ‘sleep’ mode is 21 µA (typ), which
allows the part to achieve high efficiencies under extremely light load conditions. When the output drops below
the ‘low’ PFM threshold, the cycle repeats to restore the output voltage (average voltage in PFM mode) to
<1.15% above the nominal PWM output voltage. If the load current should increase during PFM mode (see
Figure 17) causing the output voltage to fall below the ‘low2’ PFM threshold, the part will automatically transition
into fixed-frequency PWM mode. Typically when VIN = 3.6V the part transitions from PWM to PFM mode at 100
mA output current.
High PFM Threshold
PFM Mode at Light Load
~1.017*Vout
Load current
increases
Low1 PFM Threshold
~1.006*Vout
Current load
increases,
draws Vout
towards
Low2 PFM
Threshold
High PFM
Voltage
Threshold
reached,
go into
Nfet on
drains
conductor
current
until
I inductor=0
Low PFM
Threshold,
turn on
Pfet on
until
Ipfm limit
reached
PFET
Low2 PFM Threshold
Vout
sleep mode
PWM Mode at
Moderate to Heavy
Loads
Low2 PFM Threshold,
switch back to PWMmode
Figure 17. Operation in PFM Mode and Transfer to PWM Mode
SHUTDOWN MODE
During shutdown the PFET switch, reference, control and bias circuitry of the converters are turned off. The
NFET switch will be open in shutdown to discharge the output. When the converter is enabled, EN, soft start is
activated. It is recommended to disable the converter during the system power up and undervoltage conditions
when the supply is less than 2.7V.
SOFT START
The buck converter has a soft-start circuit that limits in-rush current during start-up. During start-up the switch
current limit is increased in steps. Soft start is activated only if EN goes from logic low to logic high after VIN
reaches 2.7V. Soft start is implemented by increasing switch current limit in steps of 213 mA, 425 mA, 850 mA
and 1700 mA (typ. Switch current limit). The start-up time thereby depends on the output capacitor and load
current demanded at start-up. Typical start-up times with 10 µF output capacitor and 1000 mA load current is 390
µs and with 1 mA load current it is 295 µs.
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LDO - LOW DROP OUT OPERATION
The LP3972 can operate at 100% duty cycle (no switching; PMOS switch completely on) for low drop out support
of the output voltage. In this way the output voltage will be controlled down to the lowest possible input voltage.
When the device operates near 100% duty cycle, output voltage ripple is approximately 25 mV. The minimum
input voltage needed to support the output voltage is
VIN, MIN = ILOAD * (RDSON, PFET + RINDUCTOR) + VOUT
where
•
•
•
ILOAD = Load Current
RDSON, PFET = Drain to source resistance of PFET switch in the triode region
RINDUCTOR = Inductor resistance
(1)
SPREAD SPECTRUM FEATURE
Periodic switching in the buck regulator is inherently a noisier function block compared to an LDO. It can be
challenging in some critical applications to comply with stringent regulatory standards or simply to minimize
interference to sensitive circuits in space limited portable systems. The regulator’s switching frequency and
harmonics can cause "noise" in the signal spectrum. The magnitude of this noise is measured by its power
spectral density. The power spectral density of the switching frequency, FC, is one parameter that system
designers want to be as low as practical to reduce interference to the environment and subsystems within their
products. The LP3972 has a user selectable function on chip, wherein a noise reduction technique known as
"spread spectrum" can be employed to ease customer’s design and production issues.
The principle behind spread spectrum is to modulate the switching frequency slightly and slowly, and spread the
signal frequency over a broader bandwidth. Thus, its power spectral density becomes attenuated, and the
associated interference electro-magnetic energy is reduced. The clock used to modulate the LP3972 buck
regulator can be used as a spread spectrum clock via 2 I2C control register (System Control Register 1 (SCR1)
8h’80) bits bk_ssen, and slomod. With this feature enabled, the intense energy of the clock frequency can be
spread across a small band of frequencies in the neighborhood of the center frequency. The results in a
reduction of the peak energy!
The LP3972 spread spectrum clock uses a triangular modulation profile with equal rise and fall slopes. The
modulation has the following characteristics:
•
•
•
•
The center frequency: FC = 2 MHz, and
The modulating frequency, fM = 6.8 kHz or 12 kHz.
Peak frequency deviation: Δ_f = ±100 kHz (or ±5%)
Modulation index β = Δ_f/fM = 14.7 or 8.3
Switching Energy RBW = 300 Hz
0
-10
-20
-30
-40
-50
-60
2040
2060
2080
2100
2120
2140
FREQUENCY (kHz)
Figure 18.
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I2C Compatible Interface
I2C DATA VALIDITY
The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state of
the data line can only be changed when CLK is LOW.
SCL
SDA
data
change
allowed
data valid
data
change
allowed
data
change
allowed
data valid
Figure 19.
I2C START and STOP CONDITIONS
START and STOP bits classify the beginning and the end of the I2C session. START condition is defined as SDA
signal transitioning from HIGH to LOW while SCL line is HIGH. STOP condition is defined as the SDA
transitioning from LOW to HIGH while SCL is HIGH. The I2C master always generates START and STOP bits.
The I2C bus is considered to be busy after START condition and free after STOP condition. During data
transmission, I2C master can generate repeated START conditions. First START and repeated START
conditions are equivalent, function-wise.
SDA
SCL
S
P
START condition
STOP condition
Figure 20.
TRANSFERRING DATA
Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first.
The number of bytes that can be transmitted per transfer is unrestricted. Each byte of data has to be followed by
an acknowledge bit. The acknowledge related clock pulse is generated by the master. The transmitter releases
the SDA line (HIGH) during the acknowledge clock pulse. The receiver must pull down the SDA line during the
9th clock pulse, signifying an acknowledge. A receiver which has been addressed must generate an
acknowledge after each byte has been received.
After the START condition, a chip address is sent by the I2C master. This address is seven bits long followed by
an eighth bit which is a data direction bit (R/W). The LP3972 address is 34h. For the eighth bit, a "0" indicates a
WRITE and a "1" indicates a READ. The second byte selects the register to which the data will be written. The
third byte contains data to write to the selected register.
I2C CHIP ADDRESS - 7h'34
MSB
ADR6
Bit7
ADR5
Bit6
ADR4
Bit5
ADR3
Bit4
ADR2
Bit3
ADR1
Bit2
ADR0
Bit1
R/W
Bit0
0
1
1
0
1
0
0
R/W
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Write Cycle
start
msb Chip Address lsb
w
ack
Msb Register Add lsb
ack
msb
DATA
lsb
ack stop
SCL
SDA
start
Id = 34h
w
ack
addr = 02h
ack
address h‘02 data
ack stop
Figure 21. Write cycle
Read Cycle
When a READ function is to be accomplished, a WRITE function must precede the READ function as follows.
start msb Chip Address lsb
w
msb Register Add lsb
rs
msb Chip Address lsb
r
msb
DATA
lsb
stop
ack
ack
ack
ack
SCL
SDA
start
Id = 34h
w
ack
addr = 00h
ack rs
Id = 34h
r
ack
Address h‘00 data
ack stop
w = write (SDA = "0")
r = read (SDA = "1")
ack = acknowledge (SDA pulled down by either master or slave)
rs = repeated start
id = 34h (Chip Address)
Figure 22. Read Cycle
DATA OUTPUT
BY TRANSMITTER
DATA OUTPUT
BY RECEIVER
acknowledge
SCL FROM
MASTER
1
8
9
S
clock pulse for
acknowledgement
I2C - bus.
Voltage ””B‘‘
START
condition
5 ms TYP
Voltage ””A‘‘
V
_APPS
CC
Figure 23. I2C DVM Timing for VCC_APPS (Buck1)
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MULTI-BYTE I2C COMMAND SEQUENCE
To correctly function with the Monahan’s Power Management I2C the LP3972’s I2C serial interface shall support
Random register Multi-byte command sequencing: During a multi-byte write the Master sends the Start command
followed by the Device address, which is sent only once, followed by the 8 Bit register address, then 8 bits of
data. The I2C slave must then accept the next random register address followed by 8 bits of data and continue
this process until the master sends a valid stop condition.
A Typical Multi-byte random register transfer is outlined below:
Device Address,
Register A Address, Ach,
Register A Data, Ach
Register M Address, Ach,
Register M Data, Ach
Register X Address, Ach,
Register X Data, Ach
Register Z Address, Ach,
Register Z Data, Ach, Stop
Note: The PMIC is not required to see the I2C device address for each transaction. A, M, X, and Z are Random
numbers.
ack from slave
ack from slave
ack from slave
ack from slave
ack from slave
start
msb Chip Address lsb
w
ack
msb Register Add lsb
ack
msb
DATA
lsb
ack
msb Register Add lsb
ack
msb
DATA
lsb
ack stop
Register 0x24
Register 0x2A
Figure 24.
INCREMENTAL REGISTER I2C COMMAND SEQUENCE
The LP3972 supports address increment (burst mode). When you have defined register address n data bytes
can be sent and register address is incremented after each data byte has been sent. Address incrimination may
be required for non XScale applications. User can define whether multi-byte (default) to random address or
address incrimination will be used.
ack from slave
ack from slave
ack from slave
ack from slave
ack from slave
start
msb Chip Address lsb
w
ack
msb Register Add lsb
ack
msb
DATA1
lsb
ack
msb
DATA2
lsb
ack
msb
DATA3
lsb
ack stop
Register 0x24
Data (reg_0x24)
Data (reg_0x25)
Data (reg_0x26)
Figure 25.
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LP3972 CONTROL REGISTER
Register Address
8h’07
Register Name
Read/Write
Register Description
SCR
R/W
R/W
R
System Control Register
8h’10
OVER1
OVSR1
OVER2
OVSR2
Output Voltage Enable Register 1
Output Voltage Status Register 1
Output Voltage Enable Register 2
Output Voltage Status Register 2
8h’11
8h’12
R/W
R
8h’13
8h’20
VCC1
R/W
Voltage Change Control Register
1
8h’23
8h’24
ADTV1
ADTV2
R/W
R/W
Buck1 Target Voltage 1 Register
Buck1 DVM Target Voltage 2
Register
8h’25
AVRC
R/W
VCC_APPS Voltage Ramp
Control
8h’26
8h’27
8h’29
8h’2A
8h’32
8h’33
8h’39
8h’3A
CDTC1
CDTC2
SDTV1
SDTV2
MDTV1
MDTV2
L2VCR
L34VCR
W
Dummy Register
W
Dummy Register
R/W
R/W
R/W
R/W
R/W
R/W
LDO5 Target Voltage 1
LDO5 Target Voltage 2
LDO1 Target Voltage 1 Register
LDO1 Voltage 2 Register
LDO2 Voltage Control Registers
LDO3 & LDO4 Voltage Control
Registers
8h’80
8h’81
8h’82
8h’83
8h’84
8h’85
8h’86
8h’87
8h’88
8h’89
SCR1
SCR2
OEN3
OSR3
LOER4
B2TV
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
System Control Register 1
System Control Register 2
Output Voltage Enable Register 3
Output Voltage Status Register 3
Output Voltage Enable Register 3
VCC_Buck2 Target Voltage
VCC_Buck3 Target Voltage
Buck 3:2 Voltage Ramp Control
Interrupt Status Register A
B3TV
B32RC
ISRA
BCCR
R/W
Backup Battery Charger Control
Register
8h’8E
8h’8F
II1RR
II2RR
R
R
Internal 1 Revision Register
Internal 2 Revision Register
SERIAL INTERFACE REGISTER SELECTION CODES (Bold face voltages are default values)
System Control Status Register
Register is an 8-bit register which specifies the control bits for the PMIC clocks. This register works in
conjunction with the SYNC pin where an external clock PLL buffer operating at 13 MHz is synchronized with the
oscillators of the buck converters.
System Control Register (SCR) 8h’07
Bit
7
6
5
4
Reserved
0
3
2
1
0
CLK_SCL
0
Designation
Reset Value
0
0
0
0
0
0
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System Control Register (SCR) 8h’07 Definitions
Bit
7-1
0
Access
—
Name
—
Description
Reserved
R/W
CLK_SCL
External Clock Select
0 = Internal Oscillator clock for Buck Converters
1 = External 13 MHz Oscillator clock for Buck Converters
OUTPUT VOLTAGE ENABLE REGISTER 1
This register enables or disables the low voltage supplies LDO1 and Buck1. See details below.
Output Voltage Enable Register 1 (OVER1) 8h’10
Bit
7
6
5
Reserved
0
4
3
2
S_EN
1
1
Reserved
0
0
A_EN
1
Designation
Reset Value
0
0
0
0
Output Voltage Enable Register 1 (OVER1) 8h’10 Definitions
Bit
Access
Name
Description
7-3
2
—
—
Reserved
R/W
S_EN
VCC_SRAM (LDO5) Supply Output Enabled
0 = VCC_SRAM (LDO5) Supply Output Disabled
1 = VCC_SRAM (LDO5) Supply Output Enabled
1
0
—
—
Reserved
R/W
A_EN
VCC_APPS (Buck1) Supply Output Enabled
0 = VCC_APPS (Buck1) Supply Output Disabled
1 = VCC_APPS (Buck1) Supply Output Enabled
OUTPUT VOLTAGE STATUS REGISTER
This 8 bit register is used to indicate the status of the low voltage supplies. By polling each of the specify
supplies is within its specified operating range.
Output Voltage Status Register 1 (OVSR1) 8h’11
Bit
7
LP_OK
0
6
5
4
3
2
S_OK
0
1
Reserved
0
0
A_OK
0
Designation
Reset Value
Reserved
0
0
0
0
Output Voltage Status Register 1 (OVSR1) 8h’11 Definitions
Bit
Access
Name
Description
Low Voltage Supply Output Voltage Status
7
R
LP_OK
0 - VCC_APPS (Buck1) & VCC_SRAM (LDO5) output voltage < 90% of
selected value
1 - VCC_APPS (Buck1) & VCC_SRAM (LDO5) output voltage > 90% of
selected value
6:3
2
—
R
—
Reserved
S_OK
VCC_SRAM Supply Output Voltage Status
0 - VCC_SRAM (LDO5) output voltage < 90% of selected value
1 - VCC_SRAM (LDO5) output voltage > 90% of selected value
1
0
—
R
—
Reserved
A_OK
VCC_APPS Supply output Voltage Status
0 - VCC_APPS (Buck1) output voltage < 90% of selected value
1 - VCC_APPS (Buck1) output voltage > 90% of selected value
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OUTPUT VOLTAGE ENABLE REGISTER 2
This 8 bit output register enables and disables the output voltages on the LDOs 2,3,4 supplies.
Output Voltage Enable Register 2 (OVER2) 8h’12
Bit
7
6
Reserved
0
5
4(1)
LDO4_EN
0
3(1)
LDO3_EN
0
2(1)
LDO2_EN
0
1
0
Designation
Reset Value
Reserved
0
0
0
0
(1) One-time factory programmable EPROM registers for default values
Output Voltage Enable Register 2 (OVER2) 8h’12 Definitions
Bit
7
Access
—
Name
Description
Reserved
Reserved
Reserved
—
—
6
—
5
—
—
4
R/W
LDO4_EN
LDO4 Output Voltage Enable
0 = LDO4 Supply Output Disabled, Default
1 = LDO4 Supply Output Enabled
3
2
R/W
R/W
LDO3_EN
LDO2_EN
LDO3 Output Voltage Enable
0 = LDO3 Supply Output Disabled, Default
1 = LDO3 Supply Output Enabled
LDO2 Output Voltage Enable
0 = LDO2 Supply Output Disabled, Default
1 = LDO2 Supply Output Enabled
1
0
—
—
—
—
Reserved
Reserved
OUTPUT VOLTAGE STATUS REGISTER 2
Output Voltage Status Register 2 (OVSR2) 8h’13
Bit
7
LDO_OK
0
6
N/A
0
5
N/A
0
4
LDO4_OK
0
3
LDO3_OK
0
2
LDO2_OK
0
1
N/A
0
0
N/A
0
Designation
Reset Value
Output Voltage Status Register 2 (OVSR2) 8h’13 Definitions
Bit
Access
Name
Description
7
R
LDO_OK
LDOs 2-4 Supply Output Voltage Status
0 - (LDOs 2-4) output voltage < 90% of selected value
1 - (LDOs 2-4) output voltage > 90% of selected value
6
5
4
—
—
R
—
—
Reserved
Reserved
LDO4_OK
LDO4 Output Voltage Status
0 - (VCC_LDO4) output voltage < 90% of selected value
1 - (VCC_LDO4) output voltage > 90% of selected value
3
2
R
R
LDO3_OK
LDO2_OK
LDO3 Output Voltage Status
0 - (VCC_LDO3) output voltage < 90% of selected value
1 - (VCC_LDO3) output voltage > 90% of selected value
LDO2 Output Voltage Status
0 - (VCC_LDO2) output voltage < 90% of selected value
1 - (VCC_LDO2) output voltage > 90% of selected value
1
0
—
—
—
—
Reserved
Reserved
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DVM VOLTAGE CHANGE CONTROL REGISTER 1
DVM Voltage Change Control Register 1 (VCC1) 8h’20
Bit
7
MVS
0
6
MGO
0
5
SVS
0
4
SGO
0
3
2
1
AVS
0
0
AGO
0
Designation
Reset Value
Reserved
0
0
DVM Voltage Change Control Register 1 (VCC1) 8h’20 Definitions
Bit
Access
Name
Description
VCC_MVT (LDO1) Voltage Select
7
R/W
MVS
0 - Change VCC_MVT Output Voltage to MDVT1
1 - Change VCC_MVT Output Voltage to MDVT2
6
5
4
R/W
R/W
R/W
MGO
SVS
Start VCC_MVT (LDO1) Voltage Change
0 - Hold VCC_MVT Output Voltage at current Level
1 - Ramp VCC_MVT Output Voltage as selected by MVS
VCC_SRAM (LDO5) Voltage Select
0 - Change VCC_SRAM Output Voltage to SDTV1
1 - Change VCC_SRAM Output Voltage to SDTV2
SGO
Start VCC_SRAM (LDO5) Voltage Change
0 - Hold VCC_SRAM Output Voltage at current Level
1 - Change VCC_SRAM Output Voltage as selected by SVS
3:2
1
—
—
Reserved
R/W
AVS
VCC_APPS (Buck1) Voltage Select
0 - Ramp VCC_APPS Output Voltage to ADVT1
1 - Ramp VCC_APPS Output Voltage to ADVT2
0
R/W
AGO
Start VCC_APPS(Buck1) Voltage Change
0 - Hold VCC_APPS Output Voltage at current Level
1 - Ramp VCC_APPS Output Voltage as selected by AVS
BUCK1 (VCC_APPS) VOLTAGE 1
Buck1 (VCC_APPS) Target Voltage 1 Register (ADTV1) 8h’23
Bit
7
6
Reserved
0
5
4(1)
3(1)
2(1)
1(1)
0(1)
Designation
Reset Value
Buck1 Output Voltage (B1OV1)
0
0
0
1
0
1
1
(1) One-time factory programmable
Buck1 (VCC_APPS) Target Voltage 1 Register (ADTV1) 8h’23 Definitions
Bit
7:5
4:0
Access
—
Name
—
Description
Reserved
R/W
B1OV1
Data Code
5h’0
Output Voltage
Data Code
5h’10
5h’11
5h’12
5h’13
5h’14
5h’15
5h’16
5h’17
5h’18
5h’19
5h’1A
5h’1B
5h’1C
5h’1D
5h’1E
5h’1F
Output Voltage
1.125
0.725
0.750
0.775
0.800
0.825
0.850
0.875
0.900
0.925
0.950
0.975
1.000
1.025
1.050
1.075
1.100
5h’1
5h’2
5h’3
5h’4
5h’5
5h’6
5h’7
5h’8
1.150
1.175
1.200
1.225
1.250
1.275
1.300
1.325
1.350
1.375
1.400
1.425
1.450
1.475
1.500
5h’9
5h’A
5h’B
5h’C
5h’D
5h’E
5h’F
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BUCK1 (VCC_APPS) TARGET VOLTAGE 2 REGISTER
Buck1 (VCC_APPS) Target Voltage 2 Register (ADTV2) 8h’24
Bit
7
6
Reserved
0
5
4
3
2
1
0
Designation
Reset Value
Buck1 Output Voltage (B1OV2)
0
0
0
1
0
1
1
Buck1 (VCC_APPS) Target Voltage 2 Register (ADTV2) 8h’24 Definitions
Bit
7:5
4:0
Access
—
Name
—
Description
Reserved
Data Code
R/W
B1OV2
Output Voltage
Data Code
5h’10
5h’11
5h’12
5h’13
5h’14
5h’15
5h’16
5h’17
5h’18
5h’19
5h’1A
5h’1B
5h’1C
5h’1D
5h’1E
5h’1F
Output Voltage
1.125
5h’0
5h’1
5h’2
5h’3
5h’4
5h’5
5h’6
5h’7
5h’8
5h’9
5h’A
5h’B
5h’C
5h’D
5h’E
5h’F
0.725
0.750
0.775
0.800
0.825
0.850
0.875
0.900
0.925
0.950
0.975
1.000
1.025
1.050
1.075
1.100
1.150
1.175
1.200
1.225
1.250
1.275
1.300
1.325
1.350
1.375
1.400
1.425
1.450
1.475
1.500
BUCK1 (VCC_APPS) VOLTAGE RAMP CONTROL REGISTER
Buck1 (VCC_APPS) Voltage Ramp Control Register (AVRC) 8h’25
Bit
7
6
Reserved
0
5
4
3
2
1
0
Designation
Reset Value
Ramp Rate (B1RR)
0
0
0
0
1
1
0
Buck1 (VCC_APPS) Voltage Ramp Control Register (AVRC) 8h’25 Definitions
Bit
Access
Name
Description
7:5
—
—
Reserved
DVM Ramp Speed
Data Code
Ramp Rate (mV/uS)
5h’0
5h’1
Instant
1
5h’2
2
5h’3
3
5h’4
5h’5
4
5
4:0
R/W
B1RR
5h’6
6
5h’7
7
5h’8
8
5h’9
5h’A
4h’B-4h’1F
9
10
Reserved
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VCC_COMM TARGET VOLTAGE 1 DUMMY REGISTER (CDTV1)
VCC_COMM Target Voltage 1 Dummy Register (CDTV1) 8h’26 Write Only(1)
Bit
7
6
Reserved
0
5
4
3
2
1
0
Designation
Reset Value
Output Voltage
0
0
0
0
0
0
0
(1) CDTV1 must be writable by an I2C controller. This is a dummy register
VCC_COMM TARGET VOLTAGE 2 DUMMY REGISTER (CDTV2)
VCC_COMM Target Voltage 2 Dummy Register (CDTV2) 8h’27 Write Only(1)
Bit
7
6
Reserved
0
5
4
3
2
1
0
Designation
Reset Value
Output Voltage
0
0
0
0
0
0
0
(1) CDTV2 must be writable by an I2C controller. This is a dummy register and cannot be read.
This is a variable voltage supply to the internal SRAM of the Application processor.
LDO5 (VCC_SRAM) TARGET VOLTAGE 1 REGISTER
LDO5 (VCC_SRAM) Target Voltage 1 Register (SDTV1) 8H'29
Bit
7
6
Reserved
0
5
4(1)
3(1)
2(1)
1*(1)
0(1)
Designation
Reset Value
LDO 5 Output Voltage (L5OV)
0
0
0
0
1
1
1
(1) One-time factory programmable EPROM registers for default values
LDO5 (VCC_SRAM) Target Voltage 1 Register (SDTV1) 8h’29 Definitions
Bit
7:5
4:0
Access
—
Name
—
Description
Reserved
Data Code
R/W
B1OV
Output Voltage
—
Data Code
5h’10
5h’11
5h’12
5h’13
5h’14
5h’15
5h’16
5h’17
5h’18
5h’19
5h’1A
5h’1B
5h’1C
5h’1D
5h’1E
5h’1F
Output Voltage
1.125
5h’0
5h’1
5h’2
5h’3
5h’4
5h’5
5h’6
5h’7
5h’8
5h’9
5h’A
5h’B
5h’C
5h’D
5h’E
5h’F
—
—
—
—
1.150
1.175
1.200
1.225
1.250
1.275
1.300
1.325
1.350
1.375
1.400
1.425
1.450
1.475
1.500
0.850
0.875
0.900
0.925
0.950
0.975
1.000
1.025
1.050
1.075
1.100
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LDO5 (VCC_SRAM) TARGET VOLTAGE 2 REGISTER
LDO5 (VCC_SRAM) Target Voltage 2 Register (SDTV2) 8h’2A
Bit
7
6
Reserved
0
5
4
3
2
1
0
Designation
Reset Value
LDO 5 Output Voltage (L5OV)
0
0
0
0
1
1
1
LDO5 (VCC_SRAM) Target Voltage 2 Register (SDTV2) 8h’2A Definitions
Bit
7:5
4:0
Access
—
Name
—
Description
Reserved
Data Code
R/W
B1OV
Output Voltage
—
Data Code
5h’10
5h’11
5h’12
5h’13
5h’14
5h’15
5h’16
5h’17
5h’18
5h’19
5h’1A
5h’1B
5h’1C
5h’1D
5h’1E
5h’1F
Output Voltage
1.125
5h’0
5h’1
5h’2
5h’3
5h’4
5h’5
5h’6
5h’7
5h’8
5h’9
5h’A
5h’B
5h’C
5h’D
5h’E
5h’F
—
—
—
—
1.150
1.175
1.200
1.225
1.250
1.275
1.300
1.325
1.350
1.375
1.400
1.425
1.450
1.475
1.500
0.850
0.875
0.900
0.925
0.950
0.975
1.000
1.025
1.050
1.075
1.100
VCC_MVT is low tolerance regulated power supply for the application processor ring oscillator and logic for
communicating to the LP3972. VCC_MVT is enabled when SYS_EN is asserted and disabled when SYS_EN is
deasserted.
LDO1 (VCC_MVT) TARGET VOLTAGE 1 REGISTER (MDTV1)
LDO1 (VCC_MVT) Target Voltage 1 Register (MDTV1) 8h’32
Bit
7
6
Reserved
0
5
4(1)
3(1)
2(1)
1(1)
0(1)
Designation
Reset Value
Output Voltage (OV)
1
0
0
0
0
0
0
(1) One-time factory programmable EPROM registers for default values
LDO1 (VCC_MVT) Target Voltage 1 Register (MDTV1) 8h’32 Definitions
Bit
7:5
4:0
Access
—
Name
—
Description
Reserved
Data Code
R/W
L1OV
Output Voltage
1.700
Notes:
5h’0
5h’1
1.725
5h’2
1.750
5h’3
1.775
5h’4
5h’5
1.800
1.825
5h’6
1.850
5h’7
1.875
5h’8
1.900
5h’9
1.925
5h’A
5h’B
5h’C
5h’D-5h’F
1.950
1.975
2.000
Reserved
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LDO1 (VCC_MVT) TARGET VOLTAGE 2 REGISTER
LDO1 (VCC_MVT) Target Voltage 2 Register (MDTV2) 8h’33
Bit
7
6
Reserved
0
5
4
3
2
1
0
Designation
Reset Value
Output Voltage (OV)
0
0
0
0
1
1
1
LDO1 (VCC_MVT) Target Voltage 2 Register (MDTV2) 8h’33 Definitions
Bit
7:5
4:0
Access
—
Name
—
Description
Reserved
Data Code
R/W
L1OV
Output Voltage
1.700
Notes:
5h’0
5h’1
1.725
5h’2
1.750
5h’3
1.775
5h’4
5h’5
1.800
1.825
5h’6
1.850
5h’7
1.875
5h’8
1.900
5h’9
1.925
5h’A
5h’B
5h’C
5h’D-5h’F
1.950
1.975
2.000
Reserved
LDO2 VOLTAGE CONTROL REGISTER (L12VCR)
LDO2 Voltage Control Register (L12VCR) 8h’39
Bit
7(1)
6(1)
5(1)
4(1)
3
2
1
0
Designation
Reset Value
LDO2 Output Voltage (L2OV)
Reserved
0
0
0
0
0
0
0
0
(1) One-time factory programmable EPROM registers for default values
LDO2 Voltage Control Register (L12VCR) 8h’39 Definitions
Bit
Access
Name
Description
7:4
R/W
L2OV
Data Code
4h’0
4h’1
Output Voltage
1.8 (Default)
1.9
4h’2
2.0
4h’3
2.1
4h’4
2.2
4h’5
2.3
4h’6
2.4
4h’7
2.5
4h’8
2.6
4h’9
2.7
4h’A
4h’B
4h’C
4h’D
4h’E
4h’F
2.8
2.9
3.0
3.1
3.2
3.3
3:0
—
—
Reserved
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LDO4 – LDO3 VOLTAGE CONTROL REGISTER (L34VCR)
LDO4 – LDO3 Voltage Control Register (L34VCR) 8h’3A
Bit
7(1)
6(1)
5(1)
4(1)
3(1)
2(1)
1(1)
0(1)
Designation
Reset Value
LDO4 Output Voltage (L4OV)
LDO3 Output Voltage (L3OV)
0
0
0
0
0
0
0
0
(1) One-time factory programmable EPROM registers for default values
LDO4 – LDO3 Voltage Control Register (L34VCR) 8h’3A Definitions
Bit
Access
Name
Description
7:4
R/W
L4OV
Data Code
4h’0
4h’1
Output Voltage
1.00
1.05
4h’2
1.10
4h’3
1.15
4h’4
1.20
4h’5
1.25
4h’6
1.30
4h’7
1.35
4h’8
1.40
4h’9
1.50
4h’A
4h’B
4h’C
4h’D
4h’E
4h’F
1.80
1.90
2.50
2.80
3.00 (Default)
3.30
3:0
R/W
L3OV
Data Code
4h’0
Output Voltage
1.8
1.9
4h’1
4h’2
2.0
4h’3
2.1
4h’4
2.2
4h’5
2.3
4h’6
2.4
4h’7
2.5
4h’8
2.6
4h’9
2.7
4h’A
4h’B
4h’C
4h’D
4h’E
4h’F
2.8
2.9
3.0 (Default)
3.1
3.2
3.3
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SNVS468K –SEPTEMBER 2006–REVISED MAY 2013
TI DEFINED CONTROL AND STATUS REGISTERS
SYSTEM CONTROL REGISTER 1 (SCR1)
System Control Register 1 (SCR1) 8h’80
Bit
7(1)
BPSEN
0
6(1)
5(1)
4
FPWM3
0
3
FPWM2
0
2
FPWM1
0
1
0
BK_SSEN
0
Designation
Reset Value
SENDL
BK_SLOMOD
0
1
0
(1) One-time factory programmable EPROM registers for default values
System Control Register 1 (SCR1) 8h’80 Definitions
Bit
Access
Name
Description
7
R/W
BPSEN
Bypass System enable safety Lock. Prevents activation of PWR_EN
when SYS_EN is low.
0 = PWR_EN "AND" with SYS_EN signal, Default
1 = PWR_EN independent of SYS_EN
Delay time for High Voltage Power Domains LDO2, LDO3, LDO4,
Buck2, and Buck3 after activation of SYS_EN. VCC_LDO1 has no
delay.
Data Code
2h’0
Delay (ms)
6:5
R/W
SENDL
0.0
0.5
2h’1
2h’2
2h’3
1.0 (Default)
1.4
4
3
2
1
0
R/W
R/W
R/W
R
FPWM3
FPWM2
Buck3 PWM/PFM Mode select
0 - Auto Switch between PFM and PWM operation
1 - PWM Mode Only will not switch to PFM
Buck2 PWM/PFM Mode select
0 - Auto Switch between PFM and PWM operation
1 - PWM Mode Only will not switch to PFM
FPWM1
Buck1 PWM/PFM Mode select
0 - Auto Switch between PFM and PWM operation
1 - PWM Mode Only will not switch to PFM
BK_SLOMOD
BK_SSEN
Buck Spread Spectrum Modulation Bucks 1-3
0 = 10 kHz triangular wave spread spectrum modulation
1 = 2 kHz triangular wave spread spectrum modulation
R
Spread spectrum function Bucks 1-3
0 = SS Output Disabled
1 = SS Output Enabled
SYSTEM CONTROL REGISTER 2 (SCR2)
System Control Register 2 (SCR2) 8h’81
Bit
7
BBCS
1
6
SHBU
0
5(1)
BPTR
1
4
WUP3
1
3
2
1
0
Designation
GPIO2
GPIO1
0
0
1
0
(1) One time factory programmable EPROM registers for default values
System Control Register 2 (SCR2) 8h’81 Definitions
Bit
Access
Name
Description
7
R/W
BBCS
Sets GPIO1 as control input for Back Up battery charger
0 - Back Up battery Charger GPIO Disabled
1 - Back Up battery Charger GPIO Pin Enabled
Shut down Back up battery to prevent battery drain during shipping
0 = Back up Battery Enabled
6
R/W
SHBU
1 = Back up battery Disabled
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Bit
Access
Name
Description
5
R/W
BPTR
Bypass LDO_RTC Output Voltage to LDO3 Output Voltage Tracking
0 - LDO_RTC3 Tracking enabled
1 - LDO_RTC3 Tracking disabled, Default
4
R/W
R/W
WUP3
GPIO2
Spare Wakeup control input
0 - Active High
1 - Active Low
3:2
Configure direction and output sense of GPIO2 Pin
Data Code
2h’00
GPIO2
Hi-Z
2h’01
2h’02
Output Low
Input
2h’03
Output high
1:0
R/W
GPIO1
Configure direction and output sense of GPIO1 Pin
Data Code
2h’00
GPIO1
Hi-Z
2h’01
2h’02
Output Low
Input
2h’03
Output high
OUTPUT ENABLE 3 REGISTER (OEN3) 8H’82
Bit
7
6
Reserved
0
5
4(1)
B3EN
1
3
2(1)
B2EN
1
1
Reserved
0
0(1)
L1EN
1
Designation
Reset Value
ENFLAG
0
0
0
(1) One time factory programmable EPROM registers for default values
OUTPUT ENABLE 3 REGISTER (OEN3) 8H’82 DEFINITIONS
Bit
7:5
4
Access
—
Name
—
Description
Reserved
R/W
B3EN
VCC_Buck3 Supply Output Enabled
0 = VCC_Buck3 Supply Output Disabled
1 = VCC_Buck3 Supply Output Enabled, Default
3
2
R/W
R/W
ENFLAG
B2EN
Enable for Temperature Flags (BCT)
0 = Temperature Flag Disabled
1 = Temperature Flag Enabled
VCC_Buck2 Supply Output Enabled
0 = VCC_Buck2 Supply Output Disabled
1 = VCC_Buck2 Supply Output Enabled, Default
1
0
—
—
Reserved
R/W
L1EN
LDO1 (MVT)Output Voltage Enable
0 = LDO1 Supply Output Disabled
1 = LDO1 Supply Output Enabled, Default
STATUS REGISTER 3 (OSR3) 8H’83
Bit
7
BT_OK
0
6
B3_OK
0
5
B2_OK
0
4
LDO1_OK
0
3
Reserved
0
2
BCT2
0
1
BCT1
0
0
BCT0
0
Designation
Reset Value
STATUS REGISTER 3 (OSR3) DEFINITIONS 8H’83
Bit
Access
Name
Description
7
R
BT_OK
Bucks 2-3 Supply Output Voltage Status
0 - (Bucks 1-3) output voltage < 90% Default value
1 - (Bucsk 1-3) output voltage > 90% Default value
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SNVS468K –SEPTEMBER 2006–REVISED MAY 2013
Bit
Access
Name
Description
6
R
B3_OK
Buck3 Supply Output Voltage Status
0 - (Buck3) output voltage < 90% Default value
1 - (Buck3) output voltage > 90% Default value
5
4
R
R
B2_OK
Buck2 Supply Output Voltage Status
0 - (Buck2) output voltage < 90% Default value
1 - (Buck2) output voltage > 90% Default value
LDO1_OK
LDO1 Output Voltage Status
0 - (VCC_LDO1) output voltage < 90% of selected value
1 - (VCC_LDO1) output voltage > 90% of selected value
3
—
R
—
Reserved
2:0
BCT
Binary coded thermal management flag status register
Temperature
Data Code
000
Ascending °C
40
60
001
010
80
011
100
100
120
101
140
110
160
111
Reserved
LOGIC OUTPUT ENABLE REGISTER (LOER) 8H’84
Bit
7
Reserved
0
6(1)
B3ENC
1
5(1)
B2ENC
1
4(1)
3(1)
L5EC
0
2(1)
1(1)
L3EC
1
0(1)
L2EC
1
Designation
Reset Value
B1ENC
0
L4EC
1
(1) One time factory programmable EPROM registers for default values
LOGIC OUTPUT ENABLE REGISTER (LOER) DEFINITIONS 8H’84
Bit
7
Access
—
Name
—
Description
Reserved
6
R/W
B3ENC
Connects Buck3 enable to SYS_EN or PWR_EN Logic Control pin
0 - Buck3 enable connected to PWR_EN
1 - Buck3 enable connected to SYS_EN, Default
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
B2ENC
B1ENC
L5EC
Connects Buck2 enable to SYS_EN or PWR_EN Logic Control pin
0 - Buck2 enable connected to PWR_EN
1 - Buck2 enable connected to SYS_EN, Default
Connects Buck1 enable to SYS_EN or PWR_EN Logic Control pin
0 - Buck1 enable connected to PWR_EN, Default
1 - Buck1 enable connected to SYS_EN
Connects LDO5 enable to SYS_EN or PWR_EN Logic Control pin
0 - LDO5 enable connected to PWR_EN, Default
1 - LDO5 enable connected to SYS_EN
L4EC
Connects LDO4 enable to SYS_EN or PWR_EN Logic Control pin
0 - LDO4 enable connected to PWR_EN
1 - LDO4 enable connected to SYS_EN, Default
L3EC
Connects LDO3 enable to SYS_EN or PWR_EN Logic Control pin
0 - LDO3 enable connected to PWR_EN
1 - LDO3 enable connected to SYS_EN, Default
L2EC
Connects LDO2 enable to SYS_EN or PWR_EN Logic Control pin
0 - LDO2 enable connected to PWR_EN
1 - LDO2 enable connected to SYS_EN, Default
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VCC_BUCK2 TARGET VOLTAGE REGISTER (B2TV) 8H’85
Bit
7
6
Reserved
0
5
4(1)
3(1)
2(1)
1(1)
0(1)
Designation
Reset Value
Buck2 Output Voltage (B2OV)
0
0
0
1
1
0
1
(1) One time factory programmable EPROM registers for default values
VCC_BUCK2 TARGET VOLTAGE REGISTER (B2TV) 8H’85 DEFINITIONS
Bit
7:5
4:0
Access
—
Name
Description
Reserved
R/W
B2OV
Output Voltage
Data Code
5h’01
5h’02
5h’03
5h’04
5h’05
5h’06
5h’07
5h’08
5h’09
5h’0A
5h’0B
5h’0C
(V)
Data Code
(V)
0.80
0.85
0.90
0.95
1.00
1.05
1.10
1.15
1.20
1.25
1.30
1.35
5h’0D
5h’0E
5h’0F
5h’10
5h’11
5h’12
5h’13
5h’14
5h’15
5h’16
5h’17
5h’18
5h’19
1.40
1.45
1.50
1.55
1.60
1.65
1.70
1.80
1.90
2.50
2.80
3.00
3.30
BUCK3 TARGET VOLTAGE REGISTER (B3TV) 8H’86
Bit
7
6
Reserved
0
5
4(1)
3(1)
2(1)
1(1)
0(1)
Designation
Reset Value
Buck3 Output Voltage (B3OV)
1
0
0
1
0
0
0
(1) One time factory programmable EPROM registers for default values
BUCK3 TARGET VOLTAGE REGISTER (B3TV) 8H’86 DEFINITIONS
Bit
7:5
4:0
Access
—
Name
Description
Reserved
R/W
B3OV
Output Voltage
Data Code
5h’01
5h’02
5h’03
5h’04
5h’05
5h’06
5h’07
5h’08
5h’09
5h’0A
5h’0B
5h’0C
(V)
Data Code
5h’0D
5h’0E
5h’0F
5h’11
5h’12
5h’13
5h’14
5h’15
5h’16
5h’17
5h’18
5h’19
(V)
0.80
0.85
0.90
0.95
1.00
1.05
1.10
1.15
1.20
1.25
1.30
1.35
1.40
1.45
1.50
1.60
1.65
1.70
1.80
1.90
2.50
2.80
3.00
3.30
Default
VCC_BUCK3:2 VOLTAGE RAMP CONTROL REGISTER (B32RC)
VCC_Buck3:2 Voltage Ramp Control Register (B32RC) 8h’87
Bit
7
6
5
4
3
2
1
0
Designation
Ramp Rate (B3RR)
Ramp Rate (B2RR)
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SNVS468K –SEPTEMBER 2006–REVISED MAY 2013
Bit
7
6
5
4
3
2
1
0
Reset Value
1
0
1
0
1
0
1
0
Buck3:2 Voltage Ramp Control Register (B3RC) 8h’87 Definitions
Bit
Access
Name
Description
7:4
R/W
B3RR
Data Code
4h’0
Ramp Rate mV/µS
Instant
4h’1
4h’2
1
2
4h’3
3
4h’4
4
4h’5
5
4h’6
6
4h’7
7
4h’8
8
4h’9
9
4h’A
10
3:0
R/W
B2RR
Data Code
4h’0
Ramp Rate mV/µS
Instant
4h’1
4h’2
1
2
4h’3
3
4h’4
4
4h’5
5
4h’6
6
4h’7
7
4h’8
8
4h’9
9
4h’A
10
INTERRUPT STATUS REGISTER ISRA
This register specifies the status bits for the interrupts generated by the PMIC. Thermal warning of the IC,
GPIO1, GPIO2, PWR_ON pin, TEST_JIG factory programmable on signal, and the SPARE pin.
Interrupt Status Register ISRA 8h’88
Bit
7
Reserved
0
6
T125
0
5
GPI2
0
4
GPI1
0
3
WUP3
0
2
WUP2
0
1
WUPT
0
0
WUPS
0
Designation
Reset Value
Interrupt Status Register ISRA 8h’88 Definitions
Bit
7
Access
Name
—
Description
—
R
Reserved
6
T125
Status bit for thermal warning PMIC T>125C
0 = PMIC Temp. < 125°C
1 = PMIC Temp. > 125°C
5
4
3
2
R
R
R
R
GPI2
GPI1
Status bit for the input read in from GPIO 2 when set as Input
0 = GPI2 Logic Low
1 = GPI2 Logic High
Status bit for the input read in from GPIO 1 when set as Input
0 = GPI1 Logic Low
1 = GPI1 Logic High
WUP3
WUP2
PWR_ON Pin long pulse Wake Up Status
0 = No wake up event
1 = Long pulse wake up event
PWR_ON Pin Short pulse Wake Up Status
0 = No wake up event
1 = Short pulse wake up event
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Bit
Access
Name
Description
1
R
WUPT
TEST_JIG Pin Wake Up Status
0 = No wake up event
1 = Wake up event
0
R
WUPS
SPARE Pin Wake Up Status
0 = No wake up event
1 = Wake up event
BACKUP BATTERY CHARGER CONTROL REGISTER (BCCR)
This register specifies the status of the main battery supply. NBUB bit
Backup Battery Charger Control Register (BCCR) 8h’89
Bit
7(1)
NBUB
0
6
CNBFL
0
5(1)
4(1)
nBFLT
1
3(1)
2
BUCEN
0
1
0
Designation
Reset Value
IBUC
0
0
0
1
(1) One time factory programmable EPROM registers for default values
Backup Battery Charger Control Register (BCCR) 8h’89 Definitions
Bit
Access
Name
Description
7
R/W
NBUB
No back-up battery default setting. Logic will not allow switch over to back-up
battery.
0 = Back up Battery Enabled, Default
1 = Back up Battery Disabled
6
R/W
CNBFL
Control for nBATT_FLT output signal
0 = nBATT_FLT Enabled
1 = nBATT_FLT Disabled
nBATT_FLT monitors the battery voltage and can be set to the Assert voltages
listed below.
Data Code
3h’01
Asserted
2.6
De-Asserted
2.8
3.0 (Default)
3.2
5:3
2
R/W
R/W
BFLT
3h’02
3h’03
3h’04
3h’05
2.8
3.0
3.2
3.4
3.4
3.6
BUCEN
Enables backup battery charger
0 = Back up Battery Charger Disabled
1 = Back up Battery Charger Enabled
Charger current setting for back-up battery
Data Code
2h’00
2h’01
BU Charger I (µA)
260
190 (Default)
325
1:0
R/W
IBUC
2h’02
2h’03
390
MARVELL PXA INTERNAL 1 REVISION REGISTER (II1RR) 8H’8E
Bit
7
6
5
4
3
2
1
0
Designation
Reset Value
II1RR
0
0
0
0
0
0
0
0
MARVELL PXA INTERNAL 1 REVISION REGISTER (II1RR) 8H’8E DEFINITIONS
Bit
Access
Name
Description
7:0
R
II1RR
Intel internal usage register for revision information.
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SNVS468K –SEPTEMBER 2006–REVISED MAY 2013
MARVELL PXA INTERNAL 2 REVISION REGISTER (II2RR) 8H’8F
Bit
7
6
5
4
3
2
1
0
Designation
Reset Value
II2RR
0
0
0
0
0
0
0
0
MARVELL PXA INTERNAL 2 REVISION REGISTER (II2RR) 8H’8F DEFINITIONS
Bit
Access
Name
Description
7:0
R
II2RR
Intel internal usage register for revision information.
REGISTER PROGRAMMING EXAMPLES
Example 1) Start of Day Sequence
PMIC Register
Address
PMIC Register
Name
Register Data
Description
8h’23
8h’29
8h’10
ADTVI
SDTV1
OVER1
00011011
00011011
00000111
Sets the SOD VCC_APPS voltage
Sets the SOD VCC_SRAM voltage
Enables VCC_SRAM and VCC_APPS to their programmed values.
SODl Multi-byte random register transfer is outlined below:
Device ID
W
Ack
Start
0
1
1
0
1
1
0
0
0
1
1
0
0 0
ADTV1 (8Z[23)
Register Address
Register Data (00011011)
Data
Ack
Ack
Ack
Ack
0
0
1
0
0
0
0 0 0 1 1 0 1 1
SDTV1 (8Z[29)
Register Address
Register Data (00011011)
Data
Ack
0
0
1
0
1
0
0 0 0 1 1 0 1 1
OVER1 (8Z[10)
Register Address
Register Data (00000111)
Data
Ack Stop
0
0
0
1
0
0
0 0 0 0 0 1 1 1
Figure 26.
Device Address,
Register A Address, Ach,
Register A Data, Ach
Register M Address, Ach,
Register M Data, Ach
Register X Address, Ach,
Register X Data, Ach
Register Z Address, Ach,
Register Z Data, Ach, Stop
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Example 2) Voltage change Sequence
PMIC Register
Address
PMIC Register
Name
Register Data
Description
8h’24
8h’2A
8h’20
ADTV2
SDTV2
00010111
00001111
00110011
Sets the VCC_APPS target voltage 2 to 1.3 V
Sets the VCC_SRAM target voltage 2 to 1.1 V
VCC1
Enable VCC_SRAM and VCC_APPS to change to their programmed target
values.
I2C DATA EXCHANGE BETWEEN MASTER AND SLAVE DEVICE
Device ID
W
Ack
Start
0
1
1
0
1
0
1
0
0
0
0
0
0 0
ADTV2 (8Z[24)
Register Address
Register Data (00010111)
Data
Ack
Ack
Ack
Ack
0
0
1
0
0
1
0 0 0 1 0 1 1 1
SDTV2 (8Z[2A)
Register Address
Register Data (00001111)
Data
Ack
0
0
1
0
1
0
0 0 0 0 1 1 1 1
VCC1 (8Z[20)
Register Address
Register Data (00110011)
Data
Ack Stop
0
0
1
0
0
0
0 0 1 1 0 0 1 1
Figure 27.
LP3972 Controls
DIGITAL INTERFACE CONTROL SIGNALS
Signal
Definition
Active State
High
Signal Direction
Input
SYS_EN
PWR_EN
SCL
High Voltage Power Enable
Low Voltage Power Enable
Serial Bus Clock Line
High
Input
Clock
Input
SDA
Serial Bus Data Line
Bidirectional
Input
nRSTI
Forces an unconditional
hardware reset
Low
Low
Low
nRSTO
Forces an unconditional
hardware reset
Output
Output
nBATT_FLT
Main Battery removed or
discharged indicator
PWR_ON
nTEST_JIG
SPARE
Wakeup Input to CPU
Wakeup Input to CPU
Wakeup Input to CPU
High
Low
Input
Input
High/Low
High
Input
EXT_WAKEUP
GPIO1 / nCHG_EN
GPIO2
Wake-Up Output for application
processor
Output
General Purpose I/O /External
Back-up Battery Charger enable
—
—
Bidirectional /Input
Bidirectional
General Purpose I/O
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POWER DOMAIN ENABLES
PMU Output
LDO_RTC
HW Enable
SW Enable
—
—
LDO1 (VCC_MVT)
LDO2
SYS_EN
SYS_EN
SYS_EN
SYS_EN
PWR_EN
PWR_EN
SYS_EN
SYS_EN
LDO1_EN
LDO2_EN
LDO3_EN
LDO4_EN
S_EN
LDO3
LDO4
LDO5 (VCC_SRAM)
Buck1 (VCC_APPS)
BUCK2
A_EN
B2_EN
B3_EN
BUCK3
POWER DOMAINS SEQUENCING (DELAY)
By default SYS_EN must be on to have PWR_EN enable but this feature can be switched off by register bit
BP_SYS.
By default SYS_EN enables LDO1 always first and after a typical of 1 ms delay others. Also when SYS_EN is
set off the LDO1 will go off last. This function can be switched off or delay can be changed by DELAY bits via
serial interface as seen on table below.
8h’80 Bit 5:4
DELAY bits
Delay, ms
‘00’
0
‘01’
0.5
‘10’
1.0
‘11’
1.5
LDO_RTC TRACKING (nIO_TRACK)
LP3972 has a tracking function (nIO_TRACK). When enabled, LDO_RTC voltage will track LDO3 voltage within
200 mV down to 2.8V when LDO3 is enabled. This function can be switched on/off by nIO_TRACK register bit
BPTR.
POWER SUPPLY ENABLE
SYS_EN and PWR_EN can be changed by programmable register bits.
WAKE-UP FUNCTIONALITY (PWR_ON, nTEST_JIG, SPARE AND EXT_WAKEUP)
Three input pins can be used to assert wakeup output for 10 ms for application processor notification to wakeup.
SPARE Input can be programmed through I2C compatible interface to be active low or high (SPARE bit, Default
is active low ‘1’). A reason for wakeup event can be read through I2C compatible interface also. Additionally
wakeup inputs have 30 ms de-bounce filtering. Furthermore PWR_ON have distinguishing between short and
long (∼1s) pulses (push button input). LP3972 also has an internal Thermal Shutdown early warning that
generates a wakeup to the system also. This is generated usually at 125°C.
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PWR_ON
nTEST_JIG
SPARE
OR
EXT_WAKEUP
PWR_ON
nTEST_JIG
SPARE
EXT_WAKEUP
10 ms
Internal Thermal Early Warning
Figure 28.
WAKEUP register bits
WUP0
Reason for WAKEUP
SPARE
WUP1
TEST_JIG
WUP2
PWR_ON short pulse
PWR_ON long pulse
TSD Early Warning
WUP3
TSD_EW
INTERNAL THERMAL SHUTDOWN PROCEDURE
Thermal shutdown is build to generate early warning (typ. 125°C) which triggers the EXT_WAKEUP for the
processor acknowledge. When a thermal shutdown triggers (typ. 160°C) the PMU will reset the system until the
device cools down.
BATTERY SWITCH AND BACK UP BATTERY CHARGER
When Back-Up battery is connected but the main battery has been removed or its supply voltage too low,
LP3972 uses Back-Up Battery for generating LDO_RTC voltage. When Main Battery is available the battery FET
switches over to the main battery for LDO_RTC voltage. When Main battery voltage is too low or removed
nBATT_FLT is asserted. If no back up battery exists, the battery switch to back up can be switched off by
nBU_BAT_EN bit. User can set the battery fault determination voltage and battery charger current via I2C
compatible interface. Enabling of back up battery charger can be done via serial interface (nBAT_CHG_EN) or
external charger enable pin (nCHG_EN). Pin 29 is set as external charger enable input by default.
GENERAL PURPOSE I/O FUNCTIONALITY (GPIO1 AND GPIO2)
LP3972 has 2 general purpose I/Os for system control. I2C compatible interface will be used for setting any of the
pins to input, output or hi-Z mode. Inputs value can be read via serial interface (GPIO1,2 bits). The pin 29
functionality needs to be set to GPIO by serial interface register bit nEXTCHGEN. (GPIO/CHG)
Controls
Nextchgen_sel
Port Function
GPIO1
Reg
batmonchg
Function
GPIO<1>
GPIO<1>
bucen
Gpin 1
X
X
1
X
0
1
0
X
X
0
X
0
0
1
1
1
1
X
0
0
0
0
0
Input = 0
Input = 1
X
0
0
0
Enabled
Not Enabled
X
1
X
Enabled
X
X
X
HiZ
Input (dig)->
Output = 0
Input
0
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Controls
Nextchgen_sel
Port Function
GPIO1
Reg
Gpin 1
0
batmonchg
Function
GPIO<1>
GPIO<1>
1
bucen
X
1
0
Output = 1
GPIO<1>
GPIO<1>
Factory fm disabled
GPIO_tstiob
GPIO2
gpin2
0
1
0
1
0
0
1
1
1
1
1
1
HiZ
0
input
0
Input (dig)->
Output = 0
Output = 1
0
The LP3972 has provision for two battery connections, the main battery VBAT and Backup Battery (See
Applications Schematic Diagrams 1 & 2 of the LP3972 Data Sheet).
The function of the battery switch is to connect power to the LDO_RTC from the appropriate battery, depending
on conditions described below:
•
•
•
If only the backup battery is applied, the switch will automatically connect the LDO_RTC power to this battery.
If only the main battery is applied, the switch will automatically connect the LDO_RTC power to this battery.
If both batteries are applied, and the main battery is sufficiently charged (VBAT > 3.1V), the switch will
automatically connect the RTC LDO power to the main battery.
•
As the main battery is discharged by use, the user will be warned by a separate circuit called nBATT_FLT.
Then if no action is taken to restore the charge on the main battery, and discharging is continued the battery
switch will protect the LDO_RTC by disconnecting from the main battery and connecting to the backup
battery.
–
–
The main battery voltage at which the LDO_RTC is switched from main to backup battery is 2.9V typically.
There is a hysteresis voltage in this switch operation so, the LDO_RTC will not be reconnected to main
battery until main battery voltage is greater than 3.1V typically.
•
Additionally, the user may wish to disable the battery switch, such as, in the case when only a main battery is
used. This is accomplished by setting the "no back up battery bit" in the control register 8h’89 bit 7 NBUB.
With this bit set to "1", the above described switching will not occur, that is the LDO_RTC will remain
connected to the main battery even as it is discharged below the 2.9 Volt threshold.
REGULATED VOLTAGES OK
All the power domains have own register bit (X_OK) that processor can read via serial interface to be sure that
enabled powers are OK (regulating). Note that these read only bits are only valid when regulators are settled
(avoid reading these bits during voltage change or power up).
THERMAL MANAGEMENT
Application: There is a mode wherein all 6 comparators (flags) can be turned on via the "enallflags" control
register bit. This mode allows the user to interrogate the device or system temperature under the set operating
conditions. Thus, the rate of temperature change can also be estimated. The system may then negotiate for
speed and power trade off, or deploy cooling maneuvers to optimize system performance. The "enallflags" bit
needs enabled only when the "bct<2:0> bits are read to conserve power.
Note: The thermal management flags have been verified functional. Presently these registers are accessible by
factory only. If there is a demand for this function, the relevant register controls may be shifted into the user
programmable bank; the temperature range and resolution of these flags, might also be refined/redefined.
THERMAL WARNING
2 of 6 low power comparators, each consumes less than 1 µA, are always enabled to operate the "T=125°C
warning flag with hysteresis. This allows continuous monitoring of a thermal-warning flag feature with very low
power consumption.
LP3972 THERMAL FLAGS FUNCTIONAL DIAGRAM, DATA FROM INITIAL SILICON
The following functions are extra features from the thermal shutdown circuit:
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1) Thermal warning flag @ Temp ~ > ~125oC is issued at the wakeup port:
~30oC hysteresis
Temp 125oC
Warning flag
2) Binary coded thermal management flags in status registers, bct<2:0>:
flag6
flag5
flag4
flag3
flag2
flag1
cool
17oC 20oC 43oC 46oC 62oC 65oC 83oC 86oC 106oC108oC 128oC 130oC
Temp
Figure 29.
Application Note - LP3972 Reset Sequence
INITIAL COLD START POWER ON SEQUENCE
1. The Back up battery is connected to the PMU, power is applied to the back-up battery pin, the LDO_RTC
turns on and supplies a stable output voltage to the VCC_BATT pin of the Applications processor (initiating
the power-on reset event) with nRSTO asserted from the LP3972 to the processor.
2. nRSTO de-asserts after a minimum of 50 mS.
3. The Applications processor waits for the de-assertion of nBATT_FLT to indicate system power (VIN) is
available.
4. After system power (VIN) is applied, the LP3972 de-asserts nBATT_FLT. Note that BOTH nRSTO and
nBATT_FLT need to be de-asserted before SYS_EN is enabled. The sequence of the two signals is
independent of each other.
5. The Applications processor asserts SYS_EN, the LP3972 enables the system high-voltage power supplies.
The Applications processor starts its countdown timer set to 125 mS.
6. The LP3972 enables the high-voltage power supplies.
–
LDO1 power for VCC_MVT (Power for internal logic and I/O Blocks), BG (Bandgap reference voltage),
OSC13M (13 MHz oscillator voltage) and PLL enabled first, followed by others if delay is on.
7. Countdown timer expires; the Applications processor asserts PWR_EN to enable the low-voltage power
supplies. The processor starts the countdown timer set to 125 mS period.
8. The Applications processor asserts PWR_EN (ext. pin or I2C), the LP3972 enables the low-voltage
regulators.
9. Countdown timer expires; If enabled power domains are OK (I2C read) the power up sequence continues by
enabling the processors 13 MHz oscillator and PLL’s.
10. The Applications processor begins the execution of code.
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t
t
t
4
1
3
BU Batt
V
IN
1.
VCC_RTC
nRSTO
2.
V
Main Batt
IN
3,4.
nBATT_FLT
5.
6.
SYS_EN
PXA27x Output
High-Volt_PD
PWR_EN
7.
PXA27x Output
8.
Low-Volt_PD
t
2
t
5
nRESET_OUT
13 MHZ_OSC
PXA27x Output
PXA27x Output
9,10.
* Note that BOTH nRSTO and nBATT_FLT need to be de-asserted before SYS_EN is enabled. The sequence of the
two signals is independent of each other and can occur is either order.
Figure 30.
POWER-ON TIMING
Symbol
Description
Min
Typ
Max
Unit
mS
µS
t1
t2
t3
t4
t5
Delay from VCC_RTC assertion to nRSTO de-assertion
Delay from nBATT_FLT de-assertion to nRSTI assertion
Delay from nRST de-assertion to SYS_EN assertion
Delay from SYS_EN assertion to PWR_EN assertion
Delay from PWR_EN assertion to nRSTO de-assertion
50
100
10
mS
mS
mS
125
125
HARDWARE RESET SEQUENCE
Hardware reset initiates when the nRSTI signal is asserted (low). Upon assertion of nRST the processor enters
hardware reset state. The LP3972 holds the nRST low long enough (50 ms typ.) to allow the processor time to
initiate the reset state.
RESET SEQUENCE
1. nRSTI is asserted.
2. nRSTO is asserted and will de-asserts after a minimum of 50 mS
3. The Applications processor waits for the de-assertion of nBATT_FLT to indicate system power (VIN) is
available.
4. After system power (VIN) is turned on, the LP3972 de-asserts nBATT_FLT.
5. The Applications processor asserts SYS_EN, the LP3972 enables the system high-voltage power supplies.
The Applications processor starts its countdown timer.
6. The LP3972 enables the high-voltage power supplies.
7. Countdown timer expires; the Applications processor asserts PWR_EN to enable the low-voltage power
supplies. The processor starts the countdown timer.
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8. The Applications processor asserts PWR_EN, the LP3972 enables the low-voltage regulators.
9. Countdown timer expires; If enabled power domains are OK (I2C read) the power up sequence continues by
enabling the processors 13 MHz oscillator and PLL’s.
10. The Applications processor begins the execution of code.
APPLICATION HINTS
LDO CONSIDERATIONS
External Capacitors
The LP3972’s regulators require external capacitors for regulator stability. These are specifically designed for
portable applications requiring minimum board space and smallest components. These capacitors must be
correctly selected for good performance.
Input Capacitor
An input capacitor is required for stability. It is recommended that a 1.0 µF capacitor be connected between the
LDO input pin and ground (this capacitance value may be increased without limit).
This capacitor must be located a distance of not more than 1 cm from the input pin and returned to a clean
analogue ground. Any good quality ceramic, tantalum, or film capacitor may be used at the input.
Important: Tantalum capacitors can suffer catastrophic failures due to surge current when connected to a low
impedance source of power (like a battery or a very large capacitor). If a tantalum capacitor is used at the input,
it must be ensured by the manufacturer to have a surge current rating sufficient for the application.
There are no requirements for the ESR (Equivalent Series Resistance) on the input capacitor, but tolerance and
temperature coefficient must be considered when selecting the capacitor to ensure the capacitance will remain
approximately 1.0 µF over the entire operating temperature range.
Output Capacitor
The LDOs are designed specifically to work with very small ceramic output capacitors. A 1.0 µF ceramic
capacitor (temperature types Z5U, Y5V or X7R) with ESR between 5 mΩ to 500 mΩ, are suitable in the
application circuit.
For this device the output capacitor should be connected between the VOUT pin and ground.
It is also possible to use tantalum or film capacitors at the device output, COUT (or VOUT), but these are not as
attractive for reasons of size and cost (see the section Capacitor Characteristics).
The output capacitor must meet the requirement for the minimum value of capacitance and also have an ESR
value that is within the range 5 mΩ to 500 mΩ for stability.
No-Load Stability
The LDOs will remain stable and in regulation with no external load. This is an important consideration in some
circuits, for example CMOS RAM keep-alive applications.
Capacitor Characteristics
The LDOs are designed to work with ceramic capacitors on the output to take advantage of the benefits they
offer. For capacitance values in the range of 0.47 µF to 4.7 µF, ceramic capacitors are the smallest, least
expensive and have the lowest ESR values, thus making them best for eliminating high frequency noise. The
ESR of a typical 1.0 µF ceramic capacitor is in the range of 20 mΩ to 40 mΩ, which easily meets the ESR
requirement for stability for the LDOs.
For both input and output capacitors, careful interpretation of the capacitor specification is required to ensure
correct device operation. The capacitor value can change greatly, depending on the operating conditions and
capacitor type. In particular, the output capacitor selection should take account of all the capacitor parameters, to
ensure that the specification is met within the application. The capacitance can vary with DC bias conditions as
well as temperature and frequency of operation. Capacitor values will also show some decrease over time due to
aging. The capacitor parameters are also dependant on the particular case size, with smaller sizes giving poorer
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performance figures in general. As an example, Figure 31 shows a typical graph comparing different capacitor
case sizes in a Capacitance vs. DC Bias plot. As shown in the graph, increasing the DC Bias condition can result
in the capacitance value falling below the minimum value given in the recommended capacitor specifications
table. Note that the graph shows the capacitance out of spec for the 0402 case size capacitor at higher bias
voltages. It is therefore recommended that the capacitor manufacturers’ specifications for the nominal value
capacitor are consulted for all conditions, as some capacitor sizes (e.g. 0402) may not be suitable in the actual
application.
0603, 10V, X5M
100%
80%
60%
40%
0402, 6.3V, X5R
20%
0
1.0
2.0
3.0
4.0
5.0
DC BIAS (V)
Figure 31. Graph Showing a Typical Variation in Capacitance vs. DC Bias
The ceramic capacitor’s capacitance can vary with temperature. The capacitor type X7R, which operates over a
temperature range of −55°C to +125°C, will only vary the capacitance to within ±15%. The capacitor type X5R
has a similar tolerance over a reduced temperature range of −55°C to +85°C. Many large value ceramic
capacitors, larger than 1 µF are manufactured with Z5U or Y5V temperature characteristics. Their capacitance
can drop by more than 50% as the temperature varies from 25°C to 85°C. Therefore X7R is recommended over
Z5U and Y5V in applications where the ambient temperature will change significantly above or below 25°C.
Tantalum capacitors are less desirable than ceramic for use as output capacitors because they are more
expensive when comparing equivalent capacitance and voltage ratings in the 0.47 µF to 4.7 µF range.
Another important consideration is that tantalum capacitors have higher ESR values than equivalent size
ceramics. This means that while it may be possible to find a tantalum capacitor with an ESR value within the
stable range, it would have to be larger in capacitance (which means bigger and more costly) than a ceramic
capacitor with the same ESR value. It should also be noted that the ESR of a typical tantalum will increase about
2:1 as the temperature goes from 25°C down to –40°C, so some guard band must be allowed.
BUCK CONSIDERATIONS
Inductor Selection
There are two main considerations when choosing an inductor; the inductor should not saturate, and the inductor
current ripple is small enough to achieve the desired output voltage ripple. Different saturation current rating
specs are followed by different manufacturers so attention must be given to details. Saturation current ratings are
typically specified at 25°C so ratings at max ambient temperature of application should be requested from
manufacturer.
There are two methods to choose the inductor saturation current rating.
Method 1
The saturation current is greater than the sum of the maximum load current and the worst case average to peak
inductor current. This can be written as
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ISAT > IOUTMAX + IRIPPLE
«
∆
≈
*
«
∆
∆
«
∆
∆
≈
≈
∆
∆
«
≈
∆
∆
«
≈
∆
∆
«
VIN - VOUT
VOUT
VIN
1
f
∆
where IRIPPLE
=
≈
*
L
2
*
where
•
IRIPPLE: Average to peak inductor current
•
•
•
•
•
IOUTMAX: Maximum load current (1500 mA)
VIN: Maximum input voltage in application
L: Min inductor value including worst case tolerances (30% drop can be considered for method 1)
f: Minimum switching frequency (1.6 MHz)
VOUT: Output voltage
(2)
Method 2
A more conservative and recommended approach is to choose an inductor that has saturation current rating
greater than the max current limit of 3A.
A 2.2 µH inductor with a saturation current rating of at least 3A is recommended for most applications. The
inductor’s resistance should be less than 0.3Ω for a good efficiency. Table 1 lists suggested inductors and
suppliers. For low-cost applications, an unshielded bobbin inductor could be considered. For noise critical
applications, a toroidal or shielded bobbin inductor should be used. A good practice is to lay out the board with
overlapping footprints of both types for design flexibility. This allows substitution of a low-noise shielded inductor,
in the event that noise from low-cost bobbin models is unacceptable.
Input Capacitor Selection
A ceramic input capacitor of 10 µF, 6.3V is sufficient for most applications. Place the input capacitor as close as
possible to the VIN pin of the device. A larger value may be used for improved input voltage filtering. Use X7R or
X5R types, do not use Y5V. DC bias characteristics of ceramic capacitors must be considered when selecting
case sizes like 0805 and 0603. The input filter capacitor supplies current to the PFET switch of the converter in
the first half of each cycle and reduces voltage ripple imposed on the input power source. A ceramic capacitor’s
low ESR provides the best noise filtering of the input voltage spikes due to this rapidly changing current. Select a
capacitor with sufficient ripple current rating. The input current ripple can be calculated as:
«
r2
∆
VOUT
VIN
VOUT
VIN
≈
∆
∆
*
IRMS = IOUTMAX
1 -
+
*
≈
∆
12
«
VOUT
(VIN - VOUT
)
*
where r =
VIN
L
f
IOUTMAX
*
*
*
(3)
The worst case is when VIN = 2 * VOUT
Table 1. Suggested Inductors and Their Suppliers
Model
Vendor
Toko
Dimensions LxWxH (mm)
3.0 x 3.0 x 1.2
D.C.R. (Typ)
FDSE0312-2R2M
DO1608C-222
160 mΩ
80 mΩ
Coilcraft
6.6 x 4.5 x 1.8
Output Capacitor Selection
Use a 10 µF, 6.3V ceramic capacitor. Use X7R or X5R types, do not use Y5V. DC bias characteristics of ceramic
capacitors must be considered when selecting case sizes like 0805 and 0603. DC bias characteristics vary from
manufacturer to manufacturer and dc bias curves should be requested from them as part of the capacitor
selection process. The output filter capacitor smooths out current flow from the inductor to the load, helps
maintain a steady output voltage during transient load changes and reduces output voltage ripple. These
capacitors must be selected with sufficient capacitance and sufficiently low ESR to perform these functions.
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The output voltage ripple is caused by the charging and discharging of the output capacitor and also due to its
ESR and can be calculated as:
IRIPPLE
VPP-C
=
4
f C
* *
(4)
(5)
Voltage peak-to-peak ripple due to ESR can be expressed as follows
VPP-ESR = (2 * IRIPPLE) * RESR
Because these two components are out of phase the RMS value can be used to get an approximate value of
peak-to-peak ripple.
Voltage peak-to-peak ripple, root mean squared can be expressed as follows
2
VPP-C2 + VPP-ESR
VPP-RMS
=
(6)
Note that the output voltage ripple is dependent on the inductor current ripple and the equivalent series
resistance of the output capacitor (RESR).
The RESR is frequency dependent (as well as temperature dependent); make sure the value used for calculations
is at the switching frequency of the part.
Table 2. Suggested Capacitor and Their Suppliers
Model
GRM21BR60J106K
JMK212BJ106K
Type
Ceramic, X5R
Vendor
Murata
Voltage
6.3V
Case Size Inch (mm)
0805 (2012)
Ceramic, X5R
Ceramic, X5R
Taiyo-Yuden
TDK
6.3V
0805 (2012)
C2012X5R0J106K
6.3V
0805 (2012)
Buck Output Ripple Management
If VIN and ILOAD increase, the output ripple associated with the Buck Regulators also increases. Figure 32 shows
the safe operating area. To ensure operation in the area of concern it is recommended that the system designer
circumvents the output ripple issues to install Schottky diodes on the Buck(s) that are expected to perform under
these extreme corner conditions.
(Schottky diodes are recommended to reduce the output ripple, if system requirements include this shaded area
of operation. VIN > 1.5V and ILOAD > 1.24)
5.5
5.0
4.5
4.0
3.5
3.0
0
0.5
1.0
1.5
LOAD CURRENT (A)
Figure 32.
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Board Layout Considerations
PC board layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance
of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce, and resistive voltage loss
in the traces. These can send erroneous signals to the DC-DC converter IC, resulting in poor regulation or
instability.
Good layout for the converters can be implemented by following a few simple design rules.
1. Place the converters, inductor and filter capacitors close together and make the traces short. The traces
between these components carry relatively high switching currents and act as antennas. Following this rule
reduces radiated noise. Special care must be given to place the input filter capacitor very close to the VIN
and GND pin.
2. Arrange the components so that the switching current loops curl in the same direction. During the first half of
each cycle, current flows from the input filter capacitor through the converter and inductor to the output filter
capacitor and back through ground, forming a current loop. In the second half of each cycle, current is pulled
up from ground through the converter by the inductor to the output filter capacitor and then back through
ground forming a second current loop. Routing these loops so the current curls in the same direction
prevents magnetic field reversal between the two half-cycles and reduces radiated noise.
3. Connect the ground pins of the converter and filter capacitors together using generous component-side
copper fill as a pseudo-ground plane. Then, connect this to the ground-plane (if one is used) with several
vias. This reduces ground-plane noise by preventing the switching currents from circulating through the
ground plane. It also reduces ground bounce at the converter by giving it a low-impedance ground
connection.
4. Use wide traces between the power components and for power connections to the DC-DC converter circuit.
This reduces voltage errors caused by resistive losses across the traces.
5. Route noise sensitive traces, such as the voltage feedback path, away from noisy traces between the power
components. The voltage feedback trace must remain close to the converter circuit and should be direct but
should be routed opposite to noisy components. This reduces EMI radiated onto the DC-DC converter’s own
voltage feedback trace. A good approach is to route the feedback trace on another layer and to have a
ground plane between the top layer and layer on which the feedback trace is routed. In the same manner for
the adjustable part it is desired to have the feedback dividers on the bottom layer.
6. Place noise sensitive circuitry, such as radio RF blocks, away from the DC-DC converter, CMOS digital
blocks and other noisy circuitry. Interference with noise-sensitive circuitry in the system can be reduced
through distance.
48
Submit Documentation Feedback
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LP3972
LP3972
www.ti.com
SNVS468K –SEPTEMBER 2006–REVISED MAY 2013
REVISION HISTORY
Changes from Revision J (May 2013) to Revision K
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 48
Copyright © 2006–2013, Texas Instruments Incorporated
Submit Documentation Feedback
49
Product Folder Links: LP3972
PACKAGE OPTION ADDENDUM
www.ti.com
7-Oct-2013
PACKAGING INFORMATION
Orderable Device
LP3972SQ-0514/NOPB
LP3972SQ-5810/NOPB
LP3972SQ-A413/NOPB
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
ACTIVE
WQFN
WQFN
WQFN
RSB
40
40
40
1000
Green (RoHS
& no Sb/Br)
CU SN
CU SN
CU SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
72-0514
ACTIVE
ACTIVE
RSB
RSB
1000
1000
Green (RoHS
& no Sb/Br)
72-5810
72-A413
Green (RoHS
& no Sb/Br)
-40 to 125
LP3972SQ-A514
ACTIVE
ACTIVE
WQFN
WQFN
RSB
RSB
40
40
1000
1000
TBD
Call TI
CU SN
Call TI
-40 to 125
-40 to 125
72-A514
72-A514
LP3972SQ-A514/NOPB
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
LP3972SQ-E514/NOPB
LP3972SQ-I414/NOPB
ACTIVE
ACTIVE
WQFN
WQFN
RSB
RSB
40
40
1000
1000
Green (RoHS
& no Sb/Br)
CU SN
CU SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
72-E514
72-I414
Green (RoHS
& no Sb/Br)
LP3972SQ-I514
ACTIVE
ACTIVE
WQFN
WQFN
RSB
RSB
40
40
1000
1000
TBD
Call TI
CU SN
Call TI
-40 to 125
-40 to 125
72-I514
72-I514
LP3972SQ-I514/NOPB
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
LP3972SQE-A413/NOPB
ACTIVE
WQFN
RSB
40
250
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
72-A413
LP3972SQE-A514
OBSOLETE
ACTIVE
WQFN
WQFN
RSB
RSB
40
40
TBD
TBD
Call TI
Call TI
Call TI
Call TI
LP3972SQE-A514/NOPB
250
250
LP3972SQE-E514/NOPB
LP3972SQE-I514/NOPB
LP3972SQX-0514/NOPB
LP3972SQX-5810/NOPB
LP3972SQX-A413/NOPB
LP3972SQX-A514/NOPB
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
RSB
RSB
RSB
RSB
RSB
RSB
40
40
40
40
40
40
Green (RoHS
& no Sb/Br)
CU SN
CU SN
CU SN
CU SN
CU SN
CU SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
72-E514
72-I514
72-0514
72-5810
72-A413
72-A514
250
Green (RoHS
& no Sb/Br)
4500
4500
4500
4500
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
-40 to 125
-40 to 125
Green (RoHS
& no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
7-Oct-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
LP3972SQX-E514/NOPB
LP3972SQX-I414/NOPB
LP3972SQX-I514/NOPB
ACTIVE
WQFN
WQFN
WQFN
RSB
40
40
40
4500
Green (RoHS
& no Sb/Br)
CU SN
CU SN
CU SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
72-E514
ACTIVE
ACTIVE
RSB
RSB
4500
4500
Green (RoHS
& no Sb/Br)
-40 to 125
72-I414
72-I514
Green (RoHS
& no Sb/Br)
-40 to 125
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Sep-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LP3972SQ-0514/NOPB
LP3972SQ-5810/NOPB
WQFN
WQFN
RSB
RSB
RSB
RSB
RSB
RSB
RSB
RSB
RSB
RSB
RSB
RSB
RSB
RSB
RSB
RSB
RSB
RSB
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
1000
1000
1000
1000
1000
1000
1000
1000
1000
250
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
330.0
330.0
330.0
330.0
330.0
330.0
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
1.3
1.3
1.3
1.3
1.3
1.3
1.3
1.3
1.3
1.3
1.3
1.3
1.3
1.3
1.3
1.3
1.3
1.3
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
LP3972SQ-A413/NOPB WQFN
LP3972SQ-A514 WQFN
LP3972SQ-A514/NOPB WQFN
LP3972SQ-E514/NOPB WQFN
LP3972SQ-I414/NOPB
LP3972SQ-I514
WQFN
WQFN
WQFN
LP3972SQ-I514/NOPB
LP3972SQE-A413/NOPB WQFN
LP3972SQE-E514/NOPB WQFN
LP3972SQE-I514/NOPB WQFN
LP3972SQX-0514/NOPB WQFN
LP3972SQX-5810/NOPB WQFN
LP3972SQX-A413/NOPB WQFN
LP3972SQX-A514/NOPB WQFN
LP3972SQX-E514/NOPB WQFN
LP3972SQX-I414/NOPB WQFN
250
250
4500
4500
4500
4500
4500
4500
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Sep-2013
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LP3972SQX-I514/NOPB WQFN
RSB
40
4500
330.0
12.4
5.3
5.3
1.3
8.0
12.0
Q1
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LP3972SQ-0514/NOPB
LP3972SQ-5810/NOPB
LP3972SQ-A413/NOPB
LP3972SQ-A514
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
RSB
RSB
RSB
RSB
RSB
RSB
RSB
RSB
RSB
RSB
RSB
RSB
RSB
RSB
RSB
RSB
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
1000
1000
1000
1000
1000
1000
1000
1000
1000
250
203.0
203.0
203.0
203.0
203.0
203.0
203.0
203.0
203.0
203.0
203.0
203.0
367.0
367.0
367.0
367.0
190.0
190.0
190.0
190.0
190.0
190.0
190.0
190.0
190.0
190.0
190.0
190.0
367.0
367.0
367.0
367.0
41.0
41.0
41.0
41.0
41.0
41.0
41.0
41.0
41.0
41.0
41.0
41.0
35.0
35.0
35.0
35.0
LP3972SQ-A514/NOPB
LP3972SQ-E514/NOPB
LP3972SQ-I414/NOPB
LP3972SQ-I514
LP3972SQ-I514/NOPB
LP3972SQE-A413/NOPB
LP3972SQE-E514/NOPB
LP3972SQE-I514/NOPB
LP3972SQX-0514/NOPB
LP3972SQX-5810/NOPB
LP3972SQX-A413/NOPB
LP3972SQX-A514/NOPB
250
250
4500
4500
4500
4500
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Sep-2013
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LP3972SQX-E514/NOPB
LP3972SQX-I414/NOPB
LP3972SQX-I514/NOPB
WQFN
WQFN
WQFN
RSB
RSB
RSB
40
40
40
4500
4500
4500
367.0
367.0
367.0
367.0
367.0
367.0
35.0
35.0
35.0
Pack Materials-Page 3
MECHANICAL DATA
RSB0040A
SQF40A (Rev B)
www.ti.com
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相关型号：
LP3972SQX-E514/NOPB
Power Management IC (PMIC) for Advanced Application Processors 40-WQFN -40 to 125
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