LP3986BLX-3028/NOPB [TI]
DUAL OUTPUT, FIXED POSITIVE LDO REGULATOR, PBGA8;型号: | LP3986BLX-3028/NOPB |
厂家: | TEXAS INSTRUMENTS |
描述: | DUAL OUTPUT, FIXED POSITIVE LDO REGULATOR, PBGA8 输出元件 |
文件: | 总14页 (文件大小:743K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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information and details on our current products and services.
October 2005
LP3986
Dual Micropower 150 mA Ultra Low-Dropout CMOS
Voltage Regulators in micro SMD Package
General Description
The LP3986 is a 150 mA dual low dropout regulator de-
signed for portable and wireless applications with demand-
ing performance and board space requirements.
Features
n Miniature 8-I/O micro SMD package
n Stable with 1µF ceramic and high quality tantalum
output capacitors
n Fast turn-on
n Two independent regulators
n Logic controlled enable
The LP3986 is stable with a small 1 µF 30% ceramic output
capacitor requiring smallest possible board space.
The LP3986’s performance is optimized for battery powered
systems to deliver ultra low noise, extremely low dropout
voltage and low quiescent current independent of load cur-
rent. Regulator ground current increases very slightly in
dropout, further prolonging the battery life. Optional external
bypass capacitor reduces the output noise further without
slowing down the load transient response. Fast start-up time
is achieved by utilizing a speed-up circuit that actively pre-
charges the bypass capacitor. Power supply rejection is
better than 60 dB at low frequencies and 55 dB at 10 kHz.
High power supply rejection is maintained at low input volt-
age levels common to battery operated circuits.
n Over current and thermal protection
Key Specifications
n Guaranteed 150 mA output current per regulator
n 1nA typical quiescent current when both regulators in
shutdown mode
n 60 mV typical dropout voltage at 150 mA output current
n 115 µA typical ground current
n 40 µV typical output noise
n 200 µs fast turn-on circuit
The LP3986 is available in a micro SMD package. Perfor-
mance is specified for a −40˚C to +125˚C temperature
range. For single LDO applications, please refer to the
LP3985 datasheet.
n −40˚C to +125˚C junction temperature
Applications
n CDMA cellular handsets
n GSM cellular handsets
n Portable information appliances
n Portable battery applications
Typical Application Circuit
20003401
© 2005 National Semiconductor Corporation
DS200034
www.national.com
Block Diagram
LP3986
20003402
Pin Descriptions
Name
VOUT2
EN2
*micro SMD
Function
A1
B1
C1
C2
C3
B3
A3
A2
Output Voltage of the second LDO
Enable input for the second LDO
Bypass capacitor for the bandgap
Common ground
BYPASS
GND
GND
Common ground
EN1
Enable input for the first LDO
Output Voltage of the first LDO
Common input for both LDOs
VOUT1
VIN
* Note: The pin numbering scheme for the micro SMD package was revised in April 2002 to conform to JEDEC standard. Only the pin
numbers were revised. No changes to the physical location of the inputs/outputs were made. For reference purposes, the obsolete
numbering scheme had V
as pin 8.
as pin 1, EN as pin 2, BYPASS as pin 3, GND as pins 4 and 5, EN as pin 6, V
as pin 7, and V
OUT2
2
1
OUT1 IN
Connection Diagram
20003404
Top View
8 Bump micro SMD Package
See NS Package Number BLA08
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2
Ordering Information
For micro SMD Package (BL has thickness of 0.995mm)
Output
Voltage (V)
2.5 2.5
2.5 2.8
2.5 1.8
2.6 2.6
2.8 1.8
2.8 2.8
2.85 2.85
2.9 2.9
3.0 2.8
3.0 3.0
3.1 3.1
3.1 3.3
3.3 3.3
Package
Marking
27
LP3986 Supplied as 250 Units,
Tape and Reel
LP3986 Supplied as 3000
Units, Tape and Reel
LP3986BLX-2525
LP3986BLX-2528
LP3986BLX-2518
LP3986BLX-2626
LP3986BLX-2818
LP3986BLX-2828
LP3986BLX285285
LP3986BLX-2929
LP3986BLX-3028
LP3986BLX-3030
LP3986BLX-3131
LP3986BLX-3133
LP3986BLX-3333
Grade
STD
STD
STD
STD
STD
STD
STD
STD
STD
STD
STD
STD
STD
LP3986BL-2525
LP3986BL-2528
LP3986BL-2518
LP3986BL-2626
LP3986BL-2818
LP3986BL-2828
LP3986BL-285285
LP3986BL-2929
LP3986BL-3028
LP3986BL-3030
LP3986BL-3131
LP3986BL-3133
LP3986BL-3333
14
30
29
25
10
11
15
26
12
13
16
17
For micro SMD Package (TL has thickness of 0.600mm)
Output
Voltage (V)
2.5 2.5
2.5 2.8
2.5 1.8
2.6 2.6
2.8 1.8
2.8 2.8
2.85 2.85
2.9 2.9
3.0 2.8
3.0 3.0
3.1 3.1
3.1 3.3
3.3 3.3
Package
Marking
27
LP3986 Supplied as 250 Units,
Tape and Reel
LP3986 Supplied as 3000
Units, Tape and Reel
LP3986TLX-2525
LP3986TLX-2528
LP3986TLX-2518
LP3986TLX-2626
LP3986TLX-2818
LP3986TLX-2828
LP3986TLX285285
LP3986TLX-2929
LP3986TLX-3028
LP3986TLX-3030
LP3986TLX-3131
LP3986TLX-3133
LP3986TLX-3333
Grade
STD
STD
STD
STD
STD
STD
STD
STD
STD
STD
STD
STD
STD
LP3986TL-2525
LP3986TL-2528
LP3986TL-2518
LP3986TL-2626
LP3986TL-2818
LP3986TL-2828
LP3986TL-285285
LP3986TL-2929
LP3986TL-3028
LP3986TL-3030
LP3986TL-3131
LP3986TL-3133
LP3986TL-3333
14
30
28
25
10
11
15
26
12
13
16
17
20003403
3
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Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Operating Ratings (Notes 1, 2)
VIN
2.7 to 6V
VEN
0 to (VIN+ 0.3V) ≤ 6V
Junction Temperature
Thermal Resistance
θJA
−40˚C to +125˚C
VIN, VEN
−0.3 to 6.5V
VOUT
−0.3 to (VIN+0.3V) ≤ 6.5V
150˚C
220˚C/W
250mW
Junction Temperature
Storage Temperature
Pad Temp. (Note 3)
Maximum Power Dissipation
(Note 4)
Maximum Power Dissipation (Note 6)
−65˚C to +150˚C
235˚C
364mW
ESD Rating (Note 5)
Human Body Model
Machine Model
2kV
200V
Electrical Characteristics
Unless otherwise specified: VIN = VOUT(nom) + 0.5V, CIN = 1 µF, IOUT = 1mA, COUT = 1 µF, CBYPASS = 0.01µF. Typical values
and limits appearing in standard typeface are for TJ = 25˚C. Limits appearing in boldface type apply over the entire junction
temperature range for operation, −40˚C to +125˚C. (Note 7) (Note 8)
Limit
Symbol
Parameter
Conditions
IOUT = 1mA
Typ
Units
Min
−2.5
−3.0
Max
2.5
Output Voltage
Tolerance
% of
3.0
VOUT(nom)
Line Regulation Error
(Note 9)
VIN = (VOUT(nom) + 0.5V) to
6.0V,
0.006
0.092
0.128
∆VOUT
%/V
IOUT = 1 mA
Load Regulation Error
(Note 10)
IOUT = 1mA to 150 mA
0.003
1.5
0.006
%/mA
mVP-P
0.01
Output AC Line
Regulation
VIN = VOUT(nom) + 1V,
IOUT = 150 mA (Figure 1)
VIN = 3.1V,
60
f = 1 kHz,
IOUT = 50 mA (Figure 2)
VIN = 3.1V,
Power Supply Rejection
Ratio
PSRR
dB
50
f = 10 kHz,
IOUT = 50 mA (Figure 2)
Both Regulators ON
VEN = 1.4V, IOUT = 0 mA
Both Regulators ON
VEN = 1.4V, IOUT = 0 to 150
mA
IQ
Quiescent Current
115
220
200
320
One Regulator ON
VEN = 1.4V IOUT = 0 mA
One Regulator ON
VEN = 1.4V IOUT = 0 to 150
mA
75
130
200
µA
130
VEN = 0.4V, Both Regulators
OFF (shutdown)
0.001
2
4
Dropout Voltage
(Note 11)
IOUT = 1 mA
0.4
60
2
100
mV
mA
mA
IOUT = 150 mA
ISC
Short Circuit Current
Limit
Output Grounded
600
IOUT(PK)
Peak Output
Current(Note 15)
VOUT ≥ VOUT(nom) - 5%
500
300
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4
Electrical Characteristics (Continued)
Unless otherwise specified: VIN = VOUT(nom) + 0.5V, CIN = 1 µF, IOUT = 1mA, COUT = 1 µF, CBYPASS = 0.01µF. Typical values
and limits appearing in standard typeface are for TJ = 25˚C. Limits appearing in boldface type apply over the entire junction
temperature range for operation, −40˚C to +125˚C. (Note 7) (Note 8)
Limit
Symbol
TON
Parameter
Turn-On Time
Conditions
Typ
Units
Min
Max
CBYPASS = 0.01 µF
200
µs
(Note 12)
en
Output Noise Voltage
BW = 10 Hz to 100 kHz,
COUT = 1µF
40
1
µVrms
ρn(1/f)
IEN
Output Noise Density
f = 120 Hz,
µV/
nA
V
COUT = 1µF
Maximum Input Current
at EN
VEN = 0.4 and VIN = 6V
10
VIL
Maximum Low Level
Input Voltage at EN
Minimum High Level
Input Voltage at EN
VIN = 2.7 to 6V
0.4
VIH
VIN = 2.7 to 6V
1.4
V
∆ILoad1 = 150 mA at 1KHz rate
∆ILoad2 = 1 mA
∆VOUT2/∆VOUT1
−60
−60
Xtalk
Crosstalk Rejection
dB
∆ILoad2 = 150 mA at 1KHz rate
∆ILoad1 = 1 mA
∆VOUT2/∆VOUT1
>
All VOUT = 2.5V,
1
µF
µF
Input capacitance(Note
13)
CIN
If VOUT = 1.8V,
4.7
>
VIN_MIN = 2.9V
>
COUT
Capacitance(Note 13)
All VOUT = 2.5V,
1
22
22
µF
µF
If VOUT = 1.8V,
2.2
>
VIN_MIN = 2.9V
ESR
(Note 14)
5
500
mΩ
Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device
is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical
Characteristics tables.
Note 2: All voltages are with respect to the potential at the GND pin.
Note 3: Additional information on pad temperature can be found in National Semiconductor Application Note (AN-1112).
Note 4: The Absolute Maximum power dissipation depends on the ambient temperature and can be calculated using the formula:
PD = (TJ - TA)/θJA
,
Where T is the junction temperature, T is the ambient temperature, and θ is the junction-to-ambient thermal resistance. The 364mW rating appearing under
J
A
JA
Absolute Maximum Ratings results from substituting the Absolute Maximum junction temperature, 150˚C, for T , 70˚C for T , and 220˚C/W for θ . More power can
J
A
JA
be dissipated safely at ambient temperatures below 70˚C . Less power can be dissipated safely at ambient temperatures above 70˚C. The Absolute Maximum power
dissipation can be increased by 4.5mW for each degree below 70˚C, and it must be derated by 4.5mW for each degree above 70˚C.
Note 5: The human body model is 100pF discharged through a 1.5kΩ resistor into each pin. The machine model is a 200pF capacitor discharged directly into each
pin.
Note 6: Like the Absolute Maximum power dissipation, the maximum power dissipation for operation depends on the ambient temperature. The 250mW rating
appearing under Operating Ratings results from substituting the maximum junction temperature for operation, 125˚C, for T , 70˚C for T , and 220˚C/W for θ into
J
A
JA
(1) above. More power can be dissipated at ambient temperatures below 70˚C . Less power can be dissipated at ambient temperatures above 70˚C. The maximum
power dissipation for operation can be increased by 4.5mW for each degree below 70˚C, and it must be derated by 4.5mW for each degree above 70˚C.
Note 7: All limits are guaranteed. All electrical characteristics having room temperature limits are tested during production with T = 25˚C or correlated using
J
Statistical Quality Control (SQC) methods. All hot and cold limits are guaranteed by correlating the electrical characteristics to process and temperature variations
and applying statistical process control.
Note 8: The target output voltage, which is labeled V
, is the desired voltage option.
OUT(nom)
Note 9: The output voltage changes slightly with line voltage. An increase in the line voltage results in a slight increase in the output voltage and vice versa.
Note 10: The output voltage changes slightly with load current. An increase in the load current results in a slight decrease in the output voltage and vice versa.
Tested limit applies to Vout ’s of 2.5V and greater.
Note 11: Dropout voltage is the input-to-output voltage difference at which the output voltage is 100mV below its nominal value.
Note 12: Turn-on time is that between the enable input just exceeding V and the output voltage just reaching 95% of its nominal value.
IH
Note 13: Range of capacitor values for which the device will remain stable. This electrical specification is guaranteed by design.
Note 14: Range of capacitor ESR values for which the device will remain stable. This electrical specification is guaranteed by design.
Note 15: I
guaranteed for Vout ’s of 2.5V and greater.
PEAK
5
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Test Signals
20003408
FIGURE 1. Line Regulation Input Test Signal
20003409
FIGURE 2. PSRR Input Test Signal
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6
Typical Performance Characteristics Unless otherwise specified, CIN= COUT 1µF Ceramic, C
=
BP
0.01µ F, VIN = VOUT + 0.5, TA= 25˚C, both enable pins are tied to VIN
Power Supply Rejection Ratio (CBP = 0.001µF)
Power Supply Rejection Ratio (CBP = 0.01µF)
20003410
20003447
Power Supply Rejection Ratio (CBP = 0.1µF)
Output Noise Spectral Density
20003448
20003451
Line Transient Response (CBP = 0.001µF)
Line Transient Response (CBP = 0.01µF)
20003413
20003449
7
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Typical Performance Characteristics Unless otherwise specified, CIN= COUT 1µF Ceramic, C
=
BP
0.01µ F, VIN = VOUT + 0.5, TA= 25˚C, both enable pins are tied to VIN (Continued)
Load Transient & Cross Talk (VIN = VOUT + 0.2V)
Load Transient & Cross Talk (VIN = VOUT + 0.2V)
20003417
20003416
Start-Up Time (CBP = 0.001, 0.01, 0.1µF)
Enable Response ( VIN = 4.2V )
20003411
20003414
Enable Response (VIN = VOUT+ 0.2V)
Enable Response
20003450
20003415
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Typical Performance Characteristics Unless otherwise specified, CIN= COUT 1µF Ceramic, C
=
BP
0.01µ F, VIN = VOUT + 0.5, TA= 25˚C, both enable pins are tied to VIN (Continued)
Output Short Circuit Current at VIN = 6V
Output Short Circuit Current at VIN = 3.3V
20003465
20003466
9
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Application Hints
EXTERNAL CAPACITORS
X7R is recommended over Z5U and Y5 in applications
where the ambient temperature will change significantly
above or below 25˚C.
Like any low-dropout regulator, the LP3986 requires external
capacitors for regulator stability. The LP3986 is specifically
designed for portable applications requiring minimum board
space and smallest components. These capacitors must be
correctly selected for good performance.
Tantalum capacitors are less desirable than ceramic for use
as output capacitors because they are more expensive when
comparing equivalent capacitance and voltage ratings in the
1µF to 4.7µF range.
INPUT CAPACITOR
Another important consideration is that tantalum capacitors
have higher ESR values than equivalent size ceramics. This
means that while it may be possible to find a tantalum
capacitor with an ESR value within the stable range, it would
have to be larger in capacitance (which means bigger and
more costly ) than a ceramic capacitor with the same ESR
value. It should also be noted that the ESR of a typical
tantalum will increase about 2:1 as the temperature goes
from 25˚C down to −40˚C, so some guard band must be
allowed.
An input capacitance of ) 1µF is required between the
LP3986 input pin and ground (the amount of the capacitance
may be increased without limit).
This capacitor must be located a distance of not more than
1cm from the input pin and returned to a clean analog
ground. Any good quality ceramic, tantalum, or film capacitor
may be used at the input.
Important: Tantalum capacitors can suffer catastrophic fail-
ures due to surge current when connected to a low-
impedance source of power (like a battery or a very large
capacitor). If a tantalum capacitor is used at the input, it must
be guaranteed by the manufacturer to have a surge current
rating sufficient for the application.
NOISE BYPASS CAPACITOR
Connecting a 0.01µF capacitor between the CBYPASS pin
and ground significantly reduces noise on the regulator out-
put. This cap is connected directly to a high impedance node
in the band gap reference circuit. Any significant loading on
this node will cause a change on the regulated output volt-
age. For this reason, DC leakage current through this pin
must be kept as low as possible for best output voltage
accuracy. The use of this 0.01µF bypass capacitor is strongly
recommended to prevent overshoot on the output during
start up.
There are no requirements for the ESR on the input capaci-
tor, but tolerance and temperature coefficient must be con-
sidered when selecting the capacitor to ensure the capaci-
tance will be ) 1µF over the entire operating temperature
range.
OUTPUT CAPACITOR
The LP3986 is designed specifically to work with very small
ceramic output capacitors, any ceramic capacitor (tempera-
ture characteristics X7R, X5R, Z5U or Y5V) in 1 to 22 µF
range with 5mΩ to 500mΩ ESR range is suitable in the
LP3986 application circuit.
The types of capacitors best suited for the noise bypass
capacitor are ceramic and film. High-quality ceramic capaci-
tors with either NPO or COG dielectric typically have very
low leakage. Polypropolene and polycarbonate film capaci-
tors are available in small surface-mount packages and
typically have extremely low leakage current.
It may also be possible to use tantalum or film capacitors at
the output, but these are not as attractive for reasons of size
and cost (see next section Capacitor Characteristics).
Unlike many other LDO’s, addition of a noise reduction
capacitor does not effect the transient response of the de-
vice.
The output capacitor must meet the requirement for mini-
mum amount of capacitance and also have an ESR (Equiva-
lent Series Resistance) value which is within a stable range.
ON/OFF INPUT OPERATION
The LP3986 is turned off by pulling the VEN pin low, and
turned on by pulling it high. If this feature is not used, the VEN
pin should be tied to VIN to keep the regulator output on at all
times. To assure proper operation, the signal source used to
drive the VEN input must be able to swing above and below
the specified turn-on/off voltage thresholds listed in the Elec-
NO-LOAD STABILITY
The LP3986 will remain stable and in regulation with no-load
(other than the internal voltage divider). This is specially
important in CMOS RAM keep-alive applications.
CAPACITOR CHARACTERISTICS
trical Characteristics section under VIL and VIH
.
The LP3986 is designed to work with ceramic capacitors on
the output to take advantage of the benefits they offer: for
capacitance values in the range of 1µF to 4.7µF range,
ceramic capacitors are the smallest, least expensive and
have the lowest ESR values (which makes them best for
eliminating high frequency noise). The ESR of a typical 1µF
ceramic capacitor is in the range of 20 mΩ to 40 mΩ, which
easily meets the ESR requirement for stability by the
LP3986.
FAST ON-TIME
The LP3986 outputs are turned on after Vref voltage reaches
its final value (1.23V nominal). To speed up this process, the
noise reduction capacitor at the bypass pin is charged with
an internal 70µA current source. The current source is turned
off when the bandgap voltage reaches approximately 95% of
its final value. The turn on time is determined by the time
constant of the bypass capccitor. The smaller the capacitor
value, the shorter the turn on time, but less noise gets
reduced. As a result, turn on time and noise reduction need
to be taken into design consideration when choosing the
value of the bypass capacitor.
The ceramic capacitor’s capacitance can vary with tempera-
ture. The capacitor type X7R, which operates over a tem-
perature range of -55˚C to +125˚C, will only vary the capaci-
tance to within 15%. Most large value ceramic capacitors
() 2.2µF) are manufactured with Z5U or Y5V temperature
characteristics. Their capacitance can drop by more than
50% as the temperature goes from 25˚C to 85˚C. Therefore,
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10
The wavelengths which have most detrimental effect are
reds and infra-reds, which means that the fluorescent light-
ing used inside most buildings has very little effect on per-
formance. A micro SMD test board was brought to within
1cm of a fluorescent desk lamp and the effect on the regu-
lated output voltage was negligible, showing a deviation of
less than 0.1% from nominal.
Application Hints (Continued)
MICRO SMD MOUNTING
The micro SMD package requires specific mounting tech-
niques which are detailed in National Semiconductor Appli-
cation Note (AN-1112). Referring to the section Surface
Mount Technology (SMT) Assembly Considerations.
For best results during assembly, alignment ordinals on the
PC board may be used to facilitate placement of the micro
SMD device.
MICRO SMD LIGHT SENSITIVITY
Exposing the micro SMD device to direct sunlight will cause
misoperation of the device. Light sources such as halogen
lamps can effect electrical performance if brought near to the
device.
11
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Physical Dimensions inches (millimeters) unless otherwise noted
micro SMD, 8 Bump
NS Package Number BLA08CCC
The dimensions for X1, X2 and X3 are as follows:
X1 = 1.55mm
X2 = 1.55mm
X3 = 0.995mm
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12
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
micro SMD, 8 Bump
NS Package Number ATL08CCA
The dimensions for X1, X2 and X3 are as follows:
X1 = 1.55mm
X2 = 1.55mm
X3 = 0.600mm
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
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properly used in accordance with instructions for use
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