LP3986TL-2518/NOPB [TI]
具有使能功能的 300mA、双通道可调节超低压降稳压器 | YZR | 8;
| 型号： | LP3986TL-2518/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有使能功能的 300mA、双通道可调节超低压降稳压器 | YZR | 8 输出元件 稳压器 调节器 |
| 文件： | 总18页 (文件大小：605K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LP3986
www.ti.com
SNVS142U –AUGUST 2001–REVISED FEBRUARY 2013
LP3986 Dual Micropower 150 mA Ultra Low-Dropout CMOS Voltage Regulators in DSBGA
Package
Check for Samples: LP3986
1
FEATURES
DESCRIPTION
The LP3986 is a 150 mA dual low dropout regulator
designed for portable and wireless applications with
2
•
Miniature 8-I/O DSBGA Package
•
Stable With 1µF Ceramic and High Quality
Tantalum Output Capacitors
demanding
performance
and
board
space
requirements.
•
•
•
•
Fast Turn-on
The LP3986 is stable with a small 1 µF ±30%
ceramic output capacitor requiring smallest possible
board space.
Two Independent Regulators
Logic Controlled Enable
Over Current and Thermal Protection
The LP3986's performance is optimized for battery
powered systems to deliver ultra low noise, extremely
low dropout voltage and low quiescent current
independent of load current. Regulator ground current
increases very slightly in dropout, further prolonging
the battery life. Optional external bypass capacitor
reduces the output noise further without slowing down
the load transient response. Fast start-up time is
achieved by utilizing a speed-up circuit that actively
pre-charges the bypass capacitor. Power supply
rejection is better than 60 dB at low frequencies and
55 dB at 10 kHz. High power supply rejection is
maintained at low input voltage levels common to
battery operated circuits.
APPLICATIONS
•
•
•
•
CDMA Cellular Handsets
GSM Cellular Handsets
Portable Information Appliances
Portable Battery Applications
The LP3986 is available in a DSBGA package.
Performance is specified for a −40°C to +125°C
temperature range. For single LDO applications,
please refer to the LP3985 datasheet.
Table 1. Key Specifications
VALUE
UNIT
mA
nA
Guaranteed output current per regulator
150
Typical quiescent current when both regulators in shutdown mode
Typical dropout voltage at 150 mA output current
Typical ground current
1
60
mV
µA
115
Typical output noise
40
µV
Fast turn-on circuit
200
µs
Junction temperature
−40 to +125
°C
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2001–2013, Texas Instruments Incorporated
LP3986
SNVS142U –AUGUST 2001–REVISED FEBRUARY 2013
www.ti.com
Typical Application Circuit
Input
2.7V to 6.0V
V
V
OUT1
IN
C
IN
LP3986
EN
EN
1
V
OUT2
1mF
2
1mF
BYPASS
GND
C
*
BYPASS
0.01mF
Block Diagram
LP3986
VIN
VOUT2
VOUT1
Fast Turn
On
circuit
BYPASS
Vreference
1.23V
VEN2
VEN1
Over Current &
Thermal
Protection
GND
Pin Functions
PIN DESCRIPTIONS
Name
VOUT2
EN2
DSBGA(1)
Function
A1
B1
C1
C2
C3
B3
A3
A2
Output Voltage of the second LDO
Enable input for the second LDO
Bypass capacitor for the bandgap
Common ground
BYPASS
GND
GND
Common ground
EN1
Enable input for the first LDO
Output Voltage of the first LDO
Common input for both LDOs
VOUT1
VIN
(1) The pin numbering scheme for the DSBGA package was revised in April 2002 to conform to JEDEC standard. Only the pin numbers
were revised. No changes to the physical location of the inputs/outputs were made. For reference purposes, the obsolete numbering
scheme had VOUT2 as pin 1, EN2 as pin 2, BYPASS as pin 3, GND as pins 4 and 5, EN1 as pin 6, VOUT1 as pin 7, and VIN as pin 8.
2
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SNVS142U –AUGUST 2001–REVISED FEBRUARY 2013
Connection Diagram
8 Bump DSBGA Package – Top View
See Package Number YZR0008
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
(1) (2)(3)
Absolute Maximum Ratings
VIN, VEN
−0.3 to 6.5V
−0.3 to (VIN+0.3V) ≤ 6.5V
150°C
VOUT
Junction Temperature
Storage Temperature
−65°C to +150°C
235°C
(4)
Pad Temp.
(5)
Maximum Power Dissipation
364mW
(6)
ESD Rating
Human Body Model
Machine Model
2kV
200V
(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits
and associated test conditions, see Electrical Characteristics.
(2) All voltages are with respect to the potential at the GND pin.
(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office / Distributors for
availability and specifications.
(4) Additional information on pad temperature can be found in TI's AN-1112 application report (SNVA009).
(5) The Absolute Maximum power dissipation depends on the ambient temperature and can be calculated using the formula: PD = (TJ -
TA)/θJA,Where TJ is the junction temperature, TA is the ambient temperature, and θJA is the junction-to-ambient thermal resistance. The
364mW rating appearing under Absolute Maximum Ratings results from substituting the Absolute Maximum junction temperature,
150°C, for TJ, 70°C for TA, and 220°C/W for θJA. More power can be dissipated safely at ambient temperatures below 70°C . Less
power can be dissipated safely at ambient temperatures above 70°C. The Absolute Maximum power dissipation can be increased by
4.5mW for each degree below 70°C, and it must be derated by 4.5mW for each degree above 70°C.
(6) The human body model is 100pF discharged through a 1.5kΩ resistor into each pin. The machine model is a 200pF capacitor
discharged directly into each pin.
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(1) (2)
Operating Ratings
VIN
2.7 to 6V
0 to (VIN+ 0.3V) ≤ 6V
−40°C to +125°C
VEN
Junction Temperature
Thermal Resistance
θJA
220°C/W
250mW
(3)
Maximum Power Dissipation
(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits
and associated test conditions, see Electrical Characteristics.
(2) All voltages are with respect to the potential at the GND pin.
(3) Like the Absolute Maximum power dissipation, the maximum power dissipation for operation depends on the ambient temperature. The
250mW rating appearing under Operating Ratings results from substituting the maximum junction temperature for operation, 125°C, for
TJ, 70°C for TA, and 220°C/W for θJA into (1) above. More power can be dissipated at ambient temperatures below 70°C . Less power
can be dissipated at ambient temperatures above 70°C. The maximum power dissipation for operation can be increased by 4.5mW for
each degree below 70°C, and it must be derated by 4.5mW for each degree above 70°C.
Electrical Characteristics
Unless otherwise specified: VIN = VOUT(nom) + 0.5V, CIN = 1 µF, IOUT = 1mA, COUT = 1 µF, CBYPASS = 0.01µF. Typical values and
limits appearing in standard typeface are for TJ = 25°C. Limits appearing in boldface type apply over the entire junction
(1) (2)
temperature range for operation, −40°C to +125°C.
Limit
Symbol
Parameter
Conditions
Typ
Units
Min
Max
Output Voltage
Tolerance
IOUT = 1mA
−2.5
−3.0
2.5
3.0
% of
VOUT(nom)
Line Regulation Error(3)
VIN = (VOUT(nom) + 0.5V) to 6.0V,
IOUT = 1 mA
0.006
0.003
1.5
0.092
0.128
ΔVOUT
%/V
Load Regulation Error(4)
IOUT = 1mA to 150 mA
0.006
0.01
%/mA
mVP-P
Output AC Line Regulation
VIN = VOUT(nom) + 1V,
IOUT = 150 mA (Figure 1)
VIN = 3.1V,
f = 1 kHz,
IOUT = 50 mA (Figure 2)
60
50
PSRR
IQ
Power Supply Rejection Ratio
Quiescent Current
dB
VIN = 3.1V,
f = 10 kHz,
IOUT = 50 mA (Figure 2)
Both Regulators ON
VEN = 1.4V, IOUT = 0 mA
115
220
75
200
320
130
200
Both Regulators ON
VEN = 1.4V, IOUT = 0 to 150 mA
One Regulator ON
VEN = 1.4V IOUT = 0 mA
µA
One Regulator ON
VEN = 1.4V IOUT = 0 to 150 mA
130
0.001
VEN = 0.4V, Both Regulators OFF
(shutdown)
2
4
Dropout Voltage(5)
IOUT = 1 mA
IOUT = 150 mA
0.4
60
2
100
mV
mA
ISC
Short Circuit Current Limit
Output Grounded
600
(1) All limits are guaranteed. All electrical characteristics having room temperature limits are tested during production with TJ = 25°C or
correlated using Statistical Quality Control (SQC) methods. All hot and cold limits are guaranteed by correlating the electrical
characteristics to process and temperature variations and applying statistical process control.
(2) The target output voltage, which is labeled VOUT(nom), is the desired voltage option.
(3) The output voltage changes slightly with line voltage. An increase in the line voltage results in a slight increase in the output voltage and
vice versa.
(4) The output voltage changes slightly with load current. An increase in the load current results in a slight decrease in the output voltage
and vice versa. Tested limit applies to Vout 's of 2.5V and greater.
(5) Dropout voltage is the input-to-output voltage difference at which the output voltage is 100mV below its nominal value.
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SNVS142U –AUGUST 2001–REVISED FEBRUARY 2013
Electrical Characteristics (continued)
Unless otherwise specified: VIN = VOUT(nom) + 0.5V, CIN = 1 µF, IOUT = 1mA, COUT = 1 µF, CBYPASS = 0.01µF. Typical values and
limits appearing in standard typeface are for TJ = 25°C. Limits appearing in boldface type apply over the entire junction
(1) (2)
temperature range for operation, −40°C to +125°C.
Limit
Symbol
Parameter
Conditions
Typ
Units
Min
300
Max
IOUT(PK)
Peak Output Current(6)
Turn-On Time(7)
V
OUT ≥ VOUT(nom) - 5%
500
200
40
mA
µs
TON
en
CBYPASS = 0.01 µF
Output Noise Voltage
BW = 10 Hz to 100 kHz,
COUT = 1µF
µVrms
ρn(1/f)
Output Noise Density
f = 120 Hz,
COUT = 1µF
1
µV/√Hz
IEN
VIL
Maximum Input Current at EN VEN = 0.4 and VIN = 6V
±10
nA
V
Maximum Low Level Input
Voltage at EN
VIN = 2.7 to 6V
0.4
VIH
Minimum High Level Input
Voltage at EN
VIN = 2.7 to 6V
1.4
V
ΔILoad1 = 150 mA at 1KHz rate
ΔILoad2 = 1 mA
ΔVOUT2/ΔVOUT1
−60
−60
Xtalk
Crosstalk Rejection
dB
ΔILoad2 = 150 mA at 1KHz rate
ΔILoad1 = 1 mA
ΔVOUT2/ΔVOUT1
All VOUT > = 2.5V,
1
µF
µF
CIN
Input capacitance(8)
Capacitance(8)
If VOUT = 1.8V,
VIN_MIN>= 2.9V
4.7
COUT
All VOUT > = 2.5V,
1
22
22
µF
µF
If VOUT = 1.8V,
VIN_MIN>= 2.9V
2.2
(9)
ESR
See
5
500
mΩ
(6) IPEAK guaranteed for Vout 's of 2.5V and greater.
(7) Turn-on time is that between the enable input just exceeding VIH and the output voltage just reaching 95% of its nominal value.
(8) Range of capacitor values for which the device will remain stable. This electrical specification is guaranteed by design.
(9) Range of capacitor ESR values for which the device will remain stable. This electrical specification is guaranteed by design.
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SNVS142U –AUGUST 2001–REVISED FEBRUARY 2013
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TEST SIGNALS
Figure 1. Line Regulation Input Test Signal
Figure 2. PSRR Input Test Signal
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SNVS142U –AUGUST 2001–REVISED FEBRUARY 2013
TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise specified, CIN= COUT 1µF Ceramic, C BP= 0.01µ F, VIN = VOUT + 0.5, TA= 25°C, both enable pins are tied to
VIN
Power Supply Rejection Ratio (CBP = 0.001µF)
Power Supply Rejection Ratio (CBP = 0.01µF)
Figure 3.
Figure 4.
Power Supply Rejection Ratio (CBP = 0.1µF)
Output Noise Spectral Density
Figure 5.
Figure 6.
Line Transient Response (CBP = 0.001µF)
Line Transient Response (CBP = 0.01µF)
Figure 7.
Figure 8.
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SNVS142U –AUGUST 2001–REVISED FEBRUARY 2013
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise specified, CIN= COUT 1µF Ceramic, C BP= 0.01µ F, VIN = VOUT + 0.5, TA= 25°C, both enable pins are tied to
VIN
Load Transient & Cross Talk (VIN = VOUT + 0.2V)
Load Transient & Cross Talk (VIN = VOUT + 0.2V)
Figure 9.
Figure 10.
Start-Up Time (CBP = 0.001, 0.01, 0.1µF)
Enable Response ( VIN = 4.2V )
Figure 11.
Figure 12.
Enable Response (VIN = VOUT+ 0.2V)
Enable Response
Figure 13.
Figure 14.
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SNVS142U –AUGUST 2001–REVISED FEBRUARY 2013
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise specified, CIN= COUT 1µF Ceramic, C BP= 0.01µ F, VIN = VOUT + 0.5, TA= 25°C, both enable pins are tied to
VIN
Output Short Circuit Current at VIN = 6V
Output Short Circuit Current at VIN = 3.3V
Figure 15.
Figure 16.
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SNVS142U –AUGUST 2001–REVISED FEBRUARY 2013
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APPLICATION HINTS
EXTERNAL CAPACITORS
Like any low-dropout regulator, the LP3986 requires external capacitors for regulator stability. The LP3986 is
specifically designed for portable applications requiring minimum board space and smallest components. These
capacitors must be correctly selected for good performance.
INPUT CAPACITOR
An input capacitance of ≊ 1µF is required between the LP3986 input pin and ground (the amount of the
capacitance may be increased without limit).
This capacitor must be located a distance of not more than 1cm from the input pin and returned to a clean
analog ground. Any good quality ceramic, tantalum, or film capacitor may be used at the input.
Important: Tantalum capacitors can suffer catastrophic failures due to surge current when connected to a low-
impedance source of power (like a battery or a very large capacitor). If a tantalum capacitor is used at the input,
it must be guaranteed by the manufacturer to have a surge current rating sufficient for the application.
There are no requirements for the ESR on the input capacitor, but tolerance and temperature coefficient must be
considered when selecting the capacitor to ensure the capacitance will be ≊ 1µF over the entire operating
temperature range.
OUTPUT CAPACITOR
The LP3986 is designed specifically to work with very small ceramic output capacitors, any ceramic capacitor
(temperature characteristics X7R, X5R, Z5U or Y5V) in 1 to 22 µF range with 5mΩ to 500mΩ ESR range is
suitable in the LP3986 application circuit.
It may also be possible to use tantalum or film capacitors at the output, but these are not as attractive for
reasons of size and cost (see next section Capacitor Characteristics).
The output capacitor must meet the requirement for minimum amount of capacitance and also have an ESR
(Equivalent Series Resistance) value which is within a stable range.
NO-LOAD STABILITY
The LP3986 will remain stable and in regulation with no-load (other than the internal voltage divider). This is
specially important in CMOS RAM keep-alive applications.
CAPACITOR CHARACTERISTICS
The LP3986 is designed to work with ceramic capacitors on the output to take advantage of the benefits they
offer: for capacitance values in the range of 1µF to 4.7µF range, ceramic capacitors are the smallest, least
expensive and have the lowest ESR values (which makes them best for eliminating high frequency noise). The
ESR of a typical 1µF ceramic capacitor is in the range of 20 mΩ to 40 mΩ, which easily meets the ESR
requirement for stability by the LP3986.
The ceramic capacitor's capacitance can vary with temperature. The capacitor type X7R, which operates over a
temperature range of -55°C to +125°C, will only vary the capacitance to within ±15%. Most large value ceramic
capacitors (≊ 2.2µF) are manufactured with Z5U or Y5V temperature characteristics. Their capacitance can drop
by more than 50% as the temperature goes from 25°C to 85°C. Therefore, X7R is recommended over Z5U and
Y5 in applications where the ambient temperature will change significantly above or below 25°C.
Tantalum capacitors are less desirable than ceramic for use as output capacitors because they are more
expensive when comparing equivalent capacitance and voltage ratings in the 1µF to 4.7µF range.
Another important consideration is that tantalum capacitors have higher ESR values than equivalent size
ceramics. This means that while it may be possible to find a tantalum capacitor with an ESR value within the
stable range, it would have to be larger in capacitance (which means bigger and more costly ) than a ceramic
capacitor with the same ESR value. It should also be noted that the ESR of a typical tantalum will increase about
2:1 as the temperature goes from 25°C down to −40°C, so some guard band must be allowed.
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SNVS142U –AUGUST 2001–REVISED FEBRUARY 2013
NOISE BYPASS CAPACITOR
Connecting a 0.01µF capacitor between the CBYPASS pin and ground significantly reduces noise on the regulator
output. This cap is connected directly to a high impedance node in the band gap reference circuit. Any significant
loading on this node will cause a change on the regulated output voltage. For this reason, DC leakage current
through this pin must be kept as low as possible for best output voltage accuracy. The use of this 0.01µF bypass
capacitor is strongly recommended to prevent overshoot on the output during start up.
The types of capacitors best suited for the noise bypass capacitor are ceramic and film. High-quality ceramic
capacitors with either NPO or COG dielectric typically have very low leakage. Polypropolene and polycarbonate
film capacitors are available in small surface-mount packages and typically have extremely low leakage current.
Unlike many other LDOs, addition of a noise reduction capacitor does not effect the transient response of the
device.
ON/OFF INPUT OPERATION
The LP3986 is turned off by pulling the VEN pin low, and turned on by pulling it high. If this feature is not used,
the VEN pin should be tied to VIN to keep the regulator output on at all times. To assure proper operation, the
signal source used to drive the VEN input must be able to swing above and below the specified turn-on/off voltage
thresholds listed in the Electrical Characteristics section under VIL and VIH.
FAST ON-TIME
The LP3986 outputs are turned on after Vref voltage reaches its final value (1.23V nominal). To speed up this
process, the noise reduction capacitor at the bypass pin is charged with an internal 70µA current source. The
current source is turned off when the bandgap voltage reaches approximately 95% of its final value. The turn on
time is determined by the time constant of the bypass capccitor. The smaller the capacitor value, the shorter the
turn on time, but less noise gets reduced. As a result, turn on time and noise reduction need to be taken into
design consideration when choosing the value of the bypass capacitor.
DSBGA MOUNTING
The DSBGA package requires specific mounting techniques which are detailed in TI's AN-1112 application report
(SNVA009), in particular the section Surface Mount Assembly Considerations.
For best results during assembly, alignment ordinals on the PC board may be used to facilitate placement of the
DSBGA device.
DSBGA LIGHT SENSITIVITY
Exposing the DSBGA device to direct sunlight will cause misoperation of the device. Light sources such as
halogen lamps can effect electrical performance if brought near to the device.
The wavelengths which have most detrimental effect are reds and infra-reds, which means that the fluorescent
lighting used inside most buildings has very little effect on performance. A DSBGA test board was brought to
within 1cm of a fluorescent desk lamp and the effect on the regulated output voltage was negligible, showing a
deviation of less than 0.1% from nominal.
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REVISION HISTORY
Changes from Revision T (February 2013) to Revision U
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 11
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
250
250
250
250
(1)
(2)
(3)
(4/5)
(6)
LP3986TL-2518/NOPB
LP3986TL-2525/NOPB
LP3986TL-2828/NOPB
LP3986TL-3030/NOPB
LP3986TLX285285/NOPB
ACTIVE
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
YZR
8
8
8
8
8
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
D
30
ACTIVE
ACTIVE
ACTIVE
ACTIVE
YZR
SNAGCU
SNAGCU
SNAGCU
SNAGCU
D
27
YZR
-40 to 125
-40 to 125
D
10
YZR
D
12
YZR
3000 RoHS & Green
D
11
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LP3986TL-2518/NOPB DSBGA
LP3986TL-2525/NOPB DSBGA
LP3986TL-2828/NOPB DSBGA
LP3986TL-3030/NOPB DSBGA
LP3986TLX285285/NOPB DSBGA
YZR
YZR
YZR
YZR
YZR
8
8
8
8
8
250
250
250
250
3000
178.0
178.0
178.0
178.0
178.0
8.4
8.4
8.4
8.4
8.4
1.7
1.7
1.7
1.7
1.7
1.7
1.7
1.7
1.7
1.7
0.76
0.76
0.76
0.76
0.76
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
Q1
Q1
Q1
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LP3986TL-2518/NOPB
LP3986TL-2525/NOPB
LP3986TL-2828/NOPB
LP3986TL-3030/NOPB
LP3986TLX285285/NOPB
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
YZR
YZR
YZR
YZR
YZR
8
8
8
8
8
250
250
250
250
3000
208.0
208.0
208.0
208.0
208.0
191.0
191.0
191.0
191.0
191.0
35.0
35.0
35.0
35.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
YZR0008xxx
D
0.600±0.075
E
TLA08XXX (Rev C)
D: Max = 1.591 mm, Min = 1.53 mm
E: Max = 1.591 mm, Min = 1.53 mm
4215045/A
12/12
A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.
B. This drawing is subject to change without notice.
NOTES:
www.ti.com
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