LP3988-Q1 [TI]
具有电源正常指示和使能功能的汽车类 150mA、低压降稳压器;
| 型号： | LP3988-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有电源正常指示和使能功能的汽车类 150mA、低压降稳压器 稳压器 |
| 文件： | 总17页 (文件大小：835K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LP3988-Q1
www.ti.com.cn
ZHCSB96A –MARCH 2013–REVISED JULY 2013
具有电源正常指示功能的微功耗，150mA 超低压降 CMOS 电压稳压器
查询样品: LP3988-Q1
1
特性
说明
2
•
符合汽车应用要求
LP3988-Q1 是一款 150mA 低压降稳压器，此款稳压
器被专门设计成满足便携式电池供电类应用的要求。
LP3988-Q1 与节省空间的，1µF 陶瓷电容器一同工
作。 LP3988-Q1 特有一个指示故障输出情况的错误标
志输出。
•
具有下列结果的 AEC-Q100 测试指南：
–
–
–
器件温度 1 级：-40°C 至 125°C 的环境运行温
度范围
器件人体模型 (HBM) 静电放电 (ESD) 分类等级
H2
LP3988-Q1 的性能针对电池供电类系统进行了优化以
传送低噪声、极低压降电压和低静态电流。 稳压器接
地电流只是轻微地增加了压降，这样进一步延长了电池
使用寿命。
器件充电器件模型 (CDM) ESD 分类等级 C4B
•
•
•
•
小外形尺寸晶体管 (SOT)23-5 封装
电源正常标志输出
逻辑控制使能
低频时电源抑制比好于 60dB，并且在 10kHz 时开始
下降。 此器件将高电源抑制比保持在低水平，以降低
到电池供电类电路的共同输入电压电平。
与陶瓷电容器和高品质钽电容器一起工作时保持稳
定
•
•
快速接通
热关断和短路电流限制
此器件是手机和相类似的电池供电类无线应用的理想选
择。 它在由 2.5V 至 6V 输入电压供电时，可提供高达
150mA 的电流，在禁用模式中流耗少于 1µA，并且快
速接通时间小于 200µs。
应用范围
•
•
•
•
•
•
汽车用
CDMA 手机
LP3988-Q1 采用 5 引脚 SOT-23 封装，额定运行温度
范围为 -40°C 至 125°C，并且可提供 2.85V 输出电
压。 请注意：对于其它电压选项，请与 TI 销售商取得
联系。
宽带 CDMA 手机
GSM 手机
便携式信息设备
微型 3.3V ± 5% 至 2.85V，150mA 转换器
Typical Application Circuit
(C3)
(C1)
5
1
V
V
IN
OUT
1
F
1 F
LP3988-Q1
(A1) 3
(A3)
4
POWER
GOOD
V
EN
2
(B2)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
English Data Sheet: SLAS928
LP3988-Q1
ZHCSB96A –MARCH 2013–REVISED JULY 2013
www.ti.com.cn
Block Diagram
SOT-23-5 PACKAGE
TOP VIEW
Pin Descriptions
Name
VEN
SOT-23
Function
3
2
5
1
Enable Input Logic, Enable High
GND
VOUT
VIN
Common Ground
Output Voltage of the LDO
Input Voltage of the LDO
Power Good Flag (output): open-drain output, connected to an external pull-up resistor.
Active low indicates an output voltage out of tolerance condition.
Power Good
4
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
2
Copyright © 2013, Texas Instruments Incorporated
LP3988-Q1
www.ti.com.cn
ZHCSB96A –MARCH 2013–REVISED JULY 2013
Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
VALUE
UNIT
MIN
MAX
6.5
6
Voltage
−0.3
V
V
Power good
VOUT, VEN
−0.3 V to
(VIN + 0.3 V)
Junction temperature
Storage Temperature
150
150
364
2
°C
°C
−65
(1)
Power dissipation
SOT-23-5
mW
kV
V
Human-body model (HBM) AEC-Q100 Classification Level H2
Charged-device model (CDM) AEC-Q100 Classification Level C4B
(2)
ESD rating
750
(1) The Absolute Maximum power dissipation depends on the ambient temperature and can be calculated using the formula: PD = (TJ - TA) /
θJA, where TJ is the junction temperature, TA is the ambient temperature, and θ JA is the junction-to-ambient thermal resistance. The
364-mW rating appearing under Absolute Maximum Ratings for the SOT-23-5 package results from substituting the absolute-maximum
junction temperature, 150°C, for TJ, 70°C for TA, and 175°C/W for θJA. More power can be dissipated safely at ambient temperatures
below 70°C . Less power can be dissipated safely at ambient temperatures above 70°C. The absolute-maximum power dissipation can
be increased by 4.5 mW for each degree below 70°C, and it must be derated by 4.5 mW for each degree above 70°C.
(2) The human-body model is 100 pF discharged through a 1.5-kΩ resistor into each pin. The machine model is a 200-pF capacitor
discharged directly into each pin.
Recommended Operating Conditions(1)
over operating free-air temperature range (unless otherwise noted)
MIN
2.5
0
NOM
MAX
6
UNIT
V
(2)
VIN
VOUT, VEN
VIN
125
V
Operating temperature
−40
°C
(1) All voltages are with respect to the potential at the GND pin.
(2) The minimum VIN depends on the device output option. For Vout(NOM) < 2.5V, VIN(MIN) will equal 2.5V. For Vout(NOM) ≥ 2.5V, VIN(MIN) will
equal Vout(NOM) + 200mV.
Thermal Information
SOT-23 Package
THERMAL METRIC(1)
UNIT
DBV-5
175
78
θJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
θJC(top)
θJB
31.9
3.1
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
31.4
N/A
θJC(bottom)
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Copyright © 2013, Texas Instruments Incorporated
3
LP3988-Q1
ZHCSB96A –MARCH 2013–REVISED JULY 2013
www.ti.com.cn
Electrical Characteristics
Unless otherwise specified: VEN = 1.8 V, VIN = VOUT + 0.5 V, CIN = 1 µF, IOUT = 1 mA, COUT = 1 µF. Typical values and limits
appearing in standard typeface are for TA = 25°C. Limits appearing in boldface type apply over the entire operating
(1) (2)
temperature range for operation, −40°C to 125°C.
Limit
Symbol
Parameter
Conditions
Units
Min
Typ
Max
Output voltage
−2
2
% of
tolerance
−40°C ≤ TA ≤ 125°C, SOT-23-5
−3.5
3.5
VOUT(nom)
−0.15
−0.2
0.15
0.2
ΔVOUT
Line-regulation error
VIN = VOUT (NOM) + 0.5 V to 6 V
%/V
0.005
0.007
(3)
Load-regulation error
IOUT = 1 mA to 150 mA
%/mA
VIN = VOUT(nom) + 1 V,
f = 1 kHz,
IOUT = 50 mA (Figure 3)
65
45
PSRR
Power-supply rejection ratio
Quiescent current
dB
VIN = VOUT(nom) + 1 V,
f = 10 kHz,
IOUT = 50 mA (Figure 3)
VEN = 1.4 V, IOUT = 0 mA
VEN = 1.4 V, IOUT = 0 to 150 mA
VEN = 0.4V
85
140
0.003
1
120
200
1.0
5
IQ
µA
IOUT = 1 mA
(4)
Dropout Voltage
mV
115
150
IOUT = 150 mA
80
600
220
(5)
ISC
en
Short Circuit Current Limit
Output Noise Voltage
See
mA
BW = 10 Hz to 100 kHz,
COUT = 1 µF
µVrms
(6)
Capacitance
1
5
20
µF
mΩ
°C
COUT
Output Capacitor
(6)
ESR
500
Thermal Shutdown Temperature
160
20
TSD
Thermal Shutdown Hysteresis
°C
(7)
Enable Control Characteristics
IEN
Maximum Input Current at EN
VEN = 0 and VIN = 6 V
VIN = 2.5 V to 6 V
VIN = 2.5 V to 6 V
0.1
0.5
µA
V
VIL
Logic Low Input threshold
Logic High Input threshold
VIH
1.2
V
Power Good
Power Good
VTHL
VTHH
Low threshold
High Threshold
% of VOUT (PG ON) Figure 2
% of VOUT (PG OFF) Figure 2
90
92
93
95
95
98
%
(8)
VOL
IPGL
tON
PG Output Logic Low Voltage
IPULL-UP = 100 µA, fault condition
PG off, VPG = 6 V
VIN = 4.2V
0.02
0.02
10
0.1
V
PG Output Leakage Current
µA
µs
µs
(4)
Power Good Turn On time,
(4)
tOFF
Power Good Turn Off time,
VIN = 4.2V
10
(1) All limits are specified. All electrical characteristics having room-temperature limits are tested during production with TA = 25°C or
correlated using Statistical Quality Control (SQC) methods. All hot and cold limits are specified by correlating the electrical
characteristics to process and temperature variations and applying statistical process control.
(2) The target output voltage, which is labeled VOUT(nom), is the desired voltage option.
(3) An increase in the load current results in a slight decrease in the output voltage and vice versa.
(4) Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal value.
(5) Short-circuit current is measured on input supply line after pulling down VOUT to 95% VOUT(nom)
.
(6) Specified by design. The capacitor tolerance should be ±30% or better over the full temperature range. The full range of operating
conditions such as temperature, dc bias and even capacitor case size for the capacitor in the application should be considered during
device selection to ensure this minimum capacitance specification is met. X7R capacitor types are recommended to meet the full device
temperature range.
(7) Turnon time is time measured between the enable input just exceeding VIH and the output voltage just reaching 95% of its nominal
value.
(8) The low and high thresholds are generated together. Typically a 2.6% difference is seen between these thresholds.
4
Copyright © 2013, Texas Instruments Incorporated
LP3988-Q1
www.ti.com.cn
ZHCSB96A –MARCH 2013–REVISED JULY 2013
Figure 1. Power Good Flag Timing
Figure 2. Line Transient Response Input Perturbation
Figure 3. PSRR Input Perturbation
Copyright © 2013, Texas Instruments Incorporated
5
LP3988-Q1
ZHCSB96A –MARCH 2013–REVISED JULY 2013
www.ti.com.cn
Typical Performance Characteristics
Unless otherwise specified, CIN = COUT = 1 µF ceramic, VIN = VOUT + 0.2 V, TA = 25°C, enable pin is tied to VIN.
RIPPLE REJECTION RATIO (LP3988-Q1-2.85)
RIPPLE REJECTION RATIO (LM3988-2.85)
Figure 4.
Figure 5.
POWER-GOOD RESPONSE TIME (LP3988-Q1-2.85)
(flag pin pulled to VOUT through a 100-kΩ resistor)
POWER-GOOD RESPONSE TIME (LP3988-Q1-2.85)
(flag pin pulled to VIN through a 100-kΩ resistor)
Figure 6.
Figure 7.
POWER-GOOD RESPONSE TIME (LP3988-Q1-2.85)
(flag pin pulled to VOUT through a 100-kΩ resistor)
LINE TRANSIENT RESPONSE (LP3988-Q1-2.85)
Figure 8.
Figure 9.
6
Copyright © 2013, Texas Instruments Incorporated
LP3988-Q1
www.ti.com.cn
ZHCSB96A –MARCH 2013–REVISED JULY 2013
Typical Performance Characteristics (continued)
Unless otherwise specified, CIN = COUT = 1 µF ceramic, VIN = VOUT + 0.2 V, TA = 25°C, enable pin is tied to VIN.
LINE TRANSIENT RESPONSE (LP3988-Q1-2.85)
POWER-UP RESPONSE
Figure 10.
Figure 11.
ENABLE RESPONSE
ENABLE RESPONSE
Figure 12.
Figure 13.
LOAD-TRANSIENT RESPONSE
LOAD-TRANSIENT RESPONSE
Figure 14.
Figure 15.
Copyright © 2013, Texas Instruments Incorporated
7
LP3988-Q1
ZHCSB96A –MARCH 2013–REVISED JULY 2013
www.ti.com.cn
APPLICATION INFORMATION
EXTERNAL CAPACITORS
Like any low-dropout regulator, the LP3988-Q1 requires external capacitors for regulator stability. The LP3988-
Q1 is specifically designed for portable applications requiring minimum board space and smallest components.
These capacitors must be correctly selected for good performance.
INPUT CAPACITOR
An input capacitance of ≊ 1µF is required between the LP3988-Q1 input pin and ground (the amount of the
capacitance may be increased without limit).
This capacitor must be located a distance of not more than 1 cm from the input pin and returned to a clean
analog ground. Any good-quality ceramic, tantalum, or film capacitor may be used at the input.
Important: Tantalum capacitors can suffer catastrophic failures due to surge current when connected to a low-
impedance source of power (like a battery or a very large capacitor). If a tantalum capacitor is used at the input,
it must be specified by the manufacturer to have a surge-current rating sufficient for the application.
There are no requirements for the ESR on the input capacitor, but tolerance and temperature coefficient must be
considered when selecting the capacitor to ensure the capacitance is ≊ 1 µF over the entire operating
temperature range.
OUTPUT CAPACITOR
The LP3988-Q1 is designed specifically to work with very small ceramic output capacitors. A ceramic capacitor
(dielectric types Z5U, Y5V or X7R) in the 1-µF to 22-µF range with a 5-mΩ to 500-mΩ ESR range is suitable in
the LP3988-Q1 application circuit.
It may also be possible to use tantalum or film capacitors at the output, but these are not as attractive for
reasons of size and cost (see the CAPACITOR CHARACTERISTICS section).
The output capacitor must meet the requirement for minimum amount of capacitance and also have an
Equivalent Series Resistance (ESR) value which is within a stable range (5 mΩ to 500 mΩ).
NO-LOAD STABILITY
The LP3988-Q1 remains stable and in regulation with no external load. This is specially important in CMOS RAM
keep-alive applications.
CAPACITOR CHARACTERISTICS
The LP3988-Q1 is designed to work with ceramic capacitors on the output to take advantage of the benefits they
offer: for capacitance values in the range of 1 µF to 4.7 µF, ceramic capacitors are the smallest, least expensive
and have the lowest ESR values (which makes them best for eliminating high-frequency noise). The ESR of a
typical 1-µF ceramic capacitor is in the range of 20 mΩ to 40 mΩ, which easily meets the ESR requirement for
stability by the LP3988-Q1.
The ceramic capacitor's capacitance can vary with temperature. Most large-value ceramic capacitors (≊ 2.2 µF)
are manufactured with Z5U or Y5V temperature characteristics, which results in the capacitance dropping by
more than 50% as the temperature goes from 25°C to 85°C.
A better choice for temperature coefficient in a ceramic capacitor is X7R, which holds the capacitance within
±15%.
Tantalum capacitors are less desirable than ceramic for use as output capacitors because they are more
expensive when comparing equivalent capacitance and voltage ratings in the 1-µF to 4.7-µF range.
Another important consideration is that tantalum capacitors have higher ESR values than equivalent-size
ceramics. This means that while it may be possible to find a tantalum capacitor with an ESR value within the
stable range, it would have to be larger in capacitance (which means bigger and more costly ) than a ceramic
capacitor with the same ESR value. It should also be noted that the ESR of a typical tantalum will increase about
2:1 as the temperature goes from 25°C down to −40°C, so some guard band must be allowed.
8
Copyright © 2013, Texas Instruments Incorporated
LP3988-Q1
www.ti.com.cn
ZHCSB96A –MARCH 2013–REVISED JULY 2013
ON/OFF INPUT OPERATION
The LP3988-Q1 is turned off by pulling the VEN pin low, and turned on by pulling it high. If this feature is not
used, the VEN pin should be tied to VIN to keep the regulator output on at all time. To assure proper operation,
the signal source used to drive the VEN input must be able to swing above and below the specified turnon/turnoff
voltage thresholds listed in the Electrical Characteristics section under VIL and VIH.
FAST ON-TIME
The LP3988-Q1 utilizes a speed-up circuit to ramp up the internal VREF voltage to its final value to achieve a fast
output turnon time.
Copyright © 2013, Texas Instruments Incorporated
9
LP3988-Q1
ZHCSB96A –MARCH 2013–REVISED JULY 2013
www.ti.com.cn
REVISION HISTORY
Changes from Original (March 2013) to Revision A
Page
•
•
•
•
•
Deleted 其它电压，剩下的只用 2.5V .................................................................................................................................... 1
Added TI 销售商对于额外电压的说明 ................................................................................................................................... 1
Changed θJA temp from 220°C/W to 175°C/W in Absolute Maxium Ratings table note ...................................................... 3
Changed voltage in the title of the first two Typical Characteristics graphs (Ripple Rejection Ratio) from 2.6 to 2.85 ....... 6
Changed LP3988Q to correct device name of LP3988-Q1 .................................................................................................. 9
10
Copyright © 2013, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LP3988QMFX-2P85
ACTIVE
SOT-23
DBV
5
3000 RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
RABQ
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LP3988QMFX-2P85
SOT-23
DBV
5
3000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOT-23 DBV
SPQ
Length (mm) Width (mm) Height (mm)
208.0 191.0 35.0
LP3988QMFX-2P85
5
3000
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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