LP3990QTLX-1.8Q1 [TI]
具有使能功能的汽车类 150mA、低 IQ、低压降稳压器 | YZR | 4 | -40 to 125;
| 型号： | LP3990QTLX-1.8Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有使能功能的汽车类 150mA、低 IQ、低压降稳压器 | YZR | 4 | -40 to 125 输出元件 稳压器 调节器 |
| 文件： | 总20页 (文件大小：608K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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LP3990-Q1
ZHCSD25 –OCTOBER 2014
LP3990-Q1 用于数字应用的 150mA 线性电压稳压器
1 特性
3 说明
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
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输入电压范围：2V 至 6V
LP3990-Q1 稳压器具有精确的输出电压、低噪声和低
静态电流，其设计满足便携式电池供电系统的要求。
LP3990-Q1 将在最高达 150mA 的负载电流条件下通
过 2V 低输入电压提供 0.8V 输出。 当通过使能引脚
(EN) 上的逻辑信号切换到关断模式时，器件功耗几乎
降为零。
符合 AEC-Q100 1 级标准
室温下电压精度为 1%
与陶瓷电容器搭配使用时可保持稳定
逻辑控制使能
无需噪声旁路电容
热过载保护和短路保护
输出电压范围：0.8V 至 3.3V
输出电流：150mA
LP3990-Q1 与节省空间的陶瓷电容器搭配使用时可保
持稳定，其电容值低至 1µF。
此器件的额定运行结温范围为 –40°C 至 125°C
输出稳定 - 1µF 电容
几乎零 IQ（禁用时）：< 10nA
极低 IQ（使能时）：43µA
低输出噪声：150µVRMS
电源抑制比 (PSRR)：1kHz 频率时为 55dB
快速启动：105µs
如需 0.8V、1.2V、1.35V、1.5V、1.8V、2.5V、2.8V
或 3.3V 以外的输出电压，请联系德州仪器 (TI) 销售办
事处。
器件信息(1)
器件型号
封装
封装尺寸
LP3990-Q1
1.324mm x 1.045mm（最大
值）
2 应用
DSBGA (4)
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
•
•
•
信息娱乐
仪表
车身电子装置
简化电路原理图
VIN
VOUT
IN
OUT
COUT
1 µF
CIN
1 µF
LP3990
VEN
EN
ON
OFF
GND
GND
GND
1
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
English Data Sheet: SNVSA66
LP3990-Q1
ZHCSD25 –OCTOBER 2014
www.ti.com.cn
目录
7.3 Feature Description................................................... 9
7.4 Device Functional Modes........................................ 10
Application and Implementation ........................ 11
8.1 Application Information............................................ 11
8.2 Typical Application ................................................. 11
Power Supply Recommendations...................... 14
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 Handling Ratings....................................................... 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Output Capacitor, Recommended Specifications ..... 5
6.7 Timing Requirements................................................ 6
6.8 Typical Performance Characteristics ........................ 6
Detailed Description .............................................. 9
7.1 Overview ................................................................... 9
7.2 Functional Block Diagram ......................................... 9
8
9
10 Layout................................................................... 14
10.1 Layout Guidelines ................................................. 14
10.2 Layout Example .................................................... 15
10.3 DSBGA Mounting.................................................. 15
10.4 DSBGA Light Sensitivity ....................................... 15
11 器件和文档支持 ..................................................... 16
11.1 文档支持................................................................ 16
11.2 商标....................................................................... 16
11.3 静电放电警告......................................................... 16
11.4 术语表 ................................................................... 16
12 机械封装和可订购信息 .......................................... 16
7
4 修订历史记录
日期
修订版本
注释
2014 年 10 月
*
最初发布。
2
Copyright © 2014, Texas Instruments Incorporated
LP3990-Q1
www.ti.com.cn
ZHCSD25 –OCTOBER 2014
5 Pin Configuration and Functions
4 Pins
DSBGA (YZR)
EN
A2
IN
IN
EN
A2
B2
B2
A1
B1
B1
A1
GND
OUT
OUT
GND
TOP VIEW
BOTTOM VIEW
Pin Functions
PIN
DSBGA
YZR
A1
I/O
DESCRIPTION
NAME
GND
EN
—
I
Common Ground.
A2
Enable Input; Enables the Regulator when ≥ 0.95 V.
Disables the Regulator when ≤ 0.4 V.
Enable Input has 1-MΩ (typical) pull-down resistor to GND.
OUT
IN
B1
B2
Voltage output. A 1-µF Low ESR Capacitor should be connected to this Pin. Connect this output to
the load circuit.
O
I
Voltage supply Input. A 1-µF capacitor should be connected at this input.
Copyright © 2014, Texas Instruments Incorporated
3
LP3990-Q1
ZHCSD25 –OCTOBER 2014
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)(2)(3)
MIN
–0.3
MAX
6.5
UNIT
Input voltage
Output voltage
–0.3
See(4)
V
ENABLE input voltage
Continuous power dissipation internally limited
–0.3
See(5)
6.5
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
(3) All voltages are with respect to the potential at the GND pin.
(4) The lower of VIN + 0.3 V or 6.5 V.
(5) Internal thermal shutdown circuitry protects the device from permanent damage.
6.2 Handling Ratings
MIN
–65
MAX
150
UNIT
Tstg
Storage temperature range
Electrostatic discharge
°C
Human body model (HBM), per AEC Q100-002(1)
Charged device model (CDM), per AEC Q100-011
–2000
–1500
2000
1500
V(ESD)
V
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2
NOM
MAX
6
UNIT
Input voltage, VIN
V
Enable input voltage, VEN
Junction temperature, TJ
0.0
–40
VIN
125
(1)
°C
(1) TJ(max) = (TA(max) + (RθJA × PD(max)) )
6.4 Thermal Information
LP3990
THERMAL METRIC(1)
YZR (DSBGA)
4 PINS
188.9
1.0
UNIT
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
105.3
0.7
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
105.2
N/A
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
4
Copyright © 2014, Texas Instruments Incorporated
LP3990-Q1
www.ti.com.cn
ZHCSD25 –OCTOBER 2014
6.5 Electrical Characteristics
Unless otherwise noted, VEN = 950 mV, VIN = VOUT + 1 V or VIN = 2 V, whichever is higher. CIN = 1 µF, IOUT = 1 mA, COUT
0.47 µF.
=
(1)
PARAMETER
TEST CONDITIONS
MIN
2
TYP
MAX
6
UNIT
VIN
Input voltage
See(2)
V
ILOAD = 1 mA, TJ = 25°C
–1%
1%
Output voltage tolerance
Line regulation error
Load regulation error
Over full line and load regulation
VIN = (VOUT(NOM) + 1 V) to 6 V
–2.5%
0.1
2.5%
0.1
ΔVOUT
0.02
0.002
0.0005
120
%/V
VOUT = 0.8 V to 1.95 V
VOUT = 2 V to 3.3 V
–0.005
–0.002
0.005
0.002
200
IOUT = 1 mA
to 150 mA
%/mA
VDO
Dropout voltage
Load current
IOUT = 150 mA, see(3)(4)
TJ = 25°, see(4)(5)
mV
µA
ILOAD
0
VEN = 950 mV, IOUT = 0 mA
VEN = 950 mV, IOUT = 150 mA
VEN = 0.4 V (output disabled), TJ = 25°C
43
65
80
120
IQ
Quiescent current
µA
0.002
550
0.2
ISC
Short circuit current limit See(6)
1000
mA
dB
IOUT
Maximum output current
150
ƒ = 1 kHz, IOUT = 1 mA to 150 mA
ƒ = 10 kHz, IOUT = 150 mA
VOUT = 0.8 V
55
35
Power Supply Rejection
Ratio
PSRR
60
BW = 10 Hz to 100
kHz
eη
Output noise voltage(4)
VOUT = 1.5 V
VOUT = 3.3 V
125
180
µVRMS
Junction temperature (TJ) rising until the
output is disabled
155
15
Thermal shutdown
junction temperature
TSHUTDOWN
°C
Hysteresis
ENABLE CONTROL CHARACTERISTICS
VEN = 0 V (Output is disabled)
TJ = 25°C
0.001
6
0.1
10
Maximum input current
at EN pin
(7)
IEN
µA
V
VEN = 6 V
2.5
VIN = 2 V to 6 V
VEN falling from ≥ VIH until the output is
disabled
VIL
VIH
Low input threshold
High input threshold
0.4
VIN = 2 V to 6 V
VEN rising from ≤ VIL until the output is
enabled
0.95
(1) Minimum and Maximum limits are ensured through test, design, or statistical correlation over the operating junction temperature range
(TJ) of –40°C to 125°C, unless otherwise stated. Typical values represent the most likely parametric norm at TJ = 25°C, and are
provided for reference purposes only.
(2) VIN(MIN) = VOUT(NOM) + 0.5 V, or 2 V, whichever is higher.
(3) Dropout voltage is voltage difference between input and output at which the output voltage drops to 100 mV below its nominal value.
This parameter applies only for output voltages above 2 V.
(4) This electrical specification is verified by design.
(5) The device maintains the regulated output voltage without the load.
(6) Short-circuit current is measured with VOUT pulled to 0 V and VIN worst case = 6 V.
(7) ENABLE Pin has 1-MΩ (typical) resistor connected to GND.
6.6 Output Capacitor, Recommended Specifications(1)
PARAMETER
TEST CONDITIONS
Capacitance(2)
ESR
MIN
0.7(3)
5
TYP
MAX
UNIT
µF
1
500
COUT
Output capacitance
mΩ
(1) Unless otherwise specified, values and limits apply for TJ = 25°C.
(2) The full operating conditions for the application should be considered when selecting a suitable capacitor to ensure that the minimum
value of capacitance is always met. Recommended capacitor type is X7R. However, dependent on application, X5R, Y5V, and Z5U can
also be used. (See Detailed Design Procedure.)
(3) Limit applies over the full operating junction temperature range (TJ) of −40°C to 125°C.
Copyright © 2014, Texas Instruments Incorporated
5
LP3990-Q1
ZHCSD25 –OCTOBER 2014
www.ti.com.cn
6.7 Timing Requirements
MIN
NOM(1)
80
MAX(2)
UNIT
VOUT = 0.8 V
VOUT = 1.5 V
VOUT = 3.3 V
150
200
250
From VEN ↑ VIH to
VOUT 95% level
(VIN(MIN) to 6 V)
(3)
TON
Turnon time
105
µs
175
Line transient response
Trise = Tfall = 30 µs(3)
ΔVIN = 600 mV
,
mV (pk-
pk)
8
16
(ΔVOUT
)
Transient
response
Trise = Tfall = 1 µs(3)
IOUT = 1 mA to 150 mA
COUT = 1 µF
,
Load transient response
(ΔVOUT
55
100
mV
)
(1) Nom values apply for TJ = 25°C.
(2) Maximum limits apply over the full operating junction temperature (TJ) range of −40°C to 125°C.
(3) This electrical specification is verified by design.
6.8 Typical Performance Characteristics
Unless otherwise specified, CIN = 1 µF ceramic, COUT = 0.47 µF ceramic, VIN = VOUT(NOM) + 1 V, TA = 25°C, VOUT(NOM) = 1.5 V;
VEN = VIN.
2.00
1.50
1.00
0.50
0.00
-0.50
-1.00
-1.50
-2.00
80
70
60
50
40
30
20
10
0
T
= 125°C
J
T
= -40°C
J
T
J
= 25°C
-40 -25
0
25
50
75 100 125
0
25
50
75
100
125
150
TEMPERATURE (°C)
LOAD CURRENT (mA)
Figure 1. Output Voltage Change vs Temperature
Figure 2. Ground Current vs Load Current
100
90
80
70
60
100
90
80
70
60
T
= 125°C
T = 125°C
J
J
50
40
50
40
T
J
= 25°C
T
J
= 25°C
T
J
= -40°C
T
J
= -40°C
30
20
30
20
2
2.5
3
3.5
4
4.5
5
5.5
6
2
2.5
3
3.5
4
4.5
5
5.5
6
V
V
IN
IN
ILOAD = 0 mA
ILOAD = 1 mA
Figure 3. Ground Current vs VIN
Figure 4. Ground Current vs VIN
6
Copyright © 2014, Texas Instruments Incorporated
LP3990-Q1
www.ti.com.cn
ZHCSD25 –OCTOBER 2014
Typical Performance Characteristics (continued)
Unless otherwise specified, CIN = 1 µF ceramic, COUT = 0.47 µF ceramic, VIN = VOUT(NOM) + 1 V, TA = 25°C, VOUT(NOM) = 1.5 V;
VEN = VIN.
100
V
2.5V
IN =
800
600
400
200
0
90
80
70
60
50
40
T
= 125°C
J
T
J
= 25°C
T
J
= -40°C
30
20
2
2.5
3
3.5
4
4.5
5
5.5
6
V
TIME (100 Ps/DIV)
IN
ILOAD = 150 mA
Figure 6. Short Circuit Current
Figure 5. Ground Current vs VIN
C
C
= 1 PF
IN
V
6V
IN =
800
600
400
200
0
= 0.47 PF
OUT
IL = 1 to 150 mA
3.1
2.5
TIME (100 Ps/DIV)
TIME (100 Ps/DIV)
Figure 7. Short Circuit Current
Figure 8. Line Transient
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
C
= 0.47 PF
C
OUT
= 1 PF
OUT
I
= 150 mA
I
L
= 1 mA
LOAD
C = 0.47 PF
OUT
C
OUT
= 1 PF
100
1k
10k
100k
1M
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 10. Power Supply Rejection Ratio
Figure 9. Power Supply Rejection Ratio
Copyright © 2014, Texas Instruments Incorporated
7
LP3990-Q1
ZHCSD25 –OCTOBER 2014
www.ti.com.cn
Typical Performance Characteristics (continued)
Unless otherwise specified, CIN = 1 µF ceramic, COUT = 0.47 µF ceramic, VIN = VOUT(NOM) + 1 V, TA = 25°C, VOUT(NOM) = 1.5 V;
VEN = VIN.
10
I
1 mA
L =
V
= 3.3V
OUT
1
V
= 1.5V
OUT
0.1
0.01
0.1
1
10
100
FREQUENCY (kHz)
TIME (50 Ps/DIV)
Figure 11. Enable Start-Up Time
Figure 12. Noise Density
8
Copyright © 2014, Texas Instruments Incorporated
LP3990-Q1
www.ti.com.cn
ZHCSD25 –OCTOBER 2014
7 Detailed Description
7.1 Overview
The LP3990-Q1 is designed to meet the requirements of portable, battery-powered digital systems providing an
accurate output voltage with fast start-up. When disabled via a low logic signal at the enable pin (EN), the power
consumption is reduced to virtually zero.
The device is designed to perform with a single 1-μF input capacitor and a single 1-μF ceramic output capacitor.
7.2 Functional Block Diagram
LP3990
IN
OUT
Current
Limit
Thermal
Shutdown
+
ON
V
OFF
REF
800 mV
EN
1 Mꢀꢀ
GND
7.3 Feature Description
7.3.1 Enable (EN)
The LP3990-Q1 Enable (EN) pin is internally held low by a 1-MΩ resistor to GND. The EN pin voltage must be
higher than the VIH threshold to ensure that the device is fully enabled under all operating conditions. The EN pin
voltage must be lower than the VIL threshold to ensure that the device is fully disabled. If the EN pin is left open
the LP3990-Q1 output will be disabled.
7.3.2 Thermal Overload Protection (TSD
)
Thermal Shutdown disables the output when the junction temperature rises to approximately 155°C which allows
the device to cool. When the junction temperature cools to approximately 140°C, the output circuitry enables.
Based on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may
cycle on and off. This thermal cycling limits the dissipation of the regulator and protects it from damage as a
result of overheating.
The Thermal Shutdown circuitry of the LP3990-Q1 has been designed to protect against temporary thermal
overload conditions. The Thermal Shutdown circuitry was not intended to replace proper heat-sinking.
Continuously running the LP3990-Q1 device into thermal shutdown may degrade device reliability.
Copyright © 2014, Texas Instruments Incorporated
9
LP3990-Q1
ZHCSD25 –OCTOBER 2014
www.ti.com.cn
7.4 Device Functional Modes
7.4.1 Enable (EN)
The LP3990-Q1 EN pin is internally held low by a 1-MΩ resistor to GND. The EN pin voltage must be higher than
the VIH threshold to ensure that the device is fully enabled under all operating conditions.
7.4.2 Minimum Operating Input Voltage (VIN)
The LP3990-Q1 does not include any dedicated UVLO circuitry. The LP3990-Q1 internal circuitry is not fully
functional until VIN is at least 2 V. The output voltage is not regulated until VIN ≥ (VOUT + VDO), or 2 V, whichever
is higher.
10
Copyright © 2014, Texas Instruments Incorporated
LP3990-Q1
www.ti.com.cn
ZHCSD25 –OCTOBER 2014
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LP3990-Q1 is a linear voltage regulator for digital applications designed to be stable with space-saving
ceramic capacitors as small as 1 µF.
8.2 Typical Application
Figure 13 shows the typical application circuit for the LP3990-Q1. The input and output capacitances may need
to be increased above the 1 μF shown for some applications.
VIN
VOUT
IN
OUT
COUT
1 µF
CIN
1 µF
LP3990
VEN
EN
ON
OFF
GND
GND
GND
Figure 13. LP3990-Q1 Typical Application
8.2.1 Design Requirements
DESIGN PARAMETER
Input voltage range
EXAMPLE VALUE
2 V to 6 V
1.8 V
Output voltage
Output current
100 mA
Output capacitor range
Input/output capacitor ESR range
1 µF
5 mΩ to 500 mΩ
8.2.2 Detailed Design Procedure
To begin the design process, determine the following:
•
•
•
•
Available input voltage range
Output voltage needed
Output current needed
Input and output capacitors
8.2.2.1 Power Dissipation and Device Operation
The permissible power dissipation for any package is a measure of the capability of the device to pass heat from
the power source, the junctions of the IC, to the ultimate heat sink, the ambient environment. Thus, the power
dissipation is dependent on the ambient temperature and the thermal resistance across the various interfaces
between the die junction and ambient air.
The maximum allowable power dissipation for the device in a given package can be calculated using Equation 1:
PD-MAX = ((TJ-MAX - TA) / RθJA
)
(1)
Copyright © 2014, Texas Instruments Incorporated
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LP3990-Q1
ZHCSD25 –OCTOBER 2014
www.ti.com.cn
The actual power being dissipated in the device can be represented by Equation 2:
PD = (VIN - VOUT) x IOUT
(2)
These two equations establish the relationship between the maximum power dissipation allowed due to thermal
consideration, the voltage drop across the device, and the continuous current capability of the device. These two
equations should be used to determine the optimum operating conditions for the device in the application.
In applications where lower power dissipation (PD) and/or excellent package thermal resistance (RθJA) is present,
the maximum ambient temperature (TA-MAX) may be increased.
In applications where high power dissipation and/or poor package thermal resistance is present, the maximum
ambient temperature (TA-MAX) may have to be derated. TA-MAX is dependent on the maximum operating junction
temperature (TJ-MAX-OP = 125°C), the maximum allowable power dissipation in the device package in the
application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (RθJA),
as given by Equation 3:
TA-MAX = (TJ-MAX-OP – (RθJA × PD-MAX))
(3)
Alternately, if TA-MAX can not be derated, the PD value must be reduced. This can be accomplished by reducing
VIN in the 'VIN–VOUT' term as long as the minimum VIN is met, or by reducing the IOUT term, or by some
combination of the two.
8.2.2.2 External Capacitors
In common with most regulators, the LP3990-Q1 requires external capacitors for regulator stability. The LP3990-
Q1 is specifically designed for portable applications requiring minimum board space and smallest components.
These capacitors must be correctly selected for good performance.
8.2.2.3 Input Capacitor
An input capacitor is required for stability. It is recommended that a 1-µF capacitor be connected between the
LP3990-Q1 IN pin and GND pin (this capacitance value may be increased without limit).
This capacitor must be located a distance of not more than 1 cm from the IN pin and returned to a clean
analogue ground. Any good quality ceramic, tantalum, or film capacitor may be used at the input.
Important: To ensure stable operation it is essential that good PCB design practices are employed to minimize
ground impedance and keep input inductance low. If these conditions cannot be met, or if long leads are used to
connect the battery or other power source to the LP3990-Q1, then it is recommended that the input capacitor is
increased. Also, tantalum capacitors can suffer catastrophic failures due to surge current when connected to a
low-impedance source of power (like a battery or a very large capacitor). If a tantalum capacitor is used at the
input, it must be ensured by the manufacturer to have a surge current rating sufficient for the application.
There are no requirements for the ESR (Equivalent Series Resistance) on the input capacitor, but tolerance and
temperature coefficient must be considered when selecting the capacitor to ensure the capacitance will remain
approximately 1 µF over the entire operating temperature range.
8.2.2.4 Output Capacitor
The LP3990-Q1 is designed specifically to work with very small ceramic output capacitors. A 1-µF ceramic
capacitor (temperature types Z5U, Y5V or X7R/X5R) with ESR between 5 mΩ to 500 mΩ, is suitable in the
LP3990-Q1 application circuit.
For this device the output capacitor should be connected between the OUT pin and GND pin.
It is also possible to use tantalum or film capacitors at the device output, but these are not as attractive for
reasons of size and cost (see Capacitor Characteristics).
The output capacitor must meet the requirement for the minimum value of capacitance and also have an ESR
value that is within the range 5 mΩ to 500 mΩ for stability.
8.2.2.5 No-Load Stability
The LP3990-Q1 will remain stable and in regulation with no external load. This is an important consideration in
some circuits, for example CMOS RAM keep-alive applications.
12
Copyright © 2014, Texas Instruments Incorporated
LP3990-Q1
www.ti.com.cn
ZHCSD25 –OCTOBER 2014
8.2.2.6 Capacitor Characteristics
The LP3990-Q1 is designed to work with ceramic capacitors on the output to take advantage of the benefits they
offer. For capacitance values in the range of 0.47 µF to 4.7 µF, ceramic capacitors are the smallest, least
expensive and have the lowest ESR values, thus making them best for eliminating high frequency noise. The
ESR of a typical 1-µF ceramic capacitor is in the range of 20 mΩ to 40 mΩ, which easily meets the ESR
requirement for stability for the LP3990-Q1.
For both input and output capacitors, careful interpretation of the capacitor specification is required to ensure
correct device operation. The capacitor value can change greatly, depending on the operating conditions and
capacitor type.
In particular, the output capacitor selection should take account of all the capacitor parameters, to ensure that the
specification is met within the application. The capacitance can vary with DC bias conditions as well as
temperature and frequency of operation. Capacitor values will also show some decrease over time due to aging.
The capacitor parameters are also dependant on the particular case size, with smaller sizes giving poorer
performance figures in general. As an example, Figure 14 shows a typical graph comparing different capacitor
case sizes in a Capacitance vs. DC Bias plot. As shown in the graph, increasing the DC Bias condition can result
in the capacitance value falling below the minimum value given in the recommended capacitor specifications
table (0.7 µF in this case). Note that the graph shows the capacitance out of spec for the 0402 case size
capacitor at higher bias voltages. It is therefore recommended that the capacitor manufacturers’ specifications for
the nominal value capacitor are consulted for all conditions, as some capacitor sizes (for example, 0402) may not
be suitable in the actual application.
0603, 10V, X5R
100%
80%
60%
0402, 6.3V, X5R
40%
20%
0
1.0
2.0
3.0
4.0
5.0
DC BIAS (V)
Figure 14. Typical Variation In Capacitance vs DC Bias
The ceramic capacitor’s capacitance can vary with temperature. The capacitor type X7R, which operates over a
temperature range of –55°C to 125°C, will only vary the capacitance to within ±15%. The capacitor type X5R has
a similar tolerance over a reduced temperature range of –55°C to 85°C. Many large value ceramic capacitors,
larger than 1 µF are manufactured with Z5U or Y5V temperature characteristics. Their capacitance can drop by
more than 50% as the temperature varies from 25°C to 85°C. Therefore, X7R and X5R types are recommended
over Z5U and Y5V in applications where the ambient temperature will change significantly above or below 25°C.
Tantalum capacitors are less desirable than ceramic for use as output capacitors because they are more
expensive when comparing equivalent capacitance and voltage ratings in the 0.47-µF to 4.7-µF range.
Another important consideration is that tantalum capacitors have higher ESR values than equivalent size
ceramics. This means that while it may be possible to find a tantalum capacitor with an ESR value within the
stable range, it would have to be larger in capacitance (which means bigger and more costly) than a ceramic
capacitor with the same ESR value. It should also be noted that the ESR of a typical tantalum will increase about
2:1 as the temperature goes from 25°C down to -40°C, so some guard band must be allowed.
8.2.2.7 Enable Control
The LP3990-Q1 features an active high Enable pin, EN, which turns the device on when pulled high. When not
enabled the regulator output is off and the device typically consumes 2 nA.
If the application does not require the Enable switching feature, the EN pin should be tied to VIN to keep the
regulator output permanently on.
Copyright © 2014, Texas Instruments Incorporated
13
LP3990-Q1
ZHCSD25 –OCTOBER 2014
www.ti.com.cn
To ensure proper operation, the signal source used to drive the EN input must be able to swing above and below
the specified turn-on/off voltage thresholds listed in the Electrical Characteristics section under VIL and VIH.
An internal 1-MΩ pull-down resistor ties the EN input to ground, ensuring that the device remains off if the EN pin
is left open circuit.
8.2.3 Application Curves
I
150 mA
L =
C
C
= 1 PF
IN
= 0.47 PF
OUT
150
1
TIME (20 Ps/DIV)
TIME (50 Ps/DIV)
Figure 16. Load Transient
Figure 15. Enable Start-Up Time
9 Power Supply Recommendations
This device is designed to operate from an input supply voltage range of 2 V to 6 V. The input supply should be
well regulated and free of spurious noise. To ensure that the LP3990-Q1 output voltage is well regulated, the
input supply should be at least VOUT + 0.5 V, or 2 V, whichever is higher. A minimum capacitor value of 1-μF is
required to be within 1 cm of the IN pin.
10 Layout
10.1 Layout Guidelines
The dynamic performance of the LP3990-Q1 is dependant on the layout of the PCB. PCB layout practices that
are adequate for typical LDOs may degrade the load regulation, PSRR, noise, or transient performance of the
LP3990-Q1.
Best performance is achieved by placing CIN and COUT on the same side of the PCB as the LP3990-Q1, and as
close as is practical to the package. The ground connections for CIN and COUT should be back to the LP3990-Q1
ground pin using as wide, and as short, of a copper trace as is practical.
Connections using long trace lengths, narrow trace widths, and/or connections through vias should be avoided.
These will add parasitic inductances and resistance that results in inferior performance especially during transient
conditions.
A Ground Plane, either on the opposite side of a two-layer PCB, or embedded in a multi-layer PCB, is strongly
recommended. This Ground Plane will provide a circuit reference plane to assure accuracy.
14
Copyright © 2014, Texas Instruments Incorporated
LP3990-Q1
www.ti.com.cn
ZHCSD25 –OCTOBER 2014
10.2 Layout Example
VIN
VOUT
LP3990TL
B2
B1
A1
COUT
CIN
A2
Power Ground
VEN
Figure 17. LP3990-Q1 DSBGA Layout
10.3 DSBGA Mounting
The DSBGA package requires specific mounting techniques, which are detailed in TI Application Note DSBGA
Wafer Level Chip Scale Package (SNVA009).
For best results during assembly, alignment ordinals on the PC board may be used to facilitate placement of the
DSBGA device.
10.4 DSBGA Light Sensitivity
Exposing the DSBGA device to direct light may affect the operation of the device. Light sources, such as halogen
lamps, can affect electrical performance, if placed in close proximity to the device.
Light with wavelengths in the infra-red portion of the spectrum is the most detrimental, and so, fluorescent
lighting used inside most buildings, has little or no effect on performance.
版权 © 2014, Texas Instruments Incorporated
15
LP3990-Q1
ZHCSD25 –OCTOBER 2014
www.ti.com.cn
11 器件和文档支持
11.1 文档支持
11.1.1 相关文档ꢀ
相关文档如下：
•
TI 应用手册《DSBGA 晶圆级芯片规模封装》（文献编号：SNVA009）。
11.2 商标
All trademarks are the property of their respective owners.
11.3 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.4 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、首字母缩略词和定义。
12 机械封装和可订购信息
以下页中包括机械封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不对
本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
16
版权 © 2014, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LP3990QTLX-1.2Q1
LP3990QTLX-1.8Q1
LP3990QTLX-2.8Q1
ACTIVE
ACTIVE
ACTIVE
DSBGA
DSBGA
DSBGA
YZR
YZR
YZR
4
4
4
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
SNAGCU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
SNAGCU
SNAGCU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
YZR0004
D
0.600±0.075
E
TLA04XXX (Rev D)
D: Max = 1.324 mm, Min =1.263 mm
E: Max = 1.045 mm, Min =0.984 mm
4215042/A
12/12
A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.
B. This drawing is subject to change without notice.
NOTES:
www.ti.com
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相关型号：
LP3990SD-1.2/NOPB
IC VREG 1.2 V FIXED POSITIVE REGULATOR, PDSO6, ROHS COMPLIANT, LLP-6, Fixed Positive Single Output Standard Regulator
NSC
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