LP3997MM-3.3/NOPB [TI]
具有电源正常指示和使能功能的 250mA、低压降稳压器 | DGK | 8 | -40 to 125;
| 型号： | LP3997MM-3.3/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有电源正常指示和使能功能的 250mA、低压降稳压器 | DGK | 8 | -40 to 125 光电二极管 输出元件 稳压器 调节器 |
| 文件： | 总18页 (文件大小：1038K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LP3997
www.ti.com
SNVS272B –MAY 2004–REVISED MAY 2013
Micropower 250-mA CMOS LDO Regulator With Error Flag and Power-On-Reset
Check for Samples: LP3997
1
FEATURES
DESCRIPTION
The LP3997 regulator is designed to meet the
requirements of portable, battery-powered systems,
providing accurate output voltage, low noise, and low
quiescent current. The LP3997 provides 3.3V output
at up to 250mA load current. The chip architecture is
capable of providing output voltages as low as 0.8V.
When switched in shutdown mode, the power
consumption is virtually zero.
2
•
Low 140-mV Dropout at 250-mA Load
Stable With Ceramic Capacitor.
Low Noise With Bypass Capacitor
Less Than 80 µA Typical IQ at 250 mA
Virtually Zero IQ (Disabled)
•
•
•
•
•
•
•
Thermal and Short Circuit Protection
(1)
3.3-V Output
The LP3997 is designed to be stable with space
saving ceramic output capacitor as small as 1µF.
(2)
8-Lead VSSOP Package
The LP3997 also includes an out-of-regulation error
flag. When the output is more than 5% below its
nominal voltage, the error flag sets to low. If a
capacitor is connected to device’s delay pin, a
delayed power-on reset signal will be generated.
APPLICATIONS
•
•
•
•
•
Portable Consumer Electronics
Cellular Handsets
Laptop and Palm Computers
PDAs
Digital Cameras
(1) For other voltage options, contact your TI sales office
(2) For other package options, contact your TI sales office.
Typical Application Circuit
4
5
V
V
IN
V
OUT
IN
V
OUT
6
8
2
SENSE
ERROR
SD
Enable
470k
LP3997
7
Error/POR
DELAY
1
C
BYP
GND
3
0.1 mF
2.2 mF
0.1 mF
2.2 mF
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2013, Texas Instruments Incorporated
LP3997
SNVS272B –MAY 2004–REVISED MAY 2013
www.ti.com
Functional Block Diagram
V
IN
-
V
OUT
+
SENSE
ON
SD
RFB2
RFB1
POR
OFF
2.2 mA
0.5V
ERROR
6 MW
1.2V
+
-
V
REF
GND
C
DELAY
BYP
Pin Descriptions
Pin No.
Name
Description
1
CBYP
Noise bypass pin. For low noise applications a 0.1µF or larger ceramic capacitor should be connected from
this pin to ground. This will also improve PSSR.
2
DELAY
A capacitor connected from this pin to ground will allow a delayed power-on-reset signal at the ERROR (pin
7) output. See Applications Information.
3
4
5
6
GND
VIN
Ground pin. Local ground for CBYP ,CIN, COUT and CDELAY
.
Input supply pin. Connect CIN between this pin and GND.
VOUT
SENSE
Output voltage, Connect COUT between this pin and ground.
Connect this pin to VOUT (pin 5). For best performance the connection should be made as close to the load
as possible.
7
8
ERROR
SD
This open drain output is an error flag output which goes low when VOUT drops 5% below its nominal
voltage. This pin also provides a power-on-reset signal if a capacitor is connected to the DELAY pin.
Shutdown. Disables the regulator when less than 0.4V is applied. Enables the regulator when greater than
0.9V. The Shutdown pin is pulled down internally by a 6MΩ resistor.
Connection Diagram
C
1
2
3
4
8
7
6
5
BYP
SD
DELAY
GND
ERROR
SENSE
V
V
IN
OUT
8-Lead VSSOP
Package Number DGK
2
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1) (2)(3)
Input Voltage
-0.3 to 6.5V
-0.3 to (VIN + 0.3V) with 6.5V (max)
-0.3 to (VIN + 0.3V) with 6.5V (max)
150°C
Output Voltage
SD Input Voltage
Junction Temperature
Lead/Pad Temp.
VSSOP
260°C
-65 to 150°C
Internally Limited(4)
2KV
Storage Temperature
Continuous Power Dissipation
Human Body Model(5)
Machine Model
Human Body Model(5)
All Pins Except CBYP
CBYP Pin
200V
ESD
1KV
Machine Model
100V
(1) Absolute Maximum Ratings are limits beyond which damage can occur. Operating Ratings are conditions under which operation of the
device is ensured. Operating Ratings do not imply ensured performance limits. For ensured performance limits and associated test
conditions, see the Electrical Characteristics tables.
(2) All Voltages are with respect to the potential at the GND pin.
(3) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
(4) Internal thermal shutdown circuitry protects the device from permanent damage.
(5) The human body model is 100pF discharged through a 1.5kΩ resistor into each pin. The machine model is a 200pF capacitor
discharged directly into each pin.
Operating Ratings(1)
Input Voltage
2V to 6V
-40°C to 125°C
-40°C to 85°C
Junction Temperature
Ambient Temperature TA Range(2)
(1) Absolute Maximum Ratings are limits beyond which damage can occur. Operating Ratings are conditions under which operation of the
device is ensured. Operating Ratings do not imply ensured performance limits. For ensured performance limits and associated test
conditions, see the Electrical Characteristics tables.
(2) The maximum ambient temperature (TA(max)) is dependant on the maximum operating junction temperature (TJ(max-op) = 125°C), the
maximum power dissipation of the device in the application (PD(max)), and the junction to ambient thermal resistance of the part/package
in the application (θJA), as given by the following equation: TA(max) = TJ(max-op) - (θJA × PD(max)).
Thermal Properties(1)
Junction To Ambient Thermal Resistance(2), θJA (VSSOP)
210°C/W
(1) Absolute Maximum Ratings are limits beyond which damage can occur. Operating Ratings are conditions under which operation of the
device is ensured. Operating Ratings do not imply ensured performance limits. For ensured performance limits and associated test
conditions, see the Electrical Characteristics tables.
(2) Junction to ambient thermal resistance is dependant on the application and board layout. In applications where high maximum power
dissipation is possible, special care must be paid to thermal dissipation issues in board design.
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SNVS272B –MAY 2004–REVISED MAY 2013
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Electrical Characteristics
Unless otherwise noted, SD = 950mV, VIN = VOUT + 1.0V, CIN = 2.2 µF, IOUT = 1 mA, COUT = 2.2 µF and CBYP = 0.1 µF.
Typical values and limits appearing in normal type apply for TJ = 27°C. Limits appearing in boldface type apply over the full
(1)
temperature range for operation, −40 to +125°C.
Limit
Symbol
Parameter
Test Conditions
Typ
Unit
Min
2
Max
6
VIN
Input Voltage
V
ΔVOUT
Output Voltage Tolerance
Line Regulation Error
Over full line and load regulation
-1.5
-3
+1.5
+3
%
VIN = (VOUT(NOM) + 1.0V) to 6.0V,
IOUT = 1mA
0.02
0.3
%/V
Load Regulation Error
Dropout Voltage(2)
Load Current
IOUT = 1mA to 250mA
IOUT = 250mA
20
80
µV/mA
mV
VDO
ILOAD
IQ
140
400
(3) (4)
See
0
µA
Quiescent Current
SD = 950mV, IOUT = 0mA
SD = 950mV, IOUT = 250mA
SD = 0.4V
55
80
100
150
0.5
µA
0.01
600
(5)
ISC
Short Circuit Current Limit
Maximum Output Current
See
1000
mA
mA
IOUT
PSRR
250
Power Supply Rejection Ratio CBYP = 0.1µF
f = 1kHz, IOUT
1mA to 150mA
=
61
55
61
39
f = 10kHz, IOUT
150mA
=
dB
Without CBYP
f = 1kHz, IOUT
1mA to 150mA
=
f = 10kHz, IOUT
150mA
=
w/o CBYP
180
100
150
10
BW = 10Hz to 100kHz,
VIN = VOUT(nom) +1V
en
Output noise Voltage(4)
Thermal Shutdown
µVRMS
°C
CBYP = 0.1µF
TSHUTDOWN
Temperature
Hysteresis
Shutdown Control Characteristics
ISD
Maximum Input Current at SD SD = 0.0V
0.01
1
µA
Input
(6)
SD = 6V
VIL
VIH
Low Input Threshold
High Input Threshold
VIN = 2V to 6V
VIN = 2V to 6V
0.4
V
V
0.95
Error Flag Characteristics
VTH
Power Good Trip Threshold
VIN Rising
95
2.5
0.1
91
99
%VOUT
%VOUT
VHYST
VOL
Hysteresis
VIN Rising or Falling
ISINK = 2mA
ErrorError OutputOutput low
Voltage
0.4
V
IOFF
Error Output High Leakage
Delay Pin Current Source
ERROR = VOUT(NOM)
VOUT > 95% VOUT(NOM)
10
2000
nA
µA
IDELAY
2.2
1.2
3
(1) All limits are ensured. All electrical characteristics having room-temperature limits are tested during production at TJ = 25°C or correlated
using Statistical Quality Control methods. Operation over the temperature specification is ensured by correlating the electrical
characteristics to process and temperature variations and applying statistical process control.
(2) Dropout voltage is defined as the voltage difference between input and output when the output voltage drops 100mV below its nominal
value.
(3) The device maintains the regulated output voltage without the load.
(4) This electrical specification is ensured by design.
(5) Short circuit current is measured on the input supply line at the point when the short circuit condition reduces the output voltage to 5% of
its nominal value.
(6) SD Pin has 6MΩ typical, resistor connected to GND.
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Electrical Characteristics (continued)
Unless otherwise noted, SD = 950mV, VIN = VOUT + 1.0V, CIN = 2.2 µF, IOUT = 1 mA, COUT = 2.2 µF and CBYP = 0.1 µF.
Typical values and limits appearing in normal type apply for TJ = 27°C. Limits appearing in boldface type apply over the full
(1)
temperature range for operation, −40 to +125°C.
Limit
Symbol
Parameter
Test Conditions
Typ
Unit
Min
Max
250
Timing Characteristics
(7)
tON
Turn On Time
To 95% Level
w/o CBYP
150
2
µs
CBYP = 0.1µF
w/o CBYP
ms
Transient
Response
Line Transient Response
Trise = Tfall = 30µs(7)
40
4
mV
(pk - pk)
|δVOUT
|
δVIN = 600mV
CBYP = 0.1µF
Load Transient Response
|δVOUT
Trise = Tfall = 1µs(7)
IOUT = 1mA to 150mA
70
80
mV
|
(7) This electrical specification is ensured by design.
Output Capacitor, Recommended Specifications
Limit
Symbol
Parameter
Output Capacitor
Conditions
Typ
Unit
Min
0.7
5
Max
Co
Capacitance(1)
ESR
2.2
µF
500
mΩ
(1) The capacitor tolerance should be 30% or better over temperature. The full operating conditions for the application should be considered
when selecting a suitable capacitor to ensure that the minimum value of capacitance is always met. Recommended capacitor type is
X7R. However, dependent on application, X5R, Y5V, and Z5U can also be used. (See capacitor characteristics section in Applications
Information).
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Typical Performance Characteristics.
Unless otherwise noted, SD = 950mV, VIN = VOUT + 1.0V, CIN = 2.2 µF, IOUT = 1 mA, COUT = 2.2 µF and CBYP = 0.1 µF.
Typical values and limits appearing in normal type apply for TJ = 27°C. Limits appearing in boldface type apply over the full
temperature range for operation, −40 to +125°C.
Output Voltage Change vs Temperature
Ground Current vs Load Current
100
90
80
70
60
50
40
30
20
10
0
3.00
T
A
= 125oC
2.00
1.00
T
= -40oC
A
0.00
T
A
= 25oC
-1.00
-2.00
-3.00
0
50
100
150
200
250
-50 -25
0
25
TEMPERATURE (oC)
Ground Current vs VIN. ILOAD = 0mA
50
75 100 125
LOAD CURRENT (mA)
Ground Current vs VIN. ILOAD = 1mA
120
110
100
90
120
110
100
90
80
80
T
= 25oC
T
= 25oC
A
A
70
70
= 85oC
T
= 85oC
A
T
A
60
60
50
50
40
40
T
= -40oC
T
= -40oC
A
A
30
30
20
20
3.5
4
4.5
5
5.5
6
3.5
4
4.5
5
5.5
6
V
V
IN
Ground Current vs VININ. ILOAD = 250mA
Dropout Voltage vs Load Current
120
200
180
160
140
120
100
80
110
100
90
80
70
60
50
40
30
20
T
A
= 25oC
T
A
= 85oC
T
= 125oC
A
T
A
= -40oC
T
= -40oC
A
60
40
T
A
= 25oC
20
0
3.5
4
4.5
5
5.5
6
0
50
100
150
200
250
V
IN
LOAD CURRENT (mA)
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SNVS272B –MAY 2004–REVISED MAY 2013
Typical Performance Characteristics. (continued)
Unless otherwise noted, SD = 950mV, VIN = VOUT + 1.0V, CIN = 2.2 µF, IOUT = 1 mA, COUT = 2.2 µF and CBYP = 0.1 µF.
Typical values and limits appearing in normal type apply for TJ = 27°C. Limits appearing in boldface type apply over the full
temperature range for operation, −40 to +125°C.
Line Transient
Line Transient
4.9
4.3
4.9
4.3
CIN = COUT = 2.2 mF
CIN = COUT = 2.2 mF
CBYP = 0.1 mF
CBYP = 0
IL = 1 to 250 mA
IL = 1 to 250 mA
TIME (100 ms/DIV)
Load Transient (No CBYP
TIME (100 ms/DIV)
Enable Start-up Time
= 0
)
C
BYP
C
IN
= C
= 2.2 mF
OUT
I
L
= 1 mA
250
1
TIME (500 ms/DIV)
Enable Start-up Time
TIME (100 ms/DIV)
Short Circuit Current
C
BYP
= 0.1 mF
V
IN
= 4.3V
I
L
= 1 mA
2.0
1.5
1.0
0.5
0
TIME (500 ms/DIV)
TIME (50 ms/DIV)
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Typical Performance Characteristics. (continued)
Unless otherwise noted, SD = 950mV, VIN = VOUT + 1.0V, CIN = 2.2 µF, IOUT = 1 mA, COUT = 2.2 µF and CBYP = 0.1 µF.
Typical values and limits appearing in normal type apply for TJ = 27°C. Limits appearing in boldface type apply over the full
temperature range for operation, −40 to +125°C.
Power Supply Rejection Ratio
Noise Spectrum
10
1
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
C
= 0.1 mF
BYP
I
= 150 mA
C
BYP
= 0
OUT
I
= 1 mA
OUT
C
= 0.1 mF
BYP
0.1
0.01
0.1
1
10
100
100
1k
10k
100k
1M
FREQUENCY (kHz)
FREQUENCY (kHz)
Turn-On Sequence
Turn-Off Sequence
CDELAY = 0.1 mF
CBYP = 0
VIN 2V/DIV
VIN 2V/DIV
CDELAY = 0.1 mF
CBYP = 0
ILOAD = 250 mA
ILOAD = 250 mA
VOUT 2V/DIV
VOUT 2V/DIV
CDELAY 2V/DIV
CDELAY 2V/DIV
ERROR 2V/DIV
ERROR 2V/DIV
TIME (20 ms/DIV)
TIME (50 ms/DIV)
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Applications Information
External Capacitors
In common with most regulators, the LP3997 requires the inclusion of external capacitors.
VIN
An input capacitor is required for stability. It is recommended that a minimum of 1.0µF capacitor is connected
between the LP3997 input pin and ground (this capacitance value may be increased without limit).
This capacitor must be located a distance of not more than 1cm from the input pin and returned to a clean
analog ground. Any good quality ceramic, tantalum, or film capacitor may be used at the input.
Important: To ensure stable operation it is essential that good PCB design practices are employed to minimize
ground impedance and keep input inductance low. If these conditions cannot be met, or if long wire leads are
used to connect the battery or other power source to the LP3997, then it is recommended to increase the input
capacitor to at least 2.2µF. Also, tantalum capacitors can suffer catastrophic failures due to surge current when
connected to a low-impedance source of power (like a battery or a very large capacitor). If a tantalum capacitor is
used at the input, it must be ensured by the manufacturer to have a surge current rating sufficient for the
application.
There are no requirements for the ESR (Equivalent Series Resistance) on the input capacitor, but tolerance and
temperature coefficient must be considered when selecting the capacitor to ensure the capacitance will remain ≊
1.0µF over the entire operating temperature range.
VOUT
VOUT is the output voltage of the regulator. Connect capacitance (minimum 1.0µF) to ground from this pin. To
ensure stability the capacitor must meet the minimum value for capacitance and have an ESR in the range 5mΩ
to 500mΩ. Ceramic X7R types are recommended. If an output capacitor larger than 4.7µF is fitted then checks
on in-rush current, transient performance and stability, should be made.
SENSE
SENSE is used to sense the output voltage. Connect sense to VOUT
SHUTDOWN
SD controls the turning on and off of the LP3997. VOUT is ensured to be on when the voltage on the SD pin is
greater than 0.95V. VOUT is ensured to be off when the voltage on the SD pin is less than 0.4V.
ERROR
ERROR is an open drain output which is set low when VOUT is more than 5% below its nominal value. An
external pull up resistor is required on this pin. When a capacitor is connected from DELAY to GROUND, the
error signal is delayed (see DELAY section). This delayed error signal can be used as the power-on reset signal
for the application system. The ERROR pin is disconnected when not used.
DELAY
A capacitor from DELAY to GROUND sets the time delay for ERROR changing from low to high state. The delay
time is set by the following formula.
C DELAY
VTH(DELAY)
X
t DELAY
=
I DELAY
VTH(DELAY) is nominally 1.2V.
The DELAY pin should be open circuit if not used.
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CBYP
For low noise application, connect a high frequency ceramic capacitor from CBYP to ground, A 0.01µF to 0.1µF
X5R or X7R is recommended. This capacitor is connected directly to high impedance node in the band gap
reference circuit. Any significant loading on this node will cause a change in the regulated output voltage. For this
reason, DC leakage current from this pin must be kept as low as possible for best output voltage accuracy.
CAPACITOR CHARACTERISTICS
In common with most regulators, the LP3997 requires external capacitors for regulator stability. The LP3997 is
specifically designed for portable applications requiring minimum board space and can use capacitors in the
range 1µF to 4.7µF.These capacitors must be correctly selected for good performance. Ceramic capacitors are
the smallest, least expensive and have the lowest ESR values (which makes them best for eliminating high
frequency noise). The ESR of a typical 1µF ceramic capacitor is in the range of 20 mΩ to 40 mΩ, which easily
meets the ESR requirement for stability by the LP3997.These capacitors must be correctly selected to ensure
good performance of the LP3997.
For both input and output capacitors careful interpretation of the capacitor specification is required to ensure
correct device operation. The capacitor value can change greatly dependant on the conditions of operation and
capacitor type.
In particular the output capacitor selection should take account of all the capacitor parameters to ensure that the
specification is met within the application. Capacitance value can vary with DC bias conditions as well as
temperature and frequency of operation. Capacitor values will also show some decrease over time due to aging.
The capacitor parameters are also dependant on the particular case size with smaller sizes giving poorer
performance figures in general. As an example Figure 1 shows a typical graph showing a comparison of
capacitor case sizes in a Capacitance versus DC Bias plot. As shown in the graph, as a result of the DC Bias
condition, the capacitance value may drop below the minimum capacitance value given in the recommended
capacitor table (0.7µF in this case). Note that the graph shows the capacitance out of spec for the 0402 case
size capacitor at higher bias voltages. It is therefore recommended that the capacitor manufacturers’
specifications for the nominal value capacitor are consulted for all conditions as some capacitor sizes (e.g. 0402)
may not be suitable in the actual application.
0603, 10V, X5R
100%
80%
60%
0402, 6.3V, X5R
40%
20%
0
1.0
2.0
3.0
4.0
5.0
DC BIAS (V)
Figure 1. Capacitance versus DC Bias Plot
The value of ceramic capacitors can vary with temperature. The capacitor type X7R, which operates over a
temperature range of -55°C to +125°C, will only vary the capacitance to within ±15%. The capacitor type X5R
has a similar tolerance over a reduced temperature range of -55°C to +85°C. Most large value ceramic
capacitors, larger than 1µF are manufactured with Z5U or Y5V temperature characteristics. Their capacitance
can drop by more than 50% as the temperature goes from 25°C to 85°C. Therefore X7R is recommended over
Z5U and Y5V in applications where the ambient temperature will change significantly above or below 25°C.
Tantalum capacitors are less desirable than ceramic for use as output capacitors because they are more
expensive when comparing equivalent capacitance and voltage ratings in the 1µF to 4.7µF range.
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Another important consideration is that tantalum capacitors have higher ESR values than equivalent size
ceramics. This means that while it may be possible to find a tantalum capacitor with an ESR value within the
stable range, it would have to be larger in capacitance (which means bigger and more costly ) than a ceramic
capacitor with the same ESR value. It should also be noted that the ESR of a typical tantalum will increase about
2:1 as the temperature goes from 25°C down to -40°C, so some guard band must be allowed.
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REVISION HISTORY
Changes from Revision A (May 2013) to Revision B
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 11
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LP3997MM-3.3/NOPB
ACTIVE
VSSOP
DGK
8
1000 RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
SAKB
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Oct-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LP3997MM-3.3/NOPB
VSSOP
DGK
8
1000
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Oct-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
VSSOP DGK
SPQ
Length (mm) Width (mm) Height (mm)
208.0 191.0 35.0
LP3997MM-3.3/NOPB
8
1000
Pack Materials-Page 2
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