LP4951CM/NOPB [TI]
具有电源正常指示和使能功能的 100mA、30V、可调节低压降稳压器 | D | 8 | -40 to 125;
| 型号： | LP4951CM/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有电源正常指示和使能功能的 100mA、30V、可调节低压降稳压器 | D | 8 | -40 to 125 光电二极管 输出元件 稳压器 调节器 |
| 文件： | 总24页 (文件大小：1446K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LP4950C-5V, LP4951C
www.ti.com
SNVS208C –SEPTEMBER 2002–REVISED APRIL 2013
LP4950C-5V and LP4951C Adjustable Micropower Voltage Regulators
Check for Samples: LP4950C-5V, LP4951C
1
FEATURES
DESCRIPTION
The LP4950C and LP4951C are micropower voltage
2
•
•
•
•
•
•
•
•
High Accuracy 5V Specified 100mA Output
Extremely Low Quiescent Current
Low Dropout Voltage
regulators with very low quiescent current (75μA typ.)
and very low dropout voltage (typ. 40mV at light loads
and 380mV at 100mA). They are ideally suited for
use in battery-powered systems. Furthermore, the
quiescent current of the LP4950C/LP4951C
increases only slightly in dropout, prolonging battery
life.
Extremely Tight Load and Line Regulation
Very Low Temperature Coefficient
Use as Regulator or Reference
Needs Only 1μF for Stability
The LP4950C in the popular 3-pin TO-92 package is
pin compatible with older 5V regulators. The 8-lead
LP4951C is available in a plastic surface mount
package and offers additional system functions.
Current and Thermal Limiting
.
LP4951C VERSIONS ONLY
One such feature is an error flag output which warns
of a low output voltage, often due to falling batteries
on the input. It may be used for a power-on reset. A
second feature is the logic-compatible shutdown input
which enables the regulator to be switched on and
off. Also, the part may be pin-strapped for a 5V
output or programmed from 1.24V to 29V with an
external pair of resistors.
•
•
•
Error Flag Warns of Output Dropout
Logic-controlled Electronic Shutdown
Output Pogrammable From 1.24 to 29V
Careful design of the LP4950C/LP4951C has
minimized all contributions to the error budget. This
includes a tight initial tolerance (.5% typ.), extremely
good load and line regulation (.05% typ.) and a very
low output voltage temperature coefficient, making
the part useful as a low-power voltage reference.
BLOCK DIAGRAM AND TYPICAL APPLICATIONS
LP4950C
LP4951C
Figure 1.
Figure 2.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2002–2013, Texas Instruments Incorporated
LP4950C-5V, LP4951C
SNVS208C –SEPTEMBER 2002–REVISED APRIL 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
(1)
ABSOLUTE MAXIMUM RATINGS
Input Supply Voltage
−0.3 to +30V
−0.3 to +30V
SHUTDOWN Input Voltage,
Error Comparator Output
(2)
Voltage,
(2) (3)
FEEDBACK Input Voltage
Power Dissipation
−1.5 to +30V
Internally Limited
+150°C
Junction Temperature (TJ)
Ambient Storage Temperature
ESD Rating
Human Body Model
−65° to +150°C
(4)
2 kV
For soldering specifications, see the following document: www.ti.com/lit/snoa549
(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is specified. Operating Ratings do not imply specified performance limits. For specified performance limits and
associated test conditions, see the Electrical Characteristics tables.
(2) May exceed input supply voltage.
(3) When used in dual-supply systems where the output terminal sees loads returned to a negative supply, the output voltage should be
diode-clamped to ground.
(4) Human Body Model 1.5 kΩ in series with 100 pF. LP4950 - passes 2 kV HBM. LP4951 - All pins pass 2 kV except Vfb -1000V.
(1)
OPERATING RATINGS
Maximum Input Supply Voltage
Junction Temperature Range(2)
LP4950C, LP4951C
30V
−40°C to 125°C
(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is specified. Operating Ratings do not imply specified performance limits. For specified performance limits and
associated test conditions, see the Electrical Characteristics tables.
(2) The junction-to-ambient thermal resistances are as follows: 180°C/W and 160°C/W for the TO-92 package with 0.40 inch and 0.25 inch
leads to the printed circuit board (PCB) respectively, 160°C/W for the molded plastic SOIC (D). The above thermal resistances for the
SOIC package apply when the package is soldered directly to the PCB.
2
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SNVS208C –SEPTEMBER 2002–REVISED APRIL 2013
(1)
ELECTRICAL CHARACTERISTICS
LP4950CZ
LP4951CM
Units
Conditions
Parameter
(1)
Tested
Limit(2)
5.1
Design
Limit(3)
Typ
Output Voltage
TJ = 25°C
5.0
V max
V min
V max
V min
V max
V min
V max
V min
ppm/°C
4.9
−25°C ≤ TJ ≤ 85°C
5.15
4.85
5.2
Full Operating Temperature Range
4.8
Output Voltage
100 μA ≤ IL ≤ 100 mA
TJ ≤ TJMAX
5.24
4.76
150
(4)
Output Voltage Temperature
Coefficient
(6)
Line Regulation(5)
Load Regulation(5)
Dropout Voltage(7)
6V ≤ VIN ≤ 30V
0.04
0.1
50
0.2
0.2
80
% max
% max
0.4
0.3
100μA ≤ IL ≤ 100mA
IL = 100μA
% max
% max
mV max
mV max
mV max
mV max
μA max
μA max
mA max
mA max
μA max
μA max
mA max
mA max
%/W max
μV rms
μV rms
μV rms
150
600
170
19
IL = 100mA
380
75
450
150
15
Ground Current
IL = 100μA
IL = 100mA
8
Dropout Ground Current
Current Limit
VIN = 4.5V
IL = 100μA
110
160
200
200
0.2
230
220
VOUT = 0
(8)
Thermal Regulation
0.05
430
160
100
Output Noise, 10 Hz to 100 kHz CL = 1μF
CL = 200μF
CL = 3.3μF (Bypass = 0.01μF Pins 7
to 1 (LP4951C)
(1) Unless otherwise noted all limits specified for VIN = 6V, IL = 100μA and CL = 1μF. Limits appearing in boldface type apply over the
entire junction temperature range for operation. Limits appearing in normal type apply for TA = TJ = 25°C. Additional conditions for the 8-
pin versions are FEEDBACK tied to VTAP, OUTPUT tied to SENSE (VOUT = 5V), and VSHUTDOWN ≤ 0.8V.
(2) Specified and 100% production tested.
(3) Specified but not 100% production tested. These limits are not used to calculate outgoing AQL levels.
(4) Output or reference voltage temperature coefficient is defined as the worst case voltage change divided by the total temperature range.
(5) Regulation is measured at constant junction temperature, using pulse testing with a low duty cycle. Changes in output voltage due to
heating effects are covered under the specification for thermal regulation.
(6) Line regulation for the LP4951C is tested at 150°C for IL = 1 mA. For IL = 100μA and TJ = 125°C, line regulation is specified by design to
0.2%. See Typical Performance Characteristics for line regulation versus temperature and load current.
(7) Dropout Voltage is defined as the input to output differential at which the output voltage drops 100 mV below its nominal value
measured at 1V differential. At very low values of programmed output voltage, the minimum input supply voltage of 2V (2.3V over
temperature) must be taken into account.
(8) Thermal regulation is defined as the change in output voltage at a time T after a change in power dissipation is applied, excluding load
or line regulation effects. Specifications are for a 50 mA load pulse at VIN = 30V (1.25W pulse) for T = 10ms.
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SNVS208C –SEPTEMBER 2002–REVISED APRIL 2013
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Units
ELECTRICAL CHARACTERISTICS
LP4951C
(1)
Parameter
Conditions
Typ
Tested Limit
Design Limit
(2)
(3)
8-PIN VERSIONS ONLY
Reference Voltage
1.235
1.285
1.185
V max
V max
V min
1.295
1.165
1.335
1.135
Vmin
(4)
(5)
Reference Voltage
V max
V min
Feedback Pin Bias Current
20
40
nA max
nA max
ppm/°C
60
Reference Voltage
50
Temperature Coefficient
Feedback Pin Bias Current
Temperature Coefficient
0.1
nA/°C
Error Comparator
Output Leakage Current
VOH = 30V
0.01
150
60
1
μA max
μA max
mV max
mV max
mV min
mV min
mV max
mV max
mV
2
Output Low Voltage
VIN = 4.5V
IOL = 400μA
250
40
400
25
(3)
(6)
(6)
Upper Threshold Voltage
Lower Threshold Voltage
75
95
140
Hysteresis
15
Shutdown Input
Input Logic Voltage
1.3
V
Low (Regulator ON)
High (Regulator OFF)
VSHUTDOWN = 2.4V
0.7
2.0
V max
V min
Shutdown Pin Input Current
30
450
3
50
600
10
μA max
μA max
μA max
μA max
μA max
μA max
100
750
20
VSHUTDOWN = 30V
(7)
Regulator Output Current in
Shutdown
(1) Unless otherwise noted all limits specified for VIN = 6V, IL = 100μA and CL = 1μF. Limits appearing in boldface type apply over the
entire junction temperature range for operation. Limits appearing in normal type apply for TA = TJ = 25°C. Additional conditions for the 8-
pin versions are FEEDBACK tied to VTAP, OUTPUT tied to SENSE (VOUT = 5V), and VSHUTDOWN ≤ 0.8V.
(2) Specified and 100% production tested.
(3) Specified but not 100% production tested. These limits are not used to calculate outgoing AQL levels.
(4) VREF ≤ VOUT ≤ (VIN − 1V), 2.3V ≤ VIN ≤ 30V, 100μA ≤ IL ≤ 100mA, TJ ≤ TJMAX
.
(5) Output or reference voltage temperature coefficient is defined as the worst case voltage change divided by the total temperature range.
(6) Comparator thresholds are expressed in terms of a voltage differential at the Feedback terminal below the nominal reference voltage
measured at VIN = 6V. To express these thresholds in terms of output voltage change, multiply by the error amplifier gain = VOUT/VREF
(R1 + R2)/R2.For example, at a programmed output voltage of 5V, the Error output is specified to go low when the output drops by 95
mV × 5V/1.235V = 384 mV. Thresholds remain constant as a percent of VOUT as VOUT is varied, with the dropout warning occurring at
typically 5% below nominal, 7.5% specified.
=
(7)
VSHUTDOWN ≥ 2V, VIN ≤ 30V, VOUT = 0, Feedback pin tied to VTAP.
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SNVS208C –SEPTEMBER 2002–REVISED APRIL 2013
CONNECTION DIAGRAMS
TO-92 Plastic Package
Surface-Mount Package (SOIC)
Figure 3. Bottom View
Figure 4. Top View
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SNVS208C –SEPTEMBER 2002–REVISED APRIL 2013
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TYPICAL PERFORMANCE CHARACTERISTICS
.
Quiescent Current
Dropout Characteristics
Figure 5.
Figure 6.
Input Current
Input Current
Figure 7.
Figure 8.
Output Voltage
vs.
Temperature of 3
Representative Units
Quiescent Current
Figure 9.
Figure 10.
6
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SNVS208C –SEPTEMBER 2002–REVISED APRIL 2013
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
.
Quiescent Current
Quiescent Current
Figure 11.
Figure 12.
Quiescent Current
Short Circuit Current
Figure 13.
Figure 14.
Dropout Voltage
Dropout Voltage
Figure 15.
Figure 16.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
.
LP4951C Minimum Operating Voltage
LP4951C Feedback Bias Current
Figure 17.
Figure 18.
LP4951C Feedback Pin Current
LP4951C Error Comparator Output
8
V
= 5V
OUT
6
4
2
HYSTERESIS
0
NOTE: PULLUP RESISTOR TO
SEPARATE 5V SUPPLY
-2
0
1
2
3
4
5
INPUT VOLTAGE (V)
Figure 19.
Figure 20.
LP4951C Comparator Sink Current
Line Transient Response
Figure 21.
Figure 22.
8
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SNVS208C –SEPTEMBER 2002–REVISED APRIL 2013
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
.
Load Transient Response
Load Transient Response
Figure 23.
Figure 24.
LP4951C Enable Transient
Output Impedance
Figure 25.
Figure 26.
Ripple Rejection
Ripple Rejection
Figure 27.
Figure 28.
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SNVS208C –SEPTEMBER 2002–REVISED APRIL 2013
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
.
Ripple Rejection
Output Noise
Figure 29.
Figure 30.
LP4951C Divider Resistance
Shutdown Threshold Voltage
Figure 31.
Figure 32.
Line Regulation
LP4951C Maximum Rated Output Current
Figure 33.
Figure 34.
10
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SNVS208C –SEPTEMBER 2002–REVISED APRIL 2013
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
.
Thermal Response
Figure 35.
APPLICATION HINTS
EXTERNAL CAPACITORS
A 1.0μF (or greater) capacitor is required between the output and ground for stability at output voltages of 5V or
more. At lower output voltages, more capacitance is required. Without this capacitor the part will oscillate. Most
types of tantalum or aluminum electrolytics work fine here; even film types work but are not recommended for
reasons of cost. Many aluminum electrolytics have electrolytes that freeze at about −30°C, so solid tantalums are
recommended for operation below −25°C. The important parameters of the capacitor are an ESR of about 5 Ω or
less and a resonant frequency above 500 kHz. The value of this capacitor may be increased without limit.
At lower values of output current, less output capacitance is required for stability. The capacitor can be reduced
to 0.33 μF for currents below 10 mA or 0.1 μF for currents below 1 mA. Using the 8-pin version at voltages below
5V runs the error amplifier at lower gains so that more output capacitance is needed. For the worst-case situation
of a 100 mA load at 1.23V output (Output shorted to Feedback) a 3.3 μF (or greater) capacitor should be used.
Unlike many other regulators, the LP4950C will remain stable and in regulation with no load in addition to the
internal voltage divider. This is especially important in CMOS RAM keep-alive applications. When setting the
output voltage of the LP4951C version with external resistors, a minimum load of 1μA is recommended.
A 0.1μF capacitor should be placed from the LP4950C/LP4951C input to ground if there is more than 10 inches
of wire between the input and the AC filter capacitor or if a battery is used as the input.
Stray capacitance to the LP4951C Feedback terminal (pin 7) can cause instability. This may especially be a
problem when using high value external resistors to set the output voltage. Adding a 100pF capacitor between
Output and Feedback and increasing the output capacitor to at least 3.3μF will fix this problem.
ERROR DETECTION COMPARATOR OUTPUT
The comparator produces a logic low output whenever the LP4951C output falls out of regulation by more than
approximately 5%. This figure is the comparator's built-in offset of about 60 mV divided by the 1.235 reference
voltage. (See to the block diagram in the front of the datasheet.) This trip level remains “5% below normal”
regardless of the programmed output voltage of the 4951C. For example, the error flag trip level is typically
4.75V for a 5V output or 11.4V for a 12V output. The out of regulation condition may be due either to low input
voltage, current limiting, or thermal limiting.
Figure 36 below gives a timing diagram depicting the ERROR signal and the regulated output voltage as the
LP4951C input is ramped up and down. The ERROR signal becomes valid (low) at about 1.3V input. It goes high
at about 5V input (the input voltage at which VOUT = 4.75V). Since the LP4951C's dropout voltage is load-
dependent (see curve in typical performance characteristics), the input voltage trip point (about 5V) will vary with
the load current. The output voltage trip point (approx. 4.75V) does not vary with load.
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The error comparator has an open-collector output which requires an external pullup resistor. This resistor may
be returned to the output or some other supply voltage depending on system requirements. In determining a
value for this resistor, note that while the output is rated to sink 400μA, this sink current adds to battery drain in a
low battery condition. Suggested values range from 100k to 1 MΩ. The resistor is not required if this output is
unused.
*When VIN ≤ 1.3V, the error flag pin becomes a high impedance, and the error flag voltage rises to its pull-up voltage.
Using VOUT as the pull-up voltage (see Figure 37), rather than an external 5V source, will keep the error flag voltage
under 1.2V (typ.) in this condition. The user may wish to divide down the error flag voltage using equal-value resistors
(10 kΩ suggested), to ensure a low-level logic signal during any fault condition, while still allowing a valid high logic
level during normal operation.
Figure 36. ERROR Output Timing
PROGRAMMING THE OUTPUT VOLTAGE (LP4951C)
The LP4951C may be pin-strapped for 5V using its internal voltage divider by tying the pin 1 (output) to pin 2
(sense) pins together, and also tying the pin 7 (feedback) and pin 6 (VTAP) pins together. Alternatively, it may be
programmed for any output voltage between its 1.235V reference and its 30V maximum rating. As seen in
Figure 37, an external pair of resistors is required.
The complete equation for the output voltage is
(1)
where VREF is the nominal 1.235 reference voltage and IFB is the feedback pin bias current, nominally −20 nA.
The minimum recommended load current of 1μA forces an upper limit of 1.2 MΩ on the value of R2, if the
regulator must work with no load (a condition often found in CMOS in standby). IFB will produce a 2% typical
error in VOUT which may be eliminated at room temperature by trimming R1. For better accuracy, choosing R2 =
100k reduces this error to 0.17% while increasing the resistor program current to 12μA. Since the LP4951C
typically draws 60μA at no load with Pin 2 open-circuited, this is a small price to pay.
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SNVS208C –SEPTEMBER 2002–REVISED APRIL 2013
*See Application Hints
.
. **Drive with TTL-high to shut down. Ground or leave open if shutdown feature is not to be used.
.
Note: Pins 2 and 6 are left open.
Figure 37. Adjustable Regulator (LP4951C)
REDUCING OUTPUT NOISE
In reference applications it may be advantageous to reduce the AC noise present at the output. One method is to
reduce the regulator bandwidth by increasing the size of the output capacitor. This is the only way noise can be
reduced on the 3 lead LP4950C but is relatively inefficient, as increasing the capacitor from 1μF to 220μF only
decreases the noise from 430μV to 160μV rms for a 100kHz bandwidth at 5V output.
Noise can be reduced fourfold by a bypass capacitor across R1, since it reduces the high frequency gain from 4
to unity. Pick
(2)
or about 0.01μF. When doing this, the output capacitor must be increased to 3.3μF to maintain stability. These
changes reduce the output noise from 430μV to 100μV rms for a 100kHz bandwidth at 5V output. With the
bypass capacitor added, noise no longer scales with output voltage so that improvements are more dramatic at
higher output voltages.
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SCHEMATIC DIAGRAM
14
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SNVS208C –SEPTEMBER 2002–REVISED APRIL 2013
REVISION HISTORY
Changes from Revision B (April 2013) to Revision C
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 14
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LP4951CM/NOPB
LP4951CMX/NOPB
ACTIVE
SOIC
SOIC
D
D
8
8
95
RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
LP495
1CM
ACTIVE
2500 RoHS & Green
SN
LP495
1CM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LP4951CMX/NOPB
SOIC
D
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 35.0
LP4951CMX/NOPB
D
8
2500
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
SOIC
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
LP4951CM/NOPB
D
8
95
495
8
4064
3.05
Pack Materials-Page 3
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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