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LP5521

SNVS441I –JANUARY 2007–REVISED NOVEMBER 2016

LP5521 Three-Channel RGB, White-LED Driver With Internal Program Memory and

Integrated Charge Pump

1 Features

3 Description

The LP5521 is a three-channel LED driver designed

to produce variety of lighting effects for mobile

devices. A high-efficiency charge pump enables LED

driving over full Li-Ion battery voltage range. The

device has a program memory for creating variety of

lighting sequences. When program memory has been

loaded, LP5521 can operate autonomously without

processor control allowing power savings.

1

•

Adaptive Charge Pump With 1× and 1.5× Gain

Provides Up to 95% LED Drive Efficiency

•

Charge Pump with Soft Start and Overcurrent,

Short-Circuit Protection

•

Low Input Ripple and EMI

Very Small Solution Size, No Inductor or Resistors

Required

The device maintains excellent efficiency over a wide

operating range by automatically selecting proper

charge pump gain based on LED forward voltage

requirements and is able to automatically enter

power-save mode, when LED outputs are not active

and thus lowering current consumption.

•

200-nA Typical Shutdown Current

Automatic Power Save Mode

I²C-Compatible Interface

Independently Programmable Constant Current

Outputs with 8-Bit Current Setting and 8-Bit PWM

Control

Three independent LED channels have accurate

programmable current sources and PWM control.

Each channel has program memory for creating

desired lighting sequences with PWM control.

•

Typical LED Output Saturation Voltage 50 mV and

Current Matching 1%

Three Program Execution Engines with Flexible

Instruction Set

The LP5521 has a flexible digital interface. Trigger

I/O and a 32-kHz clock input allow synchronization

between multiple devices. Interrupt output can be

used to notify processor, when LED sequence has

ended. The LP5521 has four pin selectable I²C-

compatible addresses. This allows connecting up to

four parallel devices in one I²C-compatible bus. GPO

and INT pins can be used as a digital control pin for

other devices.

•

Autonomous Operation Without External Control

Large SRAM Program Memory

Two General Purpose Digital Outputs

2 Applications

•

Fun and Indicator Lights

LCD Sub-Display Backlighting

Keypad RGB Backlighting and Phone Cosmetics

Vibra, Speakers, Waveform Generator

Blood Glucose Meter

The LP5521 requires only four small, low-cost

ceramic capacitors.

Comprehensive application tools are available,

including command compiler for easy LED sequence

programming.

Handheld POS Terminals

Electronic Access Control

Device Information⁽¹⁾

Where RGB Indication is Needed

PART NUMBER

LP5521TM

PACKAGE

DSBGA (20)

WQFN (24)

BODY SIZE

Typical Application Circuit

2.093 mm × 1.733 mm (MAX)

5.00 mm × 4.00 mm (NOM)

C_FLY1

C_FLY2

LP5521YQ

0.47 µF

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

C_OUT

1 µF

CFLY1P

VDD

CFLY1N

CFLY2P

CFLY2N

VOUT

C_IN

-

1 µF

RGB LED 0...25.5 mA/LED

SCL

SDA

R

G

B

LP5521

EN

MCU

CLK_32K

INT

TRIG

GPO

ADDR_SEL0

ADDR_SEL1

GNDs

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

LP5521

SNVS441I –JANUARY 2007–REVISED NOVEMBER 2016

www.ti.com

Table of Contents

7.4 Device Functional Modes........................................ 18

7.5 Programming........................................................... 19

7.6 Register Maps......................................................... 28

Application and Implementation ........................ 36

8.1 Application Information............................................ 36

8.2 Typical Applications ................................................ 36

8.3 Initialization Setup................................................... 39

Power Supply Recommendations...................... 40

1

2

3

4

5

6

Features.................................................................. 1

Applications ........................................................... 1

Description ............................................................. 1

Revision History..................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 5

6.1 Absolute Maximum Ratings ..................................... 5

6.2 ESD Ratings.............................................................. 5

6.3 Recommended Operating Conditions....................... 5

6.4 Thermal Information.................................................. 6

6.5 Electrical Characteristics........................................... 6

6.6 Charge Pump Electrical Characteristics ................... 7

8

9

10 Layout................................................................... 40

10.1 Layout Guidelines ................................................. 40

10.2 Layout Example .................................................... 40

11 Device and Documentation Support ................. 41

11.1 Device Support...................................................... 41

11.2 Documentation Support ........................................ 41

11.3 Receiving Notification of Documentation Updates 41

11.4 Community Resources.......................................... 41

11.5 Trademarks........................................................... 41

11.6 Electrostatic Discharge Caution............................ 41

11.7 Glossary................................................................ 41

6.7 LED Driver Electrical Characteristics (R, G, B

Outputs) ..................................................................... 7

6.8 Logic Interface Characteristics.................................. 7

6.9 I²C Timing Requirements (SDA, SCL)...................... 8

6.10 Typical Characteristics............................................ 9

Detailed Description ............................................ 11

7.1 Overview ................................................................. 11

7.2 Functional Block Diagram ....................................... 11

7.3 Feature Description................................................. 12

7

12 Mechanical, Packaging, and Orderable

Information ........................................................... 41

4 Revision History

Changes from Revision H (May 2016) to Revision I

Page

•

Changed wording of title ........................................................................................................................................................ 1

Changes from Revision G (September 2014) to Revision H

Page

•

Added several new Applications ............................................................................................................................................ 1

Changed Body Size of DSBGA package to MAX dimensions .............................................................................................. 1

Changed Handling Ratings to ESD Ratings table ................................................................................................................. 5

Changed R_θJAvalue for DSBGA from 50 – 90°C/W to 70.7°C/W and WQFN from 37 – 90°C/W to 38.4°C/W; add

additional thermal information ................................................................................................................................................ 6

•

Added Community Resources ............................................................................................................................................. 41

Changes from Revision F (February 2013) to Revision G

Page

•

Added Pin Configuration and Functions section, Handling Rating table, Feature Description section, Device

Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout

section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information

section ................................................................................................................................................................................... 1

2

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SNVS441I –JANUARY 2007–REVISED NOVEMBER 2016

5 Pin Configuration and Functions

YFQ Package

20-Pin DSBGA

Top View

YFQ Package

20-Pin DSBGA

Bottom View

CFLY

2P

CFLY

1P

GND

TRIG

INT

VDD

GND

4

3

2

1

CFLY

2P

CFLY

1P

4

3

2

1

TRIG

INT

EN

GND

VDD

GND

CLK

32K

CFLY

2N

CFLY

1N

CLK

32K

CFLY

1N

CFLY

2N

ADDR

SEL1

ADDR

SEL0

VOUT

GPO

EN

ADDR

SEL0

ADDR

SEL1

VOUT

GPO

SCL

D

SCL

B

G

R

SDA

R

SDA

E

G

B

A

B

C

D

E

C

B

A

NJA Package

24-Pin WQFN

Top View

NJA Package

24-Pin WQFN

Bottom View

19 18 17 16 15 14 13

13 14 15 16 17 18 19

20

21

22

23

24

12

11

10

9

12

11

10

9

20

21

22

23

24

8

1

2

3

4

5

6

7

6

5

4

3

2

1

Pin 1

Pin Functions LP5521TM

TYPE⁽¹⁾

DESCRIPTION

NUMBER

1A

NAME

B

A

Current source output

I²C Serial interface clock input

1B

G

A

1C

R

A

1D

SCL

SDA

VOUT

I

1E

I/OD

I²C Serial interface data input/output

2A

A

I

Charge pump output

I²C address select input

2B

ADDR_SEL1

ADDR_SEL0

GPO

2C

I

2D

O

I

General purpose output

2E

EN

Chip enable

3A

CFLY2N

CFLY1N

GND

A

G

I

Negative terminal of charge pump fly capacitor 2

Negative terminal of charge pump fly capacitor 1

Ground

3B

3C

3D

CLK_32K

32-kHz clock input

(1) A: Analog Pin, G: Ground Pin, P: Power Pin, I: Input Pin, I/O: Input/Output Pin, O: Output Pin, OD: Open Drain Pin

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Pin Functions LP5521TM (continued)

TYPE⁽¹⁾

DESCRIPTION

NUMBER

NAME

INT

3E

4A

4B

4C

4D

4E

OD/O

A

Interrupt output / General Purpose Output

CFLY2P

CFLY1P

VDD

Positive terminal of charge pump fly capacitor 2

Positive terminal of charge pump fly capacitor 1

Power supply pin

A

P

GND

G

Ground

TRIG

I/OD

Trigger input/output

Pin Functions LP5521YQ

TYPE⁽¹⁾

DESCRIPTION

NUMBER

NAME

CFLY2P

CFLY1P

VDD

1

A

Positive pin of charge pump fly capacitor 2

Positive pin of charge pump fly capacitor 1

Power supply pin

2

A

P

3

4

GND

G

Ground

5

CLK_32K

INT

I

32-kHz clock input

6

OD/O

I/OD

N/C

I/OD

I

Interrupt output / General purpose output

Trigger input/output

7

TRIG

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

SDA

EN

SCL

GPO

R

I²C serial interface data input/output

Chip enable

I²C Serial interface clock input

I

O

General purpose output

A

Current source output

G

A

Current source output

B

A

Current source output

I²C address select input

ADDR_SEL0

ADDR_SEL1

VOUT

I

A

Charge pump output

CFLY2N

A

Negative pin of charge pump fly capacitor 2

Negative pin of charge pump fly capacitor 1

CFLY1N

A

(1) A: Analog Pin, G: Ground Pin, P: Power Pin, I: Input Pin, I/O: Input/Output Pin, O: Output Pin, OD: Open Drain Pin

4

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)^(1)(2)(2)(3)

MIN

–0.3

MAX

UNIT

V

V (V_DD, V_OUT, R, G, B)

6

V_DD+ 0.3 with 6 V maximum

Internally Limited

125

Voltage on logic pins

V

Continuous power dissipation⁽⁴⁾

Junction temperature, T_J-MAX

Maximum lead temperature (soldering)

Storage temperature, T_stg

°C

See⁽⁵⁾

–65

150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to the potential at the GND pins.

(3) If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/ Distributors for availability and

specifications.

(4) Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at T_J= 150°C (typical) and

disengages at T_J= 130°C (typical).

(5) For detailed soldering specifications and information, please refer to DSBGA Wafer Level Chip Scale Package (SNVA009) or Leadless

Leadframe Package (LLP) (SNOA401).

6.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

±2000

V_(ESD)

Electrostatic discharge

V

Charged-device model (CDM), per JEDEC specification JESD22-

C101⁽²⁾

±200

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)^(1)(2)(2)

MIN

MAX

5.5

UNIT

V_DD

2.7

0

V

Recommended charge pump load current I_OUT

Junction temperature, T_J,

100

125

85

mA

°C

–30

(3)

Ambient temperature, T_A

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to the potential at the GND pins.

(3) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may

have to be derated. Maximum ambient temperature (T_A-MAX) is dependent on the maximum operating junction temperature (T_J-MAX-OP

=

125°C), the maximum power dissipation of the device in the application (P_D-MAX), and the junction-to ambient thermal resistance of the

part/package in the application (R_θJA), as given by the following equation: T_A-MAX= T_J-MAX-OP– (R_θJA× P_D-MAX).

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6.4 Thermal Information

LP5521

YFQ (DSBGA)

THERMAL METRIC⁽¹⁾

NJA (WQFN)

24 PINS

38.4

UNIT

20 PINS

70.7

0.5

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

27.3

12.1

0.2

15.4

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.2

ψ_JB

12.0

n/a

15.4

R_θJC(bot)

3.1

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

6.5 Electrical Characteristics

Unless otherwise noted, specifications apply to the LP5521 Functional Block Diagram with: 2.7 V ≤ V_DD≤ 5.5 V, C_OUT= C_IN

1 μF, C_FLY1= C_FLY2= 0.47 μF; limits are for T_J= 25°C unless specified in the test conditions.^(1)(2)(3)

=

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Standby supply current

EN = 0 (pin), CHIP_EN = 0 (bit), external 32

kHz clock running or not running

0.2

μA

EN = 0 (pin), CHIP_EN = 0 (bit), external 32-

kHz clock running or not running, –30°C < T_A

85°C

<

2

EN = 1 (pin), CHIP_EN = 0 (bit), external 32-

kHz clock not running

1

μA

EN = 1 (pin), CHIP_EN = 0 (bit), external 32-

kHz clock running

1.4

I_VDD

Normal mode supply current Charge pump and LED drivers disabled

0.25

0.7

mA

Charge pump in 1x mode, no load, LED drivers

disabled

Charge pump in 1.5x mode, no load, LED

drivers disabled

1.5

1.2

mA

Charge pump in 1x mode, no load, LED drivers

enabled

Powersave mode supply

current

External 32-kHz clock running

Internal oscillator running

10

μA

0.25

mA

–4%

–7%

4%

7%

Internal oscillator frequency

accuracy

ƒ_OSC

–30°C < T_A< 85°C

(1) All voltages are with respect to the potential at the GND pins.

(2) Minimum and Maximum limits are specified by design, test, or statistical analysis.

(3) Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics.

6

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6.6 Charge Pump Electrical Characteristics

Limits are for T_J= 25°C unless specified in the test conditions.⁽¹⁾

SYMBOL

PARAMETER

TEST CONDITION

MIN

TYP

3.5

1

MAX

UNIT

Ω

R_OUT

Charge pump output

resistance

Gain = 1.5×

Gain = 1×

Ω

f_SW

Switching frequency

1.25

MHz

–30°C < T_A< 85°C

Gain = 1.5×

–7%

7%

I_GND

Ground current

1.2

0.5

mA

Gain = 1×

V_OUTturn-on time from charge V_DD= 3.6 V, CHIP_EN = H

t_ON

100

μs

pump off to 1.5x mode

I_OUT= 60 mA

V_OUT

Charge pump output voltage

V_DD= 3.6 V, no load, Gain = 1.5×

4.55

V

(1) Input, output, and fly capacitors should be of the type X5R or X7R low ESR ceramic capacitor.

6.7 LED Driver Electrical Characteristics (R, G, B Outputs)

Limits are for T_J= 25°C unless specified in the test conditions.

SYMBOL

PARAMETER

TEST CONDITION

MIN

TYP

MAX

UNIT

I_LEAKAGE

R, G, B pin leakage current

0.1

µA

–30°C < T_A< 85°C

Outputs R, G, B

1

I_MAX

I_OUT

Maximum source current

25.5

mA

Accuracy of output current Output current set to 17.5 mA, V_DD= 3.6 V

–4%

–5%

4%

5%

Output current set to 17.5 mA, V_DD= 3.6 V,

–30°C < T_A< 85°C

I_MATCH

f_LED

Matching⁽¹⁾

I_OUT= 17.5 mA, V_DD= 3.6 V

1%

2%

LED PWM switching

frequency

PWM_HF = 1

Frequency defined by internal oscillator

558

Hz

PWM_HF = 0

Frequency defined by 32-kHz clock

(internal or external)

256

50

Hz

V_SAT

Saturation voltage⁽²⁾

I_OUTset to 17.5 mA

100

mV

(1) Matching is the maximum difference from the average of the three output's currents.

(2) Saturation voltage is defined as the voltage when the LED current has dropped 10% from the value measured at V_OUT– 1 V.

6.8 Logic Interface Characteristics

(V(EN) = 1.65 V...V_DD, and limits apply through ambient temperature range –30°C < T_A< +85°C, unless otherwise noted.

PARAMETER

LOGIC INPUT EN

TEST CONDITIONS

MIN

TYP

MAX

0.5

1

UNIT

V_IL

Input low level

V

V_IH

I_I

Input high level

Logic input current

1.2

–1

µA

µs

(1)

t_DELAY

Input delay

T_J= 25°C

2

(1) The I²C-compatible host should allow at least 1 ms before sending data to the LP5521 after the rising edge of the enable line.

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Logic Interface Characteristics (continued)

(V(EN) = 1.65 V...V_DD, and limits apply through ambient temperature range –30°C < T_A< +85°C, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

LOGIC INPUT SCL, SDA, TRIG, CLK_32K

V_IL

Input low level

Input high level

Input current

0.2 × V(EN)

V

V_IH

0.8 × V(EN)

–1

I_I

1

µA

kHz

ƒ_{CLK_32K}

ƒ_SCL

Clock frequency

T_J= 25°C

32

400

LOGIC OUTPUT SDA, TRIG, INT

I_OUT= 3 mA (pullup current),

T_J= 25°C

0.3

V_OL

I_L

Output low level

I_OUT= 3 mA (pull-up current)

0.5

1

V

Output leakage current

µA

LOGIC INPUT ADDR_SEL0, ADDR_SEL1

V_IL

V_IH

I_I

Input low level

Input high level

Input current

0.2 × V_DD

V

0.8 × V_DD

–1

1

µA

LOGIC OUTPUT GPO, INT (IN GPO STATE)

I_OUT= 3 mA, T_J= 25°C

I_OUT= 3 mA

0.3

V_OL

Output low level

0.5

1

V

T_J= 25°C

V_DD– 0.3

V_OH

I_L

Output high level

I_OUT= –2 mA

V_DD– 0.5

V

Output leakage current

µA

6.9 I²C Timing Requirements (SDA, SCL)

Limits are for T_J= 25°C⁽¹⁾

MIN

MAX

UNIT

kHz

µs

ƒ_SCL

1

Clock frequency

400

Hold time (repeated) START condition

Clock low time

0.6

1.3

2

µs

3

Clock high time

600

ns

4

Setup time for a repeated START condition

Data hold time

600

ns

5

50

ns

6

Data set-up time

100

ns

7

Rise time of SDA and SCL

Fall time of SDA and SCL

Set-up time for STOP condition

Bus-free time between a STOP and a START condition

Capacitive load for each bus line

20+0.1C_b

15+0.1C_b

600

300

ns

8

ns

9

ns

10

C_b

1.3

µs

10

200

pF

(1) Verified by design.

Figure 1. I²C Timing Diagram

8

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6.10 Typical Characteristics

Unless otherwise specified: V_DD= 3.6 V

Figure 2. LED Drive Efficiency vs Input Voltage Automatic

Gain Change

Figure 3. LED Current vs Output Pin Headroom Voltage

Figure 4. LED Current vs Current Register Code

Figure 5. LED Current vs Supply Voltage

Figure 6. Charge Pump Efficiency vs Load Current

Figure 7. Charge Pump Efficiency vs Input Voltage 1.5x

Mode

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Typical Characteristics (continued)

Unless otherwise specified: V_DD= 3.6 V

Figure 8. Charge Pump Output Voltage vs Load Current

Figure 9. Charge Pump Output Voltage vs Input Voltage

Automatic Gain Change from 1x to 1.5x

Figure 10. Charge Pump Automatic Gain Change Hysteresis

Figure 11. Charge Pump Start-Up in 1.5× Mode: No Load

Figure 12. Charge Pump Automatic Gain Change

(LED V_F= 3.6 V)

Figure 13. Standby Current vs Input Voltage

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7 Detailed Description

7.1 Overview

The LP5521 is a three-channel LED driver designed to produce variety of lighting effects for mobile devices. A

high-efficiency charge pump enables LED driving over full Li-Ion battery voltage range. The device has a

program memory for creating variety of lighting sequences. When program memory has been loaded, the

LP5521 can operate autonomously without processor control allowing power savings.

The device maintains excellent efficiency over a wide operating range by automatically selecting proper charge

pump gain based on LED forward voltage requirements. the LP5521 is able to automatically enter power-save

mode, when LED outputs are not active and thus lowering current consumption.

Three independent LED channels have accurate programmable current sources and PWM control. Each channel

has program memory for creating desired lighting sequences with PWM control.

The LP5521 has a flexible digital interface. A trigger I/O and 32-kHz clock input allow synchronization between

multiple devices. Interrupt output can be used to notify processor, when LED sequence has ended. LP5521 has

four pin-selectable I²C-compatible addresses. This allows connecting up to four parallel devices in one I²C-

compatible bus. GPO and INT pins can be used as a digital control pin for other devices.

The LP5521 requires only four small and low-cost ceramic capacitors.

Comprehensive application tools are available, including command compiler for easy LED sequence

programming.

7.2 Functional Block Diagram

C_FLY1

C_FLY2

0.47 µF

TSD

REF

POR

VOUT

CHARGE PUMP

CLK

DET

1x/1.5x

VDD

C_IN

C_OUT

1 µF

BIAS

OSC

-

1 µF

PROGRAM

MEMORY

Command based

PWM pattern generator

ADDR_SEL0

ADDR_SEL1

VDD_ IO

IDAC

VDD

SCL

I²C

SDA

EN

CLK_32K

INT

R

G

B

VOUT

Control

D

MCU

A

VOUT

TRIG

VOUT

GPO

LP5521

GND

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7.3 Feature Description

7.3.1 Charge Pump Operational Description

The LP5521 includes a pre-regulated switched-capacitor charge pump with a programmable voltage

multiplication of 1 and 1.5×.

In 1.5× mode by combining the principles of a switched-capacitor charge pump and a linear regulator, the device

generates a regulated 4.5-V output from Li-Ion input voltage range. A two-phase non-overlapping clock

generated internally controls the operation of the charge pump. During the charge phase, both flying capacitors

(C_FLY1and C_FLY2) are charged from input voltage. In the pump phase that follows, the flying capacitors are

discharged to output. A traditional switched capacitor charge pump operating in this manner uses switches with

very low on-resistance, ideally 0 Ω, to generate an output voltage that is 1.5× the input voltage. The LP5521

regulates the output voltage by controlling the resistance of the input-connected pass-transistor switches in the

charge pump.

7.3.1.1 Output Resistance

At lower input voltages, the charge pump output voltage may degrade due to effective output resistance (R_OUT) of

the charge pump. The expected voltage drop can be calculated by using a simple model for the charge pump

shown in Figure 14.

Charge Pump

1.5 x V‘

V_IN

V_OUT

V‘

REG

1.5 x

R_OUT

Figure 14. Charge Pump Block Diagram

The model shows a linear pre-regulation block (REG), a voltage multiplier (1.5×), and an output resistance

(R_OUT). Output resistance models the output voltage drop that is inherent to switched capacitor converters. The

output resistance is 3.5 Ω (typical) and is function of switching frequency, input voltage, capacitance value of the

flying capacitors, internal resistances of switches, and ESR of flying capacitors. When the output voltage is in

regulation, the regulator in the model controls the voltage V’ to keep the output voltage equal to 4.5 V (typical).

With increased output current, the voltage drop across R_OUTincreases. To prevent drop in output voltage, the

voltage drop across the regulator is reduced, V’ increases, and V_OUTremains at 4.5 V. When the output current

increases to the point that there is zero voltage drop across the regulator, V’ equals the input voltage, and the

output voltage is on the edge of regulation. Additional output current causes the output voltage to fall out of

regulation, so that the operation is similar to a basic open-loop 1.5× charge pump. In this mode, output current

results in output voltage drop proportional to the output resistance of the charge pump. The out-of-regulation

output voltage can be approximated by: V_OUT= 1.5 × V_IN– I_OUT× R_OUT

.

7.3.1.2 Controlling Charge Pump

The charge pump is controlled with two CP_MODE bits in register 08H. When both bits are low, the charge pump

is disabled, and the output voltage is pulled down with 300 kΩ. Charge pump can be forced to bypass mode, so

that battery voltage is going directly to RGB outputs. In 1.5× mode output voltage is boosted to 4.5 V. In

automatic mode, charge pump operation mode is defined by LED outputs saturation described in LED Forward

Voltage Monitoring. Table 1 lists operation modes and selection bits.

Table 1. CONFIG Register (08H)

NAME

BIT

DESCRIPTION

CP_MODE

4:3

Charge pump operation mode

00b = OFF

01b = Forced to bypass mode (1×)

10b = Forced to 1.5× mode

11b = Automatic mode selection

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7.3.1.3 LED Forward Voltage Monitoring

When charge pump automatic mode selection is enabled, voltages over LED drivers are monitored. If drivers do

not have enough headroom, charge pump gain is set to 1.5×. Driver saturation monitor does not have a fixed

voltage limit, since saturation voltage is a function of temperature and current. Charge pump gain is set to 1×,

when battery voltage is high enough to supply all LEDs.

In automatic gain change mode, charge pump is switched to bypass mode (1×), when LEDs are inactive for over

50 ms.

Charge pump gain control utilizes digital filtering to prevent supply voltage disturbances from triggering gain

changes. If the R driver current source is connected to a battery (address 08H, bit R_TO_BATT = 1), voltage

monitoring is disabled in R output, but still functional in B and G outputs.

LED forward voltage monitoring and gain control block diagram is shown in Figure 15.

PWM

VOUT

Current

Source

Charge

Pump

MODE

V_OFS

Saturation

Monitor

R/G/B

Comparator

-

Digital

Filter

Control

Registers

Program

Memory

Command

Look-ahead

Mode

Control

Figure 15. Voltage Monitoring Block Diagram for One Output

7.3.2 LED Driver Operational Description

The LP5521 LED drivers are constant current sources with 8-bit PWM control. Output current can be

programmed with I²C register up to 25.5 mA. Current setting resolution is 100 μA (8-bit control).

R driver has two modes: current source can be connected to the battery (V_DD) or to the charge pump output. If a

current source is connected to the battery, automatic charge pump gain control is not used for this output. This

approach provides better efficiency when LED with low V_Fis connected to R driver, and battery voltage is high

enough to drive this LED in all conditions. R driver mode can be selected with I²C register bit. When address

08H, bit R_TO_BATT = 1, R current source is connected to battery. When it is 0 (default), R current source is

connected to charge pump same way as in G and B drivers. G and B drivers are always connected to charge

pump output.

Some LED configuration examples are given in Table 2. When LEDs with low V_Fare used, charge pump can be

operating in bypass mode (1×). This eliminates the need of having double drivers for all outputs; one connected

to battery and another connected to charge pump output. When LP5521 is driving a RGB LED, R channel can be

configured to use battery power. This configuration increases power efficiency by minimizing the voltage drop

across the LED driver.

Table 2. LED Configuration Examples

CONFIGURATION

RGB LED with low V_Fred

3 × low V_FLED

R OUTPUT TO BATT

R OUTPUT TO CP

CP MODE

Auto (1× or 1.5×)

1×

X

3 × white LED

Auto (1× or 1.5×)

Disabled

1 × low V_FLED (R output)

X

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PWM frequency is either 256 Hz or 558 Hz, frequency is set with PWM_HF bit in register 08H. When PWM_HF

is 0, the frequency is 256 Hz, and when bit is 1, the PWM frequency is 558 Hz. Brightness adjustment is either

linear or logarithmic. This can be set with register 00H LOG_EN bit. When LOG_EN = 0 linear adjustment scale

is used, and when LOG_EN = 1 logarithmic scale is used. By using logarithmic scale the visual effect seems

linear to the eye. Register control bits are presented in Table 3, Table 4, and Table 5:

Table 3. R_CURRENT Register (05H), G_CURRENT register (06H), B_CURRENT register (07H):

NAME

BIT

DESCRIPTION

CURRENT

7:0

Current setting

bin

hex

dec

mA

0000 0000

0000 0001

0000 0010

0000 0011

0000 0100

0000 0101

0000 0110

...

00

01

02

03

04

05

06

...

0

1

2

3

4

5

6

...

0.0

0.1

0.2

0.3

0.4

0.5

0.6

...

1010 1111

...

AF

...

175

...

17.5 (def)

...

1111 1011

1111 1100

1111 1101

1111 1110

1111 1111

FB

FC

FD

FE

FF

251

252

253

254

255

25.1

25.2

25.3

25.4

25.5

Table 4. ENABLE Register (00H):

NAME

BIT

DESCRIPTION

LOG_EN

7

Logarithmic PWM adjustment enable bit

0 = Linear adjustment

1 = Logarithmic adjustment

Table 5. CONFIG Register (08H):

NAME

BIT

DESCRIPTION

PWM_HF

6

PWM clock frequency

0 = 256 Hz, frequency defined by the 32-kHz clock (internal or external)

1 = 558 Hz, frequency defined by internal oscillator

100

95

90

85

80

75

70

65

60

55

50

45

40

35

30

25

20

15

10

5

LOG_EN = 0

LOG_EN = 1

0

16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 255

CONTROL (DEC)

Figure 16. Logarithmic and Linear PWM Adjustment Curves

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7.3.3 Automatic Power Save

Automatic power save mode is enabled when PWRSAVE_EN bit in register address 08H is 1. Almost all analog

blocks are powered down in power save, if external clock is used. Only charge pump protection circuits remain

active. However if internal clock has been selected only charge pump and led drivers are disabled during power

save since digital part of the LED controller need to remain active. In both cases charge pump enters 'weak 1×'

mode. In this mode charge pump utilizes a passive current limited keep-alive switch, which keeps the output

voltage at battery level.

During program execution LP5521 can enter power save if there is no PWM activity in R, G and B outputs. To

prevent short power save sequences during program execution, LP5521 has command look-ahead filter. In every

instruction cycle R, G, B commands are analyzed, and if there is sufficient time left with no PWM activity, the

device enters power save. In power save program execution continues uninterruptedly. When a command that

requires PWM activity is executed, fast internal start-up sequence will be started automatically. Table 6 describe

commands and conditions that can activate power save. All channels (R,G,B) need to meet power save condition

in order to enable power save.

Table 6. LED Controller Operation

LED CONTROLLER OPERATION

MODE (R,G,B_MODE)

POWER SAVE CONDITION

00b

01b

Disabled mode enables power save

Load program to SRAM mode prevents power save

Run program mode enables power save if there is no PWM activity and command

look-ahead filter condition is met

10b

11b

Direct control mode enables power save if there is no PWM activity

COMMAND

POWER SAVE CONDITION

No PWM activity and current command wait time longer than 50 ms. If prescale = 1

then wait time needs to be longer than 80 ms.

Wait

Ramp Command PWM value reaches minimum 0 and current command execution

time left more than 50 ms. If prescale = 1 then time left needs to be more than 80 ms.

Ramp

Trigger

End

No PWM activity during wait for trigger command execution.

No PWM activity or Reset bit = 1

Set PWM

Enables power save if PWM set to 0 and next command generates at least 50 ms wait

No effect to power save

Other commands

See application note LP5521 Power Efficiency Considerations (SNVA185) for more information.

7.3.4 External Clock Detection

The presence of external clock can be detected by the LP5521. Program execution is clocked with internal 32

kHz clock or with external clock. Clocking is controlled with register address 08H bits, INT_CLK_EN and

CLK_DET_EN as seen on the following table.

External clock can be used if clock is present at CLK_32K pin. External clock frequency must be 32 kHz for the

program execution / PWM timing to be like specified. If higher or lower frequency is used, it will affect the

program engine execution speed. If other than 32 kHz clock frequency is used, the program execution timings

must be scaled accordingly. The external clock detector block only detects too low clock frequency (< 15 kHz). If

external clock frequency is higher than specified, the external clock detector notifies that external clock is

present. External clock status can be checked with read only bit EXT_CLK_USED in register address 0CH, when

the external clock detection is enabled (CLK_DET_EN bit = high). If EXT_CLK_USED = 1, then the external

clock is detected and it is used for timing, if automatic clock selection is enabled (see Table 7).

If external clock is stuck-at-zero or stuck-at-one, or the clock frequency is too low, the clock detector indicates

that external clock is not present.

If external clock is not used on the application, connect the CLK_32K pin to GND to prevent floating of this pin

and extra current consumption.

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Table 7. CONFIG Register (08H):

NAME

BIT

DESCRIPTION

LED controller clock source

00b = External clock source (CLK_32K)

01b = Internal clock

10b = Automatic selection

11b = Internal clock

CLK_DET_EN,

INT_CLK_EN

1:0

7.3.5 Logic Interface Operational Description

LP5521 features a flexible logic interface for connecting to processor and peripheral devices. Communication is

done with I²C compatible interface and different logic input/output pins makes it possible to synchronize

operation of several devices.

7.3.5.1 I/O Levels

I²C interface, CLK_32K and TRIG pins input levels are defined by EN pin. Using EN pin as voltage reference for

logic inputs simplifies PWB routing and eliminates the need for dedicated V_IOpin. Figure 17 describes EN pin

connections.

VDD

Input

Buffer

EN

Level

Shifter

SDA

Level

Shifter

SCL

Figure 17. Using EN Pin as Digital I/O Voltage Reference

ADDR_SEL0/1 are referenced to V_DDvoltage. GPO pin level is defined by V_DDvoltage.

7.3.5.2 GPO/INT Pins

LP5521 has one General Purpose Output pin (GPO); the INT pin can also be configured as a GPO pin. When

INT is configured as GPO output, its level is defined by the V_DDvoltage. State of the pins can be controlled with

GPO register (0EH). GPO pins are digital CMOS outputs and no pullup or pulldown resistors are needed.

When INT pin GPO function is disabled, it operates as an open drain pin. INT signal is active low; that is, when

interrupt signal is sent, the pin is pulled to GND. External pullup resistor is needed for proper functionality.

Table 8. GPO Register (0EH)

NAME

BIT

DESCRIPTION

Enable INT pin GPO function

INT_AS_GPO

2

0 = INT pin functions as a INT pin

1 = INT pin functions as a GPO pin

0 = GPO pin state is low

1 = GPO pin state is high

GPO

INT

1

0

0 = INT pin state is low (INT_AS_GPO=1)

1 = INT pin state is high (INT_AS_GPO=1)

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7.3.5.3 TRIG Pin

The TRIG pin can function as an external trigger input or output. External trigger signal is active low; that is,

when trigger is sent or received the pin is pulled to GND. TRIG is an open-drain pin and external pullup resistor

is needed for trigger line. External trigger input signal must be at least two 32-kHz clock cycles long to be

recognized. Trigger output signal is three 32-kHz clock cycles long. If TRIG pin is not used on application,

connected the TRIG pin to GND to prevent floating of this pin and extra current consumption.

7.3.5.4 ADDR_SEL0,1 Pins

The ADDR_SEL0,1 pins define the chip I²C address. Pins are referenced to V_DDsignal level. See I²C-Compatible

Serial Bus Interface for I²C address definitions.

7.3.5.5 CLK_32K Pin

The CLK_32K pin is used for connecting an external 32-kHz clock to LP5521. External clock can be used to

synchronize the sequence engines of several LP5521. Using external clock can also improve automatic power

save mode efficiency, because internal clock can be switched off automatically when device has entered power

save mode, and external clock is present. See application note LP5521 Power Efficiency Considerations

(SNVA185) for more information.

Device can be used without the external clock. If external clock is not used on the application, connect the

CLK_32K pin to GND to prevent floating of this pin and extra current consumption.

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7.4 Device Functional Modes

7.4.1 Modes of Operation

RESET:

In the RESET mode all the internal registers are reset to the default values. Reset is done always if

Reset Register (0DH) is written FFH or internal power on reset (POR) is activated. POR activates

when supply voltage is connected or when the supply voltage V_DDfalls below 1.5 V typical (0.8 V

minimum). Once V_DDrises above 1.5 V, POR inactivates, and the chip continues to the STANDBY

mode. CHIP_EN control bit is low after POR by default.

STANDBY: The STANDBY mode is entered if the register bit CHIP_EN or EN pin is LOW and Reset is not

active. This is the low power consumption mode, when all circuit functions are disabled. Registers

can be written in this mode if EN pin is high. Control bits are effective after start-up.

START-UP: When CHIP_EN bit is written high and EN pin is high, the INTERNAL STARTUP SEQUENCE

powers up all the needed internal blocks (V_REF, bias, oscillator, etc.). Start-up delay is after setting

EN pin high is 1 ms (typical). Start-up delay after setting CHIP_EN to 1 is 500 μs (typical). If the

chip temperature rises too high, the thermal shutdown (TSD) disables the chip operation, and the

chip state is in START-UP mode until no TSD event is present.⁽¹⁾

NORMAL: During NORMAL mode the user controls the chip using the Control Registers. If EN pin is set low,

the CHIP_EN bit is reset to 0.

POWER SAVE:In POWER SAVE mode analog blocks are disabled to minimize power consumption. See

Automatic Power Save for further information.

POR

RESET

2

I C reset=H and EN=H (pin)

or

POR=H

STANDBY

EN=H (pin) and

CHIP_EN=H (bit)

EN=L (pin) or

CHIP_EN=L (bit)

INTERNAL

STARTUP

SEQUENCE

TSD = L

TSD = H

NORMAL MODE

Exit power save

Enter power save

POWER SAVE

Figure 18. Modes of Operation

(1) Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at T_J= 150°C (typical) and

disengages at T_J= 130°C (typical).

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7.5 Programming

7.5.1 I²C-Compatible Serial Bus Interface

7.5.1.1 Interface Bus Overview

The I²C compatible synchronous serial interface provides access to the programmable functions and registers on

the device. This protocol uses a two-wire interface for bidirectional communications between the IC's connected

to the bus. The two interface lines are the serial data line (SDA), and the serial clock line (SCL). These lines

should be connected to a positive supply, via a pullup resistor and remain HIGH even when the bus is idle.

Every device on the bus is assigned a unique address and acts as either a Master or a Slave depending on

whether it generates or receives the serial clock (SCL).

7.5.1.2 Data Transactions

One data bit is transferred during each clock pulse. Data is sampled during the high state of the serial clock

(SCL). Consequently, throughout the high period of the clock the data should remain stable. Any changes on the

SDA line during the high state of the SCL and in the middle of a transaction, aborts the current transaction. New

data should be sent during the low SCL state. This protocol permits a single data line to transfer both

command/control information and data using the synchronous serial clock.

SCL

SDA

data

change

allowed

data

change

allowed

data

change

allowed

data

valid

data

valid

Figure 19. Data Validity

Each data transaction is composed of a start condition, a number of byte transfers (set by the software) and a

stop condition to terminate the transaction. Every byte written to the SDA bus must be 8 bits long and is

transferred with the most significant bit first. After each byte, an acknowledge signal must follow. The following

sections provide further details of this process.

Transmitter Stays off the

Bus During the

Acknowledge Clock

Acknowledge Signal

from Receiver

1

2

3...6

7

8

9

S

Start

Condition

Figure 20. Acknowledge Signal

The Master device on the bus always generates the start and stop conditions (control codes). After a start

condition is generated, the bus is considered busy and it retains this status until a certain time after a stop

condition is generated. A high-to-low transition of the data line (SDA) while the clock (SCL) is high indicates a

start condition. A low-to-high transition of the SDA line while the SCL is high indicates a stop condition.

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Programming (continued)

SDA

SCL

S

P

START condition

STOP condition

Figure 21. Start and Stop Conditions

In addition to the first start condition, a repeated start condition can be generated in the middle of a transaction.

This allows another device to be accessed, or a register read cycle.

7.5.1.3 Acknowledge Cycle

The acknowledge cycle consists of two signals: the acknowledge clock pulse the master sends with each byte

transferred, and the acknowledge signal sent by the receiving device.

The master generates the acknowledge clock pulse on the ninth clock pulse of the byte transfer. The transmitter

releases the SDA line (permits it to go high) to allow the receiver to send the acknowledge signal. The receiver

must pull down the SDA line during the acknowledge clock pulse and ensure that SDA remains low during the

high period of the clock pulse, thus signaling the correct reception of the last data byte and its readiness to

receive the next byte.

7.5.1.4 Acknowledge After Every Byte Rule

The master generates an acknowledge clock pulse after each byte transfer. The receiver sends an acknowledge

signal after every byte received.

There is one exception to the acknowledge after every byte rule. When the master is the receiver, it must

indicate to the transmitter an end of data by not-acknowledging (negative acknowledge) the last byte clocked out

of the slave. This negative acknowledge still includes the acknowledge clock pulse (generated by the master),

but the SDA line is not pulled down.

7.5.1.5 Addressing Transfer Formats

Each device on the bus has a unique slave address. The LP5521 operates as a slave device with the 7-bit

address. The LP5521 I²C address is pin selectable from four different choices. If 8-bit address is used for

programming, the 8th bit is 1 for read and 0 for write. Table 9 shows the 8-bit I²C addresses.

Table 9. 8-Bit I²C Addresses

ADDR_SEL

[1:0]

I²C ADDRESS WRITE

(8 bits)

I²C ADDRESS READ

(8 bits)

00

01

10

11

0110 0100 = 64H

0110 0110 = 66H

0110 1000 = 68H

0110 1010 = 6AH

0110 0101 = 65H

0110 0111 = 67H

0110 1001 = 69H

0110 1011 = 6BH

Before any data is transmitted, the master transmits the address of the slave being addressed. The slave device

sends an acknowledge signal on the SDA line, once it recognizes its address.

The slave address is the first seven bits after a start condition. The direction of the data transfer (R/W) depends

on the bit sent after the slave address — the eighth bit.

When the slave address is sent, each device in the system compares this slave address with its own. If there is a

match, the device considers itself addressed and sends an acknowledge signal. Depending upon the state of the

R/W bit (1:read, 0:write), the device acts as a transmitter or a receiver.

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MSB

LSB

ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 R/W

Bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

2

I C SLAVE address (chip address)

Figure 22. I²C Chip Address

7.5.1.6 Control Register Write Cycle

•

Master device generates start condition.

Master device sends slave address (7 bits) and the data direction bit (r/w = 0).

Slave device sends acknowledge signal if the slave address is correct.

Master sends control register address (8 bits).

Slave sends acknowledge signal.

Master sends data byte to be written to the addressed register.

Slave sends acknowledge signal.

If master will send further data bytes the control register address is incremented by one after acknowledge

signal.

•

Write cycle ends when the master creates stop condition.

7.5.1.7 Control Register Read Cycle

•

Master device generates a start condition.

Master device sends slave address (7 bits) and the data direction bit (r/w = 0).

Slave device sends acknowledge signal if the slave address is correct.

Master sends control register address (8 bits).

Slave sends acknowledge signal.

Master device generates repeated start condition.

Master sends the slave address (7 bits) and the data direction bit (r/w = 1).

Slave sends acknowledge signal if the slave address is correct.

Slave sends data byte from addressed register.

If the master device sends acknowledge signal, the control register address is incremented by one. Slave

device sends data byte from addressed register.

•

Read cycle ends when the master does not generate acknowledge signal after data byte and generates stop

condition.

ADDRESS MODE

<Slave Address><r/w = 0>[Ack]

<Register Addr.>[Ack]

<Slave Address><r/w = 1>[Ack]

Data Read

[Register Data]<Ack or NAck>

… additional reads from subsequent register address possible

<Slave Address><r/w=’0’>[Ack]

<Register Addr.>[Ack]

<Register Data>[Ack]

Data Write

… additional writes to subsequent register address possible

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<>Data from master [ ] Data from slave

ack from slave

ack stop

ack from slave

start

MSB Chip id LSB

w

ack MSB Register Addr LSB ack

MSB Data LSB

SCL

SDA

start

id = 011 0010b

w

ack

address = 02H

ack

address 02H data

ack stop

Figure 23. Register Write Format

When a READ function is to be accomplished, a WRITE function must precede the READ function, as shown in

Figure 24.

ack from slave

ack from slave repeated start

ack from slave data from slave nack from master

start

MSB Chip id LSB

w

MSB Register Addr LSB

rs

MSB Chip Address LSB

r

MSB Data LSB

stop

SCL

SDA

start

id = 011 0010b

w

ack

address = 00H

ack rs

id = 011 0010b

r

ack

address 00H data

nack stop

w = write (SDA = 0)

r = read (SDA = 1)

ack = acknowledge (SDA pulled down by either master or slave

rs = repeated start

id = 7-bit chip address

Figure 24. Register Read Format

7.5.2 LED Controller Operation Modes

Operation modes are defined in register address 01H. Each output channel (R, G, B) operation mode can be

configured separately. MODE registers are synchronized to a 32-kHz clock. Delay between consecutive I²C

writes to OP_MODE register (01H) need to be longer than 153 µs (typical).

Table 10. OP_MODE Register (01H):

NAME

BIT

DESCRIPTION

R_MODE

5:4

R channel operation mode

00b = Disabled, reset R channel PC

01b = Load program to SRAM, reset R channel PC

10b = Run program defined by R_EXEC

11b = Direct control, reset R channel PC

G_MODE

B_MODE

3:2

1:0

G channel operation mode

00b = Disabled, reset G channel PC

01b = Load program to SRAM, reset G channel PC

10b = Run program defined by G_EXEC

11b = Direct control, reset G channel PC

B channel operation mode

00b = Disabled, reset B channel PC

01b = Load program to SRAM, reset B channel PC

10b = Run program defined by B_EXEC

11b = Direct control, reset B channel PC

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7.5.2.1 Disabled

Each channel can be configured to disabled mode. LED output current is 0 during this mode. Disabled mode

resets PC of respective channel.

7.5.2.2 LOAD Program

LP5521 can store 16 commands for each channel (R, G, B). Each command consists of 16 bits. Because one

register has only 8 bits, one command requires two I²C register addresses. In order to reduce program load time

LP5521 supports address auto incrementation. Register address is incremented after each 8 data bits. Whole

program memory can be written in one I²C write sequence.

Program memory is defined in the LP5521 register table, 10H to 2FH for R channel, 30H to 4FH for G channel

and 50H to 6FH for B channel. In order to be able to access program memory at least one channel operation

mode needs to be LOAD Program.

Memory writes are allowed only to the channel in LOAD mode. All channels are in hold while one or several

channels are in LOAD program mode, and PWM values are frozen for the channels which are not in LOAD

mode. Program execution continues when all channels are out of LOAD program mode. LOAD Program mode

resets PC of respective channel.

7.5.2.3 RUN Program

RUN Program mode executes the commands defined in program memory for respective channel (R, G, B).

Execution register bits in ENABLE register define how program is executed. Program start position can be

programmed to Program Counter register (see the following tables). By manually selecting the PC start value,

user can write different lighting sequences to the memory, and select appropriate sequence with the PC register.

If program counter runs to end (15) the next command will be executed from program location 0.

If internal clock is used in the RUN program mode, operation mode needs to be written disabled (00b) before

disabling the chip (with CHIP_EN bit or EN pin) to ensure that the sequence starts from the correct program

counter (PC) value when restarting the sequence.

PC registers are synchronized to 32 kHz clock. Delay between consecutive I²C writes to PC registers (09H, 0AH,

0BH) need to be longer than 153 µs (typ.).

Note that entering LOAD program or Direct Control Mode from RUN PROGRAM mode is not allowed. Engine

execution mode should be set to Hold, and Operation Mode to disabled, when changing operation mode from

RUN mode.

Table 11. R Channel PC Register (09H), G CHANNEL PC Register (0AH), B CHANNEL PC Register (0BH)

NAME

BIT

DESCRIPTION

PC

3:0

Program counter value from 0 to 15d

Table 12. ENABLE Register (00H)

NAME

BIT

DESCRIPTION

R_EXEC

5:4

R channel program execution

00b = Hold: Wait until current command is finished then stop while EXEC mode is hold. PC can be read

or written only in this mode.

01b = Step: Execute instruction defined by current R channel PC value, increment PC and change

R_EXEC to 00b (Hold)

10b = Run: Start at program counter value defined by current R channel PC value

11b = Execute instruction defined by current R channel PC value and change R_EXEC to 00b (Hold)

G_EXEC

3:2

G channel program execution

00b = Hold: Wait until current command is finished then stop while EXEC mode is hold. PC can be read

or written only in this mode.

01b = Step: Execute instruction defined by current G channel PC value, increment PC and change

G_EXEC to 00b (Hold)

10b = Run: Start at program counter value defined by current G channel PC value

11b = Execute instruction defined by current G channel PC value and change G_EXEC to 00b (Hold)

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Table 12. ENABLE Register (00H) (continued)

NAME

BIT

DESCRIPTION

B_EXEC

1:0

B channel program execution

00b = Hold: Wait until current command is finished then stop while EXEC mode is hold. PC can be read

or written only in this mode.

01b = Step: Execute instruction defined by current B channel PC value, increment PC and change

B_EXEC to 00b (Hold)

10b = Run: Start at program counter value defined by current B channel PC value

11b = Execute instruction defined by current B channel PC value and change B_EXEC to 00b (Hold)

EXEC registers are synchronized to 32-kHz clock. Delay between consecutive I²C writes to ENABLE register

(00H) need to be longer than 488 μs (typ.).

7.5.2.3.1 DIRECT Control

When R, G or B channel mode is set to 11b, the LP5521 drivers work in direct control mode. LP5521 LED

channels can be controlled independently through I²C. For each channel there is a PWM control register and a

output current control register. With output current control register is set what is the maximum output current with

8-bit resolution, step size is 100 μA. Duty cycle can be set with 8-bit resolution. Direct control mode resets

respective channel’s PC. PWM control bits are presented in Table 13:

Table 13. R_PWM Register (02H), G_PWM Register (03H), B_PWM Register (04H):

NAME

BIT

DESCRIPTION

PWM

7:0

LED PWM value during direct control operation mode

0000 0000b = 0%

1111 1111b = 100%

If charge pump automatic gain change is used in this mode, then PWM values need to be written 0 before

changing the drivers’ operation mode to disabled (00b) to ensure proper automatic gain change operation.

7.5.3 LED Controller Programming Commands

LP5521 has three independent programmable channels (R, G, B). Trigger connections between channels are

common for all channels. All channels have own program memories for storing complex patterns. Brightness

control and patterns are done with 8-bit PWM control (256 steps) to get accurate and smooth color control.

Program execution is timed with 32 768 Hz clock. This clock can be generated internally or external 32 kHz clock

can be connected to CLK_32K pin. Using external clock enables synchronization of LED timing to this clock

rather than internal clock. Selection of the clock is made with address 08H bits INT_CLK_EN and CLK_DET_EN.

See External Clock Detection for details.

Supported commands are listed in Table 14. Command compiler is available for easy sequence

programming. With Command compiler it is possible to write sequences with simple ASCII commands,

which are then converted to binary or hex format. See application note "LP5521 Programming

Considerations" for examples of Command compiler usage.

Table 14. LED Controller Programming Commands

Command

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Ramp

Wait

Pre-

scale

0

Step time

Sign

Increment (number of steps)

Set PWM

0

1

0

PWM Value

Go to

Start

0

x

0

Branch

End

1

0

1

0

1

Loop count

Step / command number

Int

Reset

Wait for trigger on channels 5-0

X

Trigger

Send trigger on channels 5-0

X

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X means do not care whether 1 or 0.

7.5.3.1 RAMP/WAIT

Ramp command generates a PWM ramp starting from current value. At each ramp step the output is

incremented by one. Time for one step is defined with Prescale and Step time bits. Minimum time for one step is

0.49 ms and maximum time is 63 × 15.6 ms = 1 second/step, so it is possible to program very fast and also very

slow ramps. Increment value defines how many steps are taken in one command. Number of actual steps is

Increment + 1. Maximum value is 127d, which corresponds to half of full scale (128 steps). If during ramp

command PWM reaches minimum/maximum (0/255) ramp command is executed to the end, and PWM stays at

minimum/maximum. This enables ramp command to be used as combined ramp and wait command in a single

instruction.

Ramp command can be used as wait instruction when increment is zero.

Setting register 00H bit LOG_EN sets the scale from linear to logarithmic. When LOG_EN = 0 linear scale is

used, and when LOG_EN = 1 logarithmic scale is used. By using logarithmic scale the visual effect of the ramp

command seems linear to the eye.

Table 15. Ramp/Wait Command

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Pre-

scale

0

Step time

Sign

Increment

NAME

VALUE(d)

DESCRIPTION

0

1

Divides master clock (32 768Hz) by 16 = 2048 Hz, 0.49 ms cycle time

Divides master clock (32 768Hz) by 512 = 64 Hz, 15.6 ms cycle time

Prescale

One ramp increment done in (step time) x (clock after prescale) Note: 0 means Set

PMW command.

Step time

1-63

0

1

Increase PWM output

Decrease PWM output

Sign

Increment

0-127

The number of steps is Increment + 1. Note: 0 is a wait instruction.

Application example:

For example if following parameters are used for ramp:

•

Prescale = 1 → cycle time = 15.6 ms

Step time = 2 → time = 15.6 ms x 2 = 31.2 ms

Sign = 0 → rising ramp

Increment = 4 → 5 cycles

Ramp command will be: 0100 0010 0000 0100b = 4204H

If current PWM value is 3, and the first command is as described above and next command is a ramp with

otherwise same parameters, but with Sign = 1 (Command = 4284H), the result will be like in Figure 25:

PWM Control

Value

End of 1st Ramp command,

start next command

End of 2nd Ramp command,

start next command

Rising ramp,

Sign = 0

8

7

6

5

4

3

2

1

Increment = 4

=> 5 cycles

Current value

Downward

ramp, Sign = 1

Step time = 31.2 ms

Steps

1

2

3

4

5

6

7

8

9

10

Figure 25. Example of 2 Sequential Ramp Commands.

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7.5.3.2 Set PWM

Set PWM output value from 0 to 255. Command takes sixteen 32 kHz clock cycles (= 488 μs). Setting register

00H bit LOG_EN sets the scale from linear to logarithmic.

Table 16. Set PWM Command

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

1

0

PWM value

7.5.3.3 Go to Start

Go to start command resets Program Counter register and continues executing program from the 00H location.

Command takes sixteen 32 kHz clock cycles. Note that default value for all program memory registers is 0000H,

which is Go to start command.

Go to start command

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

7.5.3.4 Branch

When branch command is executed, the 'step number' value is loaded to PC and program execution continues

from this location. Looping is done by the number defined in loop count parameter. Nested looping is supported

(loop inside loop). The number of nested loops is not limited. Command takes sixteen 32-kHz clock cycles.

Table 17. Branch Command

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

1

0

1

Loop count

X

Step number

NAME

VALUE(d)

0-63

DESCRIPTION

loop count

step number

The number of loops to be done. 0 means infinite loop.

The step number to be loaded to program counter.

0-15

7.5.3.5 End

End program execution, resets the program counter and sets the corresponding EXEC register to 00b (hold).

Command takes sixteen 32-kHz clock cycles.

Table 18. End Command

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

1

0

int

reset

X

NAME

VALUE

DESCRIPTION

0

No interrupt will be sent.

Send interrupt to processor by pulling the INT pin down and setting corresponding status

register bit high to notify that program has ended. Interrupt can only be cleared by reading

interrupt status register 0CH.

int

1

0

1

Keep the current PWM value.

Set PWM value to 0.

reset

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7.5.3.6 Trigger

Wait or send triggers can be used to, for example, synchronize operation between different channels. Send

trigger command takes sixteen 32-kHz clock cycles, and wait for trigger takes at least sixteen 32 kHz clock

cycles. The receiving channel stores sent triggers. Received triggers are cleared by wait for trigger command if

received triggers match to channels defined in the command. Channel waits for until all defined triggers have

been received.

External trigger input signal must be at least two 32-kHz clock cycles (= 61 μs typical) long to be recognized.

Trigger output signal is three 32-kHz clock cycles (92 μs typical) long. External trigger signal is active low; that is,

when trigger is sent/received the pin is pulled to GND. Sent external trigger is masked; that is, the device which

has sent the trigger does not recognize it. If send and wait external trigger are used on the same command, the

send external trigger is executed first, then the wait external trigger.

Table 19. Trigger Command

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

wait trigger <5:0>

send trigger <5:0>

1

X

EXT

X

B

G

R

EXT

X

B

G

R

NAME

VALUE(d)

DESCRIPTION

Wait for trigger for the channel(s) defined. Several triggers can be defined in the same

command. Bit 0 is R, bit 1 is G, bit 2 is B and bit 5 is external trigger I/O. Bits 3 and 4

are not in use.

wait trigger<5:0>

send trigger<5:0>

0-31

Send trigger for the channel(s) defined. Several triggers can be defined in the same

command. Bit 0 is R, bit 1 is G, bit 2 is B and bit 5 is external trigger I/O. Bits 3 and 4

are not in use.

0-31

X means do not care whether 1 or 0.

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7.6.1 Enable Register (Enable)

Address 00H

Reset value 00H

Table 21. Enable Register

7

6

5

4

3

2

1

0

LOG_EN

CHIP_EN

R_EXEC[1]

R_EXEC[0]

G_EXEC[1]

G_EXEC[0]

B_EXEC[1]

B_EXEC[0]

NAME

BIT

ACCESS

ACTIVE

DESCRIPTION

Logarithmic PWM adjustment generation enable

LOG_EN

7

R/W

High

Master chip enable. Enables device internal startup sequence. Startup delay

after setting CHIP_EN is 500 μs. See Operation for further information.

Setting EN pin low resets the CHIP_EN state to 0.

CHIP_EN

6

R/W

High

R channel program execution.

00b = Hold: Wait until current command is finished then stop while EXEC

mode is hold. PC can be read or written only in this mode.

01b = Step: Execute instruction defined by current R channel PC value,

increment PC and change R_EXEC to 00b (Hold)

10b = Run: Start at program counter value defined by current R Channel PC

value

R_EXEC

5:4

R/W

11b = Execute instruction defined by current R channel PC value and change

R_EXEC to 00b (Hold)

G channel program execution

00b = Hold: Wait until current command is finished then stop while EXEC

mode is hold. PC can be read or written only in this mode.

01b = Step: Execute instruction defined by current G channel PC value,

increment PC and change G_EXEC to 00b (Hold)

10b = Run: Start at program counter value defined by current G Channel PC

value

G_EXEC

3:2

11b = Execute instruction defined by current G channel PC value and

change G_EXEC to 00b (Hold)

B channel program execution

00b = Hold: Wait until current command is finished then stop while EXEC

mode is hold. PC can be read or written only in this mode.

01b = Step: Execute instruction defined by current B channel PC value,

increment PC and change B_EXEC to 00b (Hold)

10b = Run: Start at program counter value defined by current B Channel PC

value

B_EXEC

1:0

11b = Execute instruction defined by current B channel PC value and change

B_EXEC to 00b (Hold)

EXEC registers are synchronized to 32 kHz clock. Delay between consecutive I²C writes to ENABLE register

(00H) need to be longer than 488 μs (typ).

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7.6.2 Operation Mode Register (OP Mode)

Address 01H

Reset value 00H

Table 22. OP Mode Register

7

6

5

4

3

2

1

0

R_MODE[1]

R_MODE[0]

G_MODE[1]

G_MODE[0]

B_MODE[1]

B_MODE[0]

NAME

BIT

ACCESS

ACTIVE

DESCRIPTION

R channel operation mode

00b = Disabled

R_MODE

5:4

R/W

01b = Load program to SRAM, reset R channel PC

10b = Run program defined by R_EXEC

11b = Direct control

G channel operation mode

00b = Disabled

01b = Load program to SRAM, reset G channel PC

10b = Run program defined by G_EXEC

11b = Direct control

G_MODE

B_MODE

3:2

1:0

B channel operation mode

00b = Disabled

01b = Load program to SRAM, reset B channel PC

10b = Run program defined by B_EXEC

11b = Direct control

MODE registers are synchronized to 32 kHz clock. Delay between consecutive I²C writes to OP_MODE register

(01H) need to be longer than 153 μs (typ).

7.6.3 R Channel PWM Control (R_PWM)

Address 02H

Reset value 00H

Table 23. R PWM Register

7

6

5

4

3

2

1

0

R_PWM[7:0]

NAME

BIT

ACCESS

ACTIVE

DESCRIPTION

R Channel PWM value during direct control operation mode

R_PWM

7:0

R/W

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7.6.4 G Channel PWM Control (G_PWM)

Address 03H

Reset value 00H

Table 24. G PWM Register

7

6

5

4

3

2

1

0

G_PWM[7:0]

NAME

BIT

ACCESS

ACTIVE DESCRIPTION

G_PWM

7:0

R/W

G Channel PWM value during direct control operation mode

7.6.5 B Channel PWM Control (B_PWM)

Address 04H

Reset value 00H

Table 25. B PWM Register

7

6

5

4

3

2

B_PWM[7:0]

NAME

BIT

ACCESS

ACTIVE DESCRIPTION

B Channel PWM value during direct control operation mode

B_PWM

7:0

R/W

7.6.6 R Channel Current (R_CURRENT)

Address 05H

Reset Value AFH

Table 26. R CURRENT Register

7

6

5

4

3

2

R_CURRENT[7:0]

NAME

BIT

ACCESS

ACTIVE

DESCRIPTION

Current setting

0000 0000b = 0.0 mA

0000 0001b = 0.1 mA

0000 0010b = 0.2 mA

0000 0011b = 0.3 mA

0000 0100b = 0.4 mA

0000 0101b = 0.5 mA

0000 0110b = 0.6 mA

...

R_CURRENT

7:0

R/W

1010 1111b = 17.5 mA (default)

...

1111 1011b = 25.1 mA

1111 1100b = 25.2 mA

1111 1101b = 25.3 mA

1111 1110b = 25.4 mA

1111 1111b = 25.5 mA

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7.6.7 G Channel Current (G_CURRENT)

Address 06H

Reset Value AFH

Table 27. G CURRENT Register

7

6

5

4

3

2

1

0

G_CURRENT[7:0]

NAME

BIT

ACCESS

ACTIVE

DESCRIPTION

Current setting

0000 0000b = 0.0 mA

0000 0001b = 0.1 mA

0000 0010b = 0.2 mA

0000 0011b = 0.3 mA

0000 0100b = 0.4 mA

0000 0101b = 0.5 mA

0000 0110b = 0.6 mA

...

G_CURRENT

7:0

R/W

1010 1111b = 17.5 mA (default)

...

1111 1011b = 25.1 mA

1111 1100b = 25.2 mA

1111 1101b = 25.3 mA

1111 1110b = 25.4 mA

1111 1111b = 25.5 mA

7.6.8 B Channel Current (B_CURRENT)

Address 07H

Reset value AFH

Table 28. B CURRENT Register

7

6

5

4

3

2

1

0

B_CURRENT[7:0]

NAME

BIT

ACCESS

ACTIVE

DESCRIPTION

Current setting

0000 0000b = 0.0 mA

0000 0001b = 0.1 mA

0000 0010b = 0.2 mA

0000 0011b = 0.3 mA

0000 0100b = 0.4 mA

0000 0101b = 0.5 mA

0000 0110b = 0.6 mA

...

B_CURRENT

7:0

R/W

1010 1111b = 17.5 mA (default)

...

1111 1011b = 25.1 mA

1111 1100b = 25.2 mA

1111 1101b = 25.3 mA

1111 1110b = 25.4 mA

1111 1111b = 25.5 mA

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7.6.9 Configuration Control (CONFIG)

Address 08H

Reset value 00H

Table 29. CONFIG Register

7

6

5

4

3

2

1

0

PWM_HF

PWRSAVE_EN

CP_MODE[1:0]

R_TO_BATT

CLK_DET_EN

INT_CLK_EN

NAME

PWM_HF

BIT

ACCESS

ACTIVE

High

DESCRIPTION

PWM clock

0 = 256 Hz PWM clock used (CLK_32K)

6

5

R/W

1 = 558 Hz PWM clock used (internal oscillator)

PWRSAVE_EN

High

Power save mode enable

Charge pump operation mode

00b = OFF

CP_MODE

4:3

2

R/W

01b = Forced to bypass mode (1x)

10b = Forced to 1.5x mode

11b = Automatic mode selection

R channel supply connection

0 = R output connected to charge pump

1 = R output connected to battery

R_TO_BATT

High

LED Controller clock source

00b = External clock source (CLK_32K)

01b = Internal clock

10b = Automatic selection

11b = Internal clock

CLK_DET_EN,

INT_CLK_EN

1:0

7.6.10 R Channel Program Counter Value (R Channel PC)

Address 09H

Reset value 00H

Table 30. R Channel PC Register

7

6

5

4

3

2

1

0

R_PC[3]

R_PC[2]

R_PC[1]

R_PC[0]

NAME

BIT

ACCESS

ACTIVE

DESCRIPTION

R channel program counter value

R_PC

3:0

R/W

PC registers are synchronized to a 32-kHz clock. Delay between consecutive I²C writes to PC registers needs to

be longer than 153 μs (typ.). PC register can be read or written only when EXEC mode is 'hold'.

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7.6.11 G Channel Program Counter Value (G Channel PC)

Address 0AH

Reset value 00H

Table 31. G Channel PC Register

7

6

5

4

3

2

1

0

G_PC[3]

G_PC[2]

G_PC[1]

G_PC[0]

NAME

BIT

ACCESS

ACTIVE

DESCRIPTION

G channel program counter value

G_PC

3:0

R/W

PC registers are synchronized to 32 kHz clock. Delay between consecutive I²C writes to PC registers needs to

be longer than 153 μs (typ.). PC register can be read or written only when EXEC mode is 'hold'.

7.6.12 B Channel Program Counter Value (B Channel PC)

Address 0BH

Reset value 00H

Table 32. B Channel PC Register

7

6

5

4

3

2

1

0

B_PC[3]

B_PC[2]

B_PC[1]

B_PC[0]

NAME

BIT

ACCESS

ACTIVE

DESCRIPTION

B channel program counter value

B_PC

3:0

R/W

PC registers are synchronized to a 32-kHz clock. Delay between consecutive I²C writes to PC registers must be

longer than 153 μs (typ.). PC register can be read or written only when EXEC mode is 'hold'.

7.6.13 Status/Interrupt Register

Address 0CH

Reset value 00H

Table 33. STATUS/INTERRUPT Register

7

6

5

4

3

2

1

0

EXT_CLK

USED

R_INT

G_INT

B_INT

NAME

BIT

ACCESS

ACTIVE

DESCRIPTION

EXT_CLK

USED

External clock state

0 = Internal 32kHz clock used

1 = External 32kHz clock used

3

R

R_INT

G_INT

B_INT

2

1

0

R

High

Interrupt from R channel

Interrupt from G channel

Interrupt from B channel

Note: Register INT bits will be cleared when read operation to Status/Interrupt register occurs. INT output pin

(active low) will go high after read operation.

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7.6.14 RESET Register

Address 0DH

Reset value 00H

Table 34. RESET Register

7

6

5

4

3

2

1

0

RESET

NAME

BIT

7:0

ACCESS

ACTIVE

DESCRIPTION

RESET

W

Reset all register values when FFH is written. No acknowledge from LP5521

after write.

7.6.15 GPO Register

Address 0EH

Reset value 00H

Table 35. GPO Register

7

6

5

4

3

2

1

0

INT_AS_GPO

GPO

INT

NAME

BIT

ACCESS

ACTIVE

DESCRIPTION

INT_AS_GPO

2

R/W

High

Enable INT pin GPO function

GPO pin state:

0 = LOW

1 = HIGH

GPO

INT

1

0

R/W

High

INT pin state (when INT_AS_GPO=1):

0 = LOW

1 = HIGH

7.6.16 Program Memory

Address 10H – 6FH

Reset values 00H

Please see LED Controller Programming Commands for further information.

Command

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Ramp

Wait

Pre-

scale

0

Step time

Sign

Increment

Set PWM

Go toStart

Branch

End

0

1

0

1

0

PWM Value

0

1

0

1

Loop Count

X

Step number

Int

Reset

Wait for trigger on channels 5-0

X

Trigger

Send trigger on channels 5-0

X

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8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The LP5521 is designed as a autonomous lighting controller for mobile devices. These devices need extremely

small form factor; therefore, the LP5521 is designed to require only 4 small capacitors: input, output, and two fly-

capacitors for charge pump. If charge pump is not needed in the application (input voltage is high enough for

driving LEDs), the charge pump capacitors can be omitted thus reducing the solution size even further. LED can

be RGB LED or any color if desired.

8.2 Typical Applications

Application with Charge Pump shows an example of typical application which uses charge pump to get high

enough voltage to drive LEDs. The device is powered from single Li-Ion battery with voltage range of 2.7 V to 4.2

V.

8.2.1 Application with Charge Pump

C_FLY1

C_FLY2

0.47 µF

C_OUT

1 µF

CFLY1P

VDD

CFLY1N

CFLY2P

CFLY2N

VOUT

C_IN

-

1 µF

RGB LED 0...25.5 mA/LED

SCL

SDA

R

G

B

LP5521

EN

MCU

CLK_32K

INT

TRIG

GPO

ADDR_SEL0

ADDR_SEL1

GNDs

Figure 26. LP5521 Typical Application Schematic With Charge Pump

8.2.1.1 Design Requirements

DESIGN PARAMETER

EXAMPLE VALUE

2.7 V to 4.2 V (single Li-Ion cell battery)

3.6 V

Input voltage range

LED V_F(maximum)

LED current

25.5 mA maximum

C_IN= 1 μF

Input capacitor

Output capacitor

Fly capacitors

C_OUT= 1 μF

C_FLY1= C_FLY2= 470 nF

Automatic or 1.5×

Charge pump mode

36

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8.2.1.2 Detailed Design Procedure

8.2.1.2.1 Capacitor Selection

The LP5521 requires 4 external capacitors for proper operation (C_IN= C_OUT= 1 μF, C_FLY1= C_FLY2= 470 nF).

Surface-mount multi-layer ceramic capacitors are recommended. These capacitors are small, inexpensive and

have very low equivalent series resistance (ESR < 20 mΩ typical). Tantalum capacitors, OS-CON capacitors,

and aluminum electrolytic capacitors are not recommended for use with the LP5521 due to their high ESR, as

compared to ceramic capacitors.

For most applications, ceramic capacitors with X7R or X5R temperature characteristic are preferred for use with

the LP5521. These capacitors have tight capacitance tolerance (as good as ±10%) and hold their value over

temperature (X7R: ±15% over –55°C to 125°C; X5R: ±15% over –55°C to 85°C).

Capacitors with Y5V or Z5U temperature characteristic are generally not recommended for use with the LP5521.

Capacitors with these temperature characteristics typically have wide capacitance tolerance (+80%, –20%) and

vary significantly over temperature (Y5V: +22%, –82% over –30°C to +85°C range; Z5U: +22%, –56% over

+10°C to +85°C range). Under some conditions, a nominal 1-μF Y5V or Z5U capacitor could have a capacitance

of only 0.1 μF. Such detrimental deviation is likely to cause Y5V and Z5U capacitors to fail to meet the minimum

capacitance requirements of the LP5521.

The minimum voltage rating acceptable for all capacitors is 6.3 V. The recommended voltage rating of the output

capacitor is 10 V to account for DC bias capacitance losses.

NOTE

Some ceramic capacitors, especially those in small packages, exhibit a strong capacitance

reduction with the increased applied voltage (DC bias effect). The capacitance value can

fall below half of the nominal capacitance. Choose output and input capacitor with DC bias

voltage effect better than –50% at 5 V voltage (0.5 μF at 5 V).

Table 36. External Component Examples

MODEL

1 μF for C_OUTand C_IN

C1005X5R1A105K

ECJ0EB1A105M

ECJUVBPA105M

470 nF for C_FLY1-2

C1005X5R1A474K

ECJ0EB0J474K

LEDs

TYPE

VENDOR

VOLTAGE RATING

SIZE INCH (mm)

Ceramic X5R

TDK

10 V

0402 (1005)

0504

Panasonic

Ceramic X5R, array of two

Ceramic X5R

TDK

10 V

0402 (1005)

Panasonic

User Defined

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8.2.1.3 Application Curves

Figure 28. Charge Pump Line Transient Response

1.5× Mode (V_IN3.5V to 4 V)

Figure 27. Charge Pump Load Transient Response in 1.5×

Mode (0 to 25.5 mA)

8.2.2 Application Without Charge Pump

In this application example the input voltage is high enough to drive the LEDs even without charge pump. In that

case the charge pump components are omitted, allowing savings on bill-of-material and also board space.

Charge pump must be set to 1× mode (bypass) in this case.

CFLY1P

CFLY1N

CFLY2P CFLY2N

VOUT

VDD

C

IN

1 mF

C

OUT

-

1 mF

RGB LED 0...25.5 mA/LED

SCL

SDA

EN

R

G

LP5521

MCU

CLK_32K

INT

B

TRIG

GPO

ADDR_SEL0

ADDR_SEL1

GNDs

Figure 29. Typical Application Schematic Without Charge Pump

8.2.2.1 Design Requirements

DESIGN PARAMETER

EXAMPLE VALUE

4.5 V to 5.5 V

3.6 V

Input voltage range

LED V_F(max)

LED current

25.5 mA maximum

C_IN= 1 μF

C_OUT= 1 μF

none

Input capacitor

Output capacitor

Fly capacitors

Charge pump mode

1X

38

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8.2.2.2 Detailed Design Procedures

Selecting input and output capacitors follows the same procedure as in the application with charge pump.

8.3 Initialization Setup

8.3.1 Program Load and Execution Example

1. Startup Device and Configure Device to SRAM Write Mode:

–

Supply e.g. 3.6 V to VDD

Supply e.g. 1.8 V to EN

Wait 1 ms (startup delay)

Generate 32 kHz clock to CLK_32K pin

Write to address 00H 0100 0000b (enable LP5521)

Wait 500 μs (startup delay)

Write to address 01H 0001 0000b (Configure R channel into "Load program to SRAM" mode)

2. Program Load to SRAM (see Figure 30):

–

Write to address 10H 0000 0011b (1st ramp command 8 MSB)

Write to address 11H 0111 1111b (1st ramp command 8 LSB)

Write to address 12H 0100 1101b (1st wait command 8 MSB)

Write to address 13H 0000 0000b (1st wait command 8 LSB)

Write to address 14H 0000 0011b (2nd ramp command 8 MSB)

Write to address 15H 1111 1111b (2nd ramp command 8 LSB)

Write to address 16H 0110 0000b (2nd wait command 8 MSB)

Write to address 17H 0000 0000b (2nd wait command 8 LSB)

3. Enable Powersave, charge pump automatic mode (1x / 1.5x) and use external 32 kHz clock:

Write to address 08H 0011 1000b

4. Run program:

–

Write to address 01H 0010 0000b (Configure LED controller operation mode to "Run program" in R

channel

–

Write to address 00H 0110 0000b (Configure program execution mode from "Hold" to "Run" in R channel

LP5521 will generate 1100 ms long LED pattern which will be repeated infinitely. LED pattern is illustrated in

Figure 30.

PWM value

255

R

127

Time (ms)

1700

1500 1600

1400

1200 1300

100

200

800

1100

900 1000

300 400 500 600 700

R program:

ramp up to PWM value 128 in 200 ms

wait 200 ms

ramp down to PWM value 0 in 200 ms

wait 500 ms

R program as binary code:

0000001101111111

0100110100000000

0000001111111111

0110000000000000

Figure 30. Sequence Diagram

8.3.2 Direct PWM Control Example

1. Start up device:

–

Supply, for example, 3.6 V to VDD

Supply, for example,1.8 V to EN

Wait 1 ms (start-up delay)

Write to address 00H 0100 0000b (enable LP5521)

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Initialization Setup (continued)

–

Wait 500 µs (start-up delay)

2. Enable charge pump 1.5x mode and use internal clock:

Write to address 08H 0001 0001b

3. Direct PWM control:

–

Write to address 01H 0011 1111b (Configure R, G and B channels into "Direct PWM control mode")

4. Write PWM values:

–

Write to address 02H 1000 0000b (R driver PWM 50% duty cycle)

Write to address 03H 1100 0000b (G driver PWM 75% duty cycle)

Write to address 04H 1111 1111b (B driver PWM 100% duty cycle)

LEDs are turned on after the PWM values are written. Changes to the PWM value registers are reflected

immediately to the LED brightness. Default LED current (17.5 mA) is used for LED outputs, if no other values are

written.

9 Power Supply Recommendations

The device is designed to operate from an input voltage supply range between 2.7 V and 5.5V. In a typical

application this is from single Li-ion battery cell. This input supply must be well regulated and able to withstand

maximum input current and maintain stable voltage without voltage drop even at load transition condition (start-

up or rapid brightness change). The resistance of the input supply rail must be low enough that the input current

transient does not cause drop below a 2.7-V level in the LP5521 supply voltage.

10 Layout

10.1 Layout Guidelines

Place capacitors as close to the LP5521 device as possible to minimize the current loops. Figure 31 shows an

example of LP5521 PCB layout and component placement.

10.2 Layout Example

aicroëiꢀs

CFLY

1P

CFLY

2P

VDD

GND

TRIG

INT

CLK

32K

CFLY

2N

CFLY

1N

/ontrol signꢀls

ADDR

SEL1

ADDR

SEL0

VOUT

B

GPO

SCL

EN

G

R

SDA

Çop [ꢀyer

Lnner [ꢀyer

ëiꢀs to Db5 plꢀne

Ço [95s

Figure 31. Example of Typical Layout

40

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11 Device and Documentation Support

11.1 Device Support

11.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT

CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES

OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER

ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

11.2 Documentation Support

11.2.1 Related Documentation

•

See LP5521 Programming Considerations for more information about programming of the device.

See LP5521 Power Efficiency Consideration for more information about powering the device and partitioning

the system.

•

See LP5521TM Evaluation Kit for more information about evaluation kit for LP5521TM.

11.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

11.4 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

11.5 Trademarks

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.6 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

11.7 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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Product Folder Links: LP5521

MECHANICAL DATA

YFQ0020xxx

D

0.600±0.075

E

TMD20XXX (Rev D)

D: Max = 2.093 mm, Min =2.033 mm

E: Max = 1.733 mm, Min =1.672 mm

4215083/A

12/12

A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.

B. This drawing is subject to change without notice.

NOTES:

www.ti.com

PACKAGE OUTLINE

NJA0024A

WQFN - 0.8 mm max height

S

C

A

L

E

2

.

8

0

PLASTIC QUAD FLATPACK - NO LEAD

4.1

3.9

A

B

PIN 1 INDEX AREA

5.1

4.9

0.8 MAX

NOTE 4

C

SEATING PLANE

0.08 C

0.110

0.035

SOLDER BUMP

2.4 0.1

2X 2

(0.2) TYP

8

12

EXPOSED

THERMAL PAD

20X 0.5

7

13

SYMM

2X

3.4 0.1

3

25

1

19

0.3

24X

0.2

0.1

0.05

24

20

SYMM

24X

C A B

PIN 1 ID

(OPTIONAL)

0.5

0.3

4215212/A 04/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

4. Package maximum height does not include the solder bump height.

www.ti.com

EXAMPLE BOARD LAYOUT

NJA0024A

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(2.4)

SYMM

24

20

24X (0.4)

1

19

2X

(0.86)

24X (0.25)

25

(3.4)

3X

SYMM

(4.4)

(1.18)

20X (0.5)

7

13

(R0.05) TYP

(

0.2) TYP

VIA

8

12

(0.95) TYP

(3.4)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:18X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

EXPOSED METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4215212/A 04/2017

NOTES: (continued)

5. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

6. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

NJA0024A

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

6X (1.06)

24

20

24X (0.4)

25

1

19

6X

(0.98)

24X (0.25)

METAL

TYP

SYMM

(4.4)

(1.18)

TYP

20X (0.5)

13

7

(R0.05) TYP

8

12

SYMM

(0.63) TYP

(3.4)

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

EXPOSED PAD 25:

76% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:25X

4215212/A 04/2017

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

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IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

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is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you

will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these

resources.

TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with

such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for

TI products.

TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	LP5521TMX/NOPB
厂家：	TEXAS INSTRUMENTS
描述：	具有内部程序存储器和集成电荷泵的 3 通道 RGB/白色 LED 驱动器 \| YFQ \| 20 \| -30 to 85 驱动泵接口集成电路存储驱动器
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