LP5891ZXLR [TI]
具有 16 位 PWM 调光和超低功耗的 48 × 16 LED 矩阵驱动器 | ZXL | 96 | -40 to 85;
| 型号： | LP5891ZXLR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 16 位 PWM 调光和超低功耗的 48 × 16 LED 矩阵驱动器 | ZXL | 96 | -40 to 85 驱动 驱动器 |
| 文件： | 总64页 (文件大小：2816K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LP5891
ZHCSQG6A –MARCH 2022 –REVISED MAY 2022
LP5891 具有48 个电流源、64 条扫描线的共阴极LED 矩阵驱动器
– 内部倍频器支持高频GCLK
• 优化了LED 矩阵显示屏的性能
1 特性
• 支持分立式VCC 和VR/G/B 电源
– 去除上下重影
– 低灰度增强
– VCC 电压范围：2.5V 至5.5V
– LED 开路/弱短路/短路检测和消除
• LP5891MRRFR 支持–55°C 至大概125°C 的工作
环境温度
– VR/G/B 电压范围：2.5V 至5.5V
• 48 个电流源通道，范围从0.2 mA 到20 mA
– 通道间精度：±0.5%（典型值），±2%（最大
值）；器件间一致性：±0.5%（典型值），±2%
（最大值）
– 低拐点电压：当IOUT = 5 mA 时为0.26V（最大
值）
2 应用
• Mini-/micro-LED 矩阵产品
• 游戏键盘RGB LED 背光
• 混音器、DJ 设备和广播
• LED 发光面板和局部调光背光
– 3 位（8 级）全局亮度控制
– 8 位（256 级）色彩亮度控制
– 最大16 位（65536 级）PWM 灰度控制
• 带190mΩRDS(ON) 的16 个线路扫描开关
• 超低功耗
3 说明
LP5891 是一款高度集成的共阴极 LED 矩阵驱动器，
具有 48 个恒流源和 16 个扫描 FET。LP5891 采用高
速rising 沿传输接口，可支持高器件数菊花链，同时尽
可能降低电磁干扰 (EMI)。内部 GCLK 速率范围为
40MHz 至 160MHz。该器件在工作期间还能实现 LED
开路/弱短路/短路检测和消除。
– 低至2.5V 的独立VCC
– 超低ICC（低至3.6 mA），具有50 MHz GCLK
– 智能省电模式，ICC 低至0.9 mA
• 内置SRAM 支持1 至64 路复用
– 单个器件可驱动48 × 16 个LED 或16 × 16 个
RGB 像素
器件信息
封装(1)
VQFN (76)
BGA (96)
封装尺寸（标称值）
9mm × 9mm
器件型号
LP5891
– 两个器件堆叠后可驱动96 × 32 个LED 或32 ×
32 个RGB 像素
– 三个器件堆叠后可驱动144 × 48 个LED 或48
× 48 个RGB 像素
– 四个器件堆叠后可驱动192 × 64 个LED 或64
× 64 个RGB 像素
6mm × 6mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
• 高速和低EMI 连续时钟串行接口(CCSI)
– 仅三条总线：SCLK/SIN/SOUT
– 外部50MHz（最大值）SCLK 具有rising 边传
输机制
LP5891 采用四器件可堆叠连接
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLDS269
LP5891
www.ti.com.cn
ZHCSQG6A –MARCH 2022 –REVISED MAY 2022
Table of Contents
7.5 Continuous Clock Series Interface............................25
7.6 PWM Grayscale Control........................................... 31
7.7 Register Maps...........................................................34
8 Application and Implementation..................................49
8.1 Application Information............................................. 49
8.2 Typical Application.................................................... 49
9 Power Supply Recommendations................................57
10 Layout...........................................................................58
10.1 Layout Guidelines................................................... 58
10.2 Layout Example...................................................... 58
11 Device and Documentation Support..........................62
11.1 Documentation Support ......................................... 62
11.2 接收文档更新通知................................................... 62
11.3 支持资源..................................................................62
11.4 Trademarks............................................................. 62
11.5 Electrostatic Discharge Caution..............................62
11.6 术语表..................................................................... 62
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................6
6.6 Timing Requirements..................................................9
6.7 Switching Characteristics............................................9
6.8 Typical Characteristics..............................................10
7 Detailed Description......................................................12
7.1 Overview...................................................................12
7.2 Functional Block Diagram.........................................12
7.3 Feature Description...................................................13
7.4 Device Functional Modes..........................................25
Information.................................................................... 63
4 Revision History
Changes from Revision * (March 2022) to Revision A (May 2022)
Page
• 首次公开发布...................................................................................................................................................... 1
• Updated the Stackable Mode section...............................................................................................................13
• Updated 图7-8 ................................................................................................................................................ 18
• Changed several field bits in the FC0 register table and Fields Description table............................................35
• Changed the name COLOR_R/G/B to LG_COLOR_R/G/B in the FC2 register table for better understanding...
39
• Changed the name of bit 7 to bit 0 in the FC3 register table for better understanding.....................................41
• Deleted some words in the SCAN_REV field description.................................................................................43
Copyright © 2022 Texas Instruments Incorporated
2
Submit Document Feedback
Product Folder Links: LP5891
LP5891
www.ti.com.cn
ZHCSQG6A –MARCH 2022 –REVISED MAY 2022
5 Pin Configuration and Functions
1
2
57
56
55
54
53
52
51
50
49
48
47
46
R0
G0
R15
G15
B15
R14
G14
B14
VG
3
B0
4
R1
5
G1
6
B1
7
GND
8
VCC
VR
VG
VB
VB
9
10
11
12
VR
R2
G2
GND
R13
G13
B13
13
45
B2
R3
G3
B3
R4
G4
14
15
16
17
18
44
43
42
41
40
R12
G12
B12
R11
G11
B11
19
39
B4
图5-1. LP5891 RRF Package 76-Pin VQFN With Exposed Thermal Pad Top View
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
L3
L4
L5
L6
L7
L8
L9
L10
L11
L12
L13
SOU
T
SCL
K
L2
L1
R1
G1
B1
B0
G0
R0
NC
SIN
NC
GND
GND
R14
G14
B14
R13
G13
R12
R11
L14
L15
GND
VG
L0
GND
GND
GND
GND
R7
GND
GND
GND
GND
B8
GND
GND
GND
GND
B9
GND
R15
G15
B15
B10
GND
VCC
VR
GND
R2
GND
R3
VG
G
H
J
G2
B2
G3
VB
VR
B3
VB
IREF
G4
R4
B13
G12
B12
K
L
B4
R6
B5
G6
B6
G7
B7
G8
R8
G9
R9
G10
R10
B11
G11
R5
G5
图5-2. LP5891 ZXL Package 96-Pin BGA Top View
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
3
Product Folder Links: LP5891
LP5891
www.ti.com.cn
ZHCSQG6A –MARCH 2022 –REVISED MAY 2022
表5-1. Pin Functions
PIN
I/O
DESCRIPTION
NAME
RRF NO.
ZXL NO.
Pin for setting the maximum constant-current value. Connecting an external
resistor between IREF and GND sets the maximum current for each constant-
current output channel. When this pin is connected directly to GND, all outputs
are forced off. The external resistor must be placed close to the device.
IREF
20
J1
I
VCC
VR
8
F1
I
I
I
I
Device power supply
9, 10
51, 50
49, 48
G1, H1
E11, F11
G11, H11
Red LED power supply
Green LED power supply
Blue LED power supply
VG
VB
1, 4, 11, 14, B5, B2,F2, F4,
17, 21, 24, J2, L1, K3, H5,
27, 32, 35, L6, L7, L8, L10,
38, 41, 44, K10, H10, E10,
R0-R15
G0-G15
B0-B15
O
O
O
Red LED constant-current output
Green LED constant-current output
Blue LED constant-current output
47, 54, 57
E8
2, 5, 12, 15, B4, C2, G2, G4,
18, 22, 25, K1, L2, K4, K5,
28, 31, 34, K6, K7, K8, L9,
37, 40, 43, K11, J10, F10,
46, 53, 56
F8
3, 6, 13, 16, B3, D2, H2, H4,
19, 23, 26, K2, L3, L4, L5,
29, 30, 33, H6, H7, H8, K9,
36, 39, 42, L11, J11, G10,
45, 52, 55
G8
76, 75, 74,
73, 72, 71,
70, 69, 68,
67, 66, 65,
64, 63, 62,
61
D1, C1, B1, A1,
A2, A3, A4, A5,
A6, A7, A8, A9,
A10, A11, B11,
C11
LINE0-
LINE15
O
Scan lines
SCLK
SIN
60
59
58
B9
B8
B7
I
I
Clock-signal input pin
Serial-data input pin
Serial data output pin
SOUT
O
C10, E1, E2,
D5, D6, D7, D8,
D10, D11,
E1,E2, E4, E5,
E6,E7, F5, F6,
F7,G5, G6, G7
GND
7
Power-ground reference
—
—
Thermal
pad
The thermal pad and the GND pin must be connected together on the board
—
—
Copyright © 2022 Texas Instruments Incorporated
4
Submit Document Feedback
Product Folder Links: LP5891
LP5891
www.ti.com.cn
ZHCSQG6A –MARCH 2022 –REVISED MAY 2022
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–40
–55
–55
MAX
6
UNIT
V
VCC
VR/G/B
6
V
Voltage
IREF, SCLK, SIN, SOUT
RX/GX/BX
6
V
6
V
LINE0 to LINE15
6
V
Operating junction temperature, TJ , LP5891RRFR and LP5891ZXLR
Operating junction temperature, TJ, LP5891MRRFR
Storage temperature, Tstg
150
150
150
°C
°C
°C
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
6.2 ESD Ratings
VALUE
±4000
±1000
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.5
NOM
MAX
5.5
UNIT
V
VCC
Device supply voltage
VLEDR/G/B LED supply voltage
2.5
5.5
V
VIH
VIL
High level logic input voltage (SCLK, SIN)
0.7 × VCC
V
Low level logic input voltage (SCLK, SIN)
High level logic output current (SOUT)
Low level logic output current (SOUT)
Constant output source current
0.3 × VCC
V
IOH
IOL
ICH
ILINE
mA
mA
mA
A
–2
2
0.2
0
20
2
Line scan switch load current
TA
TA
Ambient operating temperature (LP5891RRFR and LP5891ZXLR)
Ambient operating temperature (LP5891MRRFR)
85
°C
–40
–55
125
°C
6.4 Thermal Information
LP5891
THERMAL METRIC(1)
RRF (VQFN)
76 PINS
22.2
ZXL (BGA)
UNIT
96 PINS
33.5
18.6
11.7
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
10.7
RθJB
ψJT
Junction-to-board thermal resistance
7.2
Junction-to-top characterization parameter
Junction-to-board characterization parameter
0.1
0.3
7.1
11.6
ψJB
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
5
Product Folder Links: LP5891
LP5891
www.ti.com.cn
ZHCSQG6A –MARCH 2022 –REVISED MAY 2022
LP5891
THERMAL METRIC(1)
RRF (VQFN)
76 PINS
1.7
ZXL (BGA)
96 PINS
UNIT
RθJC(bot) Junction-to-case (bottom) thermal resistance
°C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
At VCC = VR = 2.8 V, VG/B = 3.8 V, TA = –40°C to +85°C for LP5891RRFR and LP5891ZXLR while TA = –40°C to +125°C
for LP5891MRRFR; Typical values are at TA = 25°C (unless otherwise specified)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
5.5
UNIT
VCC
Device supply voltage
Undervoltage restart
Undervoltage shutdown
2.5
V
V
V
VUVR
VUVF
VCC rising
2.3
VCC falling
2.0
Undervoltage shutdown
hysteresis
VUV(HYS)
0.1
0.9
V
SCLK/SIN = 10 MHz,
MPSM_EN=1bit, Matrix PSM enable,
internal GCLK off, GSn = 0000h, BC
= 2h, CCR/G/B = 63h, PS_EN= 1h,
VOUTn = floating, RIREF = 7.8 kΩ(In
intelligent power save mode)
mA
SCLK/SIN = 10 MHz, Standby
enable, internal GCLK off, GSn =
0000h, BC = 2h, CCR/G/B = 63h,
PS_EN= 1h, VOUTn = floating,
RIREF = 7.8 kΩ(In intelligent power
save mode)
0.9
3.6
mA
mA
SCLK/SIN = 10 MHz,
PSP_MOD=1bit, internal
GCLK=50MHz, GSn = 0000h, BC =
2h, CCR/G/B = 63h, PS_EN= 1h,
VOUTn = floating, RIREF = 7.8 kΩ(In
power save mode)
ICC
Device supply current
SCLK = 10 MHz, internal GCLK = 50
MHz, GSn = 1FFFh, BC = 2h,
CCR/G/B = 63h,VOUTn = floating,
RIREF = 7.8 kΩ, ICH = 2 mA
3.6
4.9
mA
mA
SCLK = 10 MHz, internal GCLK =
100 MHz, GSn = 1FFFh, BC = 2h,
CCR/G/B = 63h, VOUTn = floating,
RIREF = 7.8 kΩ, ICH = 2 mA
VR/G/B
VIH
LED supply voltage
2.5
5.5
V
V
High level input voltage (SCLK,
SIN)
0.7 × VCC
Low level input voltage (SCLK,
SIN)
VIL
0.3 × VCC
V
VOH
High level output voltage (SOUT)
VCC-0.4
-1
VCC
0.4
1
V
V
IOH = –2 mA at SOUT
VOL
Low level output voltage (SOUT) IOL = 2 mA at SOUT
ILOGIC
Logic pin current (SCLK, SIN)
SCLK/SIN = VCC or GND
VCC = 2.8 V, TA= 25°C
uA
Scan switches' on-state
resistance (LINE0 to LINE15)
RDS(ON)
190
0.8
mΩ
SCLK/SIN = GND, internal GCLK=
0MHz, GSn = 0000h, BC = 2h,
CCR/G/B = 63h, VOUTn = floating,
RIREF = 7.8 kΩ
VIREF
Reference voltage
V
Copyright © 2022 Texas Instruments Incorporated
6
Submit Document Feedback
Product Folder Links: LP5891
LP5891
www.ti.com.cn
ZHCSQG6A –MARCH 2022 –REVISED MAY 2022
6.5 Electrical Characteristics (continued)
At VCC = VR = 2.8 V, VG/B = 3.8 V, TA = –40°C to +85°C for LP5891RRFR and LP5891ZXLR while TA = –40°C to +125°C
for LP5891MRRFR; Typical values are at TA = 25°C (unless otherwise specified)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VLEDR/G/B ≥2.8 V, all channel
outputs on, output current at 1 mA
0.25
V
VLEDR/G/B ≥2.8 V, all channel
outputs on, output current at 5 mA
0.26
0.3
V
V
VLEDR/G/B ≥2.8 V, all channel
outputs on, output current at 10 mA
Channel knee voltage (R0-R15 /
G0-G15 / B0-B15)
VKNEE
VLEDR/G/B ≥2.8 V, IMAX = 1b, all
channel outputs on, output current at
15 mA
0.37
V
VLEDR/G/B ≥2.8 V, IMAX=1b, all
channel outputs on, output current at
20 mA
0.41
1
V
Channel leakage current (R0-
R15 / G0-G15 / B0-B15)
ICH(LKG)
Channel voltage at 0 V
uA
All CHn = on, BC = 00h, CC = 31h,
VOUTn = (VLED-1)V, RIREF = 19.05
kΩ(ICH = 0.2-mA target), TA = 25°C,
includes the VIREF tolerance, at
same color grouped outputs of R0-
R15 / G0-G15 / B0-B15
±1
±0.5
±0.5
±0.5
±0.5
±2.5
±1.5
±1.5
±2
%
%
%
%
%
All CHn = on, BC = 00h, CC = 7Dh,
VOUTn = (VLED-1)V, RIREF = 19.05
kΩ(ICH = 0.5-mA target), TA = 25°C,
includes the VIREF tolerance, at
same color grouped outputs of R0-
R15 / G0-G15 / B0-B15
All CHn = on, BC = 00h, CC = FBh,
VOUTn = (VLED-1)V, RIREF = 19.05
kΩ(ICH = 1-mA target), TA = 25°C,
includes the VIREF tolerance, at
same color grouped outputs of R0-
R15 / G0-G15 / B0-B15
Constant-current channel to
channel deviation (R0-R15 / G0-
G15 / B0-B15)(1)
ΔIERR(CC)
All CHn = on, BC = 2h, CC = FBh,
VOUTn = (VLED-1)V, RIREF = 7.8
kΩ(ICH = 5-mA target), TA = 25°C,
includes the VIREF tolerance, at
same color grouped outputs of R0-
R15 / G0-G15 / B0-B15
All CHn = on, BC = 6h, CC = A7h,
VOUTn = (VLED-1)V, RIREF = 7.8
kΩ(ICH = 10-mA target), TA = 25°C,
includes the VIREF tolerance, at
same color grouped outputs of R0-
R15 / G0-G15 / B0-B15
±2
All CHn = on, BC = 7h, CC = FBh,
IMAX=1b, VOUTn = (VLED-1)V,
RIREF = 6.8 kΩ(ICH = 20-mA target),
TA = 25°C, includes the VIREF
tolerance, at same color grouped
outputs of R0-R15 / G0-G15 / B0-
B15
±0.5
±2.5
%
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
7
Product Folder Links: LP5891
LP5891
www.ti.com.cn
ZHCSQG6A –MARCH 2022 –REVISED MAY 2022
6.5 Electrical Characteristics (continued)
At VCC = VR = 2.8 V, VG/B = 3.8 V, TA = –40°C to +85°C for LP5891RRFR and LP5891ZXLR while TA = –40°C to +125°C
for LP5891MRRFR; Typical values are at TA = 25°C (unless otherwise specified)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
All CHn = on, BC = 00h, CC = 31h,
VOUTn = (VLED-1)V, RIREF = 19.05
kΩ(ICH = 0.2-mA target), TA = 25°C,
includes the VIREF tolerance, at
same color grouped outputs of R0-
R15 / G0-G15 / B0-B15
±1
±2.5
%
All CHn = on, BC = 00h, CC = 7Dh,
VOUTn = (VLED-1)V, RIREF = 19.05
kΩ(ICH = 0.5-mA target), TA = 25°C,
includes the VIREF tolerance, at
same color grouped outputs of R0-
R15 / G0-G15 / B0-B15
±0.5
±0.5
±0.5
±0.5
±1.5
%
%
%
%
All CHn = on, BC = 00h, CC = FBh,
VOUTn = (VLED-1)V, RIREF = 19.05
kΩ(ICH = 1-mA target), TA = 25°C,
includes the VIREF tolerance, at
same color grouped outputs of R0-
R15 / G0-G15 / B0-B15
±1
Constant-current device to
device deviation (R0-R15 / G0-
G15 / B0-B15)(2)
ΔIERR(DD)
All CHn = on, BC = 2h, CC = FBh,
VOUTn = (VLED-1)V, RIREF = 7.8
kΩ(ICH = 5-mA target), TA = 25°C,
includes the VIREF tolerance, at
same color grouped outputs of R0-
R15 / G0-G15 / B0-B15
±1.5
All CHn = on, BC = 6h, CC = A7h,
VOUTn = (VLED-1)V, RIREF = 7.8
kΩ(ICH = 10-mA target), TA = 25°C,
includes the VIREF tolerance, at
same color grouped outputs of R0-
R15 / G0-G15 / B0-B15
±2
All CHn = on, BC = 7h, CC = FBh,
IMAX=1b, VOUTn = (VLED-1)V,
RIREF = 6.8 kΩ(ICH = 20-mA target),
TA = 25°C, includes the VIREF
tolerance, at same color grouped
outputs of R0-R15 / G0-G15 / B0-
B15
±0.5
±2
%
VLED = 2.5 to 5.5V, All CHn = on,
VOUTn = (VLED-1)V, at same color
grouped outputs of R0-R15 / G0-
G15 / B0-B15
Line regulation (R0-R15 / G0-
G15 / B0-B15)(3)
±1
±1
%/V
%/V
ΔIREG(LINE)
VOUTn = (VLED-1)V to (VLED-3)V,
VR=VG/B=VLED=3.8V, All CHn =
on, at same color grouped outputs of
R0-R15 / G0-G15 / B0-B15
Load regulation (R0-R15 / G0-
G15 / B0-B15)(4)
ΔIREG(LOAD)
TTSD
THYS
Thermal shutdown threshold
Thermal shutdown hysteresis
170
15
°C
°C
(1) The deviation of each output in same color group (OUTR0-15 or OUTG0-15 or OUTB0-15) from the average of same color group
+
:J
: ;
¿ % = N
F 1O × 100
+
:0 + +:1 + ® + +:14 + +:15
16
constant current. The deviation is calculated by the formula. (X = R or G or B, n = 0-15)
spacer
(2) The deviation of the average of constant-current in each color group from the ideal constant-current value. (X = R or G or B) :
Copyright © 2022 Texas Instruments Incorporated
8
Submit Document Feedback
Product Folder Links: LP5891
LP5891
www.ti.com.cn
ZHCSQG6A –MARCH 2022 –REVISED MAY 2022
+
:0
+ +:1 + ® + +:14 + +:15
16
F Ideal Output Current
: ;
¿ % =
N
O
× 100
Ideal Output Current
Ideal current is calculated by the following equation:
8
1 + %%_4(KN %%_) KN %%_$)
+4'(
+
=
× )#+0
×
+&'#._4(KN ) KN $)
($%)
4+4'(
256
spacer
(3) Line regulation is calculated by the following equation. (X = R or G or B, n = 0-15):
I
at V
LED
= 5.5 V − I at V = 2.5 V
Xn LED
Xn
100
5.5 V − 2.5 V
∆ %V =
×
I
at V = 2.5 V
LED
Xn
spacer
(4) Load regulation is calculated by the following equation. (X = R or G or B, n = 0-15):
I
at V = 1 V − I at V = 3 V
Xn Xn Xn
Xn
100
3 V − 1 V
∆ %V =
×
I
at V = 3 V
Xn
Xn
spacer
6.6 Timing Requirements
At VCC = VR = 2.8 V, VG/B = 3.8 V, TA = –40°C to +85°C for LP5891RRFR and LP5891ZXLR while TA = –40°C to +125°C
for LP5891MRRFR; Typical values are at TA = 25°C (unless otherwise specified)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fSCLK
tw(H0)
Clock frequency (SCLK)
High level pulse duration (SCLK)
50
MHz
9
ns
tw(L0)
tsu(0)
th(0)
Low level pulse duration (SCLK)
Set-up time
9
10
2
ns
ns
ns
SIN to SCLK↑
SCLK↑to SIN↑↓
Hold time
6.7 Switching Characteristics
At VCC = VR = 2.8 V, VG/B = 3.8 V, TA = –40°C to +85°C for LP5891RRFR and LP5891ZXLR while TA = –40°C to +125°C
for LP5891MRRFR; Typical values are at TA = 25°C (unless otherwise specified)
PARAMETER
Rise time (SOUT)
Fall time (SOUT)
TEST CONDITIONS
VCC = 3.3 V, CSOUT = 30 pF
VCC = 3.3 V, CSOUT = 30 pF
MIN
TYP
2
MAX
10
UNIT
ns
tr
tf
2
10
ns
SCLK↑to SOUT↑↓, full
temperature, CSOUT = 30 pF
tpd(0)
Propagation delay
3.5
14.2
ns
(1). Input pulse rise and fall time is 2 ns typically.
图6-1. Timing and Switching Diagram
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
9
Product Folder Links: LP5891
LP5891
www.ti.com.cn
ZHCSQG6A –MARCH 2022 –REVISED MAY 2022
6.8 Typical Characteristics
0.016
0.014
0.012
0.01
0.016
0.014
0.012
0.01
0.2 mA
1 mA
5 mA
10 mA
15 mA
0.2 mA
1 mA
5mA
10 mA
15 mA
0.008
0.006
0.004
0.002
0
0.008
0.006
0.004
0.002
0
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
VLED - VCH (V)
VLED - VCH (V)
Vcc = 2.8 V
图6-2. Channel Current vs (VLED-Vchannel) Voltage
Vcc = 5.5 V
图6-3. Channel Current vs (VLED-Vchannel) Voltage
1.7
11
-55oC
-40oC
25oC
10
9
8
7
6
5
4
3
2
1
0
1.1
0.5
85oC
125oC
-0.1
-0.7
125oC Min
85oC Min
25oC Min
-40oC Min
-55oC Min
125oC Max
85oC Max
25oC Max
-40oC Max
-55oC Max
-1.3
-1.9
-2.5
0
2
4
6
8
10
12
14
16
18
20
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
Output Current (mA)
VLED - VCH (V)
图6-5. Channel to Channel Accuracy vs Output Current
图6-4. Channel Current vs. (VLED-Vchannel) Voltage
0.016
0.012
0.011
0.01
0.2 mA, BC = 00h
1 mA, BC = 02h
5 mA, BC = 02h
10 mA, BC = 06h
15 mA, BC = 06h
0.014
0.012
0.01
0.009
0.008
0.007
0.006
0.005
0.004
0.003
0.008
0.006
0.004
0.002
0
0
30
60
90
120 150 180 210 240 270
40
60
80
100
120
140
160
180
Color Control Code (Decimal)
GCLK Frequency (MHz)
图6-6. Color Control Code vs Output Current
图6-7. Icc Current vs GCLK Frequency
Copyright © 2022 Texas Instruments Incorporated
10
Submit Document Feedback
Product Folder Links: LP5891
LP5891
www.ti.com.cn
ZHCSQG6A –MARCH 2022 –REVISED MAY 2022
6.8 Typical Characteristics (continued)
4.68
4.66
4.64
4.62
4.6
4.58
4.56
4.54
4.52
2.4 2.6 2.8
3
3.2 3.4 3.6 3.8
Vcc Voltage (V)
4
4.2 4.4 4.6
GCLK = 80 MHz
图6-8. Icc Current vs Vcc Voltage
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
11
Product Folder Links: LP5891
LP5891
www.ti.com.cn
ZHCSQG6A –MARCH 2022 –REVISED MAY 2022
7 Detailed Description
7.1 Overview
The LP5891 is a highly integrated RGB LED driver with 48 constant current sources and 16 scanning FETs. A
single LP5891 is capable of driving 16 × 16 RGB LED pixels while stacking four LP5891 devices can drive 64 ×
64 RGB LED pixels. To achieve low power consumption, the device supports separated power supplies for the
red, green, and blue LEDs by its common cathode structure. Furthermore, the operation power of the LP5891 is
significantly reduced by ultra-low operation voltage range (VCC down to 2.5 V) and ultra-low operation current
(ICC down to 3.6 mA).
The LP5891 supports 0.2 mA to 20 mA per channel with typical 0.5% channel-to-channel current deviation and
typical 0.5% device-to-device current deviation. The DC current value of all 48 channels is set by an external
IREF resistor and can be adjusted by the 8-step global brightness control (BC) and the 256-step per-color group
brightness control (CC_R/CC_G/CC_B).
The LP5891 implements a high speed rising-edge transmission interface to support high device count daisy-
chained and high refresh rate while minimizing electrical-magnetic interference (EMI). The LP5891 supports up
to 50-MHz SCLK (external) and up to 160-MHz GCLK (internal).
The LP5891 also implements LED open, weak-short, and short detections and can also report this information
out to the accompanying digital processor.
7.2 Functional Block Diagram
VB VG VR
VCC
Internal LDO
Bandgap
TSD
Power Save
R0
G0
B0
UVLO
IREF
GND
3-Bits
Brightness control
R/G/B 8-Bits
Color control
Channel
Drivers
Channel
Control
R15
G15
Frequency
Multiplier
Frame
Control
Digital
Core
SCLK
SIN
B15
Line
Control
Pre-discharge
LED Short Detection
SRAM
Low Grayscale
Compensation
LED Open Detection
Line Drivers
SOUT
Line Clamp
GND
LINE0
LINE15
Copyright © 2022 Texas Instruments Incorporated
12
Submit Document Feedback
Product Folder Links: LP5891
LP5891
www.ti.com.cn
ZHCSQG6A –MARCH 2022 –REVISED MAY 2022
7.3 Feature Description
7.3.1 Independent and Stackable Mode
The LP5891 can operate in two different modes: independent or stackable. In independent mode, a single
LP5891 can drive a 16 × 16 RGB LED matrix, while in stackable mode, up to four LP5891 devices can be
stacked together, which means the line switches of one device can be shared to the others. Stacking three
LP5891 devices can drive a 48 × 48 RGB LED matrix while stacking four LP5891 devices can drive a 64 × 64
RGB matrix. The mode can be configured by the MOD_SIZE (see FC2 for more details).
7.3.1.1 Independent Mode
图 7-1 shows an implementation of a 16 × 32 RGB LED matrix using two LP5891 devices in independent mode.
Each device is responsible for its own 16 ×16 RGB LED matrix, which means that all the data for section A is
stored in device 1 and the data for section B is stored in device 2.
图7-1. Two Devices in Independent Mode
The unused line must be assigned to the last several lines of the device. For example, if there are only 14
scanning lines, then the two unused lines must be assigned to 1_LS14 and 1_LS15.
7.3.1.2 Stackable Mode
While operating the LP5891 in stackable mode, as shown in below table.
表7-1. Stackable Mode
Mode
Mode1
Mode2
Mode3
Mode4
Mode5
Mode6
Mode7
Mode8
Matrix Size
16x32
Register Value
000b
Scan Sequence
D1, D2 independent
D1->D2
32x32
001b
48x48
010b
D1->D2->D3
48x48
011b
D1->D3->D2
48x64
100b
D1->D2->D3
48x64
101b
D1->D3->D2
64x64
110b
D1->D2->D3->D4
D1->D4->D2->D3
64x64
111b
图 7-2 device 2 needs to be rotated 180o relative to device 1. This action allows the position of line switches to
be near the center column of the LED matrix for better routing. For device 1, the lines connect sequentially (line
switch 0 connected to scan line 1). However on device 2, it is connected in reverse order, with the 16th scan line
is connected to line switch 15 and the 32nd scan line is connected to line switch 0.
图 7-2 shows the connection between two LP5891 devices in stackable mode driving 32 × 32 RGB LED pixels.
The MOD_SIZE must be configured to 001b. Device 1 supplies 16 line switches for the first 16 scan line, and
device 2 supplies 16 line switches for scan line 17-32. The data for matrix sections A and C are stored in device
1, while matrix sections B and D data are stored in device 2.
To make sure the scanning sequence is still from 1st line to 32nd line, the scan line switching order of the second
device must be reversed, which can be configured by the SCAN_REV (see FC4 for more details).
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
13
Product Folder Links: LP5891
LP5891
www.ti.com.cn
ZHCSQG6A –MARCH 2022 –REVISED MAY 2022
Physical Line0
A
B
1_LS0
Device1
1_LS15
Physical Line15
Physical Line16
C
D
2_LS15
Device2
2_LS0
Physical Line31
图7-2. Mode2 Diagram
图7-3. Mode3 and Mode4 Diagram
图7-4. Mode5 and Mode6 Diagram
Copyright © 2022 Texas Instruments Incorporated
14
Submit Document Feedback
Product Folder Links: LP5891
LP5891
www.ti.com.cn
ZHCSQG6A –MARCH 2022 –REVISED MAY 2022
图7-5. Mode7 and Mode8 Diagram
When two or more LP5891 devices are used in stackable mode, if there are unused line switches, these unused
line switches must be the last line switches of the first or the second device. For example, if there are only 30
scanning lines, and if,
SCAN_REV = '0'b, the unused line switches can be either of the below,
• 1_LS14, 1_LS15
• 2_LS14, 2_LS15
SCAN_REV = '1'b, the unused line switches can be either of below,
• 1_LS14, 1_LS15
• 2_LS1, 2_LS0
The unused line switches must be 2_LS14, 2_LS15 if SCAN_REV = '0'b, or 2_LS1, 2_LS0 if SCAN_REV = '1'b.
7.3.2 Current Setting
7.3.2.1 Brightness Control (BC) Function
The LP5891 device is able to adjust the output current of all constant-current outputs simultaneously. This
function is called global brightness control (BC). The global BC for all outputs is programmed with a 3-bit
register, thus all output currents can be adjusted in eight steps for a given current-programming resistor, RIREF
.
When the 3-bit BC register changes, the gain of output current, GAINBC changes as 表7-2 below.
表7-2. Current Gain Versus BC Code
BC Register (BC)
000b
Current Gain (GAINBC)
24.17
30.57
001b
010b
49.49
011b (default)
100b
86.61
103.94
129.92
148.48
101b
110b
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
15
Product Folder Links: LP5891
LP5891
www.ti.com.cn
ZHCSQG6A –MARCH 2022 –REVISED MAY 2022
表7-2. Current Gain Versus BC Code (continued)
BC Register (BC)
Current Gain (GAINBC)
111b
173.23
The maximum output current per channel, IOUTSET, is determined by resistor RIREF, and the GAINBC. The voltage
on IREF is typically 0.8 V. RIREF can be calculated by 方程式 1 below. For noise immunity purpose, suggest
R
IREF < 40 kΩ.
8
+4'((8)
8
+4'((8)
4+4'( (G×) =
=
× )#+0($%)
++4'( (I#)
+1765'6 (I#)
(1)
7.3.2.2 Color Brightness Control (CC) Function
The LP5891 device is able to adjust the output current of each of the three color groups R0-R15, G0-G15, and
B0-B15 separately. This function is called color brightness control (CC). For each color, it has 8-bit data register,
CC_R, CC_G, or CC_B. Thus, all color group output currents can be adjusted in 256 steps from 0% to 100% of
the maximum output current, IOUTSET. The output current of each color, IOUT_R (or G or B) can be calculated by
Equation 2 below.
1 + %%_4(KN %%_) KN %%_$)
+
= +1765'6 ×
176_4(KN ) KN $)
256
(2)
Table 表7-3 shows the CC data versus the constant-current against IOUTSET
:
表7-3. CC Data vs Current Ratio
CC Register (CC_R or CC_G or
Ratio of IOUTSET
CC_B)
0000 0000b
0000 0001b
...
1/256
2/256
...
0.39%
0.78%
...
0111 1111b (default)
...
128/256
...
50%
...
1111 1110b
1111 1111b
255/256
256/256
99.61%
100%
7.3.2.3 Choosing BC/CC for a Different Application
BC is mainly used for global brightness adjustment to adapt to ambient brightness, such as between day and
night, indoor and outdoor.
• Suggested BC is 3h or 4h, which is in the middle of the range, allowing flexible changes in brightness up and
down.
• If the current of one color group (usually R LEDs) is close to the output maximum current (10 mA or 20 mA),
to prevent the constant output current from exceeding the upper limit in case a larger BC code is input
accidentally, choose the maximum BC value, 7h.
• If the current of one color group (usually B LEDs) is close to the output minimum current (0.2 mA), to prevent
the constant output current from exceeding the lower limit in case a lower BC code is input accidentally,
choose the minimum BC code, 0h.
CC can be used to fine tune the brightness in 256 steps. This is suitable for white balance adjustment between
RGB color group. To get a pure white color, the general requirement for the luminous intensity ratio of R, G, B
LED is 5:3:2. Depending on the characteristics of the LED (Electro-Optical conversion efficiency), the current
ratio of R, G, B LED is much different from this ratio. Usually, the Red LED needs the largest current. Choose
255d (the maximum value) CC code for the color group that needs the largest initial current, then choose proper
CC code for the other two color groups according to the current ratio requirement of the LED used.
Copyright © 2022 Texas Instruments Incorporated
16
Submit Document Feedback
Product Folder Links: LP5891
LP5891
www.ti.com.cn
ZHCSQG6A –MARCH 2022 –REVISED MAY 2022
7.3.3 Frequency Multiplier
The LP5891 has an internal frequency multiplier to generate the GCLK by SCLK. The GCLK frequency can be
configured by FREQ_MOD (See FC0 for more details) and FREQ_MUL (see FC0 for more details ) from 40 MHz
to 160 MHz. As 图 7-6 shows, if the GCLK frequency is not higher than 80 MHz, the GCLK_MOD is set to 0 to
disable the bypass switch (enable the ½ divider), while the GCLK frequency is higher than 80 MHz, the
GCLK_MOD is set to 1 to enable the bypass switch (disable the ½ divider).
GCLK_MUL
GCLK_MOD
SCLK
GCLK
1/2
图7-6. Frequency Multiplier Block Diagram
7.3.4 Line Transitioning Sequence
The LP5891 defines a timing sequence of scan line transition, shown as 图 7-7. T_SW is the total transitioning
time. T_SW is broken up into four intervals: T0 is the time interval between the end of PWM time in current
segment and the beginning of channel pre-discharge, T1 is the time interval between the beginning of the
channel pre-discharge and the beginning of current line OFF, T2 is the time interval that the beginning of current
line OFF and the beginning of next line ON, T3 is the time interval of the beginning of next line ON and the
beginning of PWM time in next segment.
图7-7. Line Transitioning Sequence
The line switch time T_SW equals to T0 + T1 + T2 + T3. T_SW can be configured by the LINE_SWT (see FC1
register bit 40-37 in 表7-8).
表 7-4 is the relation between LINE_SWT bits and the line switch time (GCLK numbers) with different internal
GCLK frequency.
表7-4. Line Switch Time
LINE_SW
T
GCLK
Numbers
T_SW (us, 40
MHZ GCLK)
T_SW (us, 60 MHZ T_SW (us, 100 MHZ T_SW (us, 120 MHZ T_SW (us, 160 MHZ
GCLK)
0.7515
1.002
1.503
2.004
2.505
GCLK)
0.45
0.6
GCLK)
0.3735
0.498
0.747
0.996
1.245
GCLK)
0.2835
0.378
0.567
0.756
0.945
0000b
0001b
0010b
0011b
0100b
45
60
1.125
1.5
90
2.25
3
0.9
120
150
1.2
3.75
1.5
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
17
Product Folder Links: LP5891
LP5891
www.ti.com.cn
ZHCSQG6A –MARCH 2022 –REVISED MAY 2022
表7-4. Line Switch Time (continued)
LINE_SW
T
GCLK
Numbers
T_SW (us, 40
MHZ GCLK)
T_SW (us, 60 MHZ T_SW (us, 100 MHZ T_SW (us, 120 MHZ T_SW (us, 160 MHZ
GCLK)
3.006
3.507
4.008
4.509
5.01
GCLK)
1.8
2.1
2.4
2.7
3
GCLK)
1.494
1.743
1.992
2.241
2.49
GCLK)
1.134
1.323
1.512
1.701
1.89
0101b
0110b
0111b
1000b
1001b
1010b
1011b
1100b
1101b
1110b
1111b
180
210
240
270
300
330
360
390
420
450
480
4.5
5.25
6
6.75
7.5
8.25
9
5.511
6.012
6.513
7.014
7.515
8.016
3.3
3.6
3.9
4.2
4.5
4.8
2.739
2.988
3.237
3.486
3.735
3.984
2.079
2.268
2.457
2.646
2.835
3.024
9.75
10.5
11.25
12
7.3.5 Protections and Diagnostics
7.3.5.1 Thermal Shutdown Protection
The thermal shutdown (TSD) function turns off all IC constant-current outputs when the junction temperature (TJ)
exceeds 170°C (typical). The function resumes normal operation when TJ falls below 155°C (typical).
7.3.5.2 IREF Resistor Short Protection
The IREF resistor short protection (ISP) function prevents unwanted large currents from flowing through the
constant-current output when the IREF resistor is shorted accidently. The LP5891 device turns off all output
channels when the IREF pin voltage is lower than 0.19 V (typical). When the IREF pin voltage goes higher than
0.325 V (typical), the LP5891 device resumes normal operation.
7.3.5.3 LED Open Load Detection and Removal
7.3.5.3.1 LED Open Detection
The LED Open Detection (LOD) function detects faults caused by an open circuit in any LED, or a short from
OUTn to VLED with low impedance. This function was realized by comparing the OUTn voltage to the LOD
detection threshold voltage level set by LODVTH_R/LODVTH_G/LODVTH_B (See FC3 for more details). If the
OUTn voltage is higher than the programmed voltage, the corresponding output LOD bit is set to 1 to indicate an
open LED. Otherwise, the output of that LOD bit is 0. LOD data output by the detection circuit are valid only
during the OUTn turning on period.
图7-8 shows the equivalent circuit of LED open detection.
Copyright © 2022 Texas Instruments Incorporated
18
Submit Document Feedback
Product Folder Links: LP5891
LP5891
www.ti.com.cn
ZHCSQG6A –MARCH 2022 –REVISED MAY 2022
VG
LODVTH_G
VB
LODVTH_B
VR
LODVTH_R
VB
VG
LODVTH_G
VR
LODVTH_R
LODVTH_B
+
+
+
+
+
+
–
–
–
–
–
–
Channel
Control
Channel
Control
Channel
Control
Channel
Control
Channel
Control
Channel
Control
LOD Detection
0b - Normal
1b - LED-open
48-bit LOD Data
READLOD
48-bit
LSB
MSB
SCLK
SIN
48-bit Common Shift Register
SOUT
图7-8. LED Open Detection Circuit
The LED open detection function records the position of the open LED, which contains the scan line number and
relevant channel number. The scan line order is stored LOD_LINE_WARN register (see FC16, FC17 for more
details), and the channel number is latched into the internal 48-bit LOD data register (see FC20 for more details)
at the end of each segment. 图7-9 shows the bit arrangement of the LOD data register.
图7-9. Bit Arrangement in LOD Data Register
7.3.5.3.2 Read LED Open Information
The LOD readback function must be enabled before read LED open information. This function is enabled by
LOD_LSD_RB (see FC3 for more details).
图 7-10 shows the steps to read LED open information. Wait at least one sub-period time between Step2 and
Step3 command.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
19
Product Folder Links: LP5891
LP5891
www.ti.com.cn
ZHCSQG6A –MARCH 2022 –REVISED MAY 2022
图7-10. Steps to Read LED Open Information
7.3.5.3.3 LED Open Caterpillar Removal
图 7-11 shows the caterpillar issue caused by open LED. Suppose the LED0-1 is an open LED. When line 0 is
chosen and the OUT1 is turned on, the OUT1 voltage is forced to approach to VLED because of the broken path
of the current source. However, the voltage of the un-chosen lines are below the Vclamp which is much lower
than VLED, causing all LEDs which connect to the channel OUT1, light unwanted.
Copyright © 2022 Texas Instruments Incorporated
20
Submit Document Feedback
Product Folder Links: LP5891
LP5891
www.ti.com.cn
ZHCSQG6A –MARCH 2022 –REVISED MAY 2022
图7-11. LED Open Caterpillar
The LP5891 implements circuits that can eliminate the caterpillar issue caused by open LEDs. The LED open
caterpillar removal function is configured by LOD_RM_EN (see FC0 for more details). When LOD_RM_EN is set
to 1b, the caterpillar removal function is enabled. The corresponding channel OUTn is turned off when scanning
to line with open LED, The caterpillar issue is eliminated until device resets or LOD_RM_EN is set to 0b.
The internal caterpillar elimination circuit can handle a maximum of three lines that have open LEDs fault
condition. If there are open LEDs located in three or fewer lines, the LP5891 is able to handle the open LEDs all
in these lines. If there are open LEDs in more than three lines, the caterpillar issue is solved for the lines where
the first three open LEDs were detected, but the open LEDs in the fourth and subsequent lines still cause the
caterpillar issue.
7.3.5.4 LED Short and Weak Short Circuitry Detection and Removal
7.3.5.4.1 LED Short/Weak Short Detection
The LED short detection (LSD) function detects faults caused by a short circuit in any LED. This function was
realized by comparing the OUTn voltage to the LSD threshold voltage. If the OUTn voltage is lower than the
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
21
Product Folder Links: LP5891
LP5891
www.ti.com.cn
ZHCSQG6A –MARCH 2022 –REVISED MAY 2022
threshold voltage, the corresponding output LSD bit is set to 1 to indicate an short LED, otherwise, the output of
that LSD bit is 0. LSD data output by the detection circuit are valid only during the OUTn turning on period.
LSD weak short can be detected by adjusting threshold voltage, which level is set by LSDVTH_R/LSDVTH_G/
LSDVTH_B (See FC3 for more details).
图7-12 shows the equivalent circuit of LED short detection.
VG
VB
VR
VB
VG
VR
LSDVTH_G
LSDVTH_B
LSDVTH_R
LSDVTH_G
LSDVTH_B
LSDVTH_R
+
+
+
+
+
+
–
–
–
–
–
–
Channel
Control
Channel
Control
Channel
Control
Channel
Control
Channel
Control
Channel
Control
LSD Detection
0b - Normal
1b - LED-short
48-bit LSD Data
READLSD
48-bit
LSB
MSB
SCLK
SIN
48-bit Common Shift Register
SOUT
图7-12. LED Short Detection Circuit
The LED short detection function records the position of the short LED, which contains the scan line order and
relevant channel number. The scan line order is stored LSD_LINE_WARN register (see FC18, FC19 for more
details), and the channel number is latched into the internal 48-bit LSD data register (see FC21 for more details)
at the end of each segment. 图7-13 shows the bit arrangement of the LSD data register.
图7-13. Bit Arrangement in the LSD Data Register
7.3.5.4.2 Read LED Short Information
The LSD readback function must be enabled before reading LED Short information. This function is enabled by
LOD_LSD_RB (see FC3 for more details).
Copyright © 2022 Texas Instruments Incorporated
22
Submit Document Feedback
Product Folder Links: LP5891
LP5891
www.ti.com.cn
ZHCSQG6A –MARCH 2022 –REVISED MAY 2022
图 7-14 shows the steps to read LED Short information. Wait at least one sub-period time between Step2 and
Step3 command.
图7-14. Steps to Read LED Short Information
7.3.5.4.3 LSD Caterpillar Removal
图 7-15 shows the LSD caterpillar issue caused by short LED. Suppose the LED0-1 is a short LED. When it
scans to the line1 and the OUT1 is turned off, the OUT1 voltage is the same with scan line0 voltage because of
the short path of the LED0-1. At this time, there is a current path from the line0 to the GND through the LED1-1
and SW1-1, which causes LED1-1 light unwanted.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
23
Product Folder Links: LP5891
LP5891
www.ti.com.cn
ZHCSQG6A –MARCH 2022 –REVISED MAY 2022
图7-15. LED Short Caterpillar
The LP5891 device implements internal circuits that can eliminate the caterpillar issue by short LEDs. As is
shown in 图 7-15, the LED short caterpillar is caused by the voltage of the Vclamp on the line. So it can be
solved by adjusting the LSD_RM_EN (see FC3 for more details) to let the voltage drop of the LED1-1 be smaller
than LED forward voltage.
Copyright © 2022 Texas Instruments Incorporated
24
Submit Document Feedback
Product Folder Links: LP5891
LP5891
www.ti.com.cn
ZHCSQG6A –MARCH 2022 –REVISED MAY 2022
7.4 Device Functional Modes
The device functional modes are shown in 图7-16.
图7-16. Functional Modes
• Initialization: The device enters into Initialization when Vcc goes down to UVLO voltage. In this mode, all the
registers are reset. Entry can also be from any state.
• Normal: The device enters the normal mode when Vcc is higher than UVLO threshold. The display process
is shown as below in normal mode.
• Power saving: The device automatically enters and gets out from the power save mode when it detects the
condition PSin and PSout. In this mode, all channels turn off. PSin: after the device detects that the display
data of the next frame all equal to zero, it enters in to power save mode when the VSYNC comes. PSout:
after the device detects that there is non-zero display data of the next frame, it gets out from power save
mode immediately.
• IREF resistor short protection: The device automatically enters and gets out from the IREF resistor short
protection mode when it detects the condition ISPin and ISPout. In this mode, all channels turn off. ISPin: the
device detects that the reference voltage is smaller than 0.195 V ISPout: the device detects that the
reference voltage is larger than 0.325 V.
• Thermal shutdown: The device automatically enters and gets out from the thermal shutdown mode when it
detects the condition TSDin and TSDout. In this mode, all channels turn off. TSDin: the device detects that
the junction temperature exceeds 170°C TSDout: the device detects that the junction temperature is below
155°C.
7.5 Continuous Clock Series Interface
The continuous clock series interface (CCSI) provides access to the programmable functions and registers,
SRAM data of the device. The interface contains two input digital pins, they are the serial data input (SIN) and
serial clock (SCLK). Moreover, there is an another wire called serial data output (SOUT) as the output digital
signal of the device. The SIN is set to HIGH when device is in idle status and the SCLK must be existent and
continuous all the time considering as the clock source of internal Frequency Multiplier, the SOUT is used to
transmit the data or read the data of internal registers.
This protocol can support up to 32 devices cascaded in a data chain. The devices receive the chip index
command after power up. The chip index command configured addresses of the devices from 0x00 up to 0x1F
according to the sequence that receives the command. Then the controller can communicate with all the devices
through the broadcast way or particular device through non-broadcast way.
The broadcast is mainly used to transmit function control commands. All the devices in a data chain receive the
same data in this way. The non-broadcast is mainly used to transmit function control commands or display data,
and each device receives its own data in this way. These two ways are distinguished by the command
identification.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
25
Product Folder Links: LP5891
LP5891
www.ti.com.cn
ZHCSQG6A –MARCH 2022 –REVISED MAY 2022
7.5.1 Data Validity
The data on DIN wire must be stable at rising edges of the SCLK in transmission.
7.5.2 CCSI Frame Format
图7-17 defines the format of the command and data transmission. There are four states in one frame.
• IDLE: SCLK is always existent and continuous, and DIN is always HIGH.
• START: DIN changes from HIGH to LOW after the IDLE states.
• DATA:
– Head_bytes: It is the command identifier, contains one 16-bit data and one check bit. It can be WRITE
COMMAND ID or READ COMMAND ID (see Register Maps for more details).
– Data_bytes_N: The Nth data-bytes, contains 3 × 17-bit data, each 17-bit data contains one 16-bit data
and one check bit. N is the number of devices cascaded in a data chain.
• END: The device recognizes continuous 18-bit HIGH on DIN, then returns to IDLE state.
• CHECK BIT: The check bit (17th bit) value is the NOT of 16th bit value to avoid continuous 18-bit HIGH (to
distinguish with END).
图7-17. CCSI Frame
The IDLE state is not necessary, which means the START state of the next frame can connect to the END state
of the current frame.
7.5.3 Write Command
Take m devices cascaded in a data chain for example.
7.5.3.1 Chip Index Write Command
The chip index is used to set the identification of the device cascaded in a data chain. When the first device
receives the chip index command Head_bytes1, it sets the current address to 00h and meanwhile change the
chip index command Head_bytes2, then sends to the next device. When the device receives the Head_bytes2, it
sets the address to 01h and meanwhile changes the chip index command Head_bytes3, then sends to the next
device, likewise, all the cascaded devices get their unique identifications.
SOUT
SCLK
Controller
SIN
Device_1
Device_...
Device_m
ST Head_bytes1
END
ST Head_bytes...
END
ST Head_bytesm
END
图7-18. Chip Index Write Command
Copyright © 2022 Texas Instruments Incorporated
26
Submit Document Feedback
Product Folder Links: LP5891
LP5891
www.ti.com.cn
ZHCSQG6A –MARCH 2022 –REVISED MAY 2022
7.5.3.2 VSYNC Write Command
The VSYNC is used to sync the display of each frame for the devices in a cascaded chain. this command is a
write-only command. The devices receive VSYNC command one time from the controller in each frame, and the
VSYNC command needs to be active for all devices at the same time.
Because some devices receive the command earlier in the data chain, they need to wait until the last device
receives the command, then all the devices are active at that time. To realize such function, each device needs
to know its delay time from receiving VSYNC command to enabling VSYNC. The device uses some register bits
to restore the device number in a data chain. This number minuses the device identification, and the result is the
delay time of the device.
Because the sync function has been done by the device, the controller only must send the VSYNC command to
the first device in a data chain.
SOUT
SCLK
Controller
SIN
Device_1
Device_...
Device_m
ST Head_bytes
END
ST Head_bytes
END
ST Head_bytes
END
ST Head_bytes
END
图7-19. VSYNC Write Command
7.5.3.3 MPSM Write Command
The MPSM command is used to control the intelligent power save mode of devices in the same matrix. The
device detects all zero data in a stackable module and receives MPSM command in current frame, then when
VSYNC command comes, all devices in the same matrix turn off. After the device detects that there is non-zero
display data of the next frame, it gets out from intelligent power save mode until MSPM command comes in
current frame.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
27
Product Folder Links: LP5891
LP5891
www.ti.com.cn
ZHCSQG6A –MARCH 2022 –REVISED MAY 2022
图7-20. Design Procedure for MPSM Command
7.5.3.4 Standby Clear and Enable Command
Standby clear command and standby enable command are used to control intelligent power save mode of
devices in the same daisy chain. When the device receives standby enable command, it enters to intelligent
power save mode right away and does not have to wait for other devices in a module or daisy chain. After the
device receives standby enable command, it exits from intelligent power save mode immediately and does not
wait for other devices in a module or daisy chain.
7.5.3.5 Soft_Reset Command
The Soft_Reset Command is used to reset all the function registers to the default value, except for SRAM data.
The format of this command is the same with VSYNC shown as VSYNC Write Command. The difference is the
headbytes.
Copyright © 2022 Texas Instruments Incorporated
28
Submit Document Feedback
Product Folder Links: LP5891
LP5891
www.ti.com.cn
ZHCSQG6A –MARCH 2022 –REVISED MAY 2022
7.5.3.6 Data Write Command
The device can receive the function control with broadcast and non-broadcast way, which depends on the
configuration of the devices. If the cascaded devices have the same configuration, broadcast is used,. If the
cascaded devices have the different configurations, non-broadcast is used. It is always the MSB transmitted first
and the LSB transmitted last. For 48-bits RGB data, the Blue data must be transmitted first, then the Green, and
last the Red data.
For broadcast, the devices receive the same data, when devices recognize the broadcast command, they copy
the data to their internal registers. Generally, it is used for write FC0-FC13 command, LOD/LSD.
图7-21. Data Write Command with Broadcast
图7-22 shows the time diagram of the Data Write Command with Broadcast.
图7-22. Data Write Command with Broadcast (Timing Diagram)
For non-broadcast, the devices receive the different data, the controller prepares the data as the figure shows.
One pixel data is written to the corresponding device in each command. When the first device receives the END,
it cuts off the last 51-bit (3 × 17-bit) data before the END, and the left are shifted out from SDO to the second
device. Similarly, when the second device receives the END bytes from the former device, it cuts off the last 51-
bit (3 × 17-bit) data before the END, and the left are shifted out to the next device. Generally, it is used for write
SRAM command (WRTGS). Details for how to write a frame data into memory bank can be found in Write a
Frame Data into Memory Book.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
29
Product Folder Links: LP5891
LP5891
www.ti.com.cn
ZHCSQG6A –MARCH 2022 –REVISED MAY 2022
图7-23. Data Write Command with Non-Broadcast
图7-24 shows the time diagram of the Data Write Command with Non-Broadcast.
图7-24. Data Write Command with Non-Broadcast (Timing Diagram)
7.5.4 Read Command
The controller sends the read command. When the first device receives this command, it inserts its 48-bit data
before End_bytes, and meanwhile shifts out to the second device. When the second device receives this
command, it inserts its 48-bit data before End_bytes and meanwhile shifts out to the third device. The data of all
the device are shifted out from the last device SOUT with this flow. The MSB is always transmitted first and the
LSB transmitted last.
图7-25. Data Read Command
Copyright © 2022 Texas Instruments Incorporated
30
Submit Document Feedback
Product Folder Links: LP5891
LP5891
www.ti.com.cn
ZHCSQG6A –MARCH 2022 –REVISED MAY 2022
7.6 PWM Grayscale Control
7.6.1 Grayscale Data Storage and Display
7.6.1.1 Memory Structure Overview
The LP5891 implements a display memory unit to achieve high refresh rate and high contrast ratio in an LED
display products. The internal display memory unit is divided into two BANKs: BANK A and BANK B. During the
normal operation, one BANK is selected to display the data of current frame, another is used to restore the data
of next frame. The BANK switcher is controlled by the BANK_SEL bit, which is an internal flag register bit.
After power on, BANK_SEL is initialized to 0, and BANK A is selected to restore the data of next frame.
Meanwhile, the data in BANK B is read out for display. When one frame has elapsed, the controller sends the
vertical synchronization (VSYNC) command to start the next frame, the BANK_SEL bit value is toggled and the
selection of the two BANKs reverses. Repeat this operation until all the frame images are displayed.
With this method, the LP5891 device can display the current frame image at a very high refresh rate. See 图
7-26 for more details about the BANK-selection exchange operation.
图7-26. Bank Selection Exchange Operation
7.6.1.2 Details of Memory Bank
Each memory BANK contains the frame-image grayscale data of all the 64 lines. Each line comprises sixteen
48-bit-width memory units. Each memory unit contains the grayscale data of the corresponding R/G/B channels.
Depending on the number of scan lines set in SCAN_NUM (FC0 bit 21 to bit 16), the total number of memory
units that must be written in one BANK is: 48 × the number of scan lines. For example, if the number of scan
lines is set to 64, then 3072 (64 × 48 = 3072) memory units must be written during each frame period.
图7-27 shows the detailed memory structure of the LP5891 device.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
31
Product Folder Links: LP5891
LP5891
www.ti.com.cn
ZHCSQG6A –MARCH 2022 –REVISED MAY 2022
图7-27. LP5891 Memory-unit Structure
7.6.1.3 Write a Frame Data into Memory Bank
After power on, the LP5891 internal flag BANK_SEL, and counters LINE_COUNT, CHANNEL_COUNT, are all
initialized to 0. Thus, the memory unit of channel R0/G0/B0, locating in line 0 of BANK A, is selected to restore
the data transimitted the first time after VSYNC command.
When the first WRTGS command is received, all the data in the common shift register is latched into the memory
unit of channel R0/G0/B0, locating in line 0 of BANK A. Then CHANNEL_COUNT increases by 1 and
LINE_COUNT stays the same. Thus, the memory unit of channel R1/G1/B1, locating in line 0 of BANK A, is
selected to restore the data transimitted the second time after VSYNC command.
When the second WRTGS command is received, all the data in the common shift register is latched into the
memory unit of channel R1/G1/B1, locating in line 0 of BANK A. Then CHANNEL_COUNT increases by 1 and
LINE_COUNT stays the same. Thus, the memory unit of channel R2/G2/B2, locating in line 0 of BANK A, is
selected to restore the data transimitted the third time after VSYNC command.
Repeat the grayscale-data-write operation until the 16th WRTGS command is received. Then
CHANNEL_COUNT is reset to 0 and LINE_COUNT increases by 1. Thus, the memory unit of channel
R0/G0/B0, locating in line 1 of BANK A, is selected to restore the data transimitted the 17th time after VSYNC
command.
Copyright © 2022 Texas Instruments Incorporated
32
Submit Document Feedback
Product Folder Links: LP5891
LP5891
www.ti.com.cn
ZHCSQG6A –MARCH 2022 –REVISED MAY 2022
Repeat this operation for each line until the LINE_COUNT exceeds the number of scan lines set in the
SCAN_NUM (See FC0 register bit21-16 ) and all scan lines have been updated with new GS data, which means
one frame of GS data is restored into the memory BANK. Then the LINE_COUNT is reset to 0.
7.6.2 PWM Control for Display
To increase the refresh rate in time-multiplexing display system, a DS-PWM (Dynamic Spectrum-Pulse Width
Modulation) algorithm is proposed in this device. One frame is divided into many segments shown below. Note
that one frame is divided into n sub-periods, n is set by SUBP_NUM (FC0 register bit24-22), and each sub-
period is divided into 32 segments for 32 scan lines. Each segment contains GS GCLKs time for grayscale data
display and T_SW GCLKs time for switching lines. GS is configured by the SEG_LENGTH (FC1 register bit9-0 in
表 7-8) , and T_SW is the line switch time, which is configured by the LINE_SWT (see FC1 register bit 40-37 in
表7-8).
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
33
Product Folder Links: LP5891
LP5891
www.ti.com.cn
ZHCSQG6A –MARCH 2022 –REVISED MAY 2022
图7-28. DS-PWM Algorithm with 32 Scan Lines
The DS-PWM can not only increase the refresh rate meanwhile keep the same frame rate, but also decrease the
brightness loss in low grayscale, which can smoothly increase the sub-period number when the grayscale data
increases.
To achieve ultra-low luminance, the LED driver must have the ability to output a very short current pulse (1
GCLK time), however, because of the parasitic capacitor of the LEDs, such pulse can not turn on the LEDs. The
larger GCLK frequency is, the harder to turn on LEDs.
DS-PWM algorithm have a parameter called subperiod threshold, which is used to calculate when to change
subperiod number according to the giving grayscale data. Subperiod threshold defines the LED minimum turn-on
time, so as to conquer the current loss caused by LED parasitic capacitor. Subperiod threshold is configured by
the LG_STEP_R/G/B (FC1 register bit24-10 in 表7-8).
With DS-PWM algorithm, the brightness has smoothly increased with the gradient grayscale data.
7.7 Register Maps
表7-5. Register Maps
WRITE COMMAND READ COMMAND
REGISTER NAME
TYPE
DESCRIPTION
ID
ID
FC0
FC1
R/ W
R/ W
R/ W
R/ W
R/ W
R/ W
R/ W
AA00h
AA01h
AA02h
AA03h
AA04h
AA0Eh
AA0Fh
AA60h
AA61h
AA62h
AA63h
AA64h
AA6Eh
AA6Fh
Common configuration
Common configuration
Common configuration
Common configuration
Common configuration
Locate the line for LOD
Locate the line for LSD
FC2
FC3
FC4
FC14
FC15
Read the lines' warning of LOD from 64th ~ 49th
line
FC16
FC17
FC18
FC19
R
R
R
R
AAA0h
AAA1h
AAA2h
AAA3h
Read the lines' warning of LOD from 48th~1st line
Read the lines' warning of LSD from 64th ~ 49th
line
Read the lines' warning of LSD from 48th~1st line
Copyright © 2022 Texas Instruments Incorporated
34
Submit Document Feedback
Product Folder Links: LP5891
LP5891
www.ti.com.cn
ZHCSQG6A –MARCH 2022 –REVISED MAY 2022
表7-5. Register Maps (continued)
WRITE COMMAND READ COMMAND
REGISTER NAME
TYPE
DESCRIPTION
ID
ID
FC20
FC21
R
R
AAA4h
AAA5h
AA70h
Read the channel's warning of LOD
Read the channel's warning of LSD
Read/Write chip index
Chip Index
VSYNC
MPSM
R/ W
W
AA10h
AAF0h
AA90h
AAB0h
AAB1h
AA80h
AA30h
Write VSYNC command
W
Write matrix PSM command
SBY_CLR
SBY_EN
Soft_Reset
SRAM
W
Write standby clear command
Write standby enable command
Reset the all the registers expect the SRAM
Write or read the SRAM data
W
W
W
表7-6. Access Type Codes
Access Type
Code
Description
Read Type
R
R
Read
Write Type
W
W
Write
Reset or Default Value
-n
Value after reset or the default
value
7.7.1 FC0
FC0 is shown in FC0 Register and described in FC0 Register Field Descriptions.
图7-29. FC0 Register
47
46
45
44
43
42
41
25
9
40
39
38
22
6
37
36
20
4
35
19
34
33
17
1
32
16
0
LSD_R RESERVED
M_EN
GRP_DLY_B
GRP_DLY_G
GRP_DLY_R
RESERVED
R/
W-0b
R-01b
R/W-000b
R/W-000b
R/W-000b
21
R-000b
31
30
29
28
27
26
24
23
18
FREQ_MUL
R/W-0111b
14
FREQ_
MOD
RESERVED
SUBP_NUM
R/W-000b
7
SCAN_NUM
R/
W-0b
R-000b
R/W-000000b
15
13
12
11
10
8
5
3
2
LODR
M_EN
PSP_MOD
PS_EN
RESERVED
PDC_E
N
RESERVED
CHIP_NUM
R/
R/W-00b
R/
R-000b
R/
R-000b
R/W-00111b
W-0b
W-0b
W-1b
表7-7. FC0 Register Field Descriptions
Bit
Field
Type
Reset
Description
4-0
CHIP_NUM
R/W
00111b
Set the device number
00000b: 1 device
...
01111b: 16 devices
...
11111b: 32 devices
7-5
RESERVED
R
000b
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
35
Product Folder Links: LP5891
LP5891
www.ti.com.cn
ZHCSQG6A –MARCH 2022 –REVISED MAY 2022
表7-7. FC0 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
8
PDC_EN
R/W
1b
Enable or disable pre-discharge function
0b: disable
1b: enable
11-9
12
RESERVED
PS_EN
R
000b
0b
R/W
Enable or disable the power saving mode
0b: disable
1b: enable
14-13
PSP_MOD
R/W
00b
Set the powering saving plus mode
00b: disable
01b: save power at high level
10b: save power at middle level
11b: save power at low level
15
LODRM_EN
SCAN_NUM
R/W
R/W
0b
Enable or disable the LED open load removal function
0b: disable
1b: enable
21-16
000000b
Set the scan line number
000000b: 1 line
...
001111b: 16 lines
...
011111b: 32 lines
...
111111b: 64 lines
24-22
SUBP_NUM
R/W
000b
Set the subperiod number
000b: 16
001b: 32
010b: 48
011b: 64
100b: 80
101b: 96
110b: 112
111b: 128
27-25
28
RESERVED
FREQ_MOD
R
000b
0b
R/W
Set the GCLK multiplier mode
0b: low frequency mode, 40MHz to 80MHz
1b: high frequency mode, 80MHz to 160MHz
32-29
FREQ_MUL
R/W
0111b
Set the GCLK multiplier frequency
0000b: 1 x SCLK frequency
...
0111b: 8 x SCLK frequency
...
1111b: 16 x SCLK frequency
35-33
38-36
RESERVED
GRP_DLY_R
R
000b
000b
R/W
Set the Red group delay, forward PWM mode only
000b: no delay
001b: 1 GCLK
010b: 2 GCLK
011b: 3 GCLK
100b: 4 GCLK
101b: 5 GCLK
110b: 6 GCLK
111b: 7 GCLK
Copyright © 2022 Texas Instruments Incorporated
36
Submit Document Feedback
Product Folder Links: LP5891
LP5891
www.ti.com.cn
ZHCSQG6A –MARCH 2022 –REVISED MAY 2022
表7-7. FC0 Register Field Descriptions (continued)
Bit
Field
GRP_DLY_G
Type
Reset
Description
41-39
R/W
000b
Set the Green group delay, forward PWM mode only
000b: no delay
001b: 1 GCLK
010b: 2 GCLK
011b: 3 GCLK
100b: 4 GCLK
101b: 5 GCLK
110b: 6 GCLK
111b: 7 GCLK
44-42
GRP_DLY_B
R/W
000b
Set the Blue group delay, forward PWM mode only
000b: no delay
001b: 1 GCLK
010b: 2 GCLK
011b: 3 GCLK
100b: 4 GCLK
101b: 5 GCLK
110b: 6 GCLK
111b: 7 GCLK
46-45
47
RESERVED
LSD_RM_EN
R
01b
0b
R/W
Enable or disable short LED caterpillar
0b: disable
1b: enable
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
37
Product Folder Links: LP5891
LP5891
www.ti.com.cn
ZHCSQG6A –MARCH 2022 –REVISED MAY 2022
7.7.2 FC1
FC1 is shown in FC1 Register and described in FC1 Register Field Descriptions.
图7-30. FC1 Register
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17
32
RESE
RVED
BLK_ADJ
LINE_SWT
LG_ENH_B
LG_EN
H_G
R-0b
31
R/W-000000b
R/W-0111b
R/W-0000b
30
29
13
28
27
26
25
9
24
8
23
7
22
21
5
20
4
19
3
18
16
0
LG_ENH_G
R/W-0000b
14
LG_ENH_R
R/W-0000b
LG_STEP_B
R/W-01001b
6
LG_STEP_G
R/W-01001b
15
12
11
10
2
1
LG_ST
EP_G
LG_STEP_R
SEG_LENGTH
R/W-01001b
R/W-0'000'000'000b
表7-8. FC1 Register Field Descriptions
Bit
Field
Type
Reset
Description
9-0
SEG_LENGTH
LG_STEP_R
R/W
0'000'000'0 Set the GCLK number in each segment
00b
127d: 128 GCLK
...
1023d: 1024 GCLK
others: 128 GCLK
14-10
19-15
24-20
28-25
32-29
36-33
R/W
R/W
R/W
R/W
R/W
R/W
01001b
Adjust the smooth of the brightness in low grayscale
00000b: level 1
...
01111b: level 16
...
11111b: level 32
LG_STEP_G
LG_STEP_B
LG_ENH_R
LG_ENH_G
LG_ENH_B
01001b
01001b
0000b
0000b
0000b
Adjust the smooth of the brightness in low grayscale
00000b: level 1
...
01111b: level 16
...
11111b: level 32
Adjust the smooth of the brightness in low grayscale
00000b: level 1
...
01111b: level 16
...
11111b: level 32
Adjust low grayscale enhancement of red channels
0000b: level 0
...
0111b: level 7
...
1111b: level 15
Adjust low grayscale enhancement of green channels
0000b: level 0
...
0111b: level 7
...
1111b: level 15
Adjust low grayscale enhancement of blue channels
0000b: level 0
...
0111b: level 7
...
1111b: level 15
Copyright © 2022 Texas Instruments Incorporated
38
Submit Document Feedback
Product Folder Links: LP5891
LP5891
www.ti.com.cn
ZHCSQG6A –MARCH 2022 –REVISED MAY 2022
表7-8. FC1 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
40-37
LINE_SWT
R/W
0111b
Set the scan line switch time.
0000b: 45 GCLK
0001b: 2x30 GCLK
...
0111b: 8x30 GCLK
...
1111b: 16x30 GCLK
46-41
BLK_ADJ
R/W
000000b
Set the black field adjustment
000000b: 0 GCLK
...
011111b: 31 GCLK
...
111111b: 63 GCLK
47
RESERVED
R
0b
Reserved bit.
7.7.3 FC2
FC2 is shown in FC2 Register and described in FC2 Register Field Descriptions.
图7-31. FC2 Register
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
MPSM RESE
MOD_SIZE
SUBP_ CH_B_ CH_G_ CH_R_
MAX_2 IMMU IMMU IMMU
RESERVED
LG_COLOR_B
_EN
RVED
R-0b
30
56
NITY
NITY
NITY
R/
W-0b
R/W-111b
28
R/
R/
R/
R/
R-000b
21
R/W-0000b
W-0b
W-1b
W-1b
W-1b
31
29
27
11
26
25
24
23
22
20
4
19
3
18
17
16
0
LG_COLOR_G
R/W-0000b
LG_COLOR_R
R/W-0000b
DE_COUPLE1_B
R/W-0000b
DE_COUPLE1_G
R/W-0000b
15
14
13
12
10
9
8
7
6
5
2
1
DE_COUPLE1_R
R/W-0000b
V_PDC_B
R/W-0110b
V_PDC_G
R/W-0110b
V_PDC_R
R/W-0110b
表7-9. FC2 Register Field Descriptions
Bit
Field
Type
Reset
Description
3-0
V_PDC_R
R/W
0110b
Set the Red pre_discharge voltage (typical), the voltage value
must not be higher than (VR-1.3V).
0000b: 0.1V
0001b: 0.2V
0010b: 0.3V
0011b: 0.4V
0100b: 0.5V
0101b: 0.6V
0110b: 0.7V
0111b: 0.8V
1000b: 0.9V
1001b: 1.0V
1010b: 1.1V
1011b: 1.3V
1100b: 1.5V
1101b: 1.7V
1110b: 1.9V
1111b: 2.1V
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
39
Product Folder Links: LP5891
LP5891
www.ti.com.cn
ZHCSQG6A –MARCH 2022 –REVISED MAY 2022
表7-9. FC2 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
7-4
V_PDC_G
R/W
0110b
Set the Green pre_discharge voltage (typical), the voltage value
must not be higher than (VG-1.3V).
0000b: 0.1V
0001b: 0.2V
0010b: 0.3V
0011b: 0.4V
0100b: 0.5V
0101b: 0.6V
0110b: 0.7V
0111b: 0.8V
1000b: 0.9V
1001b: 1.0V
1010b: 1.1V
1011b: 1.3V
1100b: 1.5V
1101b: 1.7V
1110b: 1.9V
1111b: 2.1V
11-8
V_PDC_B
R/W
0110b
Set the Blue pre_discharge voltage (typical), the voltage value
must not be higher than (VB-1.3V).
0000b: 0.1V
0001b: 0.2V
0010b: 0.3V
0011b: 0.4V
0100b: 0.5V
0101b: 0.6V
0110b: 0.7V
0111b: 0.8V
1000b: 0.9V
1001b: 1.0V
1010b: 1.1V
1011b: 1.3V
1100b: 1.5V
1101b: 1.7V
1110b: 1.9V
1111b: 2.1V
15-12
19-16
23-20
27-24
DE_COUPLE1_R
DE_COUPLE1_G
DE_COUPLE1_B
LG_COLOR_R
R/W
R/W
R/W
R/W
0000b
0000b
0000b
0000b
Set the Red decoupling level
0000b: level 1 (lowest)
...
0111b: level 8 (middle)
...
1111b: level 16(highest)
Set the Green decoupling level
0000b: level 1 (lowest)
...
0111b: level 8 (middle)
...
1111b: level 16(highest)
Set the Blue decoupling level
0000b: level 1 (lowest)
...
0111b: level 8 (middle)
...
1111b: level 16(highest)
Set the Red brightness compensation level of the low grayscale
0000b: level 1 (lowest)
...
0111b: level 8 (middle)
...
1111b: level 16(highest)
Copyright © 2022 Texas Instruments Incorporated
40
Submit Document Feedback
Product Folder Links: LP5891
LP5891
www.ti.com.cn
ZHCSQG6A –MARCH 2022 –REVISED MAY 2022
表7-9. FC2 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
31-28
LG_COLOR_G
R/W
0000b
Set the Red brightness compensation level of the low grayscale
0000b: level 1 (lowest)
...
0111b: level 8 (middle)
...
1111b: level 16(highest)
35-32
LG_COLOR_B
R/W
0000b
Set the Red brightness compensation level of the low grayscale
0000b: level 1 (lowest)
...
0111b: level 8 (middle)
...
1111b: level 16(highest)
38-36
39
RESERVED
R
000b
1b
CH_R_IMMUNITY
R/W
Set the immunity of the Red channels group
0b: high immunity
1b: low immunity
40
41
CH_G_IMMUNITY
CH_B_IMMUNITY
SUBP_MAX_256
MOD_SIZE
R/W
R/W
R/W
R/W
1b
Set the immunity of the Green channels group
0b: high immunity
1b: low immunity
1b
Set the immunity of the Blue channels group
0b: high immunity
1b: low immunity
42
0b
Set the maximum subperiod to 256.
0b: disable
1b: enable
45-43
111b
Set the module size.
000b: 16x16 RGB pixels
001b:32x32 RGB pixels
010b:48x48 RGB pixels with D3 reverse, and scan sequence
D1,D2,D3
011b:48x48 RGB pixels with D3 reverse, and scan sequence
D1,D3,D2
100b:48x64 RGB pixels with D3, D4 reverse, and scan
sequence D1,D2,D3
101b:48x64 RGB pixels with D3,D4 reverse, and scan sequence
D1,D3,D2
110b:64x64 RGB pixels with D3,D4 reserve, and scan seqeunce
D1,D2,D3,D4
111b:64x64 RGB pixels with D3,D4 reverse,and scan sequence
D1,D4,D2,D3
46
47
RESERVED
MPSM_EN
R
0b
0b
R/W
Enable or disable matrix power saving mode.
0b: disable
1b: enable
7.7.4 FC3
FC3 is shown in FC3 Register and described in FC3 Register Field Descriptions.
图7-32. FC3 Register
47
31
15
46
45
29
13
44
28
43
LSDVTH_G
R/W-000b
27
42
26
10
41
25
9
40
39
23
7
38
22
6
37
LSD_RM
R/W-0111b
36
35
19
34
18
2
33
BC
32
16
0
LSDVTH_B
R/W-000b
30
LSDVTH_R
R/W-000b
24
R/W-011b
17
21
20
CC_B
CC_G
R/W-0111 1111b
R/W-0111 1111b
12 11
14
8
5
4
3
1
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
41
Product Folder Links: LP5891
LP5891
www.ti.com.cn
ZHCSQG6A –MARCH 2022 –REVISED MAY 2022
图7-32. FC3 Register (continued)
CC_R
LOD_L RESE
SD_RB RVED
LODVTH_B
LODVTH_G
R/W-00b
LODVTH_R
R/W-00b
R/W-0111 1111b
R/
R-0b
R/W-00b
W-0b
表7-10. FC3 Register Field Descriptions
Bit
Field
Type
Reset
Description
1-0
LODVTH_R
R/W
00b
Set the Red LED open load detection threshold
00b: (VLEDR-0.2) V
01b: (VLEDR-0.5) V
10b: (VLEDR-0.9) V
11b: (VLEDR-1.2) V
3-2
5-4
LODVTH_G
LODVTH_B
R/W
R/W
00b
00b
Set the Green LED open load detection threshold
00b: (VLEDG-0.2) V
01b: (VLEDG-0.5) V
10b: (VLEDG-0.9) V
11b: (VLEDG-1.2) V
Set the Blue LED open load detection threshold
00b: (VLEDB-0.2) V
01b: (VLEDB-0.5) V
10b: (VLEDB-0.9) V
11b: (VLEDB-1.2) V
6
7
RESERVED
R
0b
0b
LOD_LSD_RB
R/W
Enable or disable the LOD and LSD readback function
0b: disabled
01b: enabled
15-8
23-16
31-24
34-32
CC_R
CC_G
CC_B
BC
R/W
R/W
R/W
R/W
0111 1111b Set the Red color brightness level
0000 0000b: level 0 (lowest)
...
0111 1111b: level 127 (middle)
...
1111 1111b: level 255 (highest)
0111 1111b Set the Green color brightness level
0000 0000b: level 0 (lowest)
...
0111 1111b: level 127 (middle)
...
1111 1111b: level 255 (highest)
0111 1111b Set the Blue color brightness level
0000 0000b: level 0 (lowest)
...
0111 1111b: level 127 (middle)
...
1111 1111b: level 255 (highest)
011b
Set the global brightness level
000b: level 0 (lowest)
...
011b: level 3 (middle)
...
111b: level 7 (highest)
Copyright © 2022 Texas Instruments Incorporated
42
Submit Document Feedback
Product Folder Links: LP5891
LP5891
www.ti.com.cn
ZHCSQG6A –MARCH 2022 –REVISED MAY 2022
表7-10. FC3 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
38-35
LSD_RM
R/W
0111b
Set the LED short removal level
0000b: level 1
0001b: level 2
0010b: level 3
0011b: level 4
0100b: level 5
0101b: level 6
0110b: level 7
0111b: level 8
1000b: level 9
1001b: level 10
1010b: level 11
1011b: level 12
1100b: level 13
1101b: level 14
1110b: level 15
1111b: level 16
41-39
44-42
47-45
LSDVTH_R
LSDVTH_G
LSDVTH_B
R/W
R/W
R/W
000b
000b
000b
Set the Red LED short/weak short circuitry detection threshold
(typical)
000b: 0.2 V
001b: 0.4 V
010b: 0.8 V
011b: 1.0 V
100b: 1.2 V
101b: 1.4 V
110b: 1.6 V
111b: 1.8 V
Set the Green LED short/weak short circuitry detection threshold
(typical)
000b: 0.2 V
001b: 0.4 V
010b: 0.8 V
011b: 1.2 V
100b: 1.6 V
101b: 2 V
110b: 2.4 V
111b: 2.8 V
Set the Blue LED short/weak short circuitry detection threshold
(typical)
000b: 0.2 V
001b: 0.4 V
010b: 0.8 V
011b: 1.2 V
100b: 1.6 V
101b: 2 V
110b: 2.4 V
111b: 2.8 V
7.7.5 FC4
FC4 is shown in FC4 Register and described in FC4 Register Field Descriptions.
图7-33. FC4 Register
47
31
15
46
45
44
43
42
41
40
39
38
37
36
35
19
34
33
32
RESERVED
DE_COU
PLE3_EN
DE_COUPLE3
DE_COU
PLE2
FIRST_LINE_DIM
CAURSE CAURSE CAURSE
_B
R/W-0b
18
_G
R/W-0b
17
_R
R/W-0b
16
R-000b
30
R/W-0b
28
R/W-1000b
R/W-0b
23
R/W-0000b
29
27
26
SR_ON_B
25
SR_ON_G
24
22
21
20
RESERVED
SR_ON_R
SR_OFF SR_OFF SR_OFF FINE_B
FINE_G
FINE_R
_B
R/W-0b
5
_G
R/W-0b
4
_R
R/W-0b
3
R-0000b
R/W-01b
R/W-01b
R/W-01b
R/W-0b
2
R/W-0b
1
R/W-0b
0
14
13
12
11
10
9
8
7
6
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
43
Product Folder Links: LP5891
LP5891
www.ti.com.cn
ZHCSQG6A –MARCH 2022 –REVISED MAY 2022
图7-33. FC4 Register (continued)
RESERV SCAN_R
RESERVED
IMAX
RESERV
ED
ED
EV
R-0b
R/W-1b
R-0000 0000 1111b
R/W-0b
R-0b
表7-11. FC4 Register Field Descriptions
Bit
Field
Type
Reset
Description
0
1
RESERVED
IMAX
R
0b
R/W
0b
Set the maximum current of each channel
0b: 10mA maximum
01b: 20 mA maximum
13-2
14
RESERVED
SCAN_REV
R
0000 0000
1111b
R/W
1b
When 2 device stackable, the scan lines PCB layout is reversed.
For the proper scan and SRAM read sequence, SCAN_REV
register is provided.
0b: the PCB layout sequence is L0-L15, L16-L31.
1b: the PCB layout sequence is L0-L15, L31-L16.
15
16
RESERVED
FINE_R
R
0b
0b
R/W
Enable the Red brightness compensation level fine range
0b: disable
1b: enable
17
18
FINE_G
R/W
R/W
R/W
R/W
R/W
R/W
0b
0b
0b
0b
0b
01b
Enable the Green brightness compensation level fine range
0b: disable
1b: enable
FINE_B
Enable the Blue brightness compensation level fine range
0b: disable
1b: enable
19
SR_OFF_R
SR_OFF_G
SR_OFF_B
SR_ON_R
Slew rate control function when Red turns off operation
0b: slow slew rate.
1b: fast slew rate.
20
Slew rate control function when Green turns off operation
0b: slow slew rate.
1b: fast slew rate.
21
Slew rate control function when Blue turns off operation
0b: slow slew rate.
1b: fast slew rate.
23-22
Slew rate control function when Red turns on operation
00b: the slower slew rate.
01b: slow slew rate.
10b: fast slew rate.
11b: the faster slew rate.
25-24
27-26
SR_ON_G
SR_ON_B
R/W
R/W
01b
01b
Slew rate control function when Green turns on operation
00b: the slower slew rate.
01b: slow slew rate.
10b: fast slew rate.
11b: the faster slew rate.
Slew rate control function when Blue turns on operation
00b: the slower slew rate.
01b: slow slew rate.
10b: fast slew rate.
11b: the faster slew rate.
31-28
32
RESERVED
CAURSE_R
R
0000b
0b
R/W
Enable the Red brightness compensation level caurse range
0b: disable
1b: enable
33
CAURSE_G
R/W
0b
Enable the Green brightness compensation level caurse range
0b: disable
1b: enable
Copyright © 2022 Texas Instruments Incorporated
44
Submit Document Feedback
Product Folder Links: LP5891
LP5891
www.ti.com.cn
ZHCSQG6A –MARCH 2022 –REVISED MAY 2022
表7-11. FC4 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
34
CAURSE_B
R/W
0b
Enable the Blue brightness compensation level caurse range
0b: disable
1b: enable
38-35
FIRST_LINE_DIM
R/W
0000b
Adjust the first line dim level
0000b: level 1
...
0111b: level 8
...
1111b: level 16
39
DE_COUPLE2
DE_COUPLE3
R/W
R/W
0b
Decoupling between ON and OFF channels
0b: disabled
1b: enabled
43-40
1000b
Set decoupling enhancement level
0000b: level 1
...
0111b: level 8
...
1111b: level 16
44
DE_COUPLE3_EN
RESERVED
R/W
R
0b
Enable decoupling enhancement
0b: disabled
1b: enabled
47-45
000b
7.7.6 FC14
FC14 is shown in FC14 Register and described in FC14 Register Field Descriptions.
图7-34. FC14 Register
47
31
15
46
30
14
45
29
13
44
28
12
43
27
11
42
26
10
41
25
9
40
39
38
22
6
37
21
5
36
20
4
35
19
3
34
18
2
33
17
1
32
16
0
RESERVED
R-0b
24
23
RESERVED
R-0b
8
7
RESERVED
R-0b
LOD_LINE_CMD
R/W-000000b
表7-12. FC14 Register Field Descriptions
Bit
Field
Type
Reset
Description
5-0
LOD_LINE_CMD
R/W
000000b
Locate the line with LED open load warnings:
000000b: Line 0
...
011111b: Line 31
...
111111b: Line 63
47-6
RESERVED
R
0b
Reserved bits
7.7.7 FC15
FC15 is shown in FC15 Register and described in FC15 Register Field Descriptions.
图7-35. FC15 Register
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
RESERVED
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
45
Product Folder Links: LP5891
LP5891
www.ti.com.cn
ZHCSQG6A –MARCH 2022 –REVISED MAY 2022
图7-35. FC15 Register (continued)
R-0b
31
15
30
14
29
13
28
12
27
11
26
25
24
23
22
21
20
4
19
3
18
2
17
1
16
0
RESERVED
R-0b
10
9
8
7
6
5
RESERVED
R-0b
LSD_LINE_CMD
R/W-000000b
表7-13. FC15 Register Field Descriptions
Bit
Field
Type
Reset
Description
5-0
LSD_LINE_CMD
R/W
000000b
Locate the line with LED short circuitry warnings:
000000b: Line 0
...
011111b: Line 31
...
111111b: Line 63
47-6
RESERVED
R
0b
Reserved bits
7.7.8 FC16
FC16 is shown in FC16 Register and described in FC16 Register Field Descriptions.
图7-36. FC16 Register
47
31
15
46
30
14
45
29
13
44
28
12
43
27
11
42
26
10
41
25
9
40
39
38
22
6
37
21
5
36
20
4
35
19
3
34
18
2
33
17
1
32
16
0
RESERVED
R-0b
24
23
RESERVED
R-0b
8
7
LOD_LINE_WARN[63:48]
R-0b
表7-14. FC16 Register Field Descriptions
Bit
Field
Type
Reset
Description
15-0
LOD_LINE_WARN[63:48]
R
0b
Read the line with LED open load warnings:
Bit 0 = 0, Line 48 has no warning; Bit 0 = 1, Line 48 has warning
...
Bit 15 = 0, Line 63 has no warning; Bit 15 = 1, Line 63 has
warning
47-16
RESERVED
R
0b
Reserved bits
7.7.9 FC17
FC17 is shown in FC17 Register and described in FC17 Register Field Descriptions.
图7-37. FC17 Register
47
31
46
30
45
29
44
28
43
27
42
26
41
40
39
38
37
21
36
20
35
19
34
18
33
17
32
16
LOD_LINE_WARN[47:0]
R-0b
25
24
23
22
LOD_LINE_WARN[47:0]
R-0b
Copyright © 2022 Texas Instruments Incorporated
46
Submit Document Feedback
Product Folder Links: LP5891
LP5891
www.ti.com.cn
ZHCSQG6A –MARCH 2022 –REVISED MAY 2022
图7-37. FC17 Register (continued)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LOD_LINE_WARN[47:0]
R-0b
表7-15. FC17 Register Field Descriptions
Bit
47-0
Field
LOD_LINE_WARN[47:0]
Type
Reset
Description
R
0b
Read the line with LED open load warnings:
Bit 0 = 0, Line 0 has no warning; Bit 0 = 1, Line 0 has warning
...
Bit 47 = 0, Line 47 has no warning; Bit 47 = 1, Line 47 has
warning
7.7.10 FC18
FC18 is shown in FC18 Register and described in FC18 Register Field Descriptions.
图7-38. FC18 Register
47
15
31
46
14
30
45
13
29
44
12
28
43
11
27
42
10
26
41
40
39
38
37
5
36
4
35
3
34
2
33
1
32
0
RESERVED
R-0b
9
8
7
6
RESERVED
R-0b
25
24
23
22
21
20
19
18
17
16
LSD_LINE_WARN[63:48]
R-0b
表7-16. FC18 Register Field Descriptions
Bit
Field
Type
Reset
Description
47-0
LSD_LINE_WARN[63:48]
R
0b
Read the line with LED short circuitry warnings:
Bit 0 = 0, Line 48 has no warning; Bit 0 = 1, Line 48 has warning
...
Bit 15 = 0, Line 63 has no warning; Bit 15 = 1, Line 63 has
warning
47-16
RESERVED
R
0b
Reserved bits
7.7.11 FC19
FC19 is shown in FC19 Register and described in FC19 Register Field Descriptions.
图7-39. FC19 Register
47
31
15
46
30
14
45
29
13
44
28
12
43
27
11
42
26
10
41
40
39
38
37
21
5
36
20
4
35
19
3
34
18
2
33
17
1
32
16
0
LSD_LINE_WARN[47:0]
R-0b
25
24
23
22
LSD_LINE_WARN[47:0]
R-0b
9
8
7
6
LSD_LINE_WARN[47:0]
R-0b
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
47
Product Folder Links: LP5891
LP5891
www.ti.com.cn
ZHCSQG6A –MARCH 2022 –REVISED MAY 2022
表7-17. FC19 Register Field Descriptions
Bit
Field
Type
Reset
Description
47-0
LSD_LINE_WARN[47:0]
R
0b
Read the line with LED short circuitry warnings:
Bit 0 = 0, Line 0 has no warning; Bit 0 = 1, Line 0 has warning
...
Bit 47 = 0, Line 47 has no warning; Bit 47 = 1, Line 47 has
warning
7.7.12 FC20
FC20 is shown in FC20 Register and described in FC20 Register Field Descriptions.
图7-40. FC20 Register
47
31
15
46
30
14
45
29
13
44
28
12
43
27
11
42
26
10
41
25
9
40
LOD_CH
R-0b
39
38
22
6
37
21
5
36
20
4
35
19
3
34
18
2
33
17
1
32
16
0
24
23
LOD_CH
R-0b
8
7
LOD_CH
R-0b
表7-18. FC20 Register Field Descriptions
Bit
47-0
Field
LOD_CH
Type
Reset
Description
R
0b
Locate the LED opem load channel:
Bit 0 = 0, CH 0 is normal; Bit 0 = 1, CH 0 is short circuitry
...
Bit 47 = 0, CH 47 is normal; Bit 47 = 1, CH 47 is short circuitry
7.7.13 FC21
FC21 is shown in FC21 Register and described in FC21 Register Field Descriptions.
图7-41. FC21 Register
47
31
15
46
30
14
45
29
13
44
28
12
43
27
11
42
26
10
41
25
9
40
LSD_CH
R-0b
39
38
22
6
37
21
5
36
20
4
35
19
3
34
18
2
33
17
1
32
16
0
24
23
LSD_CH
R-0b
8
7
LSD_CH
R-0b
表7-19. FC21 Register Field Descriptions
Bit
47-0
Field
LSD_CH
Type
Reset
Description
R
0b
Locate the LED short circuitry channel:
Bit 0 = 0, CH 0 is normal; Bit 0 = 1, CH 0 is short circuitry
...
Bit 47 = 0, CH 47 is normal; Bit 47 = 1, CH 47 is short circuitry
Copyright © 2022 Texas Instruments Incorporated
48
Submit Document Feedback
Product Folder Links: LP5891
LP5891
www.ti.com.cn
ZHCSQG6A –MARCH 2022 –REVISED MAY 2022
8 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The LP5891 integrates 48 constant current sources and 16 scanning FETs. A single LP5891 is capable of
driving 16 × 16 RGB LED pixels while stacking two LP5891 devices can drive 32 × 32 RGB LED pixels. To
achieve low power consumption, the LP5891 supports separated power supplies for the red, green, and blue
LEDs by its common cathode structure.
The LP5891 implements a high speed rising edge transmission interface (up to 50 MHz) to support high device
count daisy-chained and high refresh rate while minimizing electrical-magnetic interference (EMI). SCLK must be
continuous, no matter there is data on SIN or not, because SCLK is not only used to sample the data on SIN, but
also used as a clock source to generate GCLK by internal frequency multiplier. Based on rising-edge CCSI
protocol, all the commands/FC registers/SRAM data are written from the SIN input terminal, and all the FC
registers/ LED open and short flag can be read out from the SOUT output terminal. Moreover, the device
supports up to 160-MHz GCLK frequency and can achieve 16-bit PWM resolution, with 3840 Hz or even higher
refresh rate.
Meanwhile, the LP5891 integrates enhanced circuits and intelligent algorithms to solve the various display
challenges in Narrow Pixel Pitch (NPP) LED display applications and mini and micro-LED products: dim at the
first scan line, upper and downside ghosting, non-uniformity in low grayscale, coupling, caterpillar caused by
open or short LEDs, which make the LP5891 a perfect choice in such applications.
The LP5891 also implements LED open, weak short, short detections and removals during operations and can
also report this information out to the accompanying digital processor.
8.2 Typical Application
The LP5891 are typically connected in series in a daisy-chain to drive the LED matrix with only a few controller
ports. 图8-1 shows a typical application diagram with two LP5891 devices stackable connection to drive 32 × 32
RGB LED pixels.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
49
Product Folder Links: LP5891
LP5891
www.ti.com.cn
ZHCSQG6A –MARCH 2022 –REVISED MAY 2022
图8-1. LP5891 with Dual Devices Stackable Connection
8.2.1 Design Requirements
Taking 4K micro-LED television for example, the resolution of the screen is 3840 × 2160, and the screen
consists of many modules. The following sections show an example to build a LED display module with 240 ×
180 pixels.
The example uses the following values as the system design parameters.
表8-1. LP5891 Design Parameters
DESIGN PARAMETER
VCC and VR
EXAMPLE VALUE
2.8 V
VG and VB
3.8 V
Maximum current per LED
PWM resolution
IRED = 3 mA, IGREEN = 2 mA, IBLUE = 1 mA
14 bits
Frame rate
120 Hz
Refresh rate
3840 Hz
Display module size
cascaded devices number
devices number per LED display module
240 × 180 pixels
8
96
8.2.1.1 System Structure
To build an LED display module with 240 × 180 pixels, 96 LP5891 devices are required.
Copyright © 2022 Texas Instruments Incorporated
50
Submit Document Feedback
Product Folder Links: LP5891
LP5891
www.ti.com.cn
ZHCSQG6A –MARCH 2022 –REVISED MAY 2022
240 Columns
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
180
Lines
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
图8-2. LED Display Module
As shown in 图 8-2, the total module can be divided into 48 32 × 32 matrix. Each matrix includes two devices
with stackable connection.
备注
To achieve the best performance, distribute the redundant channels and lines to each 32 × 32 matrix.
For this case, two Red/Green/Blue channels and two lines are not used in each matrix. And these
unused pins can be floated. For the software, TI suggests zero data to send to the unused channels.
There is no need to send the zero data to unused lines.
8.2.1.2 SCLK Frequency
The SCLK frequency is determined by the data volume of one frame and frame rate. In this application, the data
volume V_Data is 30 × 32 × 48 bits × 4 = 184.32 Kb, the frame rate is 120 Hz. Suppose the data transmission
efficiency is 0.8, the minimum frequency of SCLK must be: fSCLK = V_Data × fframe / 0.8. So the minimum SCLK
frequency is 27.65 MHz with rising-edge transmission.
8.2.1.3 Internal GCLK Frequency
The internal GCLK frequency is configured by the Frequency Multiplier (FREQ_MUL), and is determined by the
PWM resolution. The GCLK frequency can be calculated by the below equations:
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
51
Product Folder Links: LP5891
LP5891
www.ti.com.cn
ZHCSQG6A –MARCH 2022 –REVISED MAY 2022
frefresh_ rate
Nsub_ period
=
f frame_ rate
GSmax = 2K
GSmax = NGCLK _ Seg ì Nsub_ period
N
≈
∆
«
’
1
GCLK _ Seg
=
+TSW ì NScan_line ì Nsub_ period +TBlank
÷
f frame_ rate
fGCLK
◊
(3)
where
• frefresh_rate means the refresh rate
• fframe_rate means the frame rate
• K means the PWM resolution
• Nsub_period means the sub-period numbers within one frame
• NGCLK_seg means the GCLK number per segment (line switch time excluded)
• fGCLK means GCLK frequency
• TSW means line switching time
• Nscan_line means the scan line number
• Tblank means the blank time in one frame, equals to 0 in ideal configuration
• GSmax means the maximum grayscale that the device can output in one frame
表8-2 gives the values based on the system configuration and equation.
表8-2. LP5891 Design Parameters for GCLK Frequency Calculation
DESIGN PARAMETER
Nsub_period
Nscan_line
TSW
EXAMPLE VALUE
32
30
1.5 µs
0
Tblank
NGCLK_seg
GSmax
512
16383
71.3 MHz
fGCLK
Considering SCLK frequency and FREQ_MUL, the SCLK can be 27.7 MHz, and FREQ_MUL can be 0010b. So
the GCLK is 83.1 MHz.
8.2.1.4 Line Switch Time
The line switch time is digitalized with the GCLK number and can be set by the LINE_SWT (Bit 40-37 in FC1
register). In this application, it is 1.5 us × 83.1 MHz = 125 GCLKs, so the LINE_SWT equals to 0011b (120
GCLKs), the actual line switch time is 1.44 us.
8.2.1.5 Blank Time Removal
The LP5891 has an algorithm to distribute the blank time into each sub-period to prevent the black field when
taking photos or video.
From Equation 3, 83.1-MHz GCLK frequency and 1.44-us line switch time, the calculated blank time is 1.0361
ms ( 86100 GCLK ), which is too long and brings black field.
Here are detailed steps of the algorithm.
Step 1: Distribute blank time into each segment
Copyright © 2022 Texas Instruments Incorporated
52
Submit Document Feedback
Product Folder Links: LP5891
LP5891
www.ti.com.cn
ZHCSQG6A –MARCH 2022 –REVISED MAY 2022
When the blank GCLK number is larger than Nsub_period × Nscan_line, it can be distributed into each segment.
In this application, the blank GCLK number is 86100, and Nsub_period × Nscan_line is 960, so the distributed GCLK
number in each segment is 86100/960 = 89...660. These 89 GCLKs can be used to increase PWM length or
extend line switch time. If used to increase PWM length, the GCLK number in each segment will be 512 + 89 =
601, so the SEG_LENGTH ( Bit9-0 in FC1 register) is 1001011001b.
Step 2: Distribute blank time into each sub-period
If the left GCLK number is larger than Nsub_period, it can be distributed into each sub-period.
In this application, the left GCLK is 660, the distributed GCLK number in each sub-period is 660/32=20. The
BLK_ADJ (Bit46-41 in FC1 register) is 010100b.
After distributing into each sub-period, the left GCLK number is 0.
8.2.1.6 BC and CC
Select the reference current-setting resistor RIREF and configure a proper BC value to set the maximum current
of the RGB LEDs (see Brightness Control (BC) Function for more details). Here the maximum current is 3 mA,
BC value is 03h, according to equation 方程式1, the reference resistor value is 0.8 V/3 mA × 86.61 = 23 kΩ.
Configure the CC_R/CC_G/CC_B registers to set the current of Red/Green/Blue LED current to 3 mA/2 mA/1
mA (see Color Brightness Control (CC) Function for more details).
表8-3 shows the reference current setting resistor RIREF, BC and CC_R/CC_G/CC_B register value.
表8-3. Current Setting Value
DESIGN PARAMETER
EXAMPLE VALUE
23 kΩ
RIREF
BC
011 b
CC_R
CC_G
CC_B
11111110 b
10101001 b
01010100 b
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
53
Product Folder Links: LP5891
LP5891
www.ti.com.cn
ZHCSQG6A –MARCH 2022 –REVISED MAY 2022
8.2.2 Detailed Design Procedure
图8-3 gives a detail design procedure for LED display. After power on and digital signals are ready, the first step
for the controller is to send the chip index command to let the devices know their identifications. Then, the
command sends the configuration data to the FC registers. After this, it sends the VSYNC at the beginning of
each frame and also sends the data to each device. The devices displays the data of last frame when the
VSYNC comes and meanwhile receive the data of current frame transmitted from controller. The registers can
be read at anytime of the frame.
Begin
Power Supply, SCLK/SIN
Ready
Write Chip Index
Configure the
register during
sending data
Write FC Registers
Write SRAM
Write next
frame SRAM
Data in normal
operation
Wait for the end of current
frame
Write VSYNC
Read registers
during each
time of the
frame
Read Chip Index/FC/LOD/LSD
图8-3. Design Procedure for LED Display
8.2.2.1 Chip Index Command
The chip index is used to distribute the address of the devices in a data chain,. Each device gets its unique
address by this command. Details can be found in Chip Index Write Command.
8.2.2.2 FC Registers Settings
Some bits of FC0, FC1, FC2, FC3 registers must be configured properly before the devices work normally. In
this application, the registers value can be:
表8-4. FC Registers Value
FC Registers
FC0
Register Value(BIN)
Register Value(HEX)
1000 583F 0107 h
2AE0 0094 A631 h
0800 000F 0666 h
003B 54A9 FF00 h
0001 0000 0000 0000 0101 1000 0011 1111 0000 0001 0000 0111 b
0010 1010 1110 0000 0000 0000 1001 0100 1010 0110 0011 0001 b
0000 1000 0000 0000 0000 0000 0000 1111 0000 0110 0110 0110 b
0000 0000 0011 1011 0101 0100 1010 1001 1111 1111 0000 0000 b
FC1
FC2
FC3
The controller can configure the FC by the data write command with broadcast mode (see Data Write Command
for more detail), the FC0, FC1 registers are updated after the VSYNC command comes, and the other FC
registers are updated right away regardless the VSYNC command.
Copyright © 2022 Texas Instruments Incorporated
54
Submit Document Feedback
Product Folder Links: LP5891
LP5891
www.ti.com.cn
ZHCSQG6A –MARCH 2022 –REVISED MAY 2022
8.2.2.3 Grayscale Data Write
The channel grayscale data is written to SRAM of the device by the data write command with non-broadcast
way, details can be found in Data Write Command and Write a Frame Data into Memory Book.
Data Write Flow is the data write flow for this application, P (i, j) is the data of pixel locating in I + 1 row and j + 1
column. Suppose channel R15/G15/B15 of each device is not used and not connected, the channel
R14/G14/B14 is connected to P(i, 0), the channel R13/G13/B13 is connected to P (i, 1),…, and channel
R0/G0/B0 is connected to P (i, 14). The data of unused channel must be zero noting D_Zero in below figure, and
D_Zero = 00000000000000001 00000000000000001 00000000000000001b.
i=0
j=15
ST+HB+P(i, jx7)+P(i, jx6)+Y+P(i, jx1)+P(i,0)+END
j=j-1
Write one
line data
N
Write one
frame data
j=0
Y
ST+HB+D_Zero+D_Zero+Y+D_Zero+D_Zero+END
i=i+1
N
i=30
Y
图8-4. Data Write Flow
8.2.2.4 VSYNC Command
The VSYNC is used to sync the display of each frame for the devices in a cascaded chain. Details can be found
in VSYNC Write Command.
8.2.2.5 LED Open/Short Read
FC14, FC15, FC16, FC17, FC18, FC19, FC20, FC21 are the read command for LOD/LSD information. Details
can be found in Read LED-open Information and Read LED-short Information.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
55
Product Folder Links: LP5891
LP5891
www.ti.com.cn
ZHCSQG6A –MARCH 2022 –REVISED MAY 2022
8.2.3 Application Curves
图8-5. Line and Channel Waveform in One Frame
图8-6. Line and Channel Waveform in One
(GSn=0xFFFFh)
Subperiod (GSn=0xFFFFh)
图8-8. Line and Channel Waveform in One Frame
图8-7. Line and Channel Waveform in One Frame
(GSn=0x0001h)
(GSn=0x0001h)
Copyright © 2022 Texas Instruments Incorporated
56
Submit Document Feedback
Product Folder Links: LP5891
LP5891
www.ti.com.cn
ZHCSQG6A –MARCH 2022 –REVISED MAY 2022
9 Power Supply Recommendations
Decouple the VCC power supply voltage by placing a 0.1-μF ceramic capacitor close to VCC pin and GND
plane. Depending on panel size, several electrolytic capacitors must be placed on the board equally distributed
to get well regulated LED supply voltage VR/VG/VB. The ripple of the LED supply voltage must be less than 5%
of their nominal value. Generally, the green and blue LEDs have the similar forward voltage, they can be
supplied by the same power rail.
Furthermore, the VR > Vf(R) + 0.35 V (10-mA constant current example), the VG = VB > Vf (G/B) + 0.35 V (10-
mA constant current example), here Vf(R), Vf(G/B) are representative for the maximum forward voltage of red,
green/blue LEDs.
To simplify the power design, VCC can be connected to the VR power rail.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
57
Product Folder Links: LP5891
LP5891
www.ti.com.cn
ZHCSQG6A –MARCH 2022 –REVISED MAY 2022
10 Layout
10.1 Layout Guidelines
• Place the decoupling capacitor near the VCC/VR, VG/VB pins and GND plane.
• Place the current programming resistor RIREF close to IREF pin and GND plane.
• Route the GND thermal pad as widely as possible for large GND currents. Maximum GND current is
approximately 2 A for two devices (96-CH × 20 mA = 1.92 A).
• The Thermal Pad must be connected to GND plane because the pad is used as power ground pin internally.
There is a large current flow through this pad when all channels turn on. Furthermore, this pad must be
connected to a heat sink layer by thermal via to reduce device temperature. For more information about
suggested thermal via pattern and via size, see PowerPAD™ Thermally Enhanced Package application note.
• Routing between the LED Anode side and the device OUTXn pin must be as short and straight as possible to
reduce wire inductance.
• The line switch pins must be located in the middle of the matrix, which must be laid out as symmetrically as
possible.
10.2 Layout Example
To simplify the system power rails design, VR, VCC must use one power rail and VG, VB use another power rail.
图10-1 gives an example for power rails routing.
Connect the GND pin to the thermal pad on the board with the shortest wire and the thermal pad is connected to
GND plane with the vias, as many as possible to help the power dissipation.
32 RGB LEDs
VR/VCC
C
C
GND
GND
GND
GND
C
GND
C
32 Lines
VG/VB
C
C
GND
GND
T
GND
GND
C
GND
C
VR/VCC
图10-1. Power Rails Routing Suggestion
图 10-2 gives an example for line routing. Connect the line switch to the center of the line bus, so as to uniform
the current flowing from the line switch to the left side and right side LEDs in white grayscale. With this
connection, the unbalance of the parasitic inductor from the routing is the smallest and the display performance
is better, especially in low grayscale condition.
Copyright © 2022 Texas Instruments Incorporated
58
Submit Document Feedback
Product Folder Links: LP5891
LP5891
www.ti.com.cn
ZHCSQG6A –MARCH 2022 –REVISED MAY 2022
图10-2. Line Routing Suggestion
图10-3 gives an example for channel routing with the shortest wire. With this connection, the channel to the LED
path is the shortest, which can reduce the wire inductance, and be a benefit to the performance. However, the
data transmission sequence must be adjusted to follow the pins routing map. For example, R0 connects to
column 15 (LED15 ). The first data must be column 15 (LED15) rather than column 0 (LED0).
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
59
Product Folder Links: LP5891
LP5891
www.ti.com.cn
ZHCSQG6A –MARCH 2022 –REVISED MAY 2022
图10-3. Channel Routing Suggestion with Shortest Wire
图 10-4 gives an example for channel routing with pin number sequence. With this connection, the data
transmission sequence is the same with pin number sequence. For example, R0 connects to column 0 (LED0 ).
The first data is column 0 (LED0). However, with this connection, the inductance for each channel can be
different, which can bring a slight difference for the worst case.
Copyright © 2022 Texas Instruments Incorporated
60
Submit Document Feedback
Product Folder Links: LP5891
LP5891
www.ti.com.cn
ZHCSQG6A –MARCH 2022 –REVISED MAY 2022
图10-4. Channel Routing Suggestion with Channel Order Sequence
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
61
Product Folder Links: LP5891
LP5891
www.ti.com.cn
ZHCSQG6A –MARCH 2022 –REVISED MAY 2022
11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
Texas Instruments, PowerPAD™ Thermally Enhanced Package application note
11.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
Copyright © 2022 Texas Instruments Incorporated
62
Submit Document Feedback
Product Folder Links: LP5891
LP5891
www.ti.com.cn
ZHCSQG6A –MARCH 2022 –REVISED MAY 2022
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
63
Product Folder Links: LP5891
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022，德州仪器 (TI) 公司
相关型号：
LP5900
Ultra Low Noise, 100 mA Linear Regulator for RF/Analog Circuits Requires No Bypass Capacitor
NSC
LP5900
LP5900 Ultra Low Noise, 150 mA Linear Regulator for RF/Analog Circuits Requires No Bypass Capacitor
TI
LP5900SD-1.5
LP5900 Ultra Low Noise, 150 mA Linear Regulator for RF/Analog Circuits Requires No Bypass Capacitor
TI
LP5900SD-1.5/NOPB
LP5900 Ultra Low Noise, 150 mA Linear Regulator for RF/Analog Circuits Requires No Bypass Capacitor
TI
LP5900SD-1.8
LP5900 Ultra Low Noise, 150 mA Linear Regulator for RF/Analog Circuits Requires No Bypass Capacitor
TI
LP5900SD-1.8/NOPB
LP5900 Ultra Low Noise, 150 mA Linear Regulator for RF/Analog Circuits Requires No Bypass Capacitor
TI
©2020 ICPDF网 联系我们和版权申明