LP5907_V04 [TI]
LP5907 250-mA, Ultra-Low-Noise, Low-IQ LDO;
| 型号： | LP5907_V04 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LP5907 250-mA, Ultra-Low-Noise, Low-IQ LDO |
| 文件： | 总47页 (文件大小：2178K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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LP5907
SNVS798O –APRIL 2012–REVISED JUNE 2020
LP5907 250-mA, Ultra-Low-Noise, Low-IQ LDO
1 Features
3 Description
The LP5907 is a low-noise LDO that can supply up to
1
•
•
•
Input voltage range: 2.2 V to 5.5 V
Output voltage range: 1.2 V to 4.5 V
250 mA output current. Designed to meet the
requirements of RF and analog circuits, the LP5907
device provides low noise, high PSRR, low quiescent
current, and low line or load transient response
figures. Using new innovative design techniques, the
LP5907 offers class-leading noise performance
without a noise bypass capacitor and the ability for
remote output capacitor placement.
Stable with 1-µF ceramic input and output
capacitors
•
•
•
•
•
•
•
•
•
•
No noise bypass capacitor required
Remote output capacitor placement
Thermal-overload and short-circuit protection
–40°C to 125°C operating junction temperature
Low output voltage noise: < 6.5 µVRMS
PSRR: 82 dB at 1 kHz
The device is designed to work with a 1-µF input and
a 1-µF output ceramic capacitor (no separate noise
bypass capacitor is required).
Output voltage tolerance: ±2%
This device is available with fixed output voltages
from 1.2 V to 4.5 V in 25-mV steps. Contact Texas
Instruments Sales for specific voltage option needs.
Very low IQ (enabled): 12 µA
Low dropout: 120 mV (typical)
Device Information(1)
Create a custom design using the LP5907 with
the WEBENCH® Power Designer
PART NUMBER
PACKAGE
DSBGA (4)
SOT-23 (5)
X2SON (4)
BODY SIZE
0.645 mm × 0.645 mm (NOM)
2.90 mm × 1.60 mm (NOM)
1.00 mm × 1.00 mm (NOM)
2 Applications
LP5907
•
•
•
•
•
Smartphones
Tablets
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Communications equipment
Digital still cameras
Factory automation
space
space
space
Simplified Schematic
INPUT
IN
OUT
OUTPUT
1 ꢀF
1 ꢀF
LP5907
ENABLE
GND
EN
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LP5907
SNVS798O –APRIL 2012–REVISED JUNE 2020
www.ti.com
Table of Contents
7.4 Device Functional Modes........................................ 13
Application and Implementation ........................ 14
8.1 Application Information............................................ 14
8.2 Typical Application .................................................. 14
Power Supply Recommendations...................... 17
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 4
Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 ESD Ratings.............................................................. 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 6
6.5 Electrical Characteristics........................................... 6
6.6 Output and Input Capacitors..................................... 7
6.7 Typical Characteristics.............................................. 8
Detailed Description ............................................ 12
7.1 Overview ................................................................. 12
7.2 Functional Block Diagram ....................................... 12
7.3 Feature Description................................................. 12
8
9
10 Layout................................................................... 18
10.1 Layout Guidelines ................................................. 18
10.2 Layout Examples................................................... 18
11 Device and Documentation Support ................. 20
11.1 Documentation Support ........................................ 20
11.2 Receiving Notification of Documentation Updates 20
11.3 Support Resources ............................................... 20
11.4 Trademarks........................................................... 20
11.5 Electrostatic Discharge Caution............................ 20
11.6 Glossary................................................................ 20
7
12 Mechanical, Packaging, and Orderable
Information ........................................................... 21
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision N (April 2018) to Revision O
Page
•
•
•
•
Changed Applications section ................................................................................................................................................ 1
Changed DSBGA body size in Device Information table ...................................................................................................... 1
Added YKG to pinout caption of Pin Configuration and Functions section ............................................................................ 4
Added YKG column to Thermal Information table.................................................................................................................. 6
Changes from Revision M (January 2018) to Revision N
Page
•
Added Overshoot on start-up with EN row to Electrical Characteristics table ...................................................................... 7
Changes from Revision L (August 2016) to Revision M
Page
•
•
•
Added links for WEBENCH ................................................................................................................................................... 1
Added information about YKM package option ..................................................................................................................... 1
Added minor editorial changes .............................................................................................................................................. 1
Changes from Revision K (May 2016) to Revision L
Page
•
•
Changed title of data sheet and updated list of Applications and wording of 1st sentence in Description............................ 1
Changed "10 µVRMS" to "6.5 µVRMS" ....................................................................................................................................... 1
Changes from Revision J (March 2016) to Revision K
Page
•
Changed "Linear Regulator" to "LDO" in title and first sentence of Description .................................................................... 1
2
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SNVS798O –APRIL 2012–REVISED JUNE 2020
Changes from Revision I (August 2015) to Revision J
Page
•
Changed VOUT min and max values and VEN min value in Abs Max table and VEN row of ROC table to correct format
errors; replace text of footnote 2 of Abs Max table ............................................................................................................... 5
Changes from Revision H (November 2014) to Revision I
Page
•
•
•
•
Added icon for reference design to Top Navs and "ΔVOUT vs Temperature" graph to Typical Characteristics ..................... 1
Changed Storage Temperature to Abs Max table; replace Handling Ratings with ESD Ratings ......................................... 5
Deleted "VOUT ≥ 1.8 V" from first row of ΔVout spec ............................................................................................................. 6
Added "SOT-23, X2SON packages" to second row of ΔVout spec ...................................................................................... 6
Changes from Revision G (October 2013) to Revision H
Page
•
Added Device Information and Handling Rating tables, Feature Description, Device Functional Modes, Application
and Implementation, Power Supply Recommendations, Layout, Device and Documentation Support, and
Mechanical, Packaging, and Orderable Information sections; moved some curves to Application Curves section ............. 1
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SNVS798O –APRIL 2012–REVISED JUNE 2020
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5 Pin Configuration and Functions
YKE, YKG, and YKM Packages
4-Pin DSBGA
OUT
A2
OUT
IN
IN
A2
A1
A1
B2
B1
B1
B2
EN
GND
GND
EN
BOTTOM VIEW
TOP VIEW
Pin Functions: DSBGA
PIN
I/O
DESCRIPTION
DSBGA
NUMBER
NAME
A1
A2
IN
I
Input voltage supply. Connect a 1-µF capacitor at this input.
Regulated output voltage. Connect a minimum 1-µF low-ESR capacitor to this pin. Connect
this output to the load circuit. An internal 230-Ω (typical) pulldown resistor prevents a charge
remaining on VOUT when the regulator is in the shutdown mode (VEN low).
OUT
O
Enable input. A low voltage (< VIL) on this pin turns the regulator off and discharges the
output pin to GND through an internal 230-Ω pulldown resistor. A high voltage (> VIH) on this
pin enables the regulator output. This pin has an internal 1-MΩ pulldown resistor to hold the
regulator off by default.
B1
B2
EN
I
GND
—
Common ground
DQN Package
4-Pin X2SON
Bottom View
DBV Package
5-Pin SOT-23
Top View
OUT GND
1
2
1
2
3
IN
GND
EN
OUT
N/C
5
4
5
4
3
IN
EN
Pin Functions: X2SON, SOT-23
PIN
I/O
DESCRIPTION
X2SON
NUMBER
SOT-23
NUMBER
NAME
IN
4
1
I
Input voltage supply. Connect a 1-µF capacitor at this input.
Regulated output voltage. Connect a minimum 1-µF low-ESR capacitor to this
pin. Connect this output to the load circuit. An internal 230-Ω (typical) pulldown
resistor prevents a charge remaining on VOUT when the regulator is in the
shutdown mode (VEN low).
OUT
EN
1
3
5
O
Enable input. A low voltage (< VIL) on this pin turns the regulator off and
discharges the output pin to GND through an internal 230-Ω pulldown resistor. A
high voltage (> VIH) on this pin enables the regulator output. This pin has an
internal 1-MΩ pulldown resistor to hold the regulator off by default.
3
I
GND
N/C
2
2
4
—
—
Common ground
—
No internal electrical connection.
Thermal pad for X2SON package, connect to GND or leave floating. Do not
connect to any potential other than GND.
Thermal Pad
5
—
—
4
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SNVS798O –APRIL 2012–REVISED JUNE 2020
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN
–0.3
–0.3
–0.3
MAX
UNIT
VIN
Input voltage
6
See(3)
6
VOUT
VEN
Output voltage
V
Enable input voltage
Continuous power dissipation(4)
Junction temperature
Storage temperature
Internally Limited
W
°C
°C
TJMAX
Tstg
150
150
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to the GND pin.
(3) Abs Max VOUT is the lessor of VIN + 0.3 V, or 6 V.
(4) Internal thermal shutdown circuitry protects the device from permanent damage.
6.2 ESD Ratings
VALUE
±2000
±1000
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN
2.2
0
MAX
UNIT
VIN
VEN
IOUT
TJ
Input supply voltage
Enable input voltage
Output current
5.5
5.5
250
125
85
V
0
mA
°C
Junction temperature
Ambient temperature(3)
–40
–40
TA
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to the GND pin.
(3) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP
=
125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the
part/package in the application (RθJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (RθJA × PD-MAX). See Application and
Implementation.
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6.4 Thermal Information
LP5907
YKE
DBV
(SOT-23)
DQN
YKG
YKM
THERMAL METRIC(1)
UNIT
(X2SON) (DSBGA) (DSBGA) (DSBGA)
5 PINS
193.4
102.1
45.8
8.4
4 PINS
216.1
161.7
162.1
5.1
4 PINS
206.1
1.5
4 PINS
191.6
2.4
4 PINS
194.1
3.0
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
37.0
15.0
36.8
n/a
58.9
1.1
62.7
1.1
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
45.3
n/a
161.7
123.0
58.9
n/a
62.7
n/a
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
VIN = VOUT(NOM) + 1 V, VEN = 1.2 V, IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF (unless otherwise noted)(1)(2)(3)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIN
Input voltage
TA = 25°C
2.2
5.5
V
VIN = (VOUT(NOM) + 1 V) to 5.5 V,
IOUT = 1 mA to 250 mA
–2
2
Output voltage tolerance
Line regulation
%VOUT
VIN = (VOUT(NOM) + 1 V) to 5.5 V,
IOUT = 1 mA to 250 mA
(VOUT < 1.8 V, SOT-23, X2SON packages)
–3
3
ΔVOUT
VIN = (VOUT(NOM) + 1 V) to 5.5 V,
IOUT = 1 mA
0.02
%/V
Load regulation
IOUT = 1 mA to 250 mA
See(4)
0.001
%/mA
mA
Load current
0
250
ILOAD
Maximum output current
250
VEN = 1.2 V, IOUT = 0 mA
VEN = 1.2 V, IOUT = 250 mA
VEN = 0.3 V (disabled)
12
250
0.2
14
25
425
1
IQ
Quiescent current(5)
Ground current(6)
µA
µA
IG
VEN = 1.2 V, IOUT = 0 mA
IOUT = 100 mA
50
VDO
Dropout voltage(7)
IOUT = 250 mA (DSBGA package)
IOUT = 250 mA (SOT-23, X2SON packages)
TA = 25°C(8)
120
200
250
mV
mA
ISC
Short-circuit current limit
250
500
(1) All voltages are with respect to the device GND terminal, unless otherwise stated.
(2) Minimum and maximum limits are ensured through test, design, or statistical correlation over the junction temperature (TJ) range of
–40°C to 125°C, unless otherwise stated. Typical values represent the most likely parametric norm at TA = 25°C, and are provided for
reference purposes only.
(3) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP
=
125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the
part/package in the application RθJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (RθJA × PD-MAX). See Application and
Implementation.
(4) The device maintains a stable, regulated output voltage without a load current.
(5) Quiescent current is defined here as the difference in current between the input voltage source and the load at VOUT
.
(6) Ground current is defined here as the total current flowing to ground as a result of all input voltages applied to the device.
(7) Dropout voltage is the voltage difference between the input and the output at which the output voltage drops to 100 mV below its
nominal value.
(8) Short-circuit current (ISC) for the LP5907 is equivalent to current limit. To minimize thermal effects during testing, ISC is measured with
VOUT pulled to 100 mV below its nominal voltage.
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SNVS798O –APRIL 2012–REVISED JUNE 2020
Electrical Characteristics (continued)
VIN = VOUT(NOM) + 1 V, VEN = 1.2 V, IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF (unless otherwise noted)(1)(2)(3)
PARAMETER
TEST CONDITIONS
f = 100 Hz, IOUT = 20 mA
MIN
TYP
90
MAX
UNIT
f = 1 kHz, IOUT = 20 mA
f = 10 kHz, IOUT = 20 mA
f = 100 kHz, IOUT = 20 mA
82
PSRR
Power-supply rejection ratio(9)
dB
65
60
IOUT = 1 mA
10
eN
Output noise voltage(9)
BW = 10 Hz to 100 kHz
µVRMS
Ω
IOUT = 250 mA
6.5
Output automatic discharge
pulldown resistance
RAD
TSD
VEN < VIL (output disabled)
230
Thermal shutdown
Thermal hysteresis
TJ rising
160
15
°C
TJ falling from shutdown
LOGIC INPUT THRESHOLDS
VIN = 2.2 V to 5.5 V,
VEN falling until the output is disabled
VIL
VIH
Low input threshold
High input threshold
0.4
V
V
VIN = 2.2 V to 5.5 V
VEN rising until the output is enabled
1.2
VEN = 5.5 V and VIN = 5.5 V
VEN = 0 V and VIN = 5.5 V
5.5
IEN
Input current at EN pin(10)
µA
0.001
TRANSIENT CHARACTERISTICS
VIN = (VOUT(NOM) + 1 V) to
(VOUT(NOM) + 1.6 V) in 30 µs
–1
Line transient(9)
VIN = (VOUT(NOM) + 1.6 V) to
(VOUT(NOM) + 1.6 V) in 30 µs
1
mV
IOUT = 1 mA to 250 mA in 10 µs
–40
Load transient(9)
ΔVOUT
IOUT = 250 mA to 1 mA in 10 µs
40
Overshoot on start-up(9)
Stated as a percentage of VOUT(NOM)
Stated as a percentage of VOUT(NOM), VIN
5%
=
VOUT + 1 V to 5.5 V, 0.7 µF < COUT < 10 µF,
0 mA < IOUT < 250 mA, EN rising until the
output is enabled
Overshoot on start-up with EN(9)
1%
From VEN > VIH to VOUT = 95% of VOUT(NOM)
TA = 25°C
,
tON
Turnon time
80
150
µs
(9) This specification is verified by design.
(10) There is a 1-MΩ resistor between EN and ground on the device.
6.6 Output and Input Capacitors
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN(1)
TYP
MAX
UNIT
µF
CIN
Input capacitance(2)
Output capacitance(2)
Output/Input capacitance(2)
0.7
0.7
5
1
1
Capacitance for stability
COUT
ESR
10
µF
500
mΩ
(1) The minimum capacitance should be greater than 0.5 µF over the full range of operating conditions. The capacitor tolerance should be
30% or better over the full temperature range. The full range of operating conditions for the capacitor in the application must be
considered during device selection to ensure this minimum capacitance specification is met. X7R capacitors are recommended however
capacitor types X5R, Y5V and Z5U may be used with consideration of the application and conditions.
(2) This specification is verified by design.
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6.7 Typical Characteristics
VIN = 3.7 V, VOUT = 2.8 V, IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF, and TA = 25°C (unless otherwise noted)
1
0.9
0.8
0.7
0.6
0.5
16
14
12
10
8
6
4
2
VIH Rising
VIL Falling
0
2.3 2.8 3.3 3.8 4.3 4.8 5.3 5.8
(V)
2
2.5
3
3.5
4
VIN (V)
4.5
5
5.5
6
V
IN
D001
SVA-30180569
Figure 2. VEN Thresholds vs VIN
Figure 1. Quiescent Current vs Input Voltage
1.4
1.2
1
5
4.5
4
3.5
3
0.8
0.6
0.4
0.2
0
2.5
2
1.5
1
RLOAD = 1.2 kW
RLOAD = 4.8 W
RLOAD = 4.5 kW
RLOAD = 18 W
0.5
0
0
0.5
1
1.5
2
2.5
0
1
2
3
VIN (V)
4
5
6
VIN (V)
D002
D003
VOUT = 1.2 V, VEN = VIN
VOUT = 4.5 V, VEN = VIN
Figure 4. VOUT vs VIN
Figure 3. VOUT vs VIN
350
300
250
200
150
100
50
2.900
2.875
2.850
2.825
2.800
2.775
2.750
2.725
2.700
V
= 3.6V
IN
VIN = 3.0V
VIN = 3.8V
VIN = 4.2V
VIN = 5.5V
-40°C
90°C
25°C
0
0
50 100 150 200 250 300
(mA)
0
50
100
150
200
250
LOAD (mA)
I
OUT
SVA-30180567
SVA-30180571
Figure 6. Load Regulation
Figure 5. Ground Current vs Output Current
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Typical Characteristics (continued)
VIN = 3.7 V, VOUT = 2.8 V, IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF, and TA = 25°C (unless otherwise noted)
0.2
0.1
0
2.900
2.875
2.850
2.825
2.800
2.775
2.750
2.725
2.700
Load = 10 mA
-0.1
-0.2
-0.3
-0.4
-40°C
90°C
25°C
3.0
3.5
4.0
V
4.5
(V)
5.0
5.5
-50
-25
0
25
50
75
100
125
D010
IN
Junction Temperature (èC)
SVA-30180568
Figure 8. Line Regulation
Figure 7. ΔVOUT vs Temperature
2V/DIV
V
10 mV/
DIV
OUT
V
OUT
(AC Coupled)
2V/DIV
V
IN
V
V
IN = EN
1V/DIV
1A/DIV
I
IN
2 ms/DIV
10 ꢀs/DIV
SVA-30180509
SVA-30180510
VIN = 3.2 V ↔ 4.2 V, load = 1 mA
Figure 9. Inrush Current
Figure 10. Line Transient
V
10 mV/
DIV
OUT
V
OUT
100 mV/DIV
(AC Coupled)
V
1V/DIV
IN
200 mA/DIV
LOAD
10 ꢀs/DIV
100 ꢀs/DIV
SVA-30180511
SVA-30180512
VIN = 3.2 V ↔ 4.2 V, load = 250 mA
Load = 0 mA ↔ 250 mA, –40°C
Figure 11. Line Transient
Figure 12. Load Transient
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Typical Characteristics (continued)
VIN = 3.7 V, VOUT = 2.8 V, IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF, and TA = 25°C (unless otherwise noted)
V
OUT
100 mV/DIV
100 mV/DIV
V
OUT
LOAD
200 mA/DIV
LOAD
200 mA/DIV
100 ꢀs/DIV
100 ꢀs/DIV
SVA-30180513
SVA-30180514
Load = 0 mA ↔ 250 mA, 90°C
Load = 0 mA ↔ 250 mA, 25°C
Figure 13. Load Transient
Figure 14. Load Transient
1V/DIV
1V/DIV
V
OUT
V
OUT
1V/DIV
1V/DIV
EN
EN
20 ꢀs/DIV
20 ꢀs/DIV
SVA-30180516
SVA-30180515
Load = 250 mA
Load = 0 mA
Figure 15. Start-Up
Figure 16. Start-Up
140
120
100
80
60
40
Dropout Voltage
20
0
0
50
100
150
200
250
LOAD CURRENT (mA)
SVA-30180573
Figure 18. Dropout Voltage vs Load Current
Figure 17. Noise Density Test
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Typical Characteristics (continued)
VIN = 3.7 V, VOUT = 2.8 V, IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF, and TA = 25°C (unless otherwise noted)
0
0
250 mA
200 mA
150 mA
100 mA
50 mA
-20
-20
-40
-40
20 mA
-60
-60
250 mA
200 mA
150 mA
100 mA
50 mA
-80
-80
-100
-100
20 mA
-120
-120
0.1
1
10
100
0.01
0.1
1
10
FREQUENCY (kHz)
100
1000
10000
FREQUENCY (kHz)
D004
D005
Figure 19. PSRR Loads Averaged 100 Hz to 100 kHz
Figure 20. PSRR Loads Averaged 10 Hz to 10 MHz
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7 Detailed Description
7.1 Overview
Designed to meet the needs of sensitive RF and analog circuits, the LP5907 provides low noise, high PSRR, low
quiescent current, as well as low line and load transient response figures. Using new innovative design
techniques, the LP5907 offers class leading noise performance without the need for a separate noise filter
capacitor.
The LP5907 is designed to perform with a single 1-µF input capacitor and a single 1-µF ceramic output
capacitor. With a reasonable PCB layout, the single 1-µF ceramic output capacitor can be placed up to 10 cm
away from the LP5907 device.
7.2 Functional Block Diagram
OUT
IN
POR
EN
EN
+
R
F
C
F
+
V
BG
R
AD
1.20V
EN
EN
+
EN
1 Mꢀ
VIH
GND
7.3 Feature Description
7.3.1 Enable (EN)
The LP5907 EN pin is internally held low by a 1-MΩ resistor to GND. The EN pin voltage must be higher than the
VIH threshold to ensure that the device is fully enabled under all operating conditions. The EN pin voltage must
be lower than the VIL threshold to ensure that the device is fully disabled and the automatic output discharge is
activated.
7.3.2 Low Output Noise
Any internal noise at the LP5907 reference voltage is reduced by a first order low-pass RC filter before it is
passed to the output buffer stage. The low-pass RC filter has a –3 dB cut-off frequency of approximately 0.1 Hz.
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Feature Description (continued)
7.3.3 Output Automatic Discharge
The LP5907 output employs an internal 230-Ω (typical) pulldown resistance to discharge the output when the EN
pin is low, and the device is disabled.
7.3.4 Remote Output Capacitor Placement
The LP5907 requires at least a 1-µF capacitor at the OUT pin, but there are no strict requirements about the
location of the capacitor in regards the OUT pin. In practical designs, the output capacitor may be located up to
10 cm away from the LDO.
7.3.5 Thermal Overload Protection (TSD
)
Thermal shutdown disables the output when the junction temperature rises to approximately 160°C which allows
the device to cool. When the junction temperature cools to approximately 145°C, the output circuitry enables.
Based on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may
cycle on and off. This thermal cycling limits the dissipation of the regulator and protects it from damage as a
result of overheating.
The thermal shutdown circuitry of the LP5907 has been designed to protect against temporary thermal overload
conditions. The TSD circuitry was not intended to replace proper heat-sinking. Continuously running the LP5907
device into thermal shutdown may degrade device reliability.
7.4 Device Functional Modes
7.4.1 Enable (EN)
The LP5907 Enable (EN) pin is internally held low by a 1-MΩ resistor to GND. The EN pin voltage must be
higher than the VIH threshold to ensure that the device is fully enabled under all operating conditions.
When the EN pin is pulled low, and the output is disabled, the output automatic discharge circuitry is activated.
Any charge on the OUT pin is discharged to GND through the internal 230-Ω (typical) pulldown resistance.
7.4.2 Minimum Operating Input Voltage (VIN)
The LP5907 does not include any dedicated UVLO circuitry. The LP5907 internal circuitry is not fully functional
until VIN is at least 2.2 V. The output voltage is not regulated until VIN has reached at least the greater of 2.2 V or
(VOUT + VDO).
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LP5907 is designed to meet the requirements of RF and analog circuits, by providing low noise, high PSRR,
low quiescent current, and low line or load transient response figures. The device offers excellent noise
performance without the need for a noise bypass capacitor and is stable with input and output capacitors with a
value of 1 µF. The LP5907 delivers this performance in industry standard packages such as DSBGA, X2SON,
and SOT-23 which, for this device, are specified with an operating junction temperature (TJ) of –40°C to 125°C.
8.2 Typical Application
Figure 21 shows the typical application circuit for the LP5907. Input and output capacitances may need to be
increased above the 1 µF minimum for some applications.
INPUT
IN
OUT
OUTPUT
1 ꢀF
1 ꢀF
LP5907
ENABLE
GND
EN
GND
Figure 21. LP5907 Typical Application
8.2.1 Design Requirements
DESIGN PARAMETER
EXAMPLE VALUE
2.2 V to 5.5 V
1.8 V
Input voltage range
Output voltage
Output current
200 mA
Output capacitor range
Input/Output capacitor ESR range
0.7 µF to 10 µF
5 to 500 mΩ
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8.2.2 Detailed Design Procedure
8.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LP5907 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
•
•
•
•
Run electrical simulations to see important waveforms and circuit performance
Run thermal simulations to understand board thermal performance
Export customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.2.2 Power Dissipation and Device Operation
The permissible power dissipation for any package is a measure of the capability of the device to pass heat from
the power source, the junctions of the IC, to the ultimate heat sink, the ambient environment. Thus, the power
dissipation is dependent on the ambient temperature and the thermal resistance across the various interfaces
between the die junction and ambient air.
The maximum allowable power dissipation for the device in a given package can be calculated using Equation 1:
PD-MAX = ((TJ-MAX – TA) / RθJA
)
(1)
The actual power being dissipated in the device can be represented by Equation 2:
PD = (VIN – VOUT) × IOUT
(2)
These two equations establish the relationship between the maximum power dissipation allowed due to thermal
consideration, the voltage drop across the device, and the continuous current capability of the device. These two
equations should be used to determine the optimum operating conditions for the device in the application.
In applications where lower power dissipation (PD) and/or excellent package thermal resistance (RθJA) is present,
the maximum ambient temperature (TA-MAX) may be increased.
In applications where high power dissipation and/or poor package thermal resistance is present, the maximum
ambient temperature (TA-MAX) may have to be derated. TA-MAX is dependent on the maximum operating junction
temperature (TJ-MAX-OP = 125°C), the maximum allowable power dissipation in the device package in the
application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (RθJA),
as given by Equation 3:
TA-MAX = (TJ-MAX-OP – (RθJA × PD-MAX))
(3)
Alternately, if TA-MAX can not be derated, the PD value must be reduced. This can be accomplished by reducing
VIN in the VIN–VOUT term as long as the minimum VIN is met, or by reducing the IOUT term, or by some
combination of the two.
8.2.2.3 External Capacitors
Like most low-dropout regulators, the LP5907 requires external capacitors for regulator stability. The device is
specifically designed for portable applications requiring minimum board space and smallest components. These
capacitors must be correctly selected for good performance.
8.2.2.4 Input Capacitor
An input capacitor is required for stability. The input capacitor should be at least equal to, or greater than, the
output capacitor for good load transient performance. At least a 1 µF capacitor has to be connected between the
LP5907 input pin and ground for stable operation over full load current range. Basically, it is ok to have more
output capacitance than input, as long as the input is at least 1 µF.
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The input capacitor must be located a distance of not more than 1 cm from the input pin and returned to a clean
analog ground. Any good quality ceramic, tantalum, or film capacitor may be used at the input.
NOTE
To ensure stable operation it is essential that good PCB practices are employed to
minimize ground impedance and keep input inductance low. If these conditions cannot be
met, or if long leads are to be used to connect the battery or other power source to the
LP5907, TI recommends increasing the input capacitor to at least 10 µF. Also, tantalum
capacitors can suffer catastrophic failures due to surge current when connected to a low-
impedance source of power (like a battery or a very large capacitor). If a tantalum
capacitor is used at the input, it should be verified by the manufacturer to have a surge
current rating sufficient for the application. The initial tolerance, applied voltage de-rating,
and temperature coefficient must all be considered when selecting the input capacitor to
ensure the actual capacitance is never less than 0.7 µF over the entire operating range.
8.2.2.5 Output Capacitor
The LP5907 is designed specifically to work with a very small ceramic output capacitor, typically 1 µF. A ceramic
capacitor (dielectric types X5R or X7R) in the 1 µF to 10 µF range, and with ESR between 5 mΩ to 500 mΩ, is
suitable in the LP5907 application circuit. For this device the output capacitor should be connected between the
OUT pin and a good connection back to the GND pin.
It may also be possible to use tantalum or film capacitors at the device output, VOUT, but these are not as
attractive for reasons of size and cost (see Capacitor Characteristics).
The output capacitor must meet the requirement for the minimum value of capacitance and have an ESR value
that is within the range 5 mΩ to 500 mΩ for stability. Like the input capacitor, the initial tolerance, applied voltage
de-rating, and temperature coefficient must all be considered when selecting the input capacitor to ensure the
actual capacitance is never less than 0.7 µF over the entire operating range.
8.2.2.6 Capacitor Characteristics
The LP5907 is designed to work with ceramic capacitors on the input and output to take advantage of the
benefits they offer. For capacitance values in the range of 1 µF to 10 µF, ceramic capacitors are the smallest,
least expensive and have the lowest ESR values, thus making them best for eliminating high frequency noise.
The ESR of a typical 1 µF ceramic capacitor is in the range of 20 mΩ to 40 mΩ, which easily meets the ESR
requirement for stability for the LP5907.
A better choice for temperature coefficient in a ceramic capacitor is X7R. This type of capacitor is the most stable
and holds the capacitance within ±15% over the temperature range. Tantalum capacitors are less desirable than
ceramic for use as output capacitors because they are more expensive when comparing equivalent capacitance
and voltage ratings in the 1 µF to 10 µF range.
Another important consideration is that tantalum capacitors have higher ESR values than equivalent size
ceramics. This means that while it may be possible to find a tantalum capacitor with an ESR value within the
stable range, it would have to be larger in capacitance (which means bigger and more costly) than a ceramic
capacitor with the same ESR value. It should also be noted that the ESR of a typical tantalum increases about
2:1 as the temperature goes from 25°C down to –40°C, so some guard band must be allowed.
8.2.2.7 Remote Capacitor Operation
The LP5907 requires at least a 1-µF capacitor at the OUT pin, but there is no strict requirements about the
location of the capacitor in regards to the pin. In practical designs the output capacitor may be located up to 10
cm away from the LDO. This means that there is no need to have a special capacitor close to the output pin if
there is already respective capacitors in the system (like a capacitor at the input of supplied part). The remote
capacitor feature helps user to minimize the number of capacitors in the system.
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As a good design practice, keep the wiring parasitic inductance at a minimum, which means to use as wide as
possible traces from the LDO output to the capacitors, keeping the LDO output trace layer as close to ground
layer as possible and avoiding vias on the path. If there is a need to use vias, implement as many as possible
vias between the connection layers. The recommendation is to keep parasitic wiring inductance less than 35 nH.
For the applications with fast load transients, it is recommended to use an input capacitor equal to or larger to
the sum of the capacitance at the output node for the best load transient performance.
8.2.2.8 No-Load Stability
The LP5907 remains stable, and in regulation, with no external load.
8.2.2.9 Enable Control
The LP5907 may be switched ON or OFF by a logic input at the EN pin. A voltage on this pin greater than VIH
turns the device on, while a voltage less than VIL turns the device off.
When the EN pin is low, the regulator output is off and the device typically consumes less than 1 µA.
Additionally, an output pulldown circuit is activated which ensures that any charge stored on COUT is discharged
to ground.
If the application does not require the use of the shutdown feature, the EN pin can be tied directly to the IN pin to
keep the regulator output permanently on.
An internal 1-MΩ pulldown resistor ties the EN input to ground, ensuring that the device remains off if the EN pin
is left open circuit. To ensure proper operation, the signal source used to drive the EN pin must be able to swing
above and below the specified turnon or turnoff voltage thresholds listed in the Electrical Characteristics under
VIL and VIH.
8.2.3 Application Curves
1V/DIV
100 mV/DIV
V
OUT
V
OUT
1V/DIV
LOAD
200 mA/DIV
EN
100 ꢀs/DIV
20 ꢀs/DIV
SVA-30180514
SVA-30180515
Figure 23. Load Transient Response
Figure 22. Start-Up
9 Power Supply Recommendations
This device is designed to operate from an input supply voltage range of 2.2 V to 5.5 V. The input supply must
be well regulated and free of spurious noise. To ensure that the LP5907 output voltage is well regulated and
dynamic performance is optimum, the input supply must be at least VOUT + 1 V. A minimum capacitor value of 1
µF is required to be within 1 cm of the IN pin.
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10 Layout
10.1 Layout Guidelines
The dynamic performance of the LP5907 is dependant on the layout of the PCB. PCB layout practices that are
adequate for typical LDOs may degrade the PSRR, noise, or transient performance of the LP5907.
Best performance is achieved by placing CIN and COUT on the same side of the PCB as the LP5907, and as
close to the package as is practical. The ground connections for CIN and COUT must be back to the LP5907
ground pin using as wide and short a copper trace as is practical.
Connections using long trace lengths, narrow trace widths, and/or connections through vias must be avoided.
These add parasitic inductances and resistance that results in inferior performance especially during transient
conditions
10.1.1 X2SON Mounting
The X2SON package thermal pad must be soldered to the printed circuit board for proper thermal and
mechanical performance. For more information, see the QFN/SON PCB Attachment application report.
10.1.2 DSBGA Mounting
The DSBGA package requires specific mounting techniques, which are detailed in AN-1112 DSBGA Wafer Level
Chip Scale Package. For best results during assembly, alignment ordinals on the PC board may be used to
facilitate placement of the DSBGA device.
10.1.3 DSBGA Light Sensitivity
Exposing the DSBGA device to direct light may cause incorrect operation of the device. Light sources such as
halogen lamps can affect electrical performance if they are situated in proximity to the device. Light with
wavelengths in the red and infrared part of the spectrum have the most detrimental effect; thus, the fluorescent
lighting used inside most buildings has very little effect on performance.
10.2 Layout Examples
V
V
OUT
IN
C
IN
OUT
5
C
1
2
3
OUT
IN
GND
GND
GND
EN
Enable
4
N/C
Figure 24. LP5907MF-x.x (SOT-23) Typical Layout
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Layout Examples (continued)
LP5907SN
VOUT
VIN
1
4
3
COUT
CIN
2
Power Ground
VEN
Figure 25. LP5907SN-xx (X2SON) Typical Layout
VIN
VOUT
LP5907UV
A1
A2
B2
COUT
CIN
B1
Power Ground
VEN
Figure 26. LP5907A/UV-x.x (DSBGA) Typical Layout
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LP5907 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
•
•
•
•
Run electrical simulations to see important waveforms and circuit performance
Run thermal simulations to understand board thermal performance
Export customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
11.1.2 Related Documentation
For related documentation, see the following:
•
•
Texas Instruments, AN-1112 DSBGA Wafer Level Chip Scale Package application note
Texas Instruments, QFN/SON PCB Attachment application report
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
9-Oct-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
YKM
YKM
YKM
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DQN
Qty
(1)
(2)
(3)
(4/5)
(6)
LP5907A28YKMR
LP5907A29YKMR
ACTIVE
DSBGA
DSBGA
DSBGA
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
X2SON
4
4
4
5
5
5
5
5
5
5
5
5
5
5
5
4
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
Green (RoHS
& no Sb/Br)
SAC396
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
Q
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Green (RoHS
& no Sb/Br)
SAC396
SAC396
SN
Y
LP5907A33YKMR
Green (RoHS
& no Sb/Br)
N
LP5907MFX-1.2/NOPB
LP5907MFX-1.5/NOPB
LP5907MFX-1.8/NOPB
LP5907MFX-2.5/NOPB
LP5907MFX-2.8/NOPB
LP5907MFX-2.85/NOPB
LP5907MFX-2.9/NOPB
LP5907MFX-3.0/NOPB
LP5907MFX-3.1/NOPB
LP5907MFX-3.2/NOPB
LP5907MFX-3.3/NOPB
LP5907MFX-4.5/NOPB
LP5907SNX-1.2/NOPB
Green (RoHS
& no Sb/Br)
LLTB
LN8B
LLUB
LN7B
LLYB
LN4B
1E5X
LLZB
LN5B
LN6B
LLVB
LLXB
CF
Green (RoHS
& no Sb/Br)
SN
Green (RoHS
& no Sb/Br)
SN
Green (RoHS
& no Sb/Br)
SN
Green (RoHS
& no Sb/Br)
SN
Green (RoHS
& no Sb/Br)
SN
Green (RoHS
& no Sb/Br)
SN
Green (RoHS
& no Sb/Br)
SN
Green (RoHS
& no Sb/Br)
SN
Green (RoHS
& no Sb/Br)
SN
Green (RoHS
& no Sb/Br)
SN
Green (RoHS
& no Sb/Br)
SN
Green (RoHS
& no Sb/Br)
NIPDAU
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
9-Oct-2020
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
DQN
DQN
DQN
DQN
DQN
DQN
DQN
DQN
DQN
DQN
DQN
DQN
DQN
DQN
DQN
YKE
Qty
(1)
(2)
(3)
(4/5)
(6)
LP5907SNX-1.8/NOPB
LP5907SNX-1.9
ACTIVE
X2SON
X2SON
X2SON
X2SON
X2SON
X2SON
X2SON
X2SON
X2SON
X2SON
X2SON
X2SON
X2SON
X2SON
X2SON
DSBGA
DSBGA
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
250
Green (RoHS
& no Sb/Br)
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
CG
3Z
EP
F9
CH
HI
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Green (RoHS
& no Sb/Br)
NIPDAU
NIPDAU
NIPDAU
NIPDAU
LP5907SNX-2.2/NOPB
LP5907SNX-2.5/NOPB
LP5907SNX-2.7/NOPB
LP5907SNX-2.75
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS NIPDAU | NIPDAUAG Level-1-260C-UNLIM
& no Sb/Br)
LP5907SNX-2.8/NOPB
LP5907SNX-2.85/NOPB
LP5907SNX-2.9/NOPB
LP5907SNX-3.0/NOPB
LP5907SNX-3.1/NOPB
LP5907SNX-3.2/NOPB
LP5907SNX-3.3/NOPB
LP5907SNX-4.0/NOPB
LP5907SNX-4.5/NOPB
LP5907UVE-1.2/NOPB
LP5907UVE-1.8/NOPB
Green (RoHS
& no Sb/Br)
NIPDAU
Level-1-260C-UNLIM
CI
Green (RoHS NIPDAU | NIPDAUAG Level-1-260C-UNLIM
& no Sb/Br)
CJ
GV
CK
CL
CM
CN
GU
CO
R
Green (RoHS
& no Sb/Br)
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS NIPDAU | NIPDAUAG Level-1-260C-UNLIM
& no Sb/Br)
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
YKE
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
S
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
9-Oct-2020
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
YKE
YKE
YKE
YKE
YKE
YKE
YKE
YKE
YKE
YKE
YKE
YKE
YKE
YKE
YKE
YKE
YKE
Qty
(1)
(2)
(3)
(4/5)
(6)
LP5907UVE-2.8/NOPB
LP5907UVE-2.85/NOPB
LP5907UVE-3.0/NOPB
LP5907UVE-3.1/NOPB
LP5907UVE-3.2/NOPB
LP5907UVE-3.3/NOPB
LP5907UVE-4.5/NOPB
LP5907UVX-1.2/NOPB
LP5907UVX-1.6/NOPB
LP5907UVX-1.8/NOPB
LP5907UVX-2.2/NOPB
LP5907UVX-2.5/NOPB
LP5907UVX-2.8/NOPB
LP5907UVX-2.85/NOPB
LP5907UVX-3.0/NOPB
LP5907UVX-3.1/NOPB
LP5907UVX-3.2/NOPB
ACTIVE
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
U
V
B
X
C
D
Z
R
J
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
250
Green (RoHS
& no Sb/Br)
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SAC396
250
Green (RoHS
& no Sb/Br)
250
Green (RoHS
& no Sb/Br)
250
Green (RoHS
& no Sb/Br)
250
Green (RoHS
& no Sb/Br)
250
Green (RoHS
& no Sb/Br)
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
SNAGCU
SAC396
S
5
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
E
U
V
B
X
C
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
9-Oct-2020
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LP5907UVX-3.3/NOPB
LP5907UVX-4.5/NOPB
LP5907UVX19/NOPB
LP5907UVX37/NOPB
LP5907YKGR-2.0
ACTIVE
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
YKE
4
4
4
4
4
4
4
4
3000
3000
3000
3000
3000
3000
3000
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
D
Z
8
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
YKE
Green (RoHS
& no Sb/Br)
SNAGCU
SNAGCU
SNAGCU
Call TI
YKE
Green (RoHS
& no Sb/Br)
YKE
Green (RoHS
& no Sb/Br)
9
YKG
YKG
YKG
YKG
Green (RoHS
& no Sb/Br)
W
3
LP5907YKGR-2.8
Green (RoHS
& no Sb/Br)
Call TI
LP5907YKGR-2.825
LP5907YKGR-2.85
Green (RoHS
& no Sb/Br)
Call TI
5
Green (RoHS
& no Sb/Br)
SAC396
P
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 4
PACKAGE OPTION ADDENDUM
www.ti.com
9-Oct-2020
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF LP5907 :
Automotive: LP5907-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 5
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Oct-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LP5907A28YKMR
LP5907A29YKMR
LP5907A33YKMR
DSBGA
DSBGA
DSBGA
YKM
YKM
YKM
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DQN
DQN
DQN
4
4
4
5
5
5
5
5
5
5
5
5
5
5
5
4
4
4
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
180.0
180.0
180.0
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
9.5
9.5
9.5
0.74
0.74
0.74
3.2
0.74
0.74
0.74
3.2
0.54
0.54
0.54
1.4
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q1
Q1
Q1
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q2
Q2
Q2
LP5907MFX-1.2/NOPB SOT-23
LP5907MFX-1.5/NOPB SOT-23
LP5907MFX-1.8/NOPB SOT-23
LP5907MFX-2.5/NOPB SOT-23
LP5907MFX-2.8/NOPB SOT-23
LP5907MFX-2.85/NOPB SOT-23
LP5907MFX-2.9/NOPB SOT-23
LP5907MFX-3.0/NOPB SOT-23
LP5907MFX-3.1/NOPB SOT-23
LP5907MFX-3.2/NOPB SOT-23
LP5907MFX-3.3/NOPB SOT-23
LP5907MFX-4.5/NOPB SOT-23
LP5907SNX-1.2/NOPB X2SON
LP5907SNX-1.8/NOPB X2SON
3.2
3.2
1.4
3.2
3.2
1.4
3.2
3.2
1.4
3.2
3.2
1.4
3.2
3.2
1.4
3.2
3.2
1.4
3.2
3.2
1.4
3.2
3.2
1.4
3.2
3.2
1.4
3.2
3.2
1.4
3.2
3.2
1.4
1.16
1.16
1.16
1.16
1.16
1.16
0.63
0.63
0.63
LP5907SNX-1.9
X2SON
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Oct-2020
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LP5907SNX-2.2/NOPB X2SON
LP5907SNX-2.5/NOPB X2SON
LP5907SNX-2.7/NOPB X2SON
DQN
DQN
DQN
DQN
DQN
DQN
DQN
DQN
DQN
DQN
DQN
DQN
DQN
YKE
YKE
YKE
YKE
YKE
YKE
YKE
YKE
YKE
YKE
YKE
YKE
YKE
YKE
YKE
YKE
YKE
YKE
YKE
YKE
YKE
YKE
YKE
YKE
YKE
YKE
YKE
YKE
YKE
YKE
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
250
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
9.5
9.5
9.5
9.5
9.5
9.5
9.5
9.5
9.5
9.5
9.5
9.5
9.5
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
1.16
1.16
1.16
1.16
1.16
1.16
1.16
1.16
1.16
1.16
1.16
1.16
1.16
0.74
0.71
0.71
0.74
0.71
0.74
0.74
0.71
0.71
0.74
0.74
0.71
0.71
0.74
0.74
0.71
0.71
0.74
0.71
0.74
0.74
0.71
0.74
0.74
0.71
0.74
0.71
0.74
0.71
0.71
1.16
1.16
1.16
1.16
1.16
1.16
1.16
1.16
1.16
1.16
1.16
1.16
1.16
0.74
0.71
0.71
0.74
0.71
0.74
0.74
0.71
0.71
0.74
0.74
0.71
0.71
0.74
0.74
0.71
0.71
0.74
0.71
0.74
0.74
0.71
0.74
0.74
0.71
0.74
0.71
0.74
0.71
0.71
0.63
0.63
0.63
0.63
0.63
0.63
0.63
0.63
0.63
0.63
0.63
0.63
0.63
0.5
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
LP5907SNX-2.75
X2SON
LP5907SNX-2.8/NOPB X2SON
LP5907SNX-2.85/NOPB X2SON
LP5907SNX-2.9/NOPB X2SON
LP5907SNX-3.0/NOPB X2SON
LP5907SNX-3.1/NOPB X2SON
LP5907SNX-3.2/NOPB X2SON
LP5907SNX-3.3/NOPB X2SON
LP5907SNX-4.0/NOPB X2SON
LP5907SNX-4.5/NOPB X2SON
LP5907UVE-1.2/NOPB DSBGA
LP5907UVE-1.2/NOPB DSBGA
LP5907UVE-1.8/NOPB DSBGA
LP5907UVE-1.8/NOPB DSBGA
LP5907UVE-2.8/NOPB DSBGA
LP5907UVE-2.8/NOPB DSBGA
LP5907UVE-2.85/NOPB DSBGA
LP5907UVE-2.85/NOPB DSBGA
LP5907UVE-3.0/NOPB DSBGA
LP5907UVE-3.0/NOPB DSBGA
LP5907UVE-3.1/NOPB DSBGA
LP5907UVE-3.1/NOPB DSBGA
LP5907UVE-3.2/NOPB DSBGA
LP5907UVE-3.2/NOPB DSBGA
LP5907UVE-3.3/NOPB DSBGA
LP5907UVE-3.3/NOPB DSBGA
LP5907UVE-4.5/NOPB DSBGA
LP5907UVE-4.5/NOPB DSBGA
LP5907UVX-1.2/NOPB DSBGA
LP5907UVX-1.2/NOPB DSBGA
LP5907UVX-1.6/NOPB DSBGA
LP5907UVX-1.8/NOPB DSBGA
LP5907UVX-1.8/NOPB DSBGA
LP5907UVX-2.2/NOPB DSBGA
LP5907UVX-2.5/NOPB DSBGA
LP5907UVX-2.8/NOPB DSBGA
LP5907UVX-2.8/NOPB DSBGA
LP5907UVX-2.85/NOPB DSBGA
LP5907UVX-2.85/NOPB DSBGA
LP5907UVX-3.0/NOPB DSBGA
250
0.51
0.51
0.5
250
250
250
0.51
0.5
250
250
0.5
250
0.51
0.51
0.5
250
250
250
0.5
250
0.51
0.51
0.5
250
250
250
0.5
250
0.51
0.51
0.5
250
250
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
0.51
0.5
0.5
0.51
0.5
0.5
0.51
0.5
0.51
0.5
0.51
0.51
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Oct-2020
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LP5907UVX-3.0/NOPB DSBGA
LP5907UVX-3.1/NOPB DSBGA
LP5907UVX-3.1/NOPB DSBGA
LP5907UVX-3.2/NOPB DSBGA
LP5907UVX-3.2/NOPB DSBGA
LP5907UVX-3.3/NOPB DSBGA
LP5907UVX-3.3/NOPB DSBGA
LP5907UVX-4.5/NOPB DSBGA
LP5907UVX-4.5/NOPB DSBGA
YKE
YKE
YKE
YKE
YKE
YKE
YKE
YKE
YKE
YKE
YKE
YKE
YKE
YKG
YKG
YKG
YKG
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
9.2
9.2
9.2
9.2
0.74
0.71
0.74
0.74
0.71
0.71
0.74
0.74
0.71
0.71
0.74
0.74
0.71
0.72
0.72
0.72
0.72
0.74
0.71
0.74
0.74
0.71
0.71
0.74
0.74
0.71
0.71
0.74
0.74
0.71
0.72
0.72
0.72
0.72
0.5
0.51
0.5
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
0.5
0.51
0.51
0.5
0.5
0.51
0.51
0.5
LP5907UVX19/NOPB
LP5907UVX19/NOPB
LP5907UVX37/NOPB
LP5907UVX37/NOPB
LP5907YKGR-2.0
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
0.5
0.51
0.39
0.39
0.39
0.39
LP5907YKGR-2.8
LP5907YKGR-2.825
LP5907YKGR-2.85
*All dimensions are nominal
Pack Materials-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Oct-2020
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LP5907A28YKMR
LP5907A29YKMR
DSBGA
DSBGA
DSBGA
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
X2SON
X2SON
X2SON
X2SON
X2SON
X2SON
X2SON
X2SON
X2SON
X2SON
X2SON
X2SON
X2SON
X2SON
X2SON
X2SON
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
YKM
YKM
YKM
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DQN
DQN
DQN
DQN
DQN
DQN
DQN
DQN
DQN
DQN
DQN
DQN
DQN
DQN
DQN
DQN
YKE
YKE
YKE
YKE
YKE
YKE
YKE
YKE
YKE
YKE
YKE
YKE
YKE
4
4
4
5
5
5
5
5
5
5
5
5
5
5
5
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
250
220.0
220.0
220.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
184.0
184.0
184.0
184.0
184.0
184.0
184.0
184.0
184.0
184.0
184.0
184.0
184.0
184.0
184.0
184.0
220.0
210.0
210.0
220.0
210.0
220.0
220.0
210.0
210.0
220.0
220.0
210.0
210.0
220.0
220.0
220.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
184.0
184.0
184.0
184.0
184.0
184.0
184.0
184.0
184.0
184.0
184.0
184.0
184.0
184.0
184.0
184.0
220.0
185.0
185.0
220.0
185.0
220.0
220.0
185.0
185.0
220.0
220.0
185.0
185.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
19.0
19.0
19.0
19.0
19.0
19.0
19.0
19.0
19.0
19.0
19.0
19.0
19.0
19.0
19.0
19.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
LP5907A33YKMR
LP5907MFX-1.2/NOPB
LP5907MFX-1.5/NOPB
LP5907MFX-1.8/NOPB
LP5907MFX-2.5/NOPB
LP5907MFX-2.8/NOPB
LP5907MFX-2.85/NOPB
LP5907MFX-2.9/NOPB
LP5907MFX-3.0/NOPB
LP5907MFX-3.1/NOPB
LP5907MFX-3.2/NOPB
LP5907MFX-3.3/NOPB
LP5907MFX-4.5/NOPB
LP5907SNX-1.2/NOPB
LP5907SNX-1.8/NOPB
LP5907SNX-1.9
LP5907SNX-2.2/NOPB
LP5907SNX-2.5/NOPB
LP5907SNX-2.7/NOPB
LP5907SNX-2.75
LP5907SNX-2.8/NOPB
LP5907SNX-2.85/NOPB
LP5907SNX-2.9/NOPB
LP5907SNX-3.0/NOPB
LP5907SNX-3.1/NOPB
LP5907SNX-3.2/NOPB
LP5907SNX-3.3/NOPB
LP5907SNX-4.0/NOPB
LP5907SNX-4.5/NOPB
LP5907UVE-1.2/NOPB
LP5907UVE-1.2/NOPB
LP5907UVE-1.8/NOPB
LP5907UVE-1.8/NOPB
LP5907UVE-2.8/NOPB
LP5907UVE-2.8/NOPB
LP5907UVE-2.85/NOPB
LP5907UVE-2.85/NOPB
LP5907UVE-3.0/NOPB
LP5907UVE-3.0/NOPB
LP5907UVE-3.1/NOPB
LP5907UVE-3.1/NOPB
LP5907UVE-3.2/NOPB
250
250
250
250
250
250
250
250
250
250
250
250
Pack Materials-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Oct-2020
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LP5907UVE-3.2/NOPB
LP5907UVE-3.3/NOPB
LP5907UVE-3.3/NOPB
LP5907UVE-4.5/NOPB
LP5907UVE-4.5/NOPB
LP5907UVX-1.2/NOPB
LP5907UVX-1.2/NOPB
LP5907UVX-1.6/NOPB
LP5907UVX-1.8/NOPB
LP5907UVX-1.8/NOPB
LP5907UVX-2.2/NOPB
LP5907UVX-2.5/NOPB
LP5907UVX-2.8/NOPB
LP5907UVX-2.8/NOPB
LP5907UVX-2.85/NOPB
LP5907UVX-2.85/NOPB
LP5907UVX-3.0/NOPB
LP5907UVX-3.0/NOPB
LP5907UVX-3.1/NOPB
LP5907UVX-3.1/NOPB
LP5907UVX-3.2/NOPB
LP5907UVX-3.2/NOPB
LP5907UVX-3.3/NOPB
LP5907UVX-3.3/NOPB
LP5907UVX-4.5/NOPB
LP5907UVX-4.5/NOPB
LP5907UVX19/NOPB
LP5907UVX19/NOPB
LP5907UVX37/NOPB
LP5907UVX37/NOPB
LP5907YKGR-2.0
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
YKE
YKE
YKE
YKE
YKE
YKE
YKE
YKE
YKE
YKE
YKE
YKE
YKE
YKE
YKE
YKE
YKE
YKE
YKE
YKE
YKE
YKE
YKE
YKE
YKE
YKE
YKE
YKE
YKE
YKE
YKG
YKG
YKG
YKG
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
250
220.0
220.0
210.0
210.0
220.0
210.0
220.0
220.0
210.0
220.0
220.0
210.0
220.0
210.0
220.0
210.0
210.0
220.0
210.0
220.0
220.0
210.0
210.0
220.0
220.0
210.0
210.0
220.0
220.0
210.0
220.0
220.0
220.0
220.0
220.0
220.0
185.0
185.0
220.0
185.0
220.0
220.0
185.0
220.0
220.0
185.0
220.0
185.0
220.0
185.0
185.0
220.0
185.0
220.0
220.0
185.0
185.0
220.0
220.0
185.0
185.0
220.0
220.0
185.0
220.0
220.0
220.0
220.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
250
250
250
250
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
LP5907YKGR-2.8
LP5907YKGR-2.825
LP5907YKGR-2.85
Pack Materials-Page 5
PACKAGE OUTLINE
YKG0004
DSBGA - 0.33mm MAX HEIGHT
S
C
A
L
E
1
5
.
0
0
0
DIE SIZE BALL GRID ARRAY
A
D
B
E
BUMP A1 CORNER
0.33 MAX
C
SEATING PLANE
0.05 C
0.12
0.09
BUMP
0.175
B
A
D: Max = 0.675 mm, Min =0.615 mm
E: Max = 0.675 mm, Min =0.615 mm
0.175
0.35
0.20
4X
1
2
0.16
0.015
C A B
0.35
4218366/E 05/2020
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per
ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
YKG0004
DSBGA - 0.33mm MAX HEIGHT
DIE SIZE BALL GRID ARRAY
SYMM
4X ( 0.18)
(0.175)
1
2
A
SYMM
(0.35)
B
(0.175)
(0.35)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:60X
0.0375 MIN
(
0.18)
0.0375 MAX
(
0.18)
SOLDERMASK
OPENING
METAL
EXPOSED
METAL
EXPOSED
METAL
METAL UNDER
SOLDER MASK
SOLDERMASK
OPENING
NON SOLDERMASK
DEFINED
SOLDERMASK
DEFINED
(PREFERRED)
SOLDERMASK DETAILS
NOT TO SCALE
4218366/E 05/2020
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
Refer to Texas Instruments Literature No. SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YKG0004
DSBGA - 0.33mm MAX HEIGHT
DIE SIZE BALL GRID ARRAY
(R0.05)
TYP
METAL
TYP
SYMM
2
1
A
4X
(
0.21)
(0.175)
SYMM
(0.35)
B
(0.175)
(0.35)
SOLDERPASTE EXAMPLE
BASED ON 0.075 mm THICK STENCIL
SCALE:80X
4218366/E 05/2020
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
2X 0.95
1.9
3.05
2.75
1.9
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/E 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/E 09/2019
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/E 09/2019
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
YKM0004
DSBGA - 0.495 mm max height
SCALE 12.000
DIE SIZE BALL GRID ARRAY
A
D
B
E
BALL A1
CORNER
BACK COATING
0.495 MAX
C
SEATING PLANE
BALL TYP
0.18
0.14
0.35
TYP
B
0.35
TYP
D: Max = 0.675 mm, Min =0.615 mm
E: Max = 0.675 mm, Min =0.615 mm
A
0.225
0.195
C A B
1
2
4X
0.015
4223494/A 11/2014
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
YKM0004
DSBGA - 0.495 mm max height
DIE SIZE BALL GRID ARRAY
(0.35) TYP
SYMM
4X ( 0.18)
(0.35) TYP
A
B
1
2
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:40X
(
0.18)
0.04 MAX
METAL UNDER
SOLDER MASK
0.04 MIN
METAL
EXPOSED
METAL
EXPOSED
METAL
(
0.18)
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4223494/A 11/2014
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
Refer to Texas Instruments Literature No. SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YKM0004
DSBGA - 0.495 mm max height
DIE SIZE BALL GRID ARRAY
(0.35) TYP
4X ( 0.21)
(R0.05) TYP
A
B
SYMM
(0.35)
TYP
1
2
SYMM
METAL
TYP
SOLDER PASTE EXAMPLE
BASED ON 0.075 - 0.1mm THICK STENCIL
SCALE:40X
4223494/A 11/2014
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
PACKAGE OUTLINE
YKE0004
DSBGA - 0.445mm max height
SCALE 12.000
DIE SIZE BALL GRID ARRAY
A
D
B
E
BALL A1
CORNER
0.445 MAX
C
SEATING PLANE
BALL TYP
0.18
0.14
0.35
TYP
B
0.35
TYP
D: Max = 0.675 mm, Min =0.615 mm
E: Max = 0.675 mm, Min =0.615 mm
A
0.225
0.195
1
2
4X
0.005
C A
B
4220102/A 11/2014
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
YKE0004
DSBGA - 0.445mm max height
DIE SIZE BALL GRID ARRAY
(0.35) TYP
SYMM
4X 0.18 0.02
A
B
(0.35) TYP
1
2
SYMM
LAND PATTERN EXAMPLE
SCALE:40X
(
0.18)
0.04 MAX
METAL UNDER
SOLDER MASK
0.04 MIN
METAL
(
0.18)
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4220102/A 11/2014
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
Refer to Texas Instruments Literature No. SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YKE0004
DSBGA - 0.445mm max height
DIE SIZE BALL GRID ARRAY
(0.35) TYP
4X ( 0.21)
(R0.05) TYP
A
B
SYMM
(0.35)
TYP
1
2
SYMM
METAL
TYP
SOLDER PASTE EXAMPLE
BASED ON 0.075 - 0.1mm THICK STENCIL
SCALE:40X
4220102/A 11/2014
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
PACKAGE OUTLINE
X2SON - 0.4 mm max height
DQN0004A
PLASTIC SMALL OUTLINE - NO LEAD
1.05
0.95
A
B
1
1.05
0.95
PIN 1
INDEX AREA
C
0.4 MAX
SEATING PLANE
0.08
NOTE 6
+0.12
-0.1
0.05
0.00
0.48
(0.05) TYP
NOTE 6
2
1
3
EXPOSED
THERMAL PAD
5
2X 0.65
(0.07) TYP
NOTE 5
4
0.28
PIN 1 ID
(OPTIONAL)
NOTE 4
4X
0.15
(0.11)
0.3
0.2
0.1
C A B
0.05
C
0.30
0.15
3X
4215302/E 12/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
4. Features may not exist. Recommend use of pin 1 marking on top of package for orientation purposes.
5. Shape of exposed side leads may differ.
6. Number and location of exposed tie bars may vary.
www.ti.com
EXAMPLE BOARD LAYOUT
X2SON - 0.4 mm max height
DQN0004A
PLASTIC SMALL OUTLINE - NO LEAD
(0.86)
SYMM
SEE DETAIL
4X
4X (0.36)
(0.03)
4
4X (0.21)
1
5
SYMM
(0.65)
4X (0.18)
2
3
(
0.48)
(0.22) TYP
EXPOSED METAL
CLEARANCE
LAND PATTERN EXAMPLE
SCALE: 40X
0.05 MIN
ALL AROUND
SOLDER MASK
OPENING
EXPOSED METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
SOLDER MASK DETAIL
4215302/E 12/2016
NOTES: (continued)
7. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271)
.
8. If any vias are implemented, it is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
X2SON - 0.4 mm max height
DQN0004A
PLASTIC SMALL OUTLINE - NO LEAD
(0.9)
SYMM
4X (0.4)
4X (0.03)
4
1
4X (0.21)
5
SYMM
(0.65)
SOLDER MASK
EDGE
4X (0.22)
2
3
(
0.45)
4X (0.235)
SOLDER PASTE EXAMPLE
BASED ON 0.075 - 0.1mm THICK STENCIL
EXPOSED PAD
88% PRINTED SOLDER COVERAGE BY AREA
SCALE: 60X
4215302/E 12/2016
NOTES: (continued)
9. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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