LP5910-1.0DRVR [TI]
具有反向电流保护和使能功能的 300mA、低噪声、低 IQ、低压降稳压器 | DRV | 6 | -40 to 125;
| 型号： | LP5910-1.0DRVR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有反向电流保护和使能功能的 300mA、低噪声、低 IQ、低压降稳压器 | DRV | 6 | -40 to 125 光电二极管 输出元件 稳压器 调节器 |
| 文件： | 总31页 (文件大小：2342K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LP5910
SNVSA91F – SEPTEMBER 2015 – REVISED APRIL 2021
LP5910 300-mA Low-Noise, Low-IQ LDO
1 Features
3 Description
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Input voltage range: 1.3 V to 3.3 V
Output voltage range: 0.8 V to 2.3 V
Output current: 300 mA
The LP5910 is a low-noise LDO that can supply
up to 300 mA of output current. Designed to meet
the requirements of RF and analog circuits, this
device provides low noise, high PSRR, low quiescent
current, and superior line transient and load transient
response. Using new innovative design techniques
the LP5910 offers class-leading noise performance
without a noise bypass capacitor and with the option
for remote output capacitor placement.
PSRR: 75 dB at 1 kHz
Output voltage tolerance: ±2%
Low dropout: 120 mV (typical)
Very low IQ (enabled, no load): 12 µA
Low output-voltage noise: 12 µVRMS
Stable with ceramic input and output capacitors
Thermal overload protection
Short-circuit protection
Reverse current protection
Automatic output discharge for fast turnoff
The device contains a reverse current protection
circuit that prevents a reverse current flow through the
LDO to the IN pin when the input voltage is lower than
the output voltage.
2 Applications
When the Enable (EN) pin is low, and the output is
in an OFF state, an automatic output discharge circuit
discharges the output capacitance for fast turnoff.
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Mobile phones and tablets
Digital cameras and audio devices
Portable and battery-powered equipment
Portable medical equipment
Virtual reality
With its low input and low output voltage range the
LP5910 is well-suited as a post DC-DC regulator
(post BUCK regulator) or for single- or dual-cell
applications.
RF, PLL, VCO, and clock power supplies
IP cameras
The device is designed to work with a 1-μF input and
a 1-μF output ceramic capacitor. A separate noise
bypass capacitor is not required.
This device is available with fixed output voltages
from 0.8 V to 2.3 V in 25-mV steps. Contact Texas
Instruments Sales for specific voltage option needs.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE
WSON (6)
2.00 mm × 2.00 mm (NOM)
LP5910
DSBGA (4) 0.742 mm × 0.742 mm (MAX)
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
VIN
VOUT
IN
OUT
CIN
COUT
LP5910
Enable
EN
GND
Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LP5910
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SNVSA91F – SEPTEMBER 2015 – REVISED APRIL 2021
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................5
6.6 Typical Characteristics................................................7
7 Detailed Description......................................................11
7.1 Overview................................................................... 11
7.2 Functional Block Diagram......................................... 11
7.3 Feature Description...................................................11
7.4 Device Functional Modes..........................................12
8 Applications and Implementation................................13
8.1 Application Information............................................. 13
8.2 Typical Application.................................................... 13
9 Power Supply Recommendations................................17
10 Layout...........................................................................18
10.1 Layout Guidelines................................................... 18
10.2 Layout Examples.................................................... 18
11 Device and Documentation Support..........................19
11.1 Documentation Support.......................................... 19
11.2 Receiving Notification of Documentation Updates..19
11.3 Support Resources................................................. 19
11.4 Trademarks............................................................. 19
11.5 Electrostatic Discharge Caution..............................19
11.6 Glossary..................................................................19
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (July 2017) to Revision F (April 2021)
Page
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Updated the numbering format for tables, figures, and cross-references throughout the document .................1
Deleted WEBENCH links from document...........................................................................................................1
Deleted last bullet from Features section........................................................................................................... 1
Changed Dropout Voltage specifications for 1.5V ≤ VIN < 1.8V; added new rows in Dropout Voltage
specifications for this voltage range....................................................................................................................5
Deleted Custom Design With WEBENCH® Tools section from Detailed Design Procedure ...........................13
Deleted Custom Design With WEBENCH® Tools section from Documentation Support ................................19
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Changes from Revision D (August 2016) to Revision E (July 2017)
Added new package, YKA0004-C01 associated with orderables LP5910-1.1BYKAR and LP5910-1.1BYKAT;
added links for WEBENCH.................................................................................................................................1
Page
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5 Pin Configuration and Functions
IN
A1
OUT
A2
IN
OUT
A2
A1
B1
B2
B1
B2
EN
GND
GND
EN
Figure 5-1. YKA Package, 4-Pin Ultra-Thin DSBGA,
Top View
Figure 5-2. YKA Package, 4-Pin Ultra-Thin DSBGA,
Bottom View
1
6
5
4
IN
OUT
2
3
GND
EN
NC
NC
Figure 5-3. DRV Package, 6-Pin WSON With Thermal Pad, Top View
Table 5-1. Pin Functions
PIN
I/O
DESCRIPTION
NAME
DSBGA
WSON
Enable input; disables the regulator when logic low. Enables the regulator when logic
high. An internal 1-MΩ pull down resistor connects this input to ground.
EN
B1
4
I
GND
IN
B2
A1
—
5
6
—
I
Common ground
Voltage supply input. A 1-μF capacitor must be connected at this input.
No internal connection. Connect to ground or leave open.
NC
2, 3
—
Voltage output. A 1-µF low-ESR capacitor must be connected from this pin to the
GND pin. Connect this output to the load circuit.
OUT
A2
1
O
The exposed thermal pad on the bottom of the package must be connected to a
copper area under the package on the PCB. Connect to ground potential or leave
floating. Do not connect to any potential other than the same ground potential seen at
device pin 5 (GND). See the Power Dissipation section for more information.
Exposed Pad
—
Thermal Pad
—
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN
–0.3
–0.3
–0.3
MAX
3.6
UNIT
V
Input voltage, VIN
Output voltage, VOUT
3.6
V
Enable input voltage, VEN
Continuous power dissipation(3)
Junction temperature, TJ(MAX)
Storage temperature, Tstg
3.6
V
Internally limited
W
150
150
°C
°C
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to the GND pin.
(3) Internal thermal shutdown circuitry protects the device from permanent damage.
6.2 ESD Ratings
VALUE
±1000
±250
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
3.3
UNIT
V
Input voltage, VIN
1.3
0.8
0
Output voltage, VOUT
Enable input voltage, VEN
Output current, IOUT
2.3
V
3.3
V
0
300
125
85
mA
°C
°C
(1)
Junction temperature, TJ
Ambient temperature, TA
–40
–40
(1)
(1) The maximum ambient temperature, (TA(MAX)) is a recommended value only and can vary depending on device power dissipation and
RθJA. For reliable operation, the junction temperature (TJ) must be limited to a maximum of 125°C. Ambient temperature (TA), thermal
resistance (RθJA) , VIN, VOUT, and IOUT all define TJ : TJ = TA + (RθJA × ((VIN – VOUT) × IOUT).
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6.4 Thermal Information
LP5910
THERMAL METRIC(1)
YKA (DSBGA)
DRV (WSON)
6 PINS
79.2(3)
110.2
UNIT
4 PINS
202.8
3.3
(2)
RθJA
RθJC(top)
RθJB
Junction-to-ambient thermal resistance, High-K
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
36.0
0.4
48.7
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
5.2
ψJB
36.0
n/a
49.1
RθJC(bot)
18.1
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) Thermal resistance value RθJA is based on the EIA/JEDEC High-K printed circuit board defined by: JESD51-7 - High Effective Thermal
Conductivity Test Board for Leaded Surface Mount Packages.
(3) The PCB for the WSON/DRV package RθJA includes two (2) thermal vias under the exposed thermal pad per EIA/JEDEC JESD51-5.
6.5 Electrical Characteristics
VIN = VOUT(NOM) + 0.5 V, VEN = 1 V, IOUT = 1 mA, CIN = 1 µF, and COUT = 1 µF (unless otherwise noted)(1) (2) (3)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
GENERAL
ΔVOUT
VIN = (VOUT(NOM) + 0.5 V) to 3.3 V,
IOUT = 1 mA to 300 mA
Output voltage tolerance
Line regulation
–2
2
%VOUT
%/V
VIN = (VOUT(NOM) + 0.5 V) to 3.3 V,
IOUT = 1 mA
0.01
Load regulation
Load current
IOUT = 1 mA to 300 mA
See(4)
0.002
%/mA
mA
ILOAD
IQ
0
300
25
VEN = 1 V, IOUT = 0 mA
VEN = 1 V, IOUT = 300 mA
12
Quiescent current(5)
230
350
µA
Quiescent current in
shutdown(5)
IQ(SD)
VEN = 0.3 V, –40°C ≤ TJ ≤ 85°C
0.02
2
Output reverse current(7)
VOUT > VIN
VOUT = 3.3 V, VIN = VEN = 0 V
VOUT = 3.3 V, VIN = VEN = 1.3 V
IOUT = 0 mA (VOUT = 2.3 V)
1.3 V ≤ VOUT < 1.5 V,
–20
0
0
µA
µA
µA
IRO
IG
50
Ground current(6)
15
DSBGA only
200
300
235
180
370
270
220
IOUT = 300 mA
1.5 V ≤ VOUT <1.8V,
IOUT = 300 mA
DSBGA only
DSBGA only
WSON only
WSON only
WSON only
160
120
245
195
145
450
1.8 V ≤ VOUT ≤ 2.3 V,
IOUT = 300 mA
VDO
Dropout voltage(8)
mV
1.3 V ≤ VOUT < 1.5 V,
IOUT = 300 mA
1.5 V ≤ VOUT < 1.8V,
IOUT = 300 mA
1.8 V ≤ VOUT ≤ 2.3 V,
IOUT = 300 mA
VOUT = VOUT(NOM) – 0.1 V
VIN = VOUT(NOM) + 0.5 V
ILIMIT
Output current limit
mA
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UNIT
SNVSA91F – SEPTEMBER 2015 – REVISED APRIL 2021
6.5 Electrical Characteristics (continued)
VIN = VOUT(NOM) + 0.5 V, VEN = 1 V, IOUT = 1 mA, CIN = 1 µF, and COUT = 1 µF (unless otherwise noted)(1) (2) (3)
PARAMETER
TEST CONDITIONS
MIN
TYP
80
75
65
40
25
65
65
65
40
25
12
12
160
15
MAX
ƒ = 100 Hz, IOUT = 20 mA, VOUT ≥ 1 V
ƒ = 1 kHz, IOUT = 20 mA, VOUT ≥ 1 V
ƒ = 10 kHz, IOUT = 20 mA, VOUT ≥ 1 V
ƒ = 100 kHz, IOUT = 20 mA, VOUT ≥ 1 V
ƒ = 2 MHz, IOUT = 20 mA, VOUT ≥ 1 V
PSRR
Power supply rejection ratio(10)
dB
ƒ = 100 Hz, IOUT = 20 mA, 0.8 V < VOUT < 1 V
ƒ = 1 kHz, IOUT = 20 mA, 0.8 V < VOUT < 1 V
ƒ = 10 kHz, IOUT = 20 mA, 0.8 V < VOUT < 1 V
ƒ = 100 kHz, IOUT = 20 mA, 0.8 V < VOUT < 1 V
ƒ = 2 MHz, IOUT = 20 mA, 0.8 V < VOUT < 1 V
IOUT = 1 mA
BW = 10 Hz to 100 kHz
eN
Output noise voltage(10)
µVRMS
IOUT = 300 mA
Thermal shutdown
Thermal hysteresis
TJ rising until output is OFF
TJ falling from shutdown
TSD
°C
LOGIC INPUT THRESHOLDS
VIL
VIH
EN low threshold (Off)
EN high threshold (On)
0.3
V
VIN = 1.3 V to 3.3 V
1
VEN = 3.3 V, VIN = 3.3 V
VEN = 0 V, VIN = 3.3 V
3.3
IEN
EN pin current(9)
µA
0.001
TRANSIENT CHARACTERISTICS(9)
VIN = (VOUT(NOM) + 0.5 V) to (VOUT(NOM) + 1 V)
in 30 µs
IOUT = 1 mA
0
0
1
Line transient(10)
mV
mV
VIN = (VOUT(NOM) + 1 V) to (VOUT(NOM) + 0.5 V)
in 30 µs
–1
ΔVOUT
IOUT = 1 mA
IOUT = 1 mA to 100 mA in 10 µs
IOUT = 100 mA to 1 mA in 10 µs
–45
Load transient(10)
45
5%
Overshoot on start-up(10)
tON
OUTPUT DISCHARGE
Output discharge pulldown
resistance
Turnon time
From VEN > VIH to VOUT = 95% of VOUT(NOM)
80
200
µs
Ω
RAD
VEN = 0 V, VIN = 2.3 V
160
(1) All voltages are with respect to the device GND pin.
(2) Minimum and maximum limits are ensured through test, design, or statistical correlation over the TJ range of –40°C to 125°C, unless
otherwise stated. Typical values represent the most likely parametric norm at TA = 25°C, and are provided for reference purposes only.
(3) CIN, COUT: Low-ESR Surface-Mount-Ceramic Capacitors (MLCCs) used in setting electrical characteristics.
(4) The device maintains a stable, regulated output voltage without a load current.
(5) Quiescent current is defined here as the difference in current between the input voltage source and the load at VOUT. IQ = (IIN – IOUT
(6) Ground current is defined here as the total current flowing to ground as a result of all input voltages applied to the device.
(7) Output reverse current (IRO) is measured at the IN pin.
)
(8) Dropout voltage is the voltage difference between the input and the output at which the output voltage drops to 100 mV below its
nominal value. Dropout voltage is not a valid condition for output voltages less than 1.3 V as compliance with the minimum operating
input voltage can not be ensured.
(9) There is a 1-MΩ resistor between EN and ground on the device.
(10) This specification is verified by design.
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6.6 Typical Characteristics
VOUT = 1.8 V, VIN = VOUT + 0.5 V, VEN = VIN, IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF, TJ = 25°C (unless otherwise noted)
1.2
1.1
1
1.2
1.1
1
ON (VIH)
OFF (VIL)
ON (VIH)
OFF (VIL)
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
1
1
0
1.5
2
2.5
3
3.5
-50
-25
0
25
50
Junction Temperature (°C)
75
100
125
VIN (V)
D002
D001
VIN = 2.3 V
VOUT = 1.8 V
Figure 6-2. VEN Thresholds vs VIN
Figure 6-1. VEN Threshold vs Temperature
1.2
1.1
1
1.2
1.1
1
ON (VIH)
OFF (VIL)
ON (VIH)
OFF (VIL)
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
1
1.5
2
2.5
3
3.5
1.5
2
2.5
3
3.5
VIN (V)
VIN (V)
D003
D004
TJ = –40°C
Figure 6-3. VEN Thresholds vs VIN
TJ = 125°C
Figure 6-4. VEN Thresholds vs VIN
2
1.8
1.6
1.4
1.2
1
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
0.8
0.6
0.4
0.2
0
18 kW (100 µA)
1.8 kW (1 mA)
180 W (10 mA)
180 W (10 mA)
18 W (100 mA)
6 W (300 mA)
0
0.5
1
1.5
VIN (V)
2
2.5
3
3.5
0.5
1
1.5
VIN (V)
2
2.5
3
3.5
D005
D006
VEN = VIN
VEN = VIN
Figure 6-5. VOUT vs VIN
Figure 6-6. VOUT vs VIN
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6.6 Typical Characteristics (continued)
VOUT = 1.8 V, VIN = VOUT + 0.5 V, VEN = VIN, IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF, TJ = 25°C (unless otherwise noted)
25
20
15
10
5
25
20
15
10
5
125°C
85°C
25°C
-40°C
125°C
85°C
25°C
-40°C
0
0
0
0.5
1
1.5
VIN (V)
2
2.5
3
3.5
0
0.5
1
1.5
VIN (V)
2
2.5
3
3.5
D008
D007
VOUT = 1.2 V
VEN = VIN
Figure 6-8. IQ vs VIN
No load
VOUT = 0.8 V
VEN = VIN
Figure 6-7. IQ vs VIN
No load
25
25
125°C
85°C
25°C
-40°C
125°C
85°C
25°C
-40°C
20
15
10
5
20
15
10
5
0
0
0
0.5
1
1.5
VIN (V)
2
2.5
3
3.5
0
0.5
1
1.5
VIN (V)
2
2.5
3
3.5
D009
D010
VOUT = 1.8 V
VEN = VIN
Figure 6-9. IQ vs VIN
No load
VOUT = 2.3 V
VEN = VIN
Figure 6-10. IQ vs VIN
No load
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-100
10
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
100
1k
10k
Frequency (Hz)
100k
1M
10M
D012
D011
VOUT = 1.8 V
VIN = 2.3 V
IOUT = 20 mA
VOUT = 0.8 V
VIN = 1.3 V
IOUT = 20 mA
Figure 6-12. PSRR vs Frequency
Figure 6-11. PSRR vs Frequency
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6.6 Typical Characteristics (continued)
VOUT = 1.8 V, VIN = VOUT + 0.5 V, VEN = VIN, IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF, TJ = 25°C (unless otherwise noted)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0.5
0.45
0.4
1 mA
300 mA
0.35
0.3
0.25
0.2
0.15
0.1
0.05
0
10
100
1000 10000
Frequency (Hz)
100000
1000000
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
D014
D013
VOUT = 0.8 V
VIN = 1.3 V
VOUT = 2.3 V
VIN = 2.8 V
IOUT = 20 mA
Figure 6-14. Noise Density
Figure 6-13. PSRR vs Frequency
0.5
0.45
0.4
1.5
1 mA
300 mA
1.25
1
0.75
0.5
0.35
0.3
0.25
0
0.25
0.2
-0.25
-0.5
-0.75
-1
0.15
0.1
0.05
0
-1.25
-1.5
10
100
1000 10000
Frequency (Hz)
100000
1000000
-50
-25
0
25
50
Junction Temperature (°C)
75
100
125
D015
D016
VOUT = 2.3 V
VIN = 2.8 V
VIN = VOUT + 0.5 V
IOUT = 1 mA
Figure 6-15. Noise Density
Figure 6-16. ΔVOUT vs Temperature
250
250
225
200
175
150
125
100
75
VIN = 3.3 V
VIN = 1.3 V
VIN = 3.3 V
VIN = 2.3 V
225
200
175
150
125
100
75
50
50
25
25
0
0
0
50
100
150
IOUT (mA)
200
250
300
0
50
100
150
IOUT (mA)
200
250
300
D017
D018
VOUT = 0.8 V
VOUT = 1.8 V
Figure 6-17. IGND vs IOUT
Figure 6-18. IGND vs IOUT
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6.6 Typical Characteristics (continued)
VOUT = 1.8 V, VIN = VOUT + 0.5 V, VEN = VIN, IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF, TJ = 25°C (unless otherwise noted)
250
225
200
175
150
125
100
75
300
250
200
150
100
50
VIN = 3.3 V
VIN = 2.8 V
VOUT = 1.2 V
VOUT = 1.8 V
VOUT = 2.3 V
50
25
0
0
0
50
100
150
IOUT (mA)
200
250
300
0
50
100
150
IOUT (mA)
200
250
300
D019
D020
VOUT = 2.3 V
Figure 6-19. IGND vs IOUT
Figure 6-20. Dropout Voltage vs IOUT
2.5
2.5
2
120
12
8
100
80
60
40
20
0
2
1.5
1
4
1.5
1
0
-4
-8
0.5
0.5
VIN
VOUT
IOUT
DVOUT
0
0
-12
-25
0
25
50
Time (µs)
75
100
125
150
-20 -10
0
10
20
30
Time (µs)
40
50
60
70
80
D021
D022
VEN = VIN
VOUT = 1.8 V
COUT = 1 µF
VIN = 2.3 V
IOUT = 1 mA to 100 mA
VOUT = 1.8 V
COUT = 1 µF
tRISE = 10 µs
Figure 6-21. Turnon Time
Figure 6-22. Load Transient Response
120
100
80
60
40
20
0
12
3.0
2.5
2.0
1.5
1.0
0.5
0.0
12
8
IOUT
DVOUT
8
4
4
0
0
-4
-8
-12
-4
-8
-12
VIN (V)
DVOUT (mV)
-20 -10
0
10
20
30
Time (µs)
40
50
60
70
80
0
50 100 150 200 250 300 350 400 450 500
Time (ms)
D023
D024
VIN = 2.3 V
VOUT = 1.8 V
tFALL = 10 µs
COUT = 1 µF
ΔVIN = 0.5 V
VOUT = 1.8 V
IOUT = 1 mA
COUT = 1 µF
IOUT = 100 mA to 1 mA
tRISE = tFALL = 30 µs
Figure 6-23. Load Transient Response
Figure 6-24. Line Transient Response
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7 Detailed Description
7.1 Overview
The LP5910 is a linear regulator capable of supplying 300-mA output current. Designed to meet the
requirements of RF and analog circuits, the LP5910 device provides low noise, high PSRR, low quiescent
current, and low line/load transient response figures. Using new innovative design techniques the LP5910 offers
class-leading noise performance without a noise bypass capacitor and the option for remote output capacitor
placement.
7.2 Functional Block Diagram
Current
limit
IN
OUT
VIN
EA
Bandgap
Output
discharge
EN
Control
EN
7.3 Feature Description
7.3.1 No-Load Stability
The LP5910 remains stable and in regulation with no external load.
7.3.2 Thermal Overload Protection
The LP5910 contains a thermal shutdown protection circuit to turn off the output current when excessive heat
is dissipated in the LDO. Thermal shutdown occurs when the thermal junction temperature (TJ) of the main
pass-FET exceeds 160°C (typical). Thermal shutdown hysteresis assures that the LDO again resets (turns on)
when the temperature falls to 145°C (typical).
7.3.3 Short-Circuit Protection
The LP5910 contains internal current limit which reduces output current to a safe value if the output is
overloaded or shorted. Depending upon the value of VIN, thermal limiting may also become active as the
average power dissipated causes the die temperature to increase to the limit value (about 160°C). The
hysteresis of the thermal shutdown circuitry can result in a cyclic behavior on the output as the die temperature
heats and cools.
7.3.4 Output Automatic Discharge
The LP5910 output employs an internal 160-Ω (typical) pulldown resistance to discharge the output when the EN
pin is low, and the device is disabled.
7.3.5 Reverse Current Protection
The device contains a reverse current protection circuit that prevents a backward current flowing through the
LDO from the OUT pin to the IN pin.
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7.4 Device Functional Modes
7.4.1 Enable (EN)
The LP5910 may be switched to the ON or OFF state by logic input at the EN pin. A logic-high voltage on the EN
pin turns the device to the ON state. A logic-low voltage on the EN pin turns the device to the OFF state. If the
application does not require the shutdown feature, the EN pin must be tied to VIN to keep the regulator output
permanently in the ON state when power is applied
To ensure proper operation, the signal source used to drive the EN input must be able to swing above and below
the specified turnon or turnoff voltage thresholds listed in the Electrical Characteristics section under VIL and VIH.
A 1-MΩ pulldown resistor ties the EN input to ground. If the EN pin is left open, the internal 1-MΩ pulldown
resistor ensures that the device is turned into an OFF state by default.
When the EN pin is low, and the output is in an OFF state, the output activates an internal pulldown resistance to
discharge the output capacitance for fast turnoff.
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8 Applications and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The LP5910 is designed to meet the requirements of RF and analog circuits, by providing low noise, high
PSRR, low quiescent current, and low line or load transient response figures. The device offers excellent noise
performance without the need for a noise bypass capacitor and is stable with input and output capacitors with
a value of 1 µF. The LP5910 delivers this performance in an industry-standard DSBGA package which, for this
device, is specified with a TJ of –40°C to +125°C.
8.2 Typical Application
Figure 8-1 shows the typical application circuit for the LP5910. Input and output capacitances may need to be
increased above 1-µF minimum for some applications.
VIN
VOUT
IN
OUT
1 µF
1 µF
LP5910
Enable
EN
GND
Figure 8-1. LP5910 Typical Application
8.2.1 Design Requirements
For typical LP5910 applications, use the parameters listed in Table 8-1.
Table 8-1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
1.3 V to 3.3 V
0.8 V to 2.3 V
300 mA
Input voltage
Output voltage
Output current
Output capacitor range
1 µF to 10 µF
8.2.2 Detailed Design Procedure
8.2.2.1 External Capacitors
Like most low-dropout regulators, the LP5910 requires external capacitors for regulator stability. The device is
specifically designed for portable applications requiring minimum board space and smallest components. These
capacitors must be correctly selected for good performance.
8.2.2.2 Input Capacitor
An input capacitor is required for stability. It is recommended that a 1-µF capacitor be connected from the
LP5910 IN pin to ground. (This capacitance value may be increased without limit.) The input capacitor must be
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located a distance of not more than 1 cm from the IN pin and returned to a clean analog ground. Any good
quality ceramic, tantalum, or film capacitor may be used at the input.
Note
Tantalum capacitors can suffer catastrophic failures due to surge current when connected to a low-
impedance source of power (like a battery or a very large capacitor). If a tantalum capacitor is used
at the input, it must be guaranteed by the manufacturer to have a surge current rating sufficient for
the application. There are no requirements for the equivalent series resistance (ESR) on the input
capacitor, but tolerance and temperature coefficient must be considered when selecting the capacitor
to ensure the capacitance remains 1 µF ±30% over the entire operating temperature range.
8.2.2.3 Output Capacitor
For capacitance values in the range of 1 µF to 4.7 µF, ceramic capacitors are the smallest, least expensive
and have the lowest ESR values, thus making them best for eliminating high frequency noise. The ESR of a
typical 1-µF ceramic capacitor is in the range of 20 mΩ to 40 mΩ, which easily meets the ESR requirement for
stability for the LP5910. The temperature performance of ceramic capacitors varies by type. Most large value
ceramic capacitors ( ≥ 2.2 µF) are manufactured with Z5U or Y5V temperature characteristics, which results in
the capacitance dropping by more than 50% as the temperature goes from 25°C to 85°C.
A better choice for temperature coefficient in a ceramic capacitor is X7R. This type of capacitor is the
most stable and holds the capacitance within ±15% over the temperature range. Tantalum capacitors are
less desirable than ceramic for use as output capacitors because they are more expensive when comparing
equivalent capacitance and voltage ratings in the 1-µF to 4.7-µF range.
8.2.2.4 Capacitor Characteristics
The LP5910 is designed to work with ceramic capacitors on the input and output to take advantage of the
benefits they offer. For capacitance values in the range of 1 µF to 10 µF, ceramic capacitors are the smallest,
least expensive and have the lowest ESR values, thus making them best for eliminating high frequency noise.
The ESR of a typical 1-µF ceramic capacitor is in the range of 20 mΩ to 40 mΩ, which easily meets the ESR
requirement for stability for the LP5910.
A better choice for temperature coefficient in a ceramic capacitor is X7R. This type of capacitor is the
most stable and holds the capacitance within ±15% over the temperature range. Tantalum capacitors are
less desirable than ceramic for use as output capacitors because they are more expensive when comparing
equivalent capacitance and voltage ratings in the 1-µF to 10-µF range.
Another important consideration is that tantalum capacitors have higher ESR values than equivalent size
ceramics. This means that while it may be possible to find a tantalum capacitor with an ESR value within
the stable range, it would have to be larger in capacitance (which means bigger and more costly) than a ceramic
capacitor with the same ESR value. Also, the ESR of a typical tantalum increases about 2:1 as the temperature
goes from 25°C down to –40°C, so some guard band must be allowed.
8.2.2.5 Remote Capacitor Operation
The LP5910 requires at least a 1-µF capacitor at the OUT pin, but there is no strict requirements about the
location of the capacitor in regards to the pin. In practical designs the output capacitor may be located up to
10 cm away from the LDO. This means that there is no need to have a special capacitor close to the OUT pin
if there is already respective capacitors in the system (like a capacitor at the input of supplied part). The remote
capacitor feature helps user to minimize the number of capacitors in the system.
As a good design practice, keep the wiring parasitic inductance at a minimum, using as wide as possible traces
from the LDO output to the capacitors, keeping the LDO output trace layer as close as possible to ground layer
and avoiding vias on the path. If there is a need to use vias, implement as many vias as possible between the
connection layers. It is recommended to keep parasitic wiring inductance less than 35 nH. For the applications
with fast load transients, an input capacitor is recommended, equal to or larger to the sum of the capacitance at
the output node, for the best load-transient performance.
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8.2.2.6 No-Load Stability
The LP5910 remains stable, and in regulation, with no external load.
8.2.2.7 Enable Control
The LP5910 may be switched to an ON or OFF state by a logic input at the EN pin. A voltage on this pin greater
than VIH turns the device on, while a voltage less than VIL turns the device off.
When the EN pin is low, the regulator output is off and the device typically consumes less than 1 µA. Additionally,
an output pulldown circuit is activated which ensures that any charge stored on COUT is discharged to ground.
If the application does not require the use of the shutdown feature, the EN pin can be tied directly to the IN pin to
keep the regulator output permanently on.
An internal 1-MΩ pulldown resistor ties the EN input to ground, ensuring that the device remains off if the EN pin
is left open circuit. To ensure proper operation, the signal source used to drive the EN pin must be able to swing
above and below the specified turn-on/off voltage thresholds listed in the Electrical Characteristics under VIL and
VIH.
Table 8-2. Recommended Output Capacitor Specification
PARAMETER
TEST CONDITIONS
Capacitance for stability
ESR
MIN
0.7
5
NOM
MAX
10
UNIT
µF
1
Output capacitor, COUT
500
mΩ
8.2.2.8 Power Dissipation
Knowing the device power dissipation and proper sizing of the thermal plane connected to the tab or pad is
critical to ensuring reliable operation. Device power dissipation depends on input voltage, output voltage, and
load conditions and can be calculated with Equation 1.
PD(MAX) = (VIN(MAX) – VOUT) × IOUT(MAX)
(1)
Power dissipation can be minimized, and greater efficiency can be achieved, by using the lowest available
voltage drop option that would still be greater than the dropout voltage (VDO). However, keep in mind that higher
voltage drops result in better dynamic (that is, PSRR and transient) performance.
On the WSON (DRV) package, the primary conduction path for heat is through the exposed power pad to the
PCB. To ensure the device does not overheat, connect the exposed pad, through thermal vias, to an internal
ground plane with an appropriate amount of copper PCB area .
On the DSBGA (YKA) package, the primary conduction path for heat is through the four bumps to the PCB.
The maximum allowable junction temperature (TJ(MAX)) determines maximum power dissipation allowed
(PD(MAX)) for the device package.
Power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance
(RθJA) of the combined PCB and device package and the temperature of the ambient air (TA), according to
Equation 2 or Equation 3:
T
J(MAX) = TA(MAX) + (RθJA × PD(MAX)
)
(2)
(3)
PD(MAX) = (TJ(MAX) - TA(MAX)) / RθJA
Unfortunately, this RθJA is highly dependent on the heat-spreading capability of the particular PCB design,
and therefore varies according to the total copper area, copper weight, and location of the planes. The RθJA
recorded in Thermal Information is determined by the specific EIA/JEDEC JESD51-7 standard for PCB and
copper-spreading area, and is to be used only as a relative measure of package thermal performance. For
a well-designed thermal layout, RθJA is actually the sum of the package junction-to-case (bottom) thermal
resistance (RθJCbot) plus the thermal resistance contribution by the PCB copper area acting as a heat sink.
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8.2.2.9 Estimating Junction Temperature
The EIA/JEDEC standard recommends the use of psi (Ψ) thermal characteristics to estimate the junction
temperatures of surface mount devices on a typical PCB board application. These characteristics are not true
thermal resistance values, but rather package specific thermal characteristics that offer practical and relative
means of estimating junction temperatures. These psi metrics are determined to be significantly independent of
copper-spreading area. The key thermal characteristics (ΨJT and ΨJB) are given in Thermal Information and are
used in accordance with Equation 4 or Equation 5.
TJ(MAX) = TTOP + (ΨJT × PD(MAX)
)
(4)
where
•
•
PD(MAX) is explained in Equation 1.
TTOP is the temperature measured at the center-top of the device package.
TJ(MAX) = TBOARD + (ΨJB × PD(MAX)
)
(5)
where
•
•
PD(MAX) is explained in Equation 1.
TBOARD is the PCB surface temperature measured 1-mm from the device package and centered on the
package edge.
For more information about the thermal characteristics ΨJT and ΨJB, see the Semiconductor and IC Package
Thermal Metrics application report, available for download at www.ti.com.
For more information about measuring TTOP and TBOARD, see the Using New Thermal Metrics application report,
available for download at www.ti.com.
For more information about the EIA/JEDEC JESD51 PCB used for validating RθJA, see the Thermal
Characteristics of Linear and Logic Packages Using JEDEC PCB Designs application report, available for
download at www.ti.com.
8.2.3 Application Curves
2.5
2.5
2
120
100
80
60
40
20
0
12
8
2
4
1.5
1
1.5
1
0
-4
-8
0.5
0.5
IOUT
DVOUT
VIN
VOUT
-12
0
0
-20 -10
0
10
20
30
Time (µs)
40
50
60
70
80
-25
0
25
50
Time (µs)
75
100
125
150
D022
D021
VIN = 2.3 V
IOUT = 1 mA to 100 mA
VOUT = 1.8 V
COUT = 1 µF
tRISE = 10 µs
VEN = VIN
VOUT = 1.8 V
COUT = 1 µF
Figure 8-2. Turnon Time
Figure 8-3. Load Transient Response
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9 Power Supply Recommendations
This device is designed to operate from an input supply voltage range of 1.3 V to 3.3 V. The input supply must
be well regulated and free of spurious noise. To ensure that the LP5910 output voltage is well regulated and
dynamic performance is optimum, the input supply must be at least VOUT + 0.5 V.
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10 Layout
10.1 Layout Guidelines
The dynamic performance of the LP5910 is dependant on the layout of the PCB. PCB layout practices that are
adequate for typical LDOs may degrade the PSRR, noise, or transient performance of the LP5910.
Best performance is achieved by placing CIN and COUT on the same side of the PCB as the LP5910 device, and
as close as is practical to the package. The ground connections for CIN and COUT must be back to the LP5910
GND pin using as wide and as short of a copper trace as is practical.
Avoid connections using long trace lengths, narrow trace widths, and/or connections through vias. These add
parasitic inductances and resistance that results in inferior performance especially during transient conditions.
10.1.1 DSBGA Mounting
The DSBGA package requires specific mounting techniques, which are detailed in the DSBGA Wafer Level Chip
Scale Package application note. For best results during assembly, alignment ordinals on the PC board may be
used to facilitate placement of the DSBGA device.
10.1.2 DSBGA Light Sensitivity
Exposing the DSBGA device to direct light may cause incorrect operation of the device. High intensity light
sources such as halogen lamps can affect electrical performance if they are situated in close proximity to the
device. The wavelengths that have the most detrimental effect are reds and infra-reds, which means that the
fluorescent lighting used inside most buildings has little effect on performance.
10.2 Layout Examples
IN
OUT
A2
A1
COUT
CIN
Via
B1
B2
EN
GND
Figure 10-1. LP5910 Typical DSBGA Layout
1
2
3
6
5
4
IN
OUT
NC
COUT
CIN
GND
EN
NC
Figure 10-2. LP5910 Typical WSON Layout
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation, see the following:
•
•
•
•
Texas Instruments, AN-1112 DSBGA Wafer Level Chip Scale Package application note
Texas Instruments, Semiconductor and IC Package Thermal Metrics application report
Texas Instruments, Using New Thermal Metrics application report
Texas Instruments, Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs
application report
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
7-May-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LP5910-0.9YKAR
LP5910-1.0DRVR
LP5910-1.0YKAR
LP5910-1.1BYKAR
LP5910-1.1BYKAT
LP5910-1.1YKAR
LP5910-1.2PYCPR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PREVIEW
DSBGA
WSON
YKA
DRV
YKA
YKA
YKA
YKA
YCP
4
6
4
4
4
4
4
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
SNAGCU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Call TI
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
D
NIPDAU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
Call TI
59A
A
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
T
250
RoHS & Green
T
3000 RoHS & Green
E
3000
Non-RoHS &
Non-Green
LP5910-1.2YKAR
LP5910-1.725YKAR
LP5910-1.825YKAR
LP5910-1.825YKAT
LP5910-1.8DRVR
LP5910-1.8DRVT
LP5910-1.8YKAR
LP5910-1.8YKAT
PLP5910-1.2PYCPR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DSBGA
DSBGA
DSBGA
DSBGA
WSON
WSON
DSBGA
DSBGA
DSBGA
YKA
YKA
YKA
YKA
DRV
DRV
YKA
YKA
YCP
4
4
4
4
6
6
4
4
4
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
SNAGCU
SNAGCU
SNAGCU
SNAGCU
NIPDAU
NIPDAU
SNAGCU
SNAGCU
Call TI
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Call TI
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
B
N
O
250
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
RoHS & Green
O
59C
59C
C
250
RoHS & Green
C
3000
Non-RoHS &
Non-Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
7-May-2021
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
8-May-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LP5910-0.9YKAR
LP5910-1.0DRVR
LP5910-1.0YKAR
LP5910-1.1BYKAR
LP5910-1.1BYKAT
LP5910-1.1YKAR
LP5910-1.2YKAR
LP5910-1.725YKAR
LP5910-1.825YKAR
LP5910-1.825YKAT
LP5910-1.8DRVR
LP5910-1.8DRVT
LP5910-1.8YKAR
LP5910-1.8YKAT
DSBGA
WSON
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
WSON
WSON
DSBGA
DSBGA
YKA
DRV
YKA
YKA
YKA
YKA
YKA
YKA
YKA
YKA
DRV
DRV
YKA
YKA
4
6
4
4
4
4
4
4
4
4
6
6
4
4
3000
3000
3000
3000
250
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
0.8
2.3
0.8
0.8
0.8
0.8
0.8
0.8
0.8
0.8
2.3
2.3
0.8
0.8
0.8
2.3
0.8
0.8
0.8
0.8
0.8
0.8
0.8
0.8
2.3
2.3
0.8
0.8
0.47
1.15
0.47
0.47
0.47
0.47
0.47
0.47
0.47
0.47
1.15
1.15
0.47
0.47
2.0
4.0
2.0
4.0
4.0
4.0
2.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q1
Q2
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q2
Q2
Q1
Q1
3000
3000
3000
3000
250
3000
250
3000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-May-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LP5910-0.9YKAR
LP5910-1.0DRVR
LP5910-1.0YKAR
LP5910-1.1BYKAR
LP5910-1.1BYKAT
LP5910-1.1YKAR
LP5910-1.2YKAR
LP5910-1.725YKAR
LP5910-1.825YKAR
LP5910-1.825YKAT
LP5910-1.8DRVR
LP5910-1.8DRVT
LP5910-1.8YKAR
LP5910-1.8YKAT
DSBGA
WSON
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
WSON
WSON
DSBGA
DSBGA
YKA
DRV
YKA
YKA
YKA
YKA
YKA
YKA
YKA
YKA
DRV
DRV
YKA
YKA
4
6
4
4
4
4
4
4
4
4
6
6
4
4
3000
3000
3000
3000
250
182.0
182.0
182.0
182.0
182.0
182.0
182.0
182.0
182.0
182.0
182.0
182.0
182.0
182.0
182.0
182.0
182.0
182.0
182.0
182.0
182.0
182.0
182.0
182.0
182.0
182.0
182.0
182.0
20.0
20.0
20.0
20.0
20.0
20.0
20.0
20.0
20.0
20.0
20.0
20.0
20.0
20.0
3000
3000
3000
3000
250
3000
250
3000
250
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DRV 6
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4206925/F
PACKAGE OUTLINE
DRV0006A
WSON - 0.8 mm max height
SCALE 5.500
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
A
B
PIN 1 INDEX AREA
2.1
1.9
0.8
0.7
C
SEATING PLANE
0.08 C
(0.2) TYP
0.05
0.00
1
0.1
EXPOSED
THERMAL PAD
3
4
6
2X
7
1.3
1.6 0.1
1
4X 0.65
0.35
0.25
6X
PIN 1 ID
(OPTIONAL)
0.3
0.2
6X
0.1
C A
C
B
0.05
4222173/B 04/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRV0006A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
6X (0.45)
6X (0.3)
(1)
1
7
6
SYMM
(1.6)
(1.1)
4X (0.65)
4
3
SYMM
(1.95)
(R0.05) TYP
(
0.2) VIA
TYP
LAND PATTERN EXAMPLE
SCALE:25X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4222173/B 04/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown.
www.ti.com
EXAMPLE STENCIL DESIGN
DRV0006A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
7
6X (0.45)
METAL
1
6
6X (0.3)
(0.45)
SYMM
4X (0.65)
(0.7)
4
3
(R0.05) TYP
(1)
(1.95)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD #7
88% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:30X
4222173/B 04/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
YKA0004
DSBGA - 0.4 mm max height
SCALE 14.000
DIE SIZE BALL GRID ARRAY
A
D
B
E
BALL A1
CORNER
0.4 MAX
C
SEATING PLANE
0.05 C
0.18
0.13
BALL TYP
0.35 TYP
B
A
SYMM
0.35
TYP
D: Max = 0.742 mm, Min =0.682 mm
E: Max = 0.742 mm, Min =0.682 mm
1
2
0.25
0.15
C A B
4X
0.015
SYMM
4221909/B 08/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
YKA0004
DSBGA - 0.4 mm max height
DIE SIZE BALL GRID ARRAY
(0.35) TYP
4X ( 0.2)
(0.35) TYP
2
1
A
B
SYMM
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:60X
(
0.2)
0.0325 MIN
0.0325 MAX
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
(
0.2)
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4221909/B 08/2018
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YKA0004
DSBGA - 0.4 mm max height
DIE SIZE BALL GRID ARRAY
(0.35) TYP
4X ( 0.21)
(R0.05) TYP
2
1
A
B
SYMM
(0.35)
TYP
METAL
TYP
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.075 mm - 0.1 mm THICK STENCIL
SCALE:60X
4221909/B 08/2018
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
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