LP5952TL-1.3/NOPB [TI]
具有使能功能的 350mA、低输入电压 (0.9V)、线性稳压器 | YZR | 5 | -40 to 125;
| 型号： | LP5952TL-1.3/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有使能功能的 350mA、低输入电压 (0.9V)、线性稳压器 | YZR | 5 | -40 to 125 稳压器 |
| 文件： | 总26页 (文件大小：795K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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LP5952
SNVS469F –OCTOBER 2006–REVISED DECEMBER 2015
LP5952 350-mA Dual-Rail Linear Regulator
1 Features
3 Description
The LP5952 is a dual-supply-rail linear regulator
optimized for powering ultralow-voltage circuits from a
single Li-Ion cell or 3-cell NiMH/NiCd battery.
1
•
•
•
•
•
Input Voltage Range: 0.7 V to 4.5 V
2.5 V ≤ VBATT ≤ 5.5 V
0.5V ≤ VOUT ≤ 2 V
In the typical post-regulation application VBATT is
directly connected to the battery (range 2.5 V to
5.5 V), and VIN is supplied by the output voltage of
the DC-DC converter (range 0.7 V to 4.5 V).
Ensured 350-mA Output Current
For ILOAD = 350 mA:
–
V
BATT ≥ VOUT(NOM) + 1.5 V or 2.5 V
(Whichever is Higher)
For ILOAD = 150 mA:
BATT ≥ VOUT(NOM) + 1.3 V or 2.5 V
(Whichever is Higher)
The device offers superior dropout and transient
features combined with very low quiescent currents.
In shutdown mode (Enable (EN) pin pulled low) the
device turns off and reduces battery consumption to
0.1 µA (typical). The LP5952 also features internal
protection against overtemperature, overcurrent, and
undervoltage conditions.
•
•
–
V
Excellent Load Transient Response: ±15 mV
Typical
•
•
•
•
•
•
Excellent Line Transient Response: ±1 mV Typical
50-µA Typical Quiescent Current from VBATT
10-µA Typical Quiescent Current from VIN
0.1-µA Typical Quiescent Current in Shutdown
Noise voltage = 100 µVRMS Typical
Depending upon application, only one or two tiny
surface-mount external components are required;
performance is specified for a –40°C to +125°C
junction temperature range. The device is available in
fixed output voltages from 0.5 V to 2 V. For
availability, please contact your local Texas
Instruments sales office.
Operates from a Single Li-Ion Cell or 3-Cell
NiMH/NiCd Battery
Device Information(1)
•
Thermal-Overload and Short-Circuit Protection
PART NUMBER
PACKAGE
DSBGA (5)
USON (6)
BODY SIZE (NOM)
1.326 mm × 0.96 mm
2.00 mm × 2.00 mm
2 Applications
LP5952
•
•
•
•
•
•
Mobile Phones
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Hand-Held Radios
Personal Digital Assistants
Palm-Top PCs
Portable Instruments
Battery-Powered Devices
Typical Application Circuit
VBATT: 2.7 V to 5.5 V
OUT
BATT
For example, 1.2 V
C1
A3
2.2 mF
Li-Ion
or
3-cell
LP5952
For example,
1.5 V
Load
0 to 350 mA
IN A1
Pre-
NiMh/NiCd
regulator
1 mF
EN
GND
C3
B2
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LP5952
SNVS469F –OCTOBER 2006–REVISED DECEMBER 2015
www.ti.com
Table of Contents
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description................................................. 10
7.4 Device Functional Modes........................................ 11
Application and Implementation ........................ 12
8.1 Application Information............................................ 12
8.2 Typical Application ................................................. 12
Power Supply Recommendations...................... 17
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information ................................................. 5
6.5 Electrical Characteristics........................................... 5
6.6 Electrical Characteristics: Quiescent Currents.......... 6
6.7 Electrical Characteristics: Shutdown Currents.......... 6
6.8 Electrical Characteristics: Enable Control................. 6
6.9 Electrical Characteristics: Thermal Protection .......... 7
8
9
10 Layout................................................................... 18
10.1 Layout Guidelines ................................................. 18
10.2 Layout Examples................................................... 18
11 Device and Documentation Support ................. 19
11.1 Device Support .................................................... 19
11.2 Documentation Support ....................................... 19
11.3 Community Resources.......................................... 19
11.4 Trademarks........................................................... 19
11.5 Electrostatic Discharge Caution............................ 19
11.6 Glossary................................................................ 19
6.10 Electrical Characteristics: Transient
Characteristics ........................................................... 7
6.11 Input and Output Capacitors (Recommended) ....... 7
6.12 Typical Characteristics............................................ 8
Detailed Description ............................................ 10
12 Mechanical, Packaging, and Orderable
Information ........................................................... 19
7
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (May 2013) to Revision F
Page
•
Added Device Information and Pin Configuration and Functions sections, ESD Ratings and Thermal Information
tables, Feature Description, Device Functional Modes, Application and Implementation, Power Supply
Recommendations, Layout, Device and Documentation Support, and Mechanical, Packaging, and Orderable
Information sections; update pin names to TI nomenclature.................................................................................................. 1
Deleted lead temp spec - it is in POA ................................................................................................................................... 4
Updated thermal information ................................................................................................................................................. 5
Changed values for thermal specifications in Power Dissipation section per updated thermal information ....................... 14
•
•
•
Changes from Revision D (April 2013) to Revision E
Page
•
Changed layout of National Data Sheet to TI format ........................................................................................................... 18
2
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SNVS469F –OCTOBER 2006–REVISED DECEMBER 2015
5 Pin Configuration and Functions
YZR Package
5-Pin DSBGA
Top View
OUT
A3
EN
C3
A1
IN
B2
GND
C1
BATT
NC - No internal connection
NKH Package
6-Pin USON
Top View
BATT
1
EN
6
GND
2
NC
5
IN
3
OUT
4
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
USON
DSGBA
BATT
1
C1
Input
Input
Bias input voltage; input range: 2.5 V to 5.5 V
Enable pin logic input: low = shutdown, high = active, normal operation. This
pin should not be left floating. Tie to BATT if this function is not used.
EN
6
C3
GND
IN
2
3
5
4
B2
A1
—
Ground
Input
—
Ground
Power input voltage; input range: 0.7 V to 4.5 V, VIN ≤ VBATT
Do not make connections to this pin.
Regulated output voltage
NC
OUT
A3
Output
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SNVS469F –OCTOBER 2006–REVISED DECEMBER 2015
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)(2)(3)
MIN
MAX
UNIT
IN, BATT pins: Voltage to GND, VIN ≤ VBATT
BATT pin to IN pin
–0.2
V
V
V
0.2
EN pin, voltage to GND
–0.2
Continuous power dissipation(4)
Internally limited
Junction Temperature (TJ-MAX
Storage temperature, Tstg
)
150
150
°C
°C
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to the potential at the GND pin.
(3) If Military or Aerospace specified devices are required, contact Texas Instruments Sales Office or Distributors for availability and
specifications.
(4) Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 165°C (typical) and
disengages at TJ = 145°C (typical).
6.2 ESD Ratings
VALUE
±2000
±200
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Machine model
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
4.5
UNIT
Input voltage, VIN
0.7
2.5
0
V
V
Input voltage, VBATT
5.5
Input voltage, VEN
VBATT
350
125
85
V
Recommended load current
Junction temperature, TJ
0
mA
°C
°C
–40
–40
(1)
Ambient temperature, TA
(1) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP
=
125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the
part/package in the application (RθJA), as given by: TA-MAX = TJ-MAX-OP – (RθJA × PD-MAX).
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6.4 Thermal Information
LP5952
THERMAL METRIC(1)
YZR (DSBGA)
5 PINS
181.0
NKH (USON)
6 PINS
181.6
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance(2)
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
0.9
93.1
110.3
116.7
Junction-to-top characterization parameter
Junction-to-board characterization parameter
7.4
8.0
ψJB
110.3
116.7
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(2) Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power
dissipation exists, special attention must be paid to thermal dissipation issues in board design.
6.5 Electrical Characteristics
Unless otherwise noted, typical values are for TA = 25°C, and minimum and maximum limits apply over the full operating
temperature range: –40°C ≤ TJ ≤ +125°C; specifications apply to the Typical Application Circuit with VIN = VOUT(NOM) + 1 V,
(1)(2)(3)
VBATT = VOUT(NOM) + 1.5 V or 2.5 V (whichever is higher), IOUT = 1 mA, CVIN = 1 µF, COUT = 2.2 µF, VEN = VBATT
.
PARAMETER
TEST CONDITIONS
VIN = VOUT(NOM) + 0.3 V, TA = 25°C
VIN = VOUT(NOM) + 0.3 V
MIN
–1.5
2
TYP
MAX
1.5
2
UNIT
ΔVOUT / VOUT
ΔVOUT / ΔVIN
Output voltage tolerance
VIN = VOUT(NOM) + 0.3 V to 4.5 V, VBATT
4.5 V
=
1
0.3
1
mV/V
Line regulation error
Load regulation error
ΔVOUT
ΔVBATT
/
VBATT = VOUT(NOM) + 1.5 V (≥ 2.5 V) to 5.5
V
2.2
30
60
2.2
0.5
15
DSBGA
IOUT = 1 mA to 350 mA
package
30
60
µV/mA
ΔVOUT / ΔmA
USON
IOUT = 1 mA to 350 mA
package
43
µV/mA
Output current (short
circuit)
VOUT = 0 V, VEN = VIN = VBATT = VOUT(NOM)
+ 1.5 V
ISC
350
500
1.07
1.08
0.96
0.97
mA
V
IOUT = 350 mA, VIN
VOUT(NOM) + 0.3 V
=
DSBGA
package
1.5
1.5
1.3
1.3
IOUT = 350 mA
USON
V
VIN = VOUT(NOM) + 0.3 V
package
VDO_VBATT
Output voltage dropout
(4)
(5)
VBATT
IOUT = 150 mA
VIN = VOUT(NOM) + 0.3 V
DSBGA
package
V
IOUT = 150 mA
USON
V
VIN = VOUT(NOM) + 0.3 V
package
IOUT = 350 mA
VBATT = VOUT(NOM) + 1.5 V
or 2.5 V
DSBGA
package
88
200
250
mV
Output voltage dropout
VIN
VDO_VIN
IOUT = 350 mA
VBATT = VOUT(NOM) + 1.5 V
or 2.5 V
USON
package
128
100
mV
EN
Output noise
10 Hz to 100 kHz
µVRMS
(1) All voltages are with respect to the potential at the GND pin.
(2) Minimum and maximum limits are ensured by design, test, or statistical analysis. Typical numbers are not ensured, but do represent the
most likely norm. Unless otherwise specified, conditions for typical specifications are: VIN = VOUT(NOM) + 1 V, VBATT = VOUT(NOM) + 1.5 V
or 2.5 V, whichever is higher, TA = 25°C.
(3) VOUT(NOM) is the stated output voltage option
(4) This specification does not apply if the battery voltage VBATT needs to be decreased below the minimum operating limit of 2.5 V during
this test.
(5) Dropout voltage is defined as the input to output voltage differential at which the output voltage falls to 100mV below the nominal output
voltage.
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Electrical Characteristics (continued)
Unless otherwise noted, typical values are for TA = 25°C, and minimum and maximum limits apply over the full operating
temperature range: –40°C ≤ TJ ≤ +125°C; specifications apply to the Typical Application Circuit with VIN = VOUT(NOM) + 1 V,
(1)(2)(3)
VBATT = VOUT(NOM) + 1.5 V or 2.5 V (whichever is higher), IOUT = 1 mA, CVIN = 1 µF, COUT = 2.2 µF, VEN = VBATT
.
PARAMETER
TEST CONDITIONS
Sine modulated VBATT, ƒ = 10 Hz
Sine modulated VBATT, ƒ = 100 Hz
Sine modulated VBATT, ƒ = 1 kHz
Sine modulated VIN, ƒ = 10 Hz
Sine modulated VIN, ƒ = 100 Hz
Sine modulated VIN, ƒ = 1 kHz
Sine modulated VIN, ƒ = 10 kHz
Sine modulated VIN, ƒ = 100 kHz
MIN
TYP
70
65
45
80
90
95
85
64
MAX
UNIT
Power Supply Rejection
Ratio
PSRR
PSRR
dB
Power Supply Rejection
Ratio
dB
6.6 Electrical Characteristics: Quiescent Currents
Unless otherwise noted, typical values are for TA = 25°C, and minimum and maximum limits apply over the full operating
temperature range: –40°C ≤ TJ ≤ +125°C.(1)(2)(3)
PARAMETER
Current into VBATT
Current into VIN
TEST CONDITIONS
ILOAD = 0 mA to 350mA
ILOAD = 0
MIN
TYP
50
MAX
100
28
UNIT
µA
IQ_VBATT
IQ_VIN
11
µA
(1) All voltages are with respect to the potential at the GND pin.
(2) Minimum and maximum limits are ensured by design, test, or statistical analysis. Typical numbers are not ensured, but do represent the
most likely norm. Unless otherwise specified, conditions for typical specifications are: VIN = VOUT(NOM) + 1 V, VBATT = VOUT(NOM) + 1.5 V
or 2.5 V, whichever is higher, TA = 25°C.
(3) VOUT(NOM) is the stated output voltage option
6.7 Electrical Characteristics: Shutdown Currents
Unless otherwise noted, typical values are for TA = 25°C, and minimum and maximum limits apply over the full operating
temperature range: –40°C ≤ TJ ≤ +125°C.(1)(2)(3)
PARAMETER
Current into VBATT
Current into VIN
(1) All voltages are with respect to the potential at the GND pin.
TEST CONDITIONS
VEN = 0 V
VEN = 0 V
MIN
TYP
0.1
MAX
UNIT
µA
IQ_VBATT
IQ_VIN
1
1
0.1
µA
(2) Minimum and maximum limits are ensured by design, test, or statistical analysis. Typical numbers are not ensured, but do represent the
most likely norm. Unless otherwise specified, conditions for typical specifications are: VIN = VOUT(NOM) + 1 V, VBATT = VOUT(NOM) + 1.5 V
or 2.5 V, whichever is higher, TA = 25°C.
(3) VOUT(NOM) is the stated output voltage option.
6.8 Electrical Characteristics: Enable Control
Unless otherwise noted, typical values are for TA = 25°C, and minimum and maximum limits apply over the full operating
temperature range: –40°C ≤ TJ ≤ +125°C.(1)(2)(3)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
1
UNIT
µA
V
IEN
VIL
VIH
Maximum input current at EN input
Low input threshold (shutdown)
High input threshold (enable)
0.01
0.4
1
V
(1) All voltages are with respect to the potential at the GND pin.
(2) Minimum and maximum limits are ensured by design, test, or statistical analysis. Typical numbers are not ensured, but do represent the
most likely norm. Unless otherwise specified, conditions for typical specifications are: VIN = VOUT(NOM) + 1 V, VBATT = VOUT(NOM) + 1.5 V
or 2.5 V, whichever is higher, TA = 25°C.
(3) VOUT(NOM) is the stated output voltage option.
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6.9 Electrical Characteristics: Thermal Protection
Typical values are for TA = 25°C.(1)(2)(3)
PARAMETER
TEST CONDITIONS
MIN
TYP
165
20
MAX
UNIT
°C
TSHDN
Thermal-shutdown temperature
Thermal-shutdown hysteresis
ΔTSHDN
°C
(1) All voltages are with respect to the potential at the GND pin.
(2) Minimum and maximum limits are ensured by design, test, or statistical analysis. Typical numbers are not ensured, but do represent the
most likely norm. Unless otherwise specified, conditions for typical specifications are: VIN = VOUT(NOM) + 1 V, VBATT = VOUT(NOM) + 1.5 V
or 2.5 V, whichever is higher, TA = 25°C.
(3) VOUT(NOM) is the stated output voltage option.
6.10 Electrical Characteristics: Transient Characteristics
Unless otherwise noted, typical values are for TA = 25°C, and minimum and maximum limits apply over the full operating
temperature range: –40°C ≤ TJ ≤ +125°C.(1)(2)(3)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Dynamic line transient
response VIN
VIN = VOUT(NOM) + 0.3 V to
VOUT(NOM) + 0.9 V; tr, tf = 10 µs
ΔVOUT
ΔVOUT
±1
mV
Dynamic line transient
response VBATT
VBATT = VOUT(NOM) + 1.5 V to
VOUT(NOM) + 2.1 V; tr, tf = 10 µs
±15
±15
mV
mV
Pulsed load 0 ...300 mA,
di/dt = 300 mA/1 µs
DSBGA
package
Dynamic load transient
response
ΔVOUT
Pulsed load 0 ...300mA, di/dt
= 300 mA/1 µs
USON package
–35/+15
70
mV
µs
TSTARTUP Start-up time
EN to 0.95 × VOUT
150
(1) All voltages are with respect to the potential at the GND pin.
(2) Minimum and maximum limits are ensured by design, test, or statistical analysis. Typical numbers are not ensured, but do represent the
most likely norm. Unless otherwise specified, conditions for typical specifications are: VIN = VOUT(NOM) + 1 V, VBATT = VOUT(NOM) + 1.5 V
or 2.5 V, whichever is higher, TA = 25°C.
(3) VOUT(NOM) is the stated output voltage option.
6.11 Input and Output Capacitors (Recommended)
All values are for TA = 25°C.(1)(2)(3)
PARAMETER
TEST CONDITIONS
Capacitance(4)
MIN
1.5
3
TYP
MAX
10
UNIT
µF
2.2
COUT
Output capacitance
ESR
300
mΩ
Capacitance(4), not needed in typical post-
regulation application (see Figure 18)
0.47
3
1
µF
CVIN
Input capacitance at VIN
ESR
300
mΩ
(1) All voltages are with respect to the potential at the GND pin.
(2) Minimum and maximum limits are ensured by design, test, or statistical analysis. Typical numbers are not ensured, but do represent the
most likely norm. Unless otherwise specified, conditions for typical specifications are: VIN = VOUT(NOM) + 1 V, VBATT= VOUT(NOM) + 1.5 V
or 2.5 V, whichever is higher, TA = 25°C.
(3) VOUT(NOM) is the stated output voltage option.
(4) The capacitor tolerance should be 30% or better over temperature. The full operating conditions for the application should be considered
when selecting a suitable capacitor to ensure that the minimum value of capacitance is always met. Recommended capacitor type is
X7R. However, dependent on application, X5R, Y5V, and Z5U can also be used. The shown minimum limit represents real minimum
capacitance, including all tolerances and must be maintained over temperature and DC bias voltage (See Detailed Design Procedure in
Application and Implementation.)
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6.12 Typical Characteristics
Unless otherwise specified, TA = 25°C, CIN = 1-µF ceramic, COUT = 2.2-µF ceramic, VIN = VOUT(NOM) + 1 V, VBATT = VOUT(NOM)
1.5 V, EN pin is tied to VBATT (DSBGA package).
+
140
130
120
110
100
90
0.4
0.3
0.2
0.1
0.0
-0.1
-0.2
-0.3
-0.4
80
70
60
0
20 40 60 80 100 120
TEMPERATURE (°C)
-40 -20
0
20 40 60 80 100 120
-40 -20
TEMPERATURE (°C)
ILOAD = 350 mA
Figure 1. Output Voltage Change vs Temperature
Figure 2. Dropout VIN vs Temperature
90
I
= 0
LOAD
80
70
60
50
40
30
20
10
T
T
= 125°C
= 25°C
A
A
0
0
0
T
= -40°C
A
TIME (10 ms/DIV)
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
V
(V)
1.5-V Option
BATT
Figure 3. Inrush Current VIN
Figure 4. Quiescent Current IQ_VBATT vs VBATT
100
I
= 0
LOAD
90
80
70
60
50
40
30
20
T
T
= 125°C
= 25°C
A
A
T
= -40°C
A
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
LOAD CURRENT (mA)
V
/V (V)
BATT IN
Figure 5. Ground Current vs VBATT / VIN
Figure 6. Ground Current vs Load Current
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Typical Characteristics (continued)
Unless otherwise specified, TA = 25°C, CIN = 1-µF ceramic, COUT = 2.2-µF ceramic, VIN = VOUT(NOM) + 1 V, VBATT = VOUT(NOM)
+
1.5 V, EN pin is tied to VBATT (DSBGA package).
0
-20
-40
-60
-80
0
CIN = 100nF
-20
-40
-60
-80
I
L
= 300 mA
I
= 50 mA
= 0 mA
L
I
L
I
= 0 mA
L
10
100
1k
10k
100k
1M
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
1.5-V Option
1.5-V Option
Figure 7. Power Supply Rejection Ratio VIN
Figure 8. Power Supply Rejection Ratio VBATT
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7 Detailed Description
7.1 Overview
The LP5952 is a dual-supply-rail linear regulator optimized for powering ultralow-voltage circuits from a single Li-
Ion cell or 3 cell NiMH/NiCd batteries. In a typical application, BATT is connected to the battery, and IN can be
supplied by the output of front stage DC-DC Converter. IN does not exceed BATT at any time.
7.2 Functional Block Diagram
BATT
IN
VREF
+
-
OUT
Thermal,
undervoltage, and
overcurrent
Enable and
start-up
management
EN
protection
GND
7.3 Feature Description
7.3.1 Dual-Rail Supply
The LP5952 requires two different supply voltages:
•
•
VIN, the power input voltage, is regulated to the fixed output voltage.
VBATT, the bias input voltage, supplies internal circuitry.
It is important that VIN does not exceed VBATT at any time. If the device is used in the typical post-regulation
application as shown in Figure 18, the sequencing of the two power supplies is not an issue because VBATT
supplies both the DC-DC regulator and the LP5952 device. The output voltage of the DC-DC regulator takes
some time to rise up and supply the input voltage of the device. In this application VIN always ramps up more
slowly than VBATT
.
If VIN is shorted to VBATT, the voltages at the two supply pins ramp up simultaneously causing no problems.
However, in applications with two independent supplies connected to the LP5952, special care must be taken to
ensure that VIN is always ≤ VBATT
.
7.3.2 No-Load Stability
The LP5952 remains stable and in regulation with no external load. This is an important consideration in some
circuits, for example, CMOS RAM keep-alive applications.
7.3.3 Fast Turnon
Fast turnon is ensured by an optimized architecture allowing a fast ramp of the output voltage to reach the target
voltage while the inrush current is controlled low at 120 mA typical (for a COUT of 2.2 µF).
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Feature Description (continued)
7.3.4 Short-Circuit Protection
The LP5952 is short-circuit protected and, in the event of a peak overcurrent condition, the output current
through the NFET pass device is limited.
If the overcurrent condition exists for a longer time, the average power dissipation increases depending on the
input-to-output voltage difference until the thermal shutdown circuitry turns the NFET off. Refer to Power
Dissipation and Device Operation for power dissipation calculations.
7.3.5 Thermal-Overload Protection
Thermal-overload protection limits the total power dissipation in the LP5952. When the junction temperature
exceeds TJ = 165°C typical, the shutdown logic is triggered, and the NFET is turned off, allowing the device to
cool down. After the junction temperature dropped by 20°C (temperature hysteresis) typical, the NFET is
activated again. This results in a pulsed output voltage during continuous thermal-overload conditions.
The thermal-overload protection is designed to protect the LP5952 in the event of a fault condition. For normal
continuous operation, do not exceed the absolute maximum junction temperature rating of TJ = 150°C (see
Absolute Maximum Ratings).
7.3.6 Reverse Current Path
The internal NFET pass device in LP5952 has an inherent parasitic body diode. During normal operation, the
input voltage is higher than the output voltage, and the parasitic diode is reverse biased. However, if the output is
pulled above the input in an application, the current flows from the output to the input as the parasitic diode gets
forward biased. The output can be pulled above the input as long as the current in the parasitic diode is limited to
50 mA. For currents above this limit an external Schottky diode must be connected from VOUT to VIN (cathode on
VIN, anode on VOUT).
7.4 Device Functional Modes
7.4.1 Enable Operation
The LP5952 may be switched to an ON or OFF state by a logic input at the EN pin, VEN. A logic high at this pin
turns the device on. When the enable pin is low, the regulator output is off, and the device typically consumes
0.1 µA.
If the application does not require the enable switching feature, the EN pin must be tied to VBATT to keep the
regulator output permanently on.
To ensure proper operation, the signal source used to drive the EN input must be able to swing above and below
the specified turnon and turnoff voltage thresholds shown in VIL and VIH in Electrical Characteristics: Enable
Control.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LP5952 is designed to meet ultralow input-voltage application, by implementing VBATT as power supply of
this device. The VBATT is connected to the battery (range 2.5 V to 5.5 V), the VIN range can be 0.7 V to 4.5 V.
The device offers superior dropout and transient features combined with very low-quiescent currents. The
LP5952 delivers this performance in standard packages DSBGA and USON with an operating junction
temperature (TJ) of –40°C to +125°C.
8.2 Typical Application
8.2.1 Dual-Rail Linear Regulator
VBATT: 2.7 V to 5.5 V
OUT
BATT
For example, 1.2 V
C1
A3
2.2 mF
Li-Ion
or
3-cell
LP5952
For example,
1.5 V
Load
0 to 350 mA
IN A1
Pre-
NiMh/NiCd
regulator
1 mF
EN
GND
C3
B2
Figure 9. LP5952 Typical Application Circuit
8.2.1.1 Design Requirements
For typical dual-rail linear regulator parameters, see Table 1.
Table 1. Design Parameters
DESIGN PARAMETER
Input voltage range
EXAMPLE VALUE
0.7 V to 4.5 V
2.7 V to 5.5 V
1.5 V
VBATT voltage range
Output voltage
Output current
350 mA
Output capacitor range
Input/output capacitor ESR range
2.2 µF
3 mΩ to 300 mΩ
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 External Capacitors
As is common with most regulators, the LP5952 requires external capacitors to ensure stable operation. The
LP5952 is specifically designed for portable applications requiring minimum board space and the smallest size
components. These capacitors must be correctly selected for good performance.
8.2.1.2.2 Input Capacitor
If the LP5952 is used as a stand-alone device, an input capacitor at VIN is required for stability. It is
recommended that a 1-µF capacitor be connected between the LP5952 power voltage IN pin and ground. (This
capacitance value may be increased without limit).
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This capacitor must be located a distance of not more than 1 cm from the IN pin and returned to a clean analog
ground. Any good quality ceramic, tantalum, or film capacitor may be used at the input.
A capacitor at VBATT is not required if the distance to the supply does not exceed 5 cm.
If the device is used in the typical application as post regulator after a DC-DC regulator, no input capacitors are
required — the capacitors of the DC-DC regulator (CIN and COUT) are sufficient if both components are mounted
close to each other and a proper GND plane is used. If the distance between the output capacitor of the DC-DC
regulator and the IN pin of the LP5952 is larger than 5 cm, adding an input capacitor at VIN is recommended.
NOTE
Important: Tantalum capacitors can suffer catastrophic failures due to surge current
when connected to a low-impedance source of power (like a battery or a very large
capacitor). If a tantalum capacitor is used at the input, it must be ensured by the
manufacturer to have a surge current rating sufficient for the application.
The equivalent series resistance (ESR) of the input capacitor should be in the range of 3 mΩ to 300 mΩ. The
tolerance and temperature coefficient must be considered when selecting the capacitor to ensure the
capacitance remains ≥ 470 nF over the entire operating temperature range.
8.2.1.2.3 Output Capacitor
The LP5952 is designed specifically to work with very small ceramic output capacitors. A ceramic capacitor
(dielectric types X7R, Z5U, or Y5V) in the 2.2-µF range (up to 10 µF) and with an ESR between 3 mΩ to 300 mΩ
is suitable as COUT in the LP5952 application circuit.
This capacitor must be located a distance of not more than 1 cm from the OUT pin and returned to a clean
analog ground.
It is also possible to use tantalum or film capacitors at the device output, VOUT, but these are not as attractive for
reasons of size and cost (see Capacitor Characteristics).
8.2.1.2.4 Capacitor Characteristics
The LP5952 is designed to work with ceramic capacitors on the output to take advantage of the benefits they
offer. For capacitance values in the 1-µF to 4.7-µF range, ceramic capacitors are the smallest, least expensive
and have the lowest ESR values, thus making them best for eliminating high-frequency noise. The ESR of a
typical 1-µF ceramic capacitor is in the range of 3 mΩ to 40 mΩ, which easily meets the ESR requirement for
stability for the LP5952.
For both input and output capacitors, careful interpretation of the capacitor specification is required to ensure
correct device operation. The capacitor value can change greatly, depending on the operating conditions and
capacitor type.
In particular, the output capacitor selection must take account of all the capacitor parameters, to ensure that the
specification is met within the application. The capacitance can vary with DC bias conditions as well as
temperature and frequency of operation. Capacitor values show some decrease over time due to aging. The
capacitor parameters are also dependant on the particular case size, with smaller sizes giving poorer
performance figures in general. Figure 10 shows a typical graph comparing different capacitor case sizes in a
capacitance vs. DC Bias plot. As shown Figure 10, increasing the DC-bias condition can result in the capacitance
value falling below the minimum value given in Input and Output Capacitors (Recommended) (0.47 µF or 1.5 µF
in this case). The graph shows the capacitance out of specification for the 0402 case size capacitor at higher
bias voltages. It is therefore recommended that the capacitor-manufacturer specifications for the nominal value
capacitor are consulted for all conditions, as some capacitor sizes (such as 0402) may not be suitable in the
actual application.
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0603, 10V, X5R
100%
80%
60%
40%
20%
0402, 6.3V, X5R
0
1.0
2.0
3.0
4.0
5.0
DC BIAS (V)
Figure 10. Typical Variation In Capacitance vs DC Bias
Capacitance of the ceramic capacitor can vary with temperature. The capacitor type X7R, which operates over a
temperature range of –55°C to +125°C, only varies the capacitance to within ±15%. The capacitor type X5R has
a similar tolerance over a reduced temperature range of –55°C to +85°C. Many large value ceramic capacitors,
larger than 1 µF, are manufactured with Z5U or Y5V temperature characteristics. Their capacitance can drop by
more than 50% as the temperature varies from 25°C to 85°C. Therefore, X7R is recommended over Z5U and
Y5V in applications where the ambient temperature changes significantly above or below 25°C.
Tantalum capacitors are less desirable than ceramic for use as output capacitors because they are more
expensive when comparing equivalent capacitance and voltage ratings in the 1-µF to 4.7-µF range.
Another important consideration is that tantalum capacitors have higher ESR values than equivalent size
ceramics. This means that while it may be possible to find a tantalum capacitor with an ESR value within the
stable range, it would have to be larger in capacitance (which means bigger and more costly) than a ceramic
capacitor with the same ESR value. The ESR of a typical tantalum increases about 2:1 as the temperature goes
from 25°C down to –40°C, so some guard band must be allowed.
8.2.1.2.5 Power Dissipation and Device Operation
The permissible power dissipation for any package is a measure of the capability of the device to pass heat from
the power source, the junctions of the device, to the ultimate heat sink, the ambient environment. Thus the power
dissipation is dependent on the ambient temperature and the thermal resistance across the various interfaces
between the die and ambient air.
As stated in the Recommended Operating Conditions, the allowable power dissipation for the device in a given
package can be calculated using Equation 1:
PD = (TJ(MAX) – TA) / RθJA
(1)
With an RRθJA = 181°C/W, the device in the 5-pin DSBGA package returns a value of 552 mW with a maximum
junction temperature of 125°C at TA of 25°C or 221 mW at TA of 85°C.
The actual power dissipation across the device can be estimated by Equation 2:
PD = (VIN – VOUT) × IOUT
(2)
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This establishes the relationship between the power dissipation allowed due to thermal consideration, the voltage
drop across the device, and the continuous current capability of the device. Equation 1 and Equation 2 must be
used to determine the optimum operating conditions for the device in any application. As an example, to keep full
load current capability of 350 mA for a 1.5-V output voltage option at a high ambient temperature of 85°C, VIN
has to be kept ≤ 2.1 V (for DSBGA package):
VIN ≤ PD / IOUT + VOUT = 221 mW / 350 mA + 1.5 V = 2.1 V
(3)
Figure 11 shows the output current derating due to these considerations:
350
DSBGA
USON
300
250
200
150
100
50
0
0.5
1
1.5
2
2.5
3
3.5
4
VIN - VOUT (V)
D001
TA = 85°C
θJA(DSBGA) = 181°C/W
VOUT = 1.5 V
R
R
θJA(USON) = 181.6°C/W
Figure 11. Maximum Load Current vs VIN – VOUT
The typical contribution of the bias input voltage supply VBATT to the power dissipation can be neglected
(Equation 4):
PD_VBATT = VBATT × IQVBATT = 5.5 V × 50 µA = 0.275 mW typical
(4)
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8.2.1.3 Application Curves
I
= 350 mA
L
I
L
= 350 mA
0
0
0
0
TIME (10 µs/DIV)
TIME (10 µs/DIV)
0.7-V Option
1.5-V Option
Figure 12. Enable Start-Up Time
Figure 13. Enable Start-Up Time
350
350
0
0
TIME (50 µs/DIV)
TIME (50 µs/DIV)
0.7-V Option
1.5-V Option
Figure 14. Load Transient Response
Figure 15. Load Transient Response
V
= 3.1V
I
= 350 mA
BATT
L
I
L
= 350 mA
3.1
2.5
3.6
3.0
TIME (100 ms/DIV)
TIME (100 ms/DIV)
1.5-V Option
1.5-V Option
Figure 16. Line Transient Response VIN
Figure 17. Line Transient Response VBATT
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8.2.2 Additional Application Circuit
OUT
2.2 mF
BATT
IN
1.5 V
C1
A3
V
OUTDCDC
LP5952
V
BATT
3 V to 5.5 V
V
IN
Load
0 to 350 mA
1.8 V
SW
L1: 2.2 mH
A1
C3
A1
B2
4.7 mF
LM3671TL-1.8
A3
10 mF
GND
EN
EN
GND
B2
FB
C3
C1
Figure 18. Typical Application Circuit With DC-DC Converter as Pre-Regulator for VIN
9 Power Supply Recommendations
This device is designed to operate from an input supply voltage range of 0.7 V to 4.5 V. The input supply should
be well regulated and free of spurious noise. A minimum capacitor value of 1-μF is required to be within 1 cm of
the IN pin. The VBATT range is 2.5 V to 5.5 V and, in the typical application, VBATT is connected to batteries. In
any application, VIN does not exceed VBATT
.
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10 Layout
10.1 Layout Guidelines
For best overall performance, place all circuit components on the same side of the circuit board and as near to
the respective LDO pin connections as practical. Place ground return connections as close as possible to the
input and output capacitor and to the LDO ground pin, connected by a wide, copper surface. The use of vias and
long traces to create LDO circuit connection is strongly discouraged and negatively affect system performance.
10.2 Layout Examples
COUT
OUT2
EN
C3
OUT
A3
B2
C1
BATT
A1
IN
GND
CIN
CBATT
Figure 19. LP5952 DSBGA Layout Example
1
2
3
6
5
4
EN
BATT
GND
IN
CBATT
NC
CIN
COUT
OUT
Figure 20. LP5952 WSON Layout Example
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11 Device and Documentation Support
11.1 Device Support
For availability of evaluation boards, refer to the product folder of LP5952 at www.ti.com.
11.2 Documentation Support
11.2.1 Related Documentation
For information regarding evaluation boards, please refer to AN-1531 LP5952 Evaluation Board (SNVA188).
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LP5952LC-1.2/NOPB
LP5952LC-1.3/NOPB
LP5952LC-1.5/NOPB
LP5952LC-1.8/NOPB
LP5952TL-1.0/NOPB
LP5952TL-1.2/NOPB
LP5952TL-1.3/NOPB
LP5952TL-1.5/NOPB
LP5952TL-1.6/NOPB
LP5952TL-1.8/NOPB
LP5952TLX-1.0/NOPB
LP5952TLX-1.2/NOPB
LP5952TLX-1.5/NOPB
LP5952TLX-1.8/NOPB
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
USON
USON
NKH
NKH
NKH
NKH
YZR
YZR
YZR
YZR
YZR
YZR
YZR
YZR
YZR
YZR
6
6
6
6
5
5
5
5
5
5
5
5
5
5
1000 RoHS & Green
1000 RoHS & Green
1000 RoHS & Green
1000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
L28
L43
L25
L29
L
NIPDAU
NIPDAU
USON
USON
NIPDAU
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
250
250
250
250
250
250
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
7
U
T
B
8
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
L
7
T
8
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Nov-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LP5952LC-1.2/NOPB
LP5952LC-1.3/NOPB
LP5952LC-1.5/NOPB
LP5952LC-1.8/NOPB
LP5952TL-1.0/NOPB
LP5952TL-1.2/NOPB
LP5952TL-1.3/NOPB
LP5952TL-1.5/NOPB
LP5952TL-1.6/NOPB
LP5952TL-1.8/NOPB
LP5952TLX-1.0/NOPB
LP5952TLX-1.2/NOPB
LP5952TLX-1.5/NOPB
LP5952TLX-1.8/NOPB
USON
USON
NKH
NKH
NKH
NKH
YZR
YZR
YZR
YZR
YZR
YZR
YZR
YZR
YZR
YZR
6
6
6
6
5
5
5
5
5
5
5
5
5
5
1000
1000
1000
1000
250
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
12.4
12.4
12.4
12.4
8.4
2.2
2.2
2.2
2.2
2.2
2.2
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.0
1.0
8.0
8.0
8.0
8.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
12.0
12.0
12.0
12.0
8.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
USON
2.2
1.0
USON
2.2
1.0
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
1.04
1.04
1.04
1.04
1.04
1.04
1.04
1.04
1.04
1.04
0.76
0.76
0.76
0.76
0.76
0.76
0.76
0.76
0.76
0.76
250
8.4
8.0
250
8.4
8.0
250
8.4
8.0
250
8.4
8.0
250
8.4
8.0
3000
3000
3000
3000
8.4
8.0
8.4
8.0
8.4
8.0
8.4
8.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Nov-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LP5952LC-1.2/NOPB
LP5952LC-1.3/NOPB
LP5952LC-1.5/NOPB
LP5952LC-1.8/NOPB
LP5952TL-1.0/NOPB
LP5952TL-1.2/NOPB
LP5952TL-1.3/NOPB
LP5952TL-1.5/NOPB
LP5952TL-1.6/NOPB
LP5952TL-1.8/NOPB
LP5952TLX-1.0/NOPB
LP5952TLX-1.2/NOPB
LP5952TLX-1.5/NOPB
LP5952TLX-1.8/NOPB
USON
USON
NKH
NKH
NKH
NKH
YZR
YZR
YZR
YZR
YZR
YZR
YZR
YZR
YZR
YZR
6
6
6
6
5
5
5
5
5
5
5
5
5
5
1000
1000
1000
1000
250
208.0
208.0
208.0
208.0
208.0
208.0
208.0
208.0
208.0
208.0
208.0
208.0
208.0
208.0
191.0
191.0
191.0
191.0
191.0
191.0
191.0
191.0
191.0
191.0
191.0
191.0
191.0
191.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
USON
USON
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
250
250
250
250
250
3000
3000
3000
3000
Pack Materials-Page 2
MECHANICAL DATA
YZR0005xxx
D
0.600±0.075
E
TLA05XXX (Rev C)
D: Max = 1.356 mm, Min =1.296 mm
E: Max = 0.99 mm, Min = 0.93 mm
4215043/A
12/12
A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.
B. This drawing is subject to change without notice.
NOTES:
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MECHANICAL DATA
NKH0006B
LCA06B (Rev A)
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