LP5996SD-3033/NOPB [TI]
Dual Linear Regulator with 300mA and 150mA Outputs;型号: | LP5996SD-3033/NOPB |
厂家: | TEXAS INSTRUMENTS |
描述: | Dual Linear Regulator with 300mA and 150mA Outputs 输出元件 调节器 |
文件: | 总18页 (文件大小:1033K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LP5996
www.ti.com
SNVS415C –NOVEMBER 2006–REVISED MAY 2013
LP5996 Dual Linear Regulator with 300mA and 150mA Outputs
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1
FEATURES
PACKAGE
2
•
•
2 LDO Outputs with Independent Enable
•
•
All available in Lead Free option.
10 pin SON 3mm x 3mm
1.5% Accuracy at Room Temperature, 3% over
Temperature
For other package options contact your Texas Instruments sales
office.
•
•
Thermal Shutdown Protection
Stable with Ceramic Capacitors
DESCRIPTION
The LP5996 is a dual low dropout regulator. The first
regulator can source 150mA, while the second is
capable of sourcing 300mA.
APPLICATIONS
•
•
•
Cellular Handsets
PDA's
The LP5996 provides 1.5% accuracy requiring an
ultra low quiescent current of 35µA. Separate enable
pins allow each output of the LP5996 to be shut
down, drawing virtually zero current.
Wireless Network Adaptors
KEY SPECIFICATIONS
•
•
•
•
Input Voltage Range, 2.0V to 6.0V
Low Dropout Voltage at 300mA, 210mV
Ultra-Low IQ (Enabled), 35µA
The LP5996 is designed to be stable with small
footprint ceramic capacitors down to 1µF.
The LP5996 is available in fixed output voltages and
comes in a 10 pin, 3mm x 3mm package.
Virtually Zero IQ (Disabled), <10nA
Typical Application Circuit
LP5996
1
2
3
10
V
OUT1
V
V
OUT1
V
IN
IN
EN1
EN2
EN1
EN2
9
V
OUT2
V
OUT2
4
C
BYP
1 PF
10 nF
1 PF PF1
GND
6
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2013, Texas Instruments Incorporated
LP5996
SNVS415C –NOVEMBER 2006–REVISED MAY 2013
www.ti.com
Functional Block Diagram
LDO1
V
V
V
IN
OUT1
EN1
EN2
LDO2
OUT2
C
BYP
V
REF
GND
Pin Descriptions
Name
VIN
Pin No
Function
1
2
Voltage Supply Input. Connect a 1µF capacitor between this pin and GND.
EN1
Enable Input to Regulator 1. Active high input.
High = On. Low = OFF.
EN2
3
4
Enable Input to Regulator 2. Active high input.
High = On. Low = OFF.
CBYP
Internal Voltage Reference Bypass. Connect a 10nF capacitor from this pin to GND to reduce noise
and improve line transient and PSRR.
This pin may be left open.
N/C
GND
N/C
5
6
7
8
9
No Connection. Do not connect to any other pin.
Common Ground pin. Connect externally to exposed pad.
No Connection. Do not connect to any other pin.
No Connection. Do not connect to any other pin.
N/C
VOUT2
Output of Regulator 2. 300mA maximum current output. Connect a 1µF capacitor between this pin to
GND.
VOUT1
GND
10
Output of Regulator 1. 150mA maximum current output. Connect a 1µF capacitor between this pin to
GND.
Pad
Common Ground. Connect to Pin 6.
2
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Connection Diagram
10-Pin SON Package
N/C
N/C
GND
VOUT1
V
OUT2
10
9
8
7
6
GND
1
2
3
4
5
V
EN1
EN2
C
N/C
IN
BYP
Top View
Figure 1. See Package Number DSC0010A
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
(1) (2)(3)
Absolute Maximum Ratings
Input Voltage
-0.3V to 6.5V
VOUT1, VOUT2, EN1, and EN2 Voltage to GND
-0.3V to (VIN + 0.3V) with 6.5V (max)
Junction Temperature (TJ-MAX
)
150°C
235°C
(4)
Lead/Pad Temp.
Storage Temperature
-65°C to 150°C
Continuous Power Dissipation Internally Limited(5)
ESD Rating(6)
Human Body Model
2.0kV
200V
Machine Model
(1) All Voltages are with respect to the potential at the GND pin.
(2) Absolute Maximum Ratings are limits beyond which damage can occur. Operating Ratings are conditions under which operation of the
device is ensured. Operating Ratings do not imply ensured performance limits. For ensured performance limits and associated test
conditions, see the Electrical Characteristics tables.
(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office / Distributors for
availability and specifications.
(4) For detailed soldering specifications and information, please refer to Application Note AN-1187, Leadless Leadframe Package
SNOA401.
(5) Internal thermal shutdown circuitry protects the device from permanent damage.
(6) The human body model is 100pF discharged through a 1.5kΩ resistor into each pin. The machine model is a 200pF capacitor
discharged directly into each pin.
(1) (2)
Operating Ratings
Input Voltage
2.0V to 6.0V
EN1, EN2 Voltage
0 to (VIN + 0.3V) to 6.0V (max)
(1) Absolute Maximum Ratings are limits beyond which damage can occur. Operating Ratings are conditions under which operation of the
device is ensured. Operating Ratings do not imply ensured performance limits. For ensured performance limits and associated test
conditions, see the Electrical Characteristics tables.
(2) All Voltages are with respect to the potential at the GND pin.
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Operating Ratings (1) (2) (continued)
Junction Temperature
-40°C to 125°C
-40°C to 85°C
(3)
Ambient Temperature Range, TA
(3) The maximum ambient temperature (TA(max)) is dependant on the maximum operating junction temperature (TJ(max-op) = 125°C), the
maximum power dissipation of the device in the application (PD(max)), and the junction to ambient thermal resistance of the part/package
in the application (θJA), as given by the following equation: TA(max) = TJ(max-op) - (θJA × PD(max)).
(1)
Thermal Properties
Junction To Ambient Thermal Resistance(2)
θJA SON-10 Package
55°C/W
(1) Absolute Maximum Ratings are limits beyond which damage can occur. Operating Ratings are conditions under which operation of the
device is ensured. Operating Ratings do not imply ensured performance limits. For ensured performance limits and associated test
conditions, see the Electrical Characteristics tables.
(2) Junction to ambient thermal resistance is dependant on the application and board layout. In applications where high maximum power
dissipation is possible, special care must be paid to thermal dissipation issues in board design.
Electrical Characteristics(1) (2)
Unless otherwise noted, VEN = 950mV, VIN = VOUT + 1.0V, or 2.0V, whichever is higher, where VOUT is the higher of VOUT1 and
VOUT2. CIN = 1 µF, IOUT = 1 mA, COUT1 = COUT2 = 1.0µF.
Typical values and limits appearing in normal type apply for TA = 25°C. Limits appearing in boldface type apply over the full
junction temperature range for operation, −40 to +125°C.
Limit
Parameter
Test Conditions
Typ
Units
Min
Max
(3)
VIN
Input Voltage
2
6
V
ΔVOUT
Output Voltage Tolerance
IOUT = 1mA
1.5V < VOUT ≤ 3.3V
OUT ≤ 1.5V
-2.5
-3.75
+2.5
+3.75
%
V
-2.75
+2.75
-4
+4
Line Regulation Error
Load Regulation Error
VIN = (VOUT(NOM) + 1.0V) to 6.0V
0.03
85
0.3
%/V
IOUT = 1mA to 150mA
(LDO 1)
155
µV/mA
IOUT = 1mA to 300mA
(LDO 2)
26
110
210
35
85
(4)
VDO
Dropout Voltage
IOUT = 1mA to 150mA
(LDO 1)
220
550
100
110
110
170
mV
µA
IOUT = 1mA to 300mA
(LDO 2)
IQ
Quiescent Current
LDO 1 ON, LDO 2 ON
IOUT1= IOUT2 = 0mA
LDO 1 ON, LDO 2 OFF
IOUT1 = 150mA
45
LDO 1 OFF, LDO 2 ON
IOUT2 = 300mA
45
LDO 1 ON, LDO 2 ON
IOUT1 = 150mA, IOUT2 = 300m
70
VEN1 = VEN2 = 0.4V
LDO 1
0.5
420
550
10
nA
ISC
Short Circuit Current Limit
Maximum Output Current
750
840
mA
LDO 2
IOUT
LDO 1
150
300
mA
LDO 2
(1) All Voltages are with respect to the potential at the GND pin.
(2) Min Max limits are ensured by design, test or statistical analysis. Typical numbers are not ensured, but do represent the most likely
norm.
(3) VIN(MIN) = VOUT(NOM) + 0.5V, or 2.0V, whichever is higher.
(4) Dropout voltage is voltage difference between input and output at which the output voltage drops to 100mV below its nominal value.
This parameter only for output voltages above 2.0V
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Electrical Characteristics(1) (2) (continued)
Unless otherwise noted, VEN = 950mV, VIN = VOUT + 1.0V, or 2.0V, whichever is higher, where VOUT is the higher of VOUT1 and
VOUT2. CIN = 1 µF, IOUT = 1 mA, COUT1 = COUT2 = 1.0µF.
Typical values and limits appearing in normal type apply for TA = 25°C. Limits appearing in boldface type apply over the full
junction temperature range for operation, −40 to +125°C.
Limit
Parameter
Test Conditions
Typ
Units
Min
Max
PSRR
Power Supply Rejection
Ratio(5)
f = 1kHz, IOUT = 1mA LDO1
58
70
45
60
36
75
to 150mA
CBYP = 10nF
LDO2
dB
f = 20kHz, IOUT
1mA to 150mA
CBYP = 10nF
=
LDO1
LDO2
en
Output noise Voltage(5)
BW = 10Hz to
100kHz
CBYP = 10nF
VOUT = 0.8V
VOUT = 3.3V
µVRMS
TSHUTDOWN Thermal Shutdown
Temperature
Hysteresis
160
20
°C
Enable Control Characteristics
IEN
Input Current at VEN1 or VEN2 VEN = 0.0V
0.005
2
0.1
5
µA
VEN = 6V
VIL
VIH
Low Input Threshold
High Input Threshold
0.4
V
V
0.95
Timing Characteristics
(5)
TON
Turn On Time
To 95% Level
CBYP = 10nF
300
20
µs
Transient
Response
Line Transient Response
Trise = Tfall = 10µs
δVIN = 1VCBYP = 10nF
(5)
|δVOUT
|
Load Transient Response
Trise = Tfall = 1µs
LDO 1
IOUT = 1mA to 150mA
mV
(pk - pk)
175
150
(5)
|δVOUT
|
LDO 2
IOUT = 1mA to 300mA
(5) This electrical specification is ensured by design.
Output Capacitor, Recommended Specifications
Limit
Parameter
Test Conditions
Nom
Units
Min
0.7
5
Max
COUT
Output Capacitance
Capacitance
1.0
µF
(1)
ESR
500
mΩ
(1) The Capacitor tolerance should be 30% or better over temperature. The full operating conditions for the application should be
considered when selecting a suitable capacitor to ensure that the minimum value of capacitance is always met. Recommended
capacitor is X7R. However, depending on the application, X5R, Y5V and Z5U can also be used. (See capacitor section in Applications
Hints).
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Typical Performance Characteristics.
Unless otherwise specified, CIN = 1.0µF Ceramic, COUT1 = COUT2 = 1.0µF Ceramic, CBYP = 10nF, VIN = VOUT2(NOM) + 1.0V, TA =
25°C, VOUT1(NOM) = 3.3V, VOUT2(NOM) = 3.3V, Enable pins are tied to VIN.
Output Voltage Change vs Temperature
Ground Current vs Load Current,LDO1
Figure 2.
Figure 3.
Ground Current vs Load Current, LDO2
Ground Current vs VIN, ILOAD = 1mA
Figure 4.
Figure 5.
Dropout Voltage vs ILOAD, LDO1
Dropout Voltage vs ILOAD, LDO2
Figure 6.
Figure 7.
6
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Typical Performance Characteristics. (continued)
Unless otherwise specified, CIN = 1.0µF Ceramic, COUT1 = COUT2 = 1.0µF Ceramic, CBYP = 10nF, VIN = VOUT2(NOM) + 1.0V, TA =
25°C, VOUT1(NOM) = 3.3V, VOUT2(NOM) = 3.3V, Enable pins are tied to VIN.
Line Transient, CBYP = 10nF
Line Transient, CBYP = 0
Figure 8.
Figure 9.
Load Transient, LDO1
Load Transient, LDO2
Figure 10.
Figure 11.
Noise Density, LDO1
Noise Density, LDO2
Figure 12.
Figure 13.
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Typical Performance Characteristics. (continued)
Unless otherwise specified, CIN = 1.0µF Ceramic, COUT1 = COUT2 = 1.0µF Ceramic, CBYP = 10nF, VIN = VOUT2(NOM) + 1.0V, TA =
25°C, VOUT1(NOM) = 3.3V, VOUT2(NOM) = 3.3V, Enable pins are tied to VIN.
Short Circuit Current, LDO1
Short Circuit Current, LDO2
Figure 14.
Figure 15.
Power Supply Rejection Ratio, LDO1
Power Supply Rejection Ratio, LDO2
Figure 16.
Figure 17.
Enable Start-up Time, CBYP = 0
Enable Start-up Time, CBYP = 10nF
Figure 18.
Figure 19.
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SNVS415C –NOVEMBER 2006–REVISED MAY 2013
APPLICATION HINTS
OPERATION DESCRIPTION
The LP5996 is a low quiescent current, power management IC, designed specifically for portable applications
requiring minimum board space and smallest components. The LP5996 contains two independently selectable
LDOs. The first is capable of sourcing 150mA at outputs between 0.8V and 3.3V. The second can source 300mA
at an output voltage of 0.8V to 3.3V.
INPUT CAPACITOR
An input capacitor is required for stability. It is recommended that a 1.0µF capacitor be connected between the
LP5996 input pin and ground (this capacitance value may be increased without limit).
This capacitor must be located a distance of not more than 1cm from the input pin and returned to a clean
analogue ground. Any good quality ceramic, tantalum, or film capacitor may be used at the input.
Important: Tantalum capacitors can suffer catastrophic failures due to surge current when connected to a low-
impedance source of power (like a battery or a very large capacitor). If a tantalum capacitor is used at the input,
it must be ensured by the manufacturer to have a surge current rating sufficient for the application.
There are no requirements for the ESR (Equivalent Series Resistance) on the input capacitor, but tolerance and
temperature coefficient must be considered when selecting the capacitor to ensure the capacitance will remain
approximately 1.0µF over the entire operating temperature range.
OUTPUT CAPACITOR
The LP5996 is designed specifically to work with very small ceramic output capacitors. A 1.0µF ceramic
capacitor (temperature types Z5U, Y5V or X7R) with ESR between 5mΩ to 500mΩ, is suitable in the LP5996
application circuit.
For this device the output capacitor should be connected between the VOUT pin and ground.
It is also possible to use tantalum or film capacitors at the device output, COUT (or VOUT), but these are not as
attractive for reasons of size and cost (see the section Capacitor Characteristics).
The output capacitor must meet the requirement for the minimum value of capacitance and also have an ESR
value that is within the range 5mΩ to 500mΩ for stability.
NO-LOAD STABILITY
The LP5996 will remain stable and in regulation with no external load. This is an important consideration in some
circuits, for example CMOS RAM keep-alive applications.
CAPACITOR CHARACTERISTICS
The LP5996 is designed to work with ceramic capacitors on the output to take advantage of the benefits they
offer. For capacitance values in the range of 0.47µF to 4.7µF, ceramic capacitors are the smallest, least
expensive and have the lowest ESR values, thus making them best for eliminating high frequency noise. The
ESR of a typical 1.0µF ceramic capacitor is in the range of 20mΩ to 40mΩ, which easily meets the ESR
requirement for stability for the LP5996.
For both input and output capacitors, careful interpretation of the capacitor specification is required to ensure
correct device operation. The capacitor value can change greatly, depending on the operating conditions and
capacitor type.
In particular, the output capacitor selection should take account of all the capacitor parameters, to ensure that the
specification is met within the application. The capacitance can vary with DC bias conditions as well as
temperature and frequency of operation. Capacitor values will also show some decrease over time due to aging.
The capacitor parameters are also dependant on the particular case size, with smaller sizes giving poorer
performance figures in general. As an example, Figure 20 shows a typical graph comparing different capacitor
case sizes in a Capacitance vs. DC Bias plot. As shown in the graph, increasing the DC Bias condition can result
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in the capacitance value falling below the minimum value given in the recommended capacitor specifications
table (0.7µF in this case). Note that the graph shows the capacitance out of spec for the 0402 case size
capacitor at higher bias voltages. It is therefore recommended that the capacitor manufacturers’ specifications for
the nominal value capacitor are consulted for all conditions, as some capacitor sizes (e.g. 0402) may not be
suitable in the actual application.
0603, 10V, X5R
100%
80%
60%
0402, 6.3V, X5R
40%_
20%
_
2.0
_
3.0
_
4.0
_
5.0
_
0
1.0
DC BIAS (V)
Figure 20. Graph Showing a Typical Variation in Capacitance vs DC Bias
The capacitance value of ceramic capacitors varies with temperature. The capacitor type X7R, which operates
over a temperature range of -55°C to +125°C, will only vary the capacitance to within ±15%. The capacitor type
X5R has a similar tolerance over a reduced temperature range of -55°C to +85°C. Many large value ceramic
capacitors, larger than 1µF are manufactured with Z5U or Y5V temperature characteristics. Their capacitance
can drop by more than 50% as the temperature varies from 25°C to 85°C. Therefore X7R is recommended over
Z5U and Y5V in applications where the ambient temperature will change significantly above or below 25°C.
Tantalum capacitors are less desirable than ceramic for use as output capacitors because they are more
expensive when comparing equivalent capacitance and voltage ratings in the 0.47µF to 4.7µF range.
Another important consideration is that tantalum capacitors have higher ESR values than equivalent size
ceramics. This means that while it may be possible to find a tantalum capacitor with an ESR value within the
stable range, it would have to be larger in capacitance (which means bigger and more costly) than a ceramic
capacitor with the same ESR value. It should also be noted that the ESR of a typical tantalum will increase about
2:1 as the temperature goes from 25°C down to -40°C, so some guard band must be allowed.
ENABLE CONTROL
The LP5996 features active high enable pins for each regulator, EN1 and EN2, which turns the corresponding
LDO off when pulled low. The device outputs are enabled when the enable pins are set to high. When not
enabled the regulator output is off and the device typically consumes 2nA.
If the application does not require the Enable switching feature, one or both enable pins should be tied to VIN to
keep the regulator output permanently on.
To ensure proper operation, the signal source used to drive the enable inputs must be able to swing above and
below the specified turn-on/off voltage thresholds listed in the Electrical Characteristics section under VIL and VIH.
BYPASS CAPACITOR
The internal voltage reference circuit of the LP5996 is connected to the CBYP pin via a high value internal resistor.
An external capacitor, connected to this pin, forms a low-pass filter which reduces the noise level on both outputs
of the device. There is also some improvement in PSSR and line transient performance. Internal circuitry ensures
rapid charging of the CBYP capacitor during start-up. A 10nF, high quality ceramic capacitor with either NPO or
COG dielectric is recommended due to their low leakage characteristics and low noise performance.
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SAFE AREA OF OPERATION
Due consideration should be given to operating conditions to avoid excessive thermal dissipation of the LP5996
or triggering its thermal shutdown circuit. When both outputs are enabled, the total power dissipation will be
PD(LDO1) + PD(LDO2) where PD = (VIN - VOUT) x IOUT for each LDO
In general, device options which have a large difference in output voltage will dissipate more power with both
outputs enabled, due to the input voltage required for the higher output voltage LDO. In such cases, especially at
elevated ambient temperature, it may not be possible to operate both outputs at maximum current at the same
time.
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REVISION HISTORY
Changes from Revision B (April 2013) to Revision C
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 11
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PACKAGE OPTION ADDENDUM
www.ti.com
8-Oct-2015
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
LP5996SD-1018/NOPB
LP5996SD-1525/NOPB
LP5996SD-1833/NOPB
LP5996SD-2533/NOPB
LP5996SD-2828/NOPB
LP5996SD-3033/NOPB
LP5996SD-3333/NOPB
ACTIVE
WSON
WSON
WSON
WSON
WSON
WSON
WSON
DSC
10
10
10
10
10
10
10
1000
Green (RoHS
& no Sb/Br)
CU SN
CU SN
CU SN
CU SN
CU SN
CU SN
CU SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
L224B
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DSC
DSC
DSC
DSC
DSC
DSC
1000
1000
1000
1000
1000
1000
Green (RoHS
& no Sb/Br)
-40 to 85
L177B
L225B
L226B
L180B
L179B
L182B
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
-40 to 85
-40 to 85
-40 to 85
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
8-Oct-2015
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
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value exceeds the maximum column width.
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Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Sep-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LP5996SD-1018/NOPB
LP5996SD-1525/NOPB
LP5996SD-1833/NOPB
LP5996SD-2533/NOPB
LP5996SD-2828/NOPB
LP5996SD-3033/NOPB
LP5996SD-3333/NOPB
WSON
WSON
WSON
WSON
WSON
WSON
WSON
DSC
DSC
DSC
DSC
DSC
DSC
DSC
10
10
10
10
10
10
10
1000
1000
1000
1000
1000
1000
1000
178.0
178.0
178.0
178.0
178.0
178.0
178.0
12.4
12.4
12.4
12.4
12.4
12.4
12.4
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
1.0
1.0
1.0
1.0
1.0
1.0
1.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Sep-2015
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LP5996SD-1018/NOPB
LP5996SD-1525/NOPB
LP5996SD-1833/NOPB
LP5996SD-2533/NOPB
LP5996SD-2828/NOPB
LP5996SD-3033/NOPB
LP5996SD-3333/NOPB
WSON
WSON
WSON
WSON
WSON
WSON
WSON
DSC
DSC
DSC
DSC
DSC
DSC
DSC
10
10
10
10
10
10
10
1000
1000
1000
1000
1000
1000
1000
210.0
210.0
210.0
210.0
210.0
210.0
210.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
DSC0010A
SDA10A (Rev A)
www.ti.com
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相关型号:
LP5996SDX-1833
IC VREG DUAL OUTPUT, FIXED POSITIVE LDO REGULATOR, DSO10, 3 X 3 MM, LLP-10, Fixed Positive Multiple Output LDO Regulator
NSC
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